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54 | pj | 1 | /***************************************************************************\ |
2 | |* *| |
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3 | |* Copyright (c) 1996-1998 NVIDIA, Corp. All rights reserved. *| |
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4 | |* *| |
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5 | |* NOTICE TO USER: The source code is copyrighted under U.S. and *| |
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6 | |* international laws. NVIDIA, Corp. of Sunnyvale, California owns *| |
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7 | |* the copyright and as design patents pending on the design and *| |
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8 | |* interface of the NV chips. Users and possessors of this source *| |
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9 | |* code are hereby granted a nonexclusive, royalty-free copyright *| |
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10 | |* and design patent license to use this code in individual and *| |
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11 | |* commercial software. *| |
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12 | |* *| |
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13 | |* Any use of this source code must include, in the user documenta- *| |
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14 | |* tion and internal comments to the code, notices to the end user *| |
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15 | |* as follows: *| |
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16 | |* *| |
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17 | |* Copyright (c) 1996-1998 NVIDIA, Corp. NVIDIA design patents *| |
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18 | |* pending in the U.S. and foreign countries. *| |
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19 | |* *| |
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20 | |* NVIDIA, CORP. MAKES NO REPRESENTATION ABOUT THE SUITABILITY OF *| |
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21 | |* THIS SOURCE CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" WITHOUT *| |
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22 | |* EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORP. DISCLAIMS *| |
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23 | |* ALL WARRANTIES WITH REGARD TO THIS SOURCE CODE, INCLUDING ALL *| |
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24 | |* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *| |
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25 | |* PARTICULAR PURPOSE. IN NO EVENT SHALL NVIDIA, CORP. BE LIABLE *| |
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26 | |* FOR ANY SPECIAL, INDIRECT, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, *| |
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27 | |* OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR *| |
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28 | |* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER *| |
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29 | |* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR *| |
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30 | |* PERFORMANCE OF THIS SOURCE CODE. *| |
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31 | |* *| |
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32 | \***************************************************************************/ |
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33 | |||
34 | /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/nv/nv3ref.h,v 1.1.2.3 1998/01/24 00:04:39 robin Exp $ */ |
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35 | |||
36 | #ifndef __NV3REF_H__ |
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37 | #define __NV3REF_H__ |
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38 | |||
39 | |||
40 | /* Magic values to lock/unlock extended regs */ |
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41 | #define UNLOCK_EXT_MAGIC 0x57 |
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42 | #define LOCK_EXT_MAGIC 0x99 /* Any value other than 0x57 will do */ |
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43 | |||
44 | #define LOCK_EXT_INDEX 0x6 |
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45 | |||
46 | /* Extended offset and start address */ |
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47 | #define NV_PCRTC_REPAINT0 0x19 |
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48 | #define NV_PCRTC_REPAINT0_OFFSET_10_8 7:5 |
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49 | #define NV_PCRTC_REPAINT0_START_ADDR_20_16 4:0 |
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50 | |||
51 | /* Horizonal extended bits */ |
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52 | #define NV_PCRTC_HORIZ_EXTRA 0x2d |
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53 | #define NV_PCRTC_HORIZ_EXTRA_INTER_HALF_START_8 4:4 |
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54 | #define NV_PCRTC_HORIZ_EXTRA_HORIZ_RETRACE_START_8 3:3 |
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55 | #define NV_PCRTC_HORIZ_EXTRA_HORIZ_BLANK_START_8 2:2 |
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56 | #define NV_PCRTC_HORIZ_EXTRA_DISPLAY_END_8 1:1 |
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57 | #define NV_PCRTC_HORIZ_EXTRA_DISPLAY_TOTAL_8 0:0 |
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58 | |||
59 | /* Assorted extra bits */ |
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60 | #define NV_PCRTC_EXTRA 0x25 |
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61 | #define NV_PCRTC_EXTRA_OFFSET_11 5:5 |
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62 | #define NV_PCRTC_EXTRA_HORIZ_BLANK_END_6 4:4 |
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63 | #define NV_PCRTC_EXTRA_VERT_BLANK_START_10 3:3 |
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64 | #define NV_PCRTC_EXTRA_VERT_RETRACE_START_10 2:2 |
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65 | #define NV_PCRTC_EXTRA_VERT_DISPLAY_END_10 1:1 |
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66 | #define NV_PCRTC_EXTRA_VERT_TOTAL_10 0:0 |
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67 | |||
68 | |||
69 | /* Controls how much data the refresh fifo requests */ |
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70 | #define NV_PCRTC_FIFO_CONTROL 0x1b |
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71 | #define NV_PCRTC_FIFO_CONTROL_UNDERFLOW_WARN 7:7 |
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72 | #define NV_PCRTC_FIFO_CONTROL_BURST_LENGTH 2:0 |
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73 | #define NV_PCRTC_FIFO_CONTROL_BURST_LENGTH_8 0x0 |
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74 | #define NV_PCRTC_FIFO_CONTROL_BURST_LENGTH_32 0x1 |
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75 | #define NV_PCRTC_FIFO_CONTROL_BURST_LENGTH_64 0x2 |
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76 | #define NV_PCRTC_FIFO_CONTROL_BURST_LENGTH_128 0x3 |
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77 | #define NV_PCRTC_FIFO_CONTROL_BURST_LENGTH_256 0x4 |
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78 | |||
79 | /* When the fifo occupancy falls below *twice* the watermark, |
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80 | * the refresh fifo will start to be refilled. If this value is |
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81 | * too low, you will get junk on the screen. Too high, and performance |
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82 | * will suffer. Watermark in units of 8 bytes |
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83 | */ |
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84 | #define NV_PCRTC_FIFO 0x20 |
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85 | #define NV_PCRTC_FIFO_RESET 7:7 |
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86 | #define NV_PCRTC_FIFO_WATERMARK 5:0 |
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87 | |||
88 | |||
89 | /* Various flags */ |
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90 | #define NV_PCRTC_REPAINT1 0x1a |
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91 | #define NV_PCRTC_REPAINT1_HSYNC 7:7 |
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92 | #define NV_PCRTC_REPAINT1_HYSNC_DISABLE 0x01 |
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93 | #define NV_PCRTC_REPAINT1_HYSNC_ENABLE 0x00 |
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94 | #define NV_PCRTC_REPAINT1_VSYNC 6:6 |
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95 | #define NV_PCRTC_REPAINT1_VYSNC_DISABLE 0x01 |
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96 | #define NV_PCRTC_REPAINT1_VYSNC_ENABLE 0x00 |
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97 | #define NV_PCRTC_REPAINT1_COMPATIBLE_TEXT 4:4 |
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98 | #define NV_PCRTC_REPAINT1_COMPATIBLE_TEXT_ENABLE 0x01 |
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99 | #define NV_PCRTC_REPAINT1_COMPATIBLE_TEXT_DISABLE 0x00 |
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100 | #define NV_PCRTC_REPAINT1_LARGE_SCREEN 2:2 |
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101 | #define NV_PCRTC_REPAINT1_LARGE_SCREEN_DISABLE 0x01 |
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102 | #define NV_PCRTC_REPAINT1_LARGE_SCREEN_ENABLE 0x00 /* >=1280 */ |
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103 | #define NV_PCRTC_REPAINT1_PALETTE_WIDTH 1:1 |
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104 | #define NV_PCRTC_REPAINT1_PALETTE_WIDTH_8BITS 0x00 |
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105 | #define NV_PCRTC_REPAINT1_PALETTE_WIDTH_6BITS 0x01 |
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106 | |||
107 | |||
108 | #define NV_PCRTC_GRCURSOR0 0x30 |
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109 | #define NV_PCRTC_GRCURSOR0_START_ADDR_21_16 5:0 |
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110 | |||
111 | #define NV_PCRTC_GRCURSOR1 0x31 |
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112 | #define NV_PCRTC_GRCURSOR1_START_ADDR_15_11 7:3 |
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113 | #define NV_PCRTC_GRCURSOR1_SCAN_DBL 1:1 |
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114 | #define NV_PCRTC_GRCURSOR1_SCAN_DBL_DISABLE 0 |
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115 | #define NV_PCRTC_GRCURSOR1_SCAN_DBL_ENABLE 1 |
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116 | #define NV_PCRTC_GRCURSOR1_CURSOR 0:0 |
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117 | #define NV_PCRTC_GRCURSOR1_CURSOR_DISABLE 0 |
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118 | #define NV_PCRTC_GRCURSOR1_CURSOR_ENABLE 1 |
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119 | |||
120 | #define NV_PCRTC_SCREEN 0x41 |
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121 | |||
122 | |||
123 | /* Controls what the format of the framebuffer is */ |
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124 | #define NV_PCRTC_PIXEL 0x28 |
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125 | #define NV_PCRTC_PIXEL_MODE 7:7 |
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126 | #define NV_PCRTC_PIXEL_MODE_TV 0x01 |
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127 | #define NV_PCRTC_PIXEL_MODE_VGA 0x00 |
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128 | #define NV_PCRTC_PIXEL_TV_MODE 6:6 |
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129 | #define NV_PCRTC_PIXEL_TV_MODE_NTSC 0x00 |
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130 | #define NV_PCRTC_PIXEL_TV_MODE_PAL 0x01 |
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131 | #define NV_PCRTC_PIXEL_TV_HORIZ_ADJUST 5:3 |
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132 | #define NV_PCRTC_PIXEL_FORMAT 1:0 |
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133 | #define NV_PCRTC_PIXEL_FORMAT_VGA 0x00 |
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134 | #define NV_PCRTC_PIXEL_FORMAT_8BPP 0x01 |
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135 | #define NV_PCRTC_PIXEL_FORMAT_16BPP 0x02 |
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136 | #define NV_PCRTC_PIXEL_FORMAT_32BPP 0x03 |
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137 | |||
138 | #define NV_PEXTDEV 0x00101fff:0x00101000 |
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139 | #define NV_PEXTDEV_0 0x00101000 |
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140 | |||
141 | #define NV_PRAMDAC 0x00680FFF:0x00680000 /* RW--D */ |
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142 | |||
143 | #define NV_PRAMDAC_VPLL_COEFF 0x00680508 /* RW-4R */ |
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144 | #define NV_PRAMDAC_VPLL_COEFF_MDIV 7:0 /* RWIUF */ |
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145 | #define NV_PRAMDAC_VPLL_COEFF_NDIV 15:8 /* RWIUF */ |
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146 | #define NV_PRAMDAC_VPLL_COEFF_PDIV 18:16 /* RWIVF */ |
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147 | |||
148 | |||
149 | #define NV_PRAMDAC_PLL_COEFF_SELECT 0x0068050C /* RW-4R */ |
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150 | #define NV_PRAMDAC_PLL_COEFF_SELECT_DLL_BYPASS 4:4 /* RWIVF */ |
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151 | #define NV_PRAMDAC_PLL_COEFF_SELECT_DLL_BYPASS_FALSE 0x00000000 /* RWI-V */ |
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152 | #define NV_PRAMDAC_PLL_COEFF_SELECT_DLL_BYPASS_TRUE 0x00000001 /* RW--V */ |
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153 | #define NV_PRAMDAC_PLL_COEFF_SELECT_MPLL_SOURCE 8:8 /* RWIVF */ |
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154 | #define NV_PRAMDAC_PLL_COEFF_SELECT_MPLL_SOURCE_DEFAULT 0x00000000 /* RWI-V */ |
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155 | #define NV_PRAMDAC_PLL_COEFF_SELECT_MPLL_SOURCE_PROG 0x00000001 /* RW--V */ |
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156 | #define NV_PRAMDAC_PLL_COEFF_SELECT_MPLL_BYPASS 12:12 /* RWIVF */ |
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157 | #define NV_PRAMDAC_PLL_COEFF_SELECT_MPLL_BYPASS_FALSE 0x00000000 /* RWI-V */ |
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158 | #define NV_PRAMDAC_PLL_COEFF_SELECT_MPLL_BYPASS_TRUE 0x00000001 /* RW--V */ |
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159 | #define NV_PRAMDAC_PLL_COEFF_SELECT_VPLL_SOURCE 16:16 /* RWIVF */ |
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160 | #define NV_PRAMDAC_PLL_COEFF_SELECT_VPLL_SOURCE_DEFAULT 0x00000000 /* RWI-V */ |
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161 | #define NV_PRAMDAC_PLL_COEFF_SELECT_VPLL_SOURCE_PROG 0x00000001 /* RW--V */ |
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162 | #define NV_PRAMDAC_PLL_COEFF_SELECT_VPLL_BYPASS 20:20 /* RWIVF */ |
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163 | #define NV_PRAMDAC_PLL_COEFF_SELECT_VPLL_BYPASS_FALSE 0x00000000 /* RWI-V */ |
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164 | #define NV_PRAMDAC_PLL_COEFF_SELECT_VPLL_BYPASS_TRUE 0x00000001 /* RW--V */ |
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165 | #define NV_PRAMDAC_PLL_COEFF_SELECT_PCLK_SOURCE 25:24 /* RWIVF */ |
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166 | #define NV_PRAMDAC_PLL_COEFF_SELECT_PCLK_SOURCE_VPLL 0x00000000 /* RWI-V */ |
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167 | #define NV_PRAMDAC_PLL_COEFF_SELECT_PCLK_SOURCE_VIP 0x00000001 /* RW--V */ |
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168 | #define NV_PRAMDAC_PLL_COEFF_SELECT_PCLK_SOURCE_XTALOSC 0x00000002 /* RW--V */ |
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169 | #define NV_PRAMDAC_PLL_COEFF_SELECT_VCLK_RATIO 28:28 /* RWIVF */ |
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170 | #define NV_PRAMDAC_PLL_COEFF_SELECT_VCLK_RATIO_DB1 0x00000000 /* RWI-V */ |
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171 | #define NV_PRAMDAC_PLL_COEFF_SELECT_VCLK_RATIO_DB2 0x00000001 /* RW--V */ |
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172 | |||
173 | |||
174 | /* Various flags for DAC. BPC controls the width of the palette */ |
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175 | |||
176 | #define NV_PRAMDAC_GENERAL_CONTROL 0x00680600 /* RW-4R */ |
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177 | #define NV_PRAMDAC_GENERAL_CONTROL_FF_COEFF 1:0 /* RWIVF */ |
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178 | #define NV_PRAMDAC_GENERAL_CONTROL_FF_COEFF_DEF 0x00000000 /* RWI-V */ |
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179 | #define NV_PRAMDAC_GENERAL_CONTROL_IDC_MODE 4:4 /* RWIVF */ |
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180 | #define NV_PRAMDAC_GENERAL_CONTROL_IDC_MODE_GAMMA 0x00000000 /* RWI-V */ |
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181 | #define NV_PRAMDAC_GENERAL_CONTROL_IDC_MODE_INDEX 0x00000001 /* RW--V */ |
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182 | #define NV_PRAMDAC_GENERAL_CONTROL_VGA_STATE 8:8 /* RWIVF */ |
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183 | #define NV_PRAMDAC_GENERAL_CONTROL_VGA_STATE_NOTSE 0x00000000 /* RWI-V */ |
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184 | #define NV_PRAMDAC_GENERAL_CONTROL_VGA_STATE_SEL 0x00000001 /* RW--V */ |
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185 | #define NV_PRAMDAC_GENERAL_CONTROL_565_MODE 12:12 /* RWIVF */ |
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186 | #define NV_PRAMDAC_GENERAL_CONTROL_565_MODE_NOTSEL 0x00000000 /* RWI-V */ |
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187 | #define NV_PRAMDAC_GENERAL_CONTROL_565_MODE_SEL 0x00000001 /* RW--V */ |
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188 | #define NV_PRAMDAC_GENERAL_CONTROL_BLK_PEDSTL 16:16 /* RWIVF */ |
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189 | #define NV_PRAMDAC_GENERAL_CONTROL_BLK_PEDSTL_OFF 0x00000000 /* RWI-V */ |
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190 | #define NV_PRAMDAC_GENERAL_CONTROL_BLK_PEDSTL_ON 0x00000001 /* RW--V */ |
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191 | #define NV_PRAMDAC_GENERAL_CONTROL_TERMINATION 17:17 /* RWIVF */ |
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192 | #define NV_PRAMDAC_GENERAL_CONTROL_TERMINATION_37OHM 0x00000000 /* RWI-V */ |
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193 | #define NV_PRAMDAC_GENERAL_CONTROL_TERMINATION_75OHM 0x00000001 /* RW--V */ |
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194 | #define NV_PRAMDAC_GENERAL_CONTROL_BPC 20:20 /* RWIVF */ |
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195 | #define NV_PRAMDAC_GENERAL_CONTROL_BPC_6BITS 0x00000000 /* RWI-V */ |
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196 | #define NV_PRAMDAC_GENERAL_CONTROL_BPC_8BITS 0x00000001 /* RW--V */ |
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197 | #define NV_PRAMDAC_GENERAL_CONTROL_DAC_SLEEP 24:24 /* RWIVF */ |
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198 | #define NV_PRAMDAC_GENERAL_CONTROL_DAC_SLEEP_DIS 0x00000000 /* RWI-V */ |
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199 | #define NV_PRAMDAC_GENERAL_CONTROL_DAC_SLEEP_EN 0x00000001 /* RW--V */ |
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200 | #define NV_PRAMDAC_GENERAL_CONTROL_PALETTE_CLK 28:28 /* RWIVF */ |
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201 | #define NV_PRAMDAC_GENERAL_CONTROL_PALETTE_CLK_EN 0x00000000 /* RWI-V */ |
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202 | #define NV_PRAMDAC_GENERAL_CONTROL_PALETTE_CLK_DIS 0x00000001 /* RW--V */ |
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203 | |||
204 | |||
205 | #define NV_PRAMDAC_GRCURSOR_START_POS 0x00680300 /* RW-4R */ |
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206 | #define NV_PRAMDAC_GRCURSOR_START_POS_X 11:0 /* RWXSF */ |
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207 | #define NV_PRAMDAC_GRCURSOR_START_POS_Y 27:16 /* RWXSF */ |
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208 | |||
209 | #define NV_PMC 0x00000FFF:0x00000000 /* RW--D */ |
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210 | #define NV_PMC_INTR_0 0x00000100 /* RW-4R */ |
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211 | #define NV_PMC_INTR_0_PAUDIO 0:0 /* R--VF */ |
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212 | #define NV_PMC_INTR_0_PAUDIO_NOT_PENDING 0x00000000 /* R---V */ |
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213 | #define NV_PMC_INTR_0_PAUDIO_PENDING 0x00000001 /* R---V */ |
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214 | #define NV_PMC_INTR_0_PMEDIA 4:4 /* R--VF */ |
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215 | #define NV_PMC_INTR_0_PMEDIA_NOT_PENDING 0x00000000 /* R---V */ |
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216 | #define NV_PMC_INTR_0_PMEDIA_PENDING 0x00000001 /* R---V */ |
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217 | #define NV_PMC_INTR_0_PFIFO 8:8 /* R--VF */ |
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218 | #define NV_PMC_INTR_0_PFIFO_NOT_PENDING 0x00000000 /* R---V */ |
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219 | #define NV_PMC_INTR_0_PFIFO_PENDING 0x00000001 /* R---V */ |
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220 | #define NV_PMC_INTR_0_PGRAPH0 12:12 /* R--VF */ |
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221 | #define NV_PMC_INTR_0_PGRAPH0_NOT_PENDING 0x00000000 /* R---V */ |
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222 | #define NV_PMC_INTR_0_PGRAPH0_PENDING 0x00000001 /* R---V */ |
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223 | #define NV_PMC_INTR_0_PGRAPH1 13:13 /* R--VF */ |
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224 | #define NV_PMC_INTR_0_PGRAPH1_NOT_PENDING 0x00000000 /* R---V */ |
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225 | #define NV_PMC_INTR_0_PGRAPH1_PENDING 0x00000001 /* R---V */ |
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226 | #define NV_PMC_INTR_0_PVIDEO 16:16 /* R--VF */ |
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227 | #define NV_PMC_INTR_0_PVIDEO_NOT_PENDING 0x00000000 /* R---V */ |
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228 | #define NV_PMC_INTR_0_PVIDEO_PENDING 0x00000001 /* R---V */ |
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229 | #define NV_PMC_INTR_0_PTIMER 20:20 /* R--VF */ |
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230 | #define NV_PMC_INTR_0_PTIMER_NOT_PENDING 0x00000000 /* R---V */ |
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231 | #define NV_PMC_INTR_0_PTIMER_PENDING 0x00000001 /* R---V */ |
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232 | #define NV_PMC_INTR_0_PFB 24:24 /* R--VF */ |
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233 | #define NV_PMC_INTR_0_PFB_NOT_PENDING 0x00000000 /* R---V */ |
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234 | #define NV_PMC_INTR_0_PFB_PENDING 0x00000001 /* R---V */ |
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235 | #define NV_PMC_INTR_0_PBUS 28:28 /* R--VF */ |
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236 | #define NV_PMC_INTR_0_PBUS_NOT_PENDING 0x00000000 /* R---V */ |
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237 | #define NV_PMC_INTR_0_PBUS_PENDING 0x00000001 /* R---V */ |
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238 | #define NV_PMC_INTR_0_SOFTWARE 31:31 /* RWIVF */ |
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239 | #define NV_PMC_INTR_0_SOFTWARE_NOT_PENDING 0x00000000 /* RWI-V */ |
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240 | #define NV_PMC_INTR_0_SOFTWARE_PENDING 0x00000001 /* RW--V */ |
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241 | |||
242 | #define NV_PMC_INTR_EN_0 0x00000140 /* RW-4R */ |
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243 | #define NV_PMC_INTR_EN_0_INTA 1:0 /* RWIVF */ |
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244 | #define NV_PMC_INTR_EN_0_INTA_DISABLED 0x00000000 /* RWI-V */ |
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245 | #define NV_PMC_INTR_EN_0_INTA_HARDWARE 0x00000001 /* RW--V */ |
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246 | #define NV_PMC_INTR_EN_0_INTA_SOFTWARE 0x00000002 /* RW--V */ |
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247 | |||
248 | #define NV_PMC_ENABLE 0x00000200 /* RW-4R */ |
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249 | |||
250 | #define NV_PFIFO 0x00003FFF:0x00002000 /* RW--D */ |
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251 | #define NV_PFIFO_INTR_0 0x00002100 /* RW-4R */ |
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252 | #define NV_PFIFO_INTR_0_CACHE_ERROR 0:0 /* RWXVF */ |
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253 | #define NV_PFIFO_INTR_0_CACHE_ERROR_NOT_PENDING 0x00000000 /* R---V */ |
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254 | #define NV_PFIFO_INTR_0_CACHE_ERROR_PENDING 0x00000001 /* R---V */ |
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255 | #define NV_PFIFO_INTR_0_CACHE_ERROR_RESET 0x00000001 /* -W--V */ |
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256 | #define NV_PFIFO_INTR_0_RUNOUT 4:4 /* RWXVF */ |
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257 | #define NV_PFIFO_INTR_0_RUNOUT_NOT_PENDING 0x00000000 /* R---V */ |
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258 | #define NV_PFIFO_INTR_0_RUNOUT_PENDING 0x00000001 /* R---V */ |
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259 | #define NV_PFIFO_INTR_0_RUNOUT_RESET 0x00000001 /* -W--V */ |
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260 | #define NV_PFIFO_INTR_0_RUNOUT_OVERFLOW 8:8 /* RWXVF */ |
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261 | #define NV_PFIFO_INTR_0_RUNOUT_OVERFLOW_NOT_PENDING 0x00000000 /* R---V */ |
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262 | #define NV_PFIFO_INTR_0_RUNOUT_OVERFLOW_PENDING 0x00000001 /* R---V */ |
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263 | #define NV_PFIFO_INTR_0_RUNOUT_OVERFLOW_RESET 0x00000001 /* -W--V */ |
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264 | #define NV_PFIFO_INTR_0_DMA_PUSHER 12:12 /* RWXVF */ |
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265 | #define NV_PFIFO_INTR_0_DMA_PUSHER_NOT_PENDING 0x00000000 /* R---V */ |
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266 | #define NV_PFIFO_INTR_0_DMA_PUSHER_PENDING 0x00000001 /* R---V */ |
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267 | #define NV_PFIFO_INTR_0_DMA_PUSHER_RESET 0x00000001 /* -W--V */ |
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268 | #define NV_PFIFO_INTR_0_DMA_PTE 16:16 /* RWXVF */ |
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269 | #define NV_PFIFO_INTR_0_DMA_PTE_NOT_PENDING 0x00000000 /* R---V */ |
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270 | #define NV_PFIFO_INTR_0_DMA_PTE_PENDING 0x00000001 /* R---V */ |
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271 | #define NV_PFIFO_INTR_0_DMA_PTE_RESET 0x00000001 /* -W--V */ |
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272 | #define NV_PFIFO_INTR_EN_0 0x00002140 /* RW-4R */ |
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273 | #define NV_PFIFO_INTR_EN_0_CACHE_ERROR 0:0 /* RWIVF */ |
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274 | #define NV_PFIFO_INTR_EN_0_CACHE_ERROR_DISABLED 0x00000000 /* RWI-V */ |
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275 | #define NV_PFIFO_INTR_EN_0_CACHE_ERROR_ENABLED 0x00000001 /* RW--V */ |
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276 | #define NV_PFIFO_INTR_EN_0_RUNOUT 4:4 /* RWIVF */ |
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277 | #define NV_PFIFO_INTR_EN_0_RUNOUT_DISABLED 0x00000000 /* RWI-V */ |
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278 | #define NV_PFIFO_INTR_EN_0_RUNOUT_ENABLED 0x00000001 /* RW--V */ |
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279 | #define NV_PFIFO_INTR_EN_0_RUNOUT_OVERFLOW 8:8 /* RWIVF */ |
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280 | #define NV_PFIFO_INTR_EN_0_RUNOUT_OVERFLOW_DISABLED 0x00000000 /* RWI-V */ |
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281 | #define NV_PFIFO_INTR_EN_0_RUNOUT_OVERFLOW_ENABLED 0x00000001 /* RW--V */ |
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282 | #define NV_PFIFO_CONFIG_0 0x00002200 /* RW-4R */ |
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283 | #define NV_PFIFO_RAMHT 0x00002210 /* RW-4R */ |
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284 | #define NV_PFIFO_RAMHT_BASE_ADDRESS 15:12 /* RWXVF */ |
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285 | #define NV_PFIFO_RAMHT_SIZE 17:16 /* RWXVF */ |
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286 | #define NV_PFIFO_RAMHT_SIZE_4K 0x00000000 /* RWI-V */ |
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287 | #define NV_PFIFO_RAMHT_SIZE_8K 0x00000001 /* RW--V */ |
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288 | #define NV_PFIFO_RAMHT_SIZE_16K 0x00000002 /* RW--V */ |
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289 | #define NV_PFIFO_RAMHT_SIZE_32K 0x00000003 /* RW--V */ |
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290 | #define NV_PFIFO_RAMFC 0x00002214 /* RW-4R */ |
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291 | #define NV_PFIFO_RAMFC_BASE_ADDRESS 15:9 /* RWXVF */ |
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292 | #define NV_PFIFO_RAMRO 0x00002218 /* RW-4R */ |
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293 | #define NV_PFIFO_RAMRO_BASE_ADDRESS 15:9 /* RWXVF */ |
||
294 | #define NV_PFIFO_RAMRO_SIZE 16:16 /* RWXVF */ |
||
295 | #define NV_PFIFO_RAMRO_SIZE_512 0x00000000 /* RWI-V */ |
||
296 | #define NV_PFIFO_RAMRO_SIZE_8K 0x00000001 /* RW--V */ |
||
297 | #define NV_PFIFO_CACHES 0x00002500 /* RW-4R */ |
||
298 | #define NV_PFIFO_CACHES_REASSIGN 0:0 /* RWIVF */ |
||
299 | #define NV_PFIFO_CACHES_REASSIGN_DISABLED 0x00000000 /* RWI-V */ |
||
300 | #define NV_PFIFO_CACHES_REASSIGN_ENABLED 0x00000001 /* RW--V */ |
||
301 | #define NV_PFIFO_CACHE0_PUSH0 0x00003000 /* RW-4R */ |
||
302 | #define NV_PFIFO_CACHE0_PUSH0_ACCESS 0:0 /* RWIVF */ |
||
303 | #define NV_PFIFO_CACHE0_PUSH0_ACCESS_DISABLED 0x00000000 /* RWI-V */ |
||
304 | #define NV_PFIFO_CACHE0_PUSH0_ACCESS_ENABLED 0x00000001 /* RW--V */ |
||
305 | #define NV_PFIFO_CACHE1_PUSH0 0x00003200 /* RW-4R */ |
||
306 | #define NV_PFIFO_CACHE1_PUSH0_ACCESS 0:0 /* RWIVF */ |
||
307 | #define NV_PFIFO_CACHE1_PUSH0_ACCESS_DISABLED 0x00000000 /* RWI-V */ |
||
308 | #define NV_PFIFO_CACHE1_PUSH0_ACCESS_ENABLED 0x00000001 /* RW--V */ |
||
309 | #define NV_PFIFO_CACHE0_PUSH1 0x00003004 /* RW-4R */ |
||
310 | #define NV_PFIFO_CACHE0_PUSH1_CHID 6:0 /* RWXUF */ |
||
311 | #define NV_PFIFO_CACHE1_PUSH1 0x00003204 /* RW-4R */ |
||
312 | #define NV_PFIFO_CACHE1_PUSH1_CHID 6:0 /* RWXUF */ |
||
313 | #define NV_PFIFO_CACHE1_DMA0 0x00003220 /* RW-4R */ |
||
314 | #define NV_PFIFO_CACHE1_DMA1 0x00003224 /* RW-4R */ |
||
315 | #define NV_PFIFO_CACHE1_DMA2 0x00003228 /* RW-4R */ |
||
316 | #define NV_PFIFO_CACHE0_PULL0 0x00003040 /* RW-4R */ |
||
317 | #define NV_PFIFO_CACHE0_PULL0_ACCESS 0:0 /* RWIVF */ |
||
318 | #define NV_PFIFO_CACHE0_PULL0_ACCESS_DISABLED 0x00000000 /* RWI-V */ |
||
319 | #define NV_PFIFO_CACHE0_PULL0_ACCESS_ENABLED 0x00000001 /* RW--V */ |
||
320 | #define NV_PFIFO_CACHE1_PULL0 0x00003240 /* RW-4R */ |
||
321 | #define NV_PFIFO_CACHE1_PULL0_ACCESS 0:0 /* RWIVF */ |
||
322 | #define NV_PFIFO_CACHE1_PULL0_ACCESS_DISABLED 0x00000000 /* RWI-V */ |
||
323 | #define NV_PFIFO_CACHE1_PULL0_ACCESS_ENABLED 0x00000001 /* RW--V */ |
||
324 | #define NV_PFIFO_CACHE1_PULL1 0x00003250 /* RW-4R */ |
||
325 | #define NV_PFIFO_CACHE1_PULL1_CTX 4:4 /* RWXVF */ |
||
326 | #define NV_PFIFO_CACHE1_PULL1_CTX_CLEAN 0x00000000 /* RW--V */ |
||
327 | #define NV_PFIFO_CACHE1_PULL1_CTX_DIRTY 0x00000001 /* RW--V */ |
||
328 | #define NV_PFIFO_CACHE1_PUT 0x00003210 /* RW-4R */ |
||
329 | #define NV_PFIFO_CACHE1_PUT_ADDRESS 6:2 /* RWXUF */ |
||
330 | #define NV_PFIFO_CACHE1_GET 0x00003270 /* RW-4R */ |
||
331 | #define NV_PFIFO_CACHE1_GET_ADDRESS 6:2 /* RWXUF */ |
||
332 | #define NV_PFIFO_CACHE1_CTX(i) (0x00003280+(i)*16) /* RW-4A */ |
||
333 | #define NV_PFIFO_CACHE1_CTX__SIZE_1 8 /* */ |
||
334 | #define NV_PFIFO_RUNOUT_PUT 0x00002410 /* RW-4R */ |
||
335 | #define NV_PFIFO_RUNOUT_GET 0x00002420 /* RW-4R */ |
||
336 | #define NV_PFIFO_RUNOUT_STATUS 0x00002400 /* R--4R */ |
||
337 | |||
338 | #define NV_PGRAPH 0x00401FFF:0x00400000 /* RW--D */ |
||
339 | #define NV_PGRAPH_DEBUG_0 0x00400080 /* RW-4R */ |
||
340 | #define NV_PGRAPH_DEBUG_0_STATE 0:0 /* CW-VF */ |
||
341 | #define NV_PGRAPH_DEBUG_0_STATE_NORMAL 0x00000000 /* CW--V */ |
||
342 | #define NV_PGRAPH_DEBUG_0_STATE_RESET 0x00000001 /* -W--V */ |
||
343 | #define NV_PGRAPH_DEBUG_0_BULK_READS 4:4 /* RWIVF */ |
||
344 | #define NV_PGRAPH_DEBUG_0_BULK_READS_DISABLED 0x00000000 /* RWI-V */ |
||
345 | #define NV_PGRAPH_DEBUG_0_BULK_READS_ENABLED 0x00000001 /* RW--V */ |
||
346 | #define NV_PGRAPH_DEBUG_0_WRITE_ONLY_ROPS_2D 20:20 /* RWIVF */ |
||
347 | #define NV_PGRAPH_DEBUG_0_WRITE_ONLY_ROPS_2D_DISABLED 0x00000000 /* RWI-V */ |
||
348 | #define NV_PGRAPH_DEBUG_0_WRITE_ONLY_ROPS_2D_ENABLED 0x00000001 /* RW--V */ |
||
349 | #define NV_PGRAPH_DEBUG_0_DRAWDIR_AUTO 24:24 /* RWIVF */ |
||
350 | #define NV_PGRAPH_DEBUG_0_DRAWDIR_AUTO_DISABLED 0x00000000 /* RWI-V */ |
||
351 | #define NV_PGRAPH_DEBUG_0_DRAWDIR_AUTO_ENABLED 0x00000001 /* RW--V */ |
||
352 | #define NV_PGRAPH_DEBUG_1 0x00400084 /* RW-4R */ |
||
353 | #define NV_PGRAPH_DEBUG_1_VOLATILE_RESET 0:0 /* RWIVF */ |
||
354 | #define NV_PGRAPH_DEBUG_1_VOLATILE_RESET_NOT_LAST 0x00000000 /* RWI-V */ |
||
355 | #define NV_PGRAPH_DEBUG_1_VOLATILE_RESET_LAST 0x00000001 /* RW--V */ |
||
356 | #define NV_PGRAPH_DEBUG_1_INSTANCE 16:16 /* RWIVF */ |
||
357 | #define NV_PGRAPH_DEBUG_1_INSTANCE_DISABLED 0x00000000 /* RWI-V */ |
||
358 | #define NV_PGRAPH_DEBUG_1_INSTANCE_ENABLED 0x00000001 /* RW--V */ |
||
359 | #define NV_PGRAPH_DEBUG_1_CTX 20:20 /* RWIVF */ |
||
360 | #define NV_PGRAPH_DEBUG_1_CTX_DISABLED 0x00000000 /* RWI-V */ |
||
361 | #define NV_PGRAPH_DEBUG_1_CTX_ENABLED 0x00000001 /* RW--V */ |
||
362 | #define NV_PGRAPH_DEBUG_2 0x00400088 /* RW-4R */ |
||
363 | #define NV_PGRAPH_DEBUG_2_AVOID_RMW_BLEND 0:0 /* RWIVF */ |
||
364 | #define NV_PGRAPH_DEBUG_2_AVOID_RMW_BLEND_DISABLED 0x00000000 /* RWI-V */ |
||
365 | #define NV_PGRAPH_DEBUG_2_AVOID_RMW_BLEND_ENABLED 0x00000001 /* RW--V */ |
||
366 | #define NV_PGRAPH_DEBUG_2_DPWR_FIFO 8:8 /* RWIVF */ |
||
367 | #define NV_PGRAPH_DEBUG_2_DPWR_FIFO_DISABLED 0x00000000 /* RWI-V */ |
||
368 | #define NV_PGRAPH_DEBUG_2_DPWR_FIFO_ENABLED 0x00000001 /* RW--V */ |
||
369 | #define NV_PGRAPH_DEBUG_2_VOLATILE_RESET 28:28 /* RWIVF */ |
||
370 | #define NV_PGRAPH_DEBUG_2_VOLATILE_RESET_DISABLED 0x00000000 /* RWI-V */ |
||
371 | #define NV_PGRAPH_DEBUG_2_VOLATILE_RESET_ENABLED 0x00000001 /* RW--V */ |
||
372 | #define NV_PGRAPH_DEBUG_3 0x0040008C /* RW-4R */ |
||
373 | #define NV_PGRAPH_DEBUG_3_HONOR_ALPHA 24:24 /* RWIVF */ |
||
374 | #define NV_PGRAPH_DEBUG_3_HONOR_ALPHA_DISABLED 0x00000000 /* RWI-V */ |
||
375 | #define NV_PGRAPH_DEBUG_3_HONOR_ALPHA_ENABLED 0x00000001 /* RW--V */ |
||
376 | |||
377 | #define NV_PGRAPH_INTR_0 0x00400100 /* RW-4R */ |
||
378 | #define NV_PGRAPH_INTR_0_RESERVED 0:0 /* RW-VF */ |
||
379 | #define NV_PGRAPH_INTR_0_RESERVED_NOT_PENDING 0x00000000 /* R---V */ |
||
380 | #define NV_PGRAPH_INTR_0_RESERVED_PENDING 0x00000001 /* R---V */ |
||
381 | #define NV_PGRAPH_INTR_0_RESERVED_RESET 0x00000001 /* -W--V */ |
||
382 | #define NV_PGRAPH_INTR_0_CONTEXT_SWITCH 4:4 /* RWIVF */ |
||
383 | #define NV_PGRAPH_INTR_0_CONTEXT_SWITCH_NOT_PENDING 0x00000000 /* R-I-V */ |
||
384 | #define NV_PGRAPH_INTR_0_CONTEXT_SWITCH_PENDING 0x00000001 /* R---V */ |
||
385 | #define NV_PGRAPH_INTR_0_CONTEXT_SWITCH_RESET 0x00000001 /* -W--V */ |
||
386 | #define NV_PGRAPH_INTR_0_VBLANK 8:8 /* RWIVF */ |
||
387 | #define NV_PGRAPH_INTR_0_VBLANK_NOT_PENDING 0x00000000 /* R-I-V */ |
||
388 | #define NV_PGRAPH_INTR_0_VBLANK_PENDING 0x00000001 /* R---V */ |
||
389 | #define NV_PGRAPH_INTR_0_VBLANK_RESET 0x00000001 /* -W--V */ |
||
390 | #define NV_PGRAPH_INTR_0_RANGE 12:12 /* RWIVF */ |
||
391 | #define NV_PGRAPH_INTR_0_RANGE_NOT_PENDING 0x00000000 /* R-I-V */ |
||
392 | #define NV_PGRAPH_INTR_0_RANGE_PENDING 0x00000001 /* R---V */ |
||
393 | #define NV_PGRAPH_INTR_0_RANGE_RESET 0x00000001 /* -W--V */ |
||
394 | #define NV_PGRAPH_INTR_0_METHOD_COUNT 16:16 /* RWIVF */ |
||
395 | #define NV_PGRAPH_INTR_0_METHOD_COUNT_NOT_PENDING 0x00000000 /* R-I-V */ |
||
396 | #define NV_PGRAPH_INTR_0_METHOD_COUNT_PENDING 0x00000001 /* R---V */ |
||
397 | #define NV_PGRAPH_INTR_0_METHOD_COUNT_RESET 0x00000001 /* -W--V */ |
||
398 | #define NV_PGRAPH_INTR_0_FORMAT 20:20 /* RWIVF */ |
||
399 | #define NV_PGRAPH_INTR_0_FORMAT_NOT_PENDING 0x00000000 /* R-I-V */ |
||
400 | #define NV_PGRAPH_INTR_0_FORMAT_PENDING 0x00000001 /* R---V */ |
||
401 | #define NV_PGRAPH_INTR_0_FORMAT_RESET 0x00000001 /* -W--V */ |
||
402 | #define NV_PGRAPH_INTR_0_COMPLEX_CLIP 24:24 /* RWIVF */ |
||
403 | #define NV_PGRAPH_INTR_0_COMPLEX_CLIP_NOT_PENDING 0x00000000 /* R-I-V */ |
||
404 | #define NV_PGRAPH_INTR_0_COMPLEX_CLIP_PENDING 0x00000001 /* R---V */ |
||
405 | #define NV_PGRAPH_INTR_0_COMPLEX_CLIP_RESET 0x00000001 /* -W--V */ |
||
406 | #define NV_PGRAPH_INTR_0_NOTIFY 28:28 /* RWIVF */ |
||
407 | #define NV_PGRAPH_INTR_0_NOTIFY_NOT_PENDING 0x00000000 /* R-I-V */ |
||
408 | #define NV_PGRAPH_INTR_0_NOTIFY_PENDING 0x00000001 /* R---V */ |
||
409 | #define NV_PGRAPH_INTR_0_NOTIFY_RESET 0x00000001 /* -W--V */ |
||
410 | |||
411 | #define NV_PGRAPH_INTR_1 0x00400104 /* RW-4R */ |
||
412 | #define NV_PGRAPH_INTR_1_METHOD 0:0 /* RWIVF */ |
||
413 | #define NV_PGRAPH_INTR_1_METHOD_NOT_PENDING 0x00000000 /* R-I-V */ |
||
414 | #define NV_PGRAPH_INTR_1_METHOD_PENDING 0x00000001 /* R---V */ |
||
415 | #define NV_PGRAPH_INTR_1_METHOD_RESET 0x00000001 /* -W--V */ |
||
416 | #define NV_PGRAPH_INTR_1_DATA 4:4 /* RWIVF */ |
||
417 | #define NV_PGRAPH_INTR_1_DATA_NOT_PENDING 0x00000000 /* R-I-V */ |
||
418 | #define NV_PGRAPH_INTR_1_DATA_PENDING 0x00000001 /* R---V */ |
||
419 | #define NV_PGRAPH_INTR_1_DATA_RESET 0x00000001 /* -W--V */ |
||
420 | #define NV_PGRAPH_INTR_1_DOUBLE_NOTIFY 12:12 /* RWIVF */ |
||
421 | #define NV_PGRAPH_INTR_1_DOUBLE_NOTIFY_NOT_PENDING 0x00000000 /* R-I-V */ |
||
422 | #define NV_PGRAPH_INTR_1_DOUBLE_NOTIFY_PENDING 0x00000001 /* R---V */ |
||
423 | #define NV_PGRAPH_INTR_1_DOUBLE_NOTIFY_RESET 0x00000001 /* -W--V */ |
||
424 | #define NV_PGRAPH_INTR_1_CTXSW_NOTIFY 16:16 /* RWIVF */ |
||
425 | #define NV_PGRAPH_INTR_1_CTXSW_NOTIFY_NOT_PENDING 0x00000000 /* R-I-V */ |
||
426 | #define NV_PGRAPH_INTR_1_CTXSW_NOTIFY_PENDING 0x00000001 /* R---V */ |
||
427 | #define NV_PGRAPH_INTR_1_CTXSW_NOTIFY_RESET 0x00000001 /* -W--V */ |
||
428 | |||
429 | #define NV_PGRAPH_INTR_EN_0 0x00400140 /* RW-4R */ |
||
430 | |||
431 | #define NV_PGRAPH_INTR_EN_1 0x00400144 /* RW-4R */ |
||
432 | |||
433 | #define NV_PGRAPH_CTX_CACHE(i) (0x004001a0+(i)*4) /* RW-4A */ |
||
434 | #define NV_PGRAPH_CTX_CACHE__SIZE_1 8 /* */ |
||
435 | |||
436 | #define NV_PGRAPH_CTX_SWITCH 0x00400180 /* RW-4R */ |
||
437 | |||
438 | #define NV_PGRAPH_CTX_CONTROL 0x00400190 /* RW-4R */ |
||
439 | #define NV_PGRAPH_CTX_CONTROL_MINIMUM_TIME 1:0 /* RWIVF */ |
||
440 | #define NV_PGRAPH_CTX_CONTROL_MINIMUM_TIME_33US 0x00000000 /* RWI-V */ |
||
441 | #define NV_PGRAPH_CTX_CONTROL_MINIMUM_TIME_262US 0x00000001 /* RW--V */ |
||
442 | #define NV_PGRAPH_CTX_CONTROL_MINIMUM_TIME_2MS 0x00000002 /* RW--V */ |
||
443 | #define NV_PGRAPH_CTX_CONTROL_MINIMUM_TIME_17MS 0x00000003 /* RW--V */ |
||
444 | #define NV_PGRAPH_CTX_CONTROL_TIME 8:8 /* RWIVF */ |
||
445 | #define NV_PGRAPH_CTX_CONTROL_TIME_EXPIRED 0x00000000 /* RWI-V */ |
||
446 | #define NV_PGRAPH_CTX_CONTROL_TIME_NOT_EXPIRED 0x00000001 /* RW--V */ |
||
447 | #define NV_PGRAPH_CTX_CONTROL_CHID 16:16 /* RWIVF */ |
||
448 | #define NV_PGRAPH_CTX_CONTROL_CHID_INVALID 0x00000000 /* RWI-V */ |
||
449 | #define NV_PGRAPH_CTX_CONTROL_CHID_VALID 0x00000001 /* RW--V */ |
||
450 | #define NV_PGRAPH_CTX_CONTROL_SWITCH 20:20 /* R--VF */ |
||
451 | #define NV_PGRAPH_CTX_CONTROL_SWITCH_UNAVAILABLE 0x00000000 /* R---V */ |
||
452 | #define NV_PGRAPH_CTX_CONTROL_SWITCH_AVAILABLE 0x00000001 /* R---V */ |
||
453 | #define NV_PGRAPH_CTX_CONTROL_SWITCHING 24:24 /* RWIVF */ |
||
454 | #define NV_PGRAPH_CTX_CONTROL_SWITCHING_IDLE 0x00000000 /* RWI-V */ |
||
455 | #define NV_PGRAPH_CTX_CONTROL_SWITCHING_BUSY 0x00000001 /* RW--V */ |
||
456 | #define NV_PGRAPH_CTX_CONTROL_DEVICE 28:28 /* RWIVF */ |
||
457 | #define NV_PGRAPH_CTX_CONTROL_DEVICE_DISABLED 0x00000000 /* RWI-V */ |
||
458 | #define NV_PGRAPH_CTX_CONTROL_DEVICE_ENABLED 0x00000001 /* RW--V */ |
||
459 | |||
460 | #define NV_PGRAPH_CTX_USER 0x00400194 /* RW-4R */ |
||
461 | |||
462 | #define NV_PGRAPH_FIFO 0x004006A4 /* RW-4R */ |
||
463 | #define NV_PGRAPH_FIFO_ACCESS 0:0 /* RWIVF */ |
||
464 | #define NV_PGRAPH_FIFO_ACCESS_DISABLED 0x00000000 /* RW--V */ |
||
465 | #define NV_PGRAPH_FIFO_ACCESS_ENABLED 0x00000001 /* RWI-V */ |
||
466 | |||
467 | #define NV_PGRAPH_STATUS 0x004006B0 /* R--4R */ |
||
468 | |||
469 | #define NV_PGRAPH_CLIP_MISC 0x004006A0 /* RW-4R */ |
||
470 | #define NV_PGRAPH_SRC_CANVAS_MIN 0x00400550 /* RW-4R */ |
||
471 | #define NV_PGRAPH_DST_CANVAS_MIN 0x00400558 /* RW-4R */ |
||
472 | #define NV_PGRAPH_SRC_CANVAS_MAX 0x00400554 /* RW-4R */ |
||
473 | #define NV_PGRAPH_DST_CANVAS_MAX 0x0040055C /* RW-4R */ |
||
474 | #define NV_PGRAPH_CLIP0_MIN 0x00400690 /* RW-4R */ |
||
475 | #define NV_PGRAPH_CLIP1_MIN 0x00400698 /* RW-4R */ |
||
476 | #define NV_PGRAPH_CLIP0_MAX 0x00400694 /* RW-4R */ |
||
477 | #define NV_PGRAPH_CLIP1_MAX 0x0040069C /* RW-4R */ |
||
478 | #define NV_PGRAPH_DMA 0x00400680 /* RW-4R */ |
||
479 | #define NV_PGRAPH_NOTIFY 0x00400684 /* RW-4R */ |
||
480 | #define NV_PGRAPH_INSTANCE 0x00400688 /* RW-4R */ |
||
481 | #define NV_PGRAPH_MEMFMT 0x0040068C /* RW-4R */ |
||
482 | #define NV_PGRAPH_BOFFSET0 0x00400630 /* RW-4R */ |
||
483 | #define NV_PGRAPH_BOFFSET1 0x00400634 /* RW-4R */ |
||
484 | #define NV_PGRAPH_BOFFSET2 0x00400638 /* RW-4R */ |
||
485 | #define NV_PGRAPH_BOFFSET3 0x0040063C /* RW-4R */ |
||
486 | #define NV_PGRAPH_BPITCH0 0x00400650 /* RW-4R */ |
||
487 | #define NV_PGRAPH_BPITCH1 0x00400654 /* RW-4R */ |
||
488 | #define NV_PGRAPH_BPITCH2 0x00400658 /* RW-4R */ |
||
489 | #define NV_PGRAPH_BPITCH3 0x0040065C /* RW-4R */ |
||
490 | |||
491 | #define NV_PGRAPH_BPIXEL 0x004006a8 /* RW-4R */ |
||
492 | #define NV_PGRAPH_BPIXEL_DEPTH0_FMT 1:0 /* RWXVF */ |
||
493 | #define NV_PGRAPH_BPIXEL_DEPTH0_FMT_Y16_BITS 0x00000000 /* RW--V */ |
||
494 | #define NV_PGRAPH_BPIXEL_DEPTH0_FMT_BITS_8 0x00000001 /* RW--V */ |
||
495 | #define NV_PGRAPH_BPIXEL_DEPTH0_FMT_BITS_16 0x00000002 /* RW--V */ |
||
496 | #define NV_PGRAPH_BPIXEL_DEPTH0_FMT_BITS_32 0x00000003 /* RW--V */ |
||
497 | #define NV_PGRAPH_BPIXEL_DEPTH0 2:2 /* RWXVF */ |
||
498 | #define NV_PGRAPH_BPIXEL_DEPTH0_NOT_VALID 0x00000000 /* RW--V */ |
||
499 | #define NV_PGRAPH_BPIXEL_DEPTH0_VALID 0x00000001 /* RW--V */ |
||
500 | #define NV_PGRAPH_BPIXEL_DEPTH1_FMT 5:4 /* RWXVF */ |
||
501 | #define NV_PGRAPH_BPIXEL_DEPTH1_FMT_Y16_BITS 0x00000000 /* RW--V */ |
||
502 | #define NV_PGRAPH_BPIXEL_DEPTH1_FMT_BITS_8 0x00000001 /* RW--V */ |
||
503 | #define NV_PGRAPH_BPIXEL_DEPTH1_FMT_BITS_16 0x00000002 /* RW--V */ |
||
504 | #define NV_PGRAPH_BPIXEL_DEPTH1_FMT_BITS_32 0x00000003 /* RW--V */ |
||
505 | #define NV_PGRAPH_BPIXEL_DEPTH1 6:6 /* RWXVF */ |
||
506 | #define NV_PGRAPH_BPIXEL_DEPTH1_NOT_VALID 0x00000000 /* RW--V */ |
||
507 | #define NV_PGRAPH_BPIXEL_DEPTH1_VALID 0x00000001 /* RW--V */ |
||
508 | #define NV_PGRAPH_BPIXEL_DEPTH2_FMT 9:8 /* RWXVF */ |
||
509 | #define NV_PGRAPH_BPIXEL_DEPTH2_FMT_Y16_BITS 0x00000000 /* RW--V */ |
||
510 | #define NV_PGRAPH_BPIXEL_DEPTH2_FMT_BITS_8 0x00000001 /* RW--V */ |
||
511 | #define NV_PGRAPH_BPIXEL_DEPTH2_FMT_BITS_16 0x00000002 /* RW--V */ |
||
512 | #define NV_PGRAPH_BPIXEL_DEPTH2_FMT_BITS_32 0x00000003 /* RW--V */ |
||
513 | #define NV_PGRAPH_BPIXEL_DEPTH2 10:10 /* RWXVF */ |
||
514 | #define NV_PGRAPH_BPIXEL_DEPTH2_NOT_VALID 0x00000000 /* RW--V */ |
||
515 | #define NV_PGRAPH_BPIXEL_DEPTH2_VALID 0x00000001 /* RW--V */ |
||
516 | #define NV_PGRAPH_BPIXEL_DEPTH3_FMT 13:12 /* RWXVF */ |
||
517 | #define NV_PGRAPH_BPIXEL_DEPTH3_FMT_Y16_BITS 0x00000000 /* RW--V */ |
||
518 | #define NV_PGRAPH_BPIXEL_DEPTH3_FMT_BITS_8 0x00000001 /* RW--V */ |
||
519 | #define NV_PGRAPH_BPIXEL_DEPTH3_FMT_BITS_16 0x00000002 /* RW--V */ |
||
520 | #define NV_PGRAPH_BPIXEL_DEPTH3_FMT_BITS_32 0x00000003 /* RW--V */ |
||
521 | #define NV_PGRAPH_BPIXEL_DEPTH3 14:14 /* RWXVF */ |
||
522 | #define NV_PGRAPH_BPIXEL_DEPTH3_NOT_VALID 0x00000000 /* RW--V */ |
||
523 | #define NV_PGRAPH_BPIXEL_DEPTH3_VALID 0x00000001 /* RW--V */ |
||
524 | |||
525 | #define NV_PGRAPH_PATT_COLOR0_0 0x00400600 /* RW-4R */ |
||
526 | #define NV_PGRAPH_PATT_COLOR0_1 0x00400604 /* RW-4R */ |
||
527 | #define NV_PGRAPH_PATT_COLOR1_0 0x00400608 /* RW-4R */ |
||
528 | #define NV_PGRAPH_PATT_COLOR1_1 0x0040060C /* RW-4R */ |
||
529 | #define NV_PGRAPH_PATTERN(i) (0x00400610+(i)*4) /* RW-4A */ |
||
530 | #define NV_PGRAPH_PATTERN_SHAPE 0x00400618 /* RW-4R */ |
||
531 | #define NV_PGRAPH_PATTERN_SHAPE_VALUE 1:0 /* RWXVF */ |
||
532 | #define NV_PGRAPH_PATTERN_SHAPE_VALUE_8X8 0x00000000 /* RW--V */ |
||
533 | #define NV_PGRAPH_PATTERN_SHAPE_VALUE_64X1 0x00000001 /* RW--V */ |
||
534 | #define NV_PGRAPH_PATTERN_SHAPE_VALUE_1X64 0x00000002 /* RW--V */ |
||
535 | #define NV_PGRAPH_MONO_COLOR0 0x0040061C /* RW-4R */ |
||
536 | #define NV_PGRAPH_ROP3 0x00400624 /* RW-4R */ |
||
537 | #define NV_PGRAPH_PLANE_MASK 0x00400628 /* RW-4R */ |
||
538 | #define NV_PGRAPH_CHROMA 0x0040062C /* RW-4R */ |
||
539 | #define NV_PGRAPH_BETA 0x00400640 /* RW-4R */ |
||
540 | #define NV_PGRAPH_CONTROL_OUT 0x00400644 /* RW-4R */ |
||
541 | #define NV_PGRAPH_ABS_X_RAM(i) (0x00400400+(i)*4) /* RW-4A */ |
||
542 | #define NV_PGRAPH_ABS_X_RAM__SIZE_1 32 /* */ |
||
543 | #define NV_PGRAPH_ABS_Y_RAM(i) (0x00400480+(i)*4) /* RW-4A */ |
||
544 | #define NV_PGRAPH_ABS_Y_RAM__SIZE_1 32 /* */ |
||
545 | |||
546 | #define NV_PGRAPH_XY_LOGIC_MISC0 0x00400514 /* RW-4R */ |
||
547 | #define NV_PGRAPH_XY_LOGIC_MISC1 0x00400518 /* RW-4R */ |
||
548 | #define NV_PGRAPH_XY_LOGIC_MISC2 0x0040051C /* RW-4R */ |
||
549 | #define NV_PGRAPH_XY_LOGIC_MISC1_DVDY_VALUE 0x00000000 /* RWI-V */ |
||
550 | #define NV_PGRAPH_XY_LOGIC_MISC3 0x00400520 /* RW-4R */ |
||
551 | #define NV_PGRAPH_X_MISC 0x00400500 /* RW-4R */ |
||
552 | #define NV_PGRAPH_Y_MISC 0x00400504 /* RW-4R */ |
||
553 | #define NV_PGRAPH_ABS_UCLIP_XMIN 0x0040053C /* RW-4R */ |
||
554 | #define NV_PGRAPH_ABS_UCLIP_XMAX 0x00400544 /* RW-4R */ |
||
555 | #define NV_PGRAPH_ABS_UCLIP_YMIN 0x00400540 /* RW-4R */ |
||
556 | #define NV_PGRAPH_ABS_UCLIP_YMAX 0x00400548 /* RW-4R */ |
||
557 | #define NV_PGRAPH_ABS_UCLIPA_XMIN 0x00400560 /* RW-4R */ |
||
558 | #define NV_PGRAPH_ABS_UCLIPA_XMAX 0x00400568 /* RW-4R */ |
||
559 | #define NV_PGRAPH_ABS_UCLIPA_YMIN 0x00400564 /* RW-4R */ |
||
560 | #define NV_PGRAPH_ABS_UCLIPA_YMAX 0x0040056C /* RW-4R */ |
||
561 | #define NV_PGRAPH_SOURCE_COLOR 0x0040050C /* RW-4R */ |
||
562 | #define NV_PGRAPH_EXCEPTIONS 0x00400508 /* RW-4R */ |
||
563 | #define NV_PGRAPH_ABS_ICLIP_XMAX 0x00400534 /* RW-4R */ |
||
564 | #define NV_PGRAPH_ABS_ICLIP_YMAX 0x00400538 /* RW-4R */ |
||
565 | #define NV_PGRAPH_CLIPX_0 0x00400524 /* RW-4R */ |
||
566 | #define NV_PGRAPH_CLIPX_1 0x00400528 /* RW-4R */ |
||
567 | #define NV_PGRAPH_CLIPY_0 0x0040052c /* RW-4R */ |
||
568 | #define NV_PGRAPH_CLIPY_1 0x00400530 /* RW-4R */ |
||
569 | #define NV_PGRAPH_DMA_INTR_0 0x00401100 /* RW-4R */ |
||
570 | #define NV_PGRAPH_DMA_INTR_0_INSTANCE 0:0 /* RWXVF */ |
||
571 | #define NV_PGRAPH_DMA_INTR_0_INSTANCE_NOT_PENDING 0x00000000 /* R---V */ |
||
572 | #define NV_PGRAPH_DMA_INTR_0_INSTANCE_PENDING 0x00000001 /* R---V */ |
||
573 | #define NV_PGRAPH_DMA_INTR_0_INSTANCE_RESET 0x00000001 /* -W--V */ |
||
574 | #define NV_PGRAPH_DMA_INTR_0_PRESENT 4:4 /* RWXVF */ |
||
575 | #define NV_PGRAPH_DMA_INTR_0_PRESENT_NOT_PENDING 0x00000000 /* R---V */ |
||
576 | #define NV_PGRAPH_DMA_INTR_0_PRESENT_PENDING 0x00000001 /* R---V */ |
||
577 | #define NV_PGRAPH_DMA_INTR_0_PRESENT_RESET 0x00000001 /* -W--V */ |
||
578 | #define NV_PGRAPH_DMA_INTR_0_PROTECTION 8:8 /* RWXVF */ |
||
579 | #define NV_PGRAPH_DMA_INTR_0_PROTECTION_NOT_PENDING 0x00000000 /* R---V */ |
||
580 | #define NV_PGRAPH_DMA_INTR_0_PROTECTION_PENDING 0x00000001 /* R---V */ |
||
581 | #define NV_PGRAPH_DMA_INTR_0_PROTECTION_RESET 0x00000001 /* -W--V */ |
||
582 | #define NV_PGRAPH_DMA_INTR_0_LINEAR 12:12 /* RWXVF */ |
||
583 | #define NV_PGRAPH_DMA_INTR_0_LINEAR_NOT_PENDING 0x00000000 /* R---V */ |
||
584 | #define NV_PGRAPH_DMA_INTR_0_LINEAR_PENDING 0x00000001 /* R---V */ |
||
585 | #define NV_PGRAPH_DMA_INTR_0_LINEAR_RESET 0x00000001 /* -W--V */ |
||
586 | #define NV_PGRAPH_DMA_INTR_0_NOTIFY 16:16 /* RWXVF */ |
||
587 | #define NV_PGRAPH_DMA_INTR_0_NOTIFY_NOT_PENDING 0x00000000 /* R---V */ |
||
588 | #define NV_PGRAPH_DMA_INTR_0_NOTIFY_PENDING 0x00000001 /* R---V */ |
||
589 | #define NV_PGRAPH_DMA_INTR_0_NOTIFY_RESET 0x00000001 /* -W--V */ |
||
590 | #define NV_PGRAPH_DMA_INTR_EN_0 0x00401140 /* RW-4R */ |
||
591 | #define NV_PGRAPH_DMA_CONTROL 0x00401210 /* RW-4R */ |
||
592 | |||
593 | #define NV_PFB 0x00100FFF:0x00100000 /* RW--D */ |
||
594 | #define NV_PFB_BOOT_0 0x00100000 /* RW-4R */ |
||
595 | #define NV_PFB_BOOT_0_RAM_AMOUNT 1:0 /* RWIVF */ |
||
596 | #define NV_PFB_BOOT_0_RAM_AMOUNT_1MB 0x00000000 /* RW--V */ |
||
597 | #define NV_PFB_BOOT_0_RAM_AMOUNT_2MB 0x00000001 /* RW--V */ |
||
598 | #define NV_PFB_BOOT_0_RAM_AMOUNT_4MB 0x00000002 /* RW--V */ |
||
599 | |||
600 | #define NV_PFB_CONFIG_0 0x00100200 /* RW-4R */ |
||
601 | #define NV_PFB_CONFIG_0_RESOLUTION 5:0 /* RWIVF */ |
||
602 | #define NV_PFB_CONFIG_0_RESOLUTION_320_PIXELS 0x0000000a /* RW--V */ |
||
603 | #define NV_PFB_CONFIG_0_RESOLUTION_400_PIXELS 0x0000000d /* RW--V */ |
||
604 | #define NV_PFB_CONFIG_0_RESOLUTION_480_PIXELS 0x0000000f /* RW--V */ |
||
605 | #define NV_PFB_CONFIG_0_RESOLUTION_512_PIXELS 0x00000010 /* RW--V */ |
||
606 | #define NV_PFB_CONFIG_0_RESOLUTION_640_PIXELS 0x00000014 /* RW--V */ |
||
607 | #define NV_PFB_CONFIG_0_RESOLUTION_800_PIXELS 0x00000019 /* RW--V */ |
||
608 | #define NV_PFB_CONFIG_0_RESOLUTION_960_PIXELS 0x0000001e /* RW--V */ |
||
609 | #define NV_PFB_CONFIG_0_RESOLUTION_1024_PIXELS 0x00000020 /* RW--V */ |
||
610 | #define NV_PFB_CONFIG_0_RESOLUTION_1152_PIXELS 0x00000024 /* RW--V */ |
||
611 | #define NV_PFB_CONFIG_0_RESOLUTION_1280_PIXELS 0x00000028 /* RW--V */ |
||
612 | #define NV_PFB_CONFIG_0_RESOLUTION_1600_PIXELS 0x00000032 /* RW--V */ |
||
613 | #define NV_PFB_CONFIG_0_RESOLUTION_DEFAULT 0x00000014 /* RWI-V */ |
||
614 | #define NV_PFB_CONFIG_0_PIXEL_DEPTH 9:8 /* RWIVF */ |
||
615 | #define NV_PFB_CONFIG_0_PIXEL_DEPTH_8_BITS 0x00000001 /* RW--V */ |
||
616 | #define NV_PFB_CONFIG_0_PIXEL_DEPTH_16_BITS 0x00000002 /* RW--V */ |
||
617 | #define NV_PFB_CONFIG_0_PIXEL_DEPTH_32_BITS 0x00000003 /* RW--V */ |
||
618 | #define NV_PFB_CONFIG_0_PIXEL_DEPTH_DEFAULT 0x00000001 /* RWI-V */ |
||
619 | #define NV_PFB_CONFIG_0_TILING 12:12 /* RWIVF */ |
||
620 | #define NV_PFB_CONFIG_0_TILING_ENABLED 0x00000000 /* RW--V */ |
||
621 | #define NV_PFB_CONFIG_0_TILING_DISABLED 0x00000001 /* RWI-V */ |
||
622 | |||
623 | #define NV_PFB_BOOT_10 0x0010020C /* RW-4R */ |
||
624 | |||
625 | |||
626 | #define NV_PRAMIN 0x00FFFFFF:0x00C00000 |
||
627 | #define NV_PNVM 0x00BFFFFF:0x00800000 |
||
628 | #define NV_CHAN0 0x0080ffff:0x00800000 |
||
629 | |||
630 | #define NV_UROP 0x00421FFF:0x00420000 /* -W--D */ |
||
631 | #define NV_UCHROMA 0x00431FFF:0x00430000 /* -W--D */ |
||
632 | #define NV_UPLANE 0x00441FFF:0x00440000 /* -W--D */ |
||
633 | #define NV_UCLIP 0x00451FFF:0x00450000 /* -W--D */ |
||
634 | #define NV_UPATT 0x00461FFF:0x00460000 /* -W--D */ |
||
635 | #define NV_ULINE 0x00491FFF:0x00490000 /* -W--D */ |
||
636 | #define NV_ULIN 0x004A1FFF:0x004A0000 /* -W--D */ |
||
637 | #define NV_UTRI 0x004B1FFF:0x004B0000 /* -W--D */ |
||
638 | #define NV_URECT 0x00471FFF:0x00470000 /* -W--D */ |
||
639 | #define NV_UBLIT 0x00501FFF:0x00500000 /* -W--D */ |
||
640 | #define NV_UBITMAP 0x00521FFF:0x00520000 /* -W--D */ |
||
641 | |||
642 | #define NV_PVGA0 0x000C0000 |
||
643 | #define NV_PVGA1 0x00601000 |
||
644 | #define NV_PVGA2 0x00681000 |
||
645 | |||
646 | #endif |