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74 | giacomo | 1 | /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/r128_reg.h,v 1.6 2000/12/12 17:17:13 dawes Exp $ */ |
2 | /* |
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3 | * Copyright 1999, 2000 ATI Technologies Inc., Markham, Ontario, |
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4 | * Precision Insight, Inc., Cedar Park, Texas, and |
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5 | * VA Linux Systems Inc., Fremont, California. |
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6 | * |
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7 | * All Rights Reserved. |
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8 | * |
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9 | * Permission is hereby granted, free of charge, to any person obtaining |
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10 | * a copy of this software and associated documentation files (the |
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11 | * "Software"), to deal in the Software without restriction, including |
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12 | * without limitation on the rights to use, copy, modify, merge, |
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13 | * publish, distribute, sublicense, and/or sell copies of the Software, |
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14 | * and to permit persons to whom the Software is furnished to do so, |
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15 | * subject to the following conditions: |
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16 | * |
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17 | * The above copyright notice and this permission notice (including the |
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18 | * next paragraph) shall be included in all copies or substantial |
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19 | * portions of the Software. |
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20 | * |
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21 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
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22 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
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23 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
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24 | * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, PRECISION INSIGHT, VA LINUX |
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25 | * SYSTEMS AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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26 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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27 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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28 | * OTHER DEALINGS IN THE SOFTWARE. |
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29 | */ |
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30 | |||
31 | /* |
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32 | * Authors: |
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33 | * Rickard E. Faith <faith@valinux.com> |
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34 | * Kevin E. Martin <martin@valinux.com> |
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35 | * Gareth Hughes <gareth@valinux.com> |
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36 | * |
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37 | * References: |
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38 | * |
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39 | * RAGE 128 VR/ RAGE 128 GL Register Reference Manual (Technical |
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40 | * Reference Manual P/N RRG-G04100-C Rev. 0.04), ATI Technologies: April |
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41 | * 1999. |
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42 | * |
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43 | * RAGE 128 Software Development Manual (Technical Reference Manual P/N |
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44 | * SDK-G04000 Rev. 0.01), ATI Technologies: June 1999. |
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45 | * |
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46 | */ |
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47 | |||
48 | #ifndef _R128_REG_H_ |
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49 | #define _R128_REG_H_ |
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50 | |||
51 | #define R128_TIMEOUT 2000000 |
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52 | |||
53 | #define MMIO_IN8(dummy, addr) v_readb(addr) |
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54 | #define MMIO_IN16(dummy, addr) v_readw(addr) |
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55 | #define MMIO_IN32(dummy, addr) LE32(v_readl(addr)) |
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56 | |||
57 | #define MMIO_OUT8(dummy, addr, val) v_writeb(val, addr) |
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58 | #define MMIO_OUT16(dummy, addr, val) v_writew(val, addr) |
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59 | #define MMIO_OUT32(dummy, addr, val) v_writel(LE32(val), addr) |
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60 | |||
61 | /* Memory mapped register access macros */ |
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62 | #define INREG8(addr) MMIO_IN8(R128MMIO, addr) |
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63 | #define INREG16(addr) MMIO_IN16(R128MMIO, addr) |
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64 | #define INREG(addr) MMIO_IN32(R128MMIO, addr) |
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65 | #define OUTREG8(addr, val) MMIO_OUT8(R128MMIO, addr, val) |
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66 | #define OUTREG16(addr, val) MMIO_OUT16(R128MMIO, addr, val) |
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67 | #define OUTREG(addr, val) MMIO_OUT32(R128MMIO, addr, val) |
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68 | |||
69 | #if 0 |
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70 | #define R128_BIOS8(v) (VBIOS[v]) |
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71 | #define R128_BIOS16(v) (VBIOS[v] | \ |
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72 | (VBIOS[(v) + 1] << 8)) |
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73 | #define R128_BIOS32(v) (VBIOS[v] | \ |
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74 | (VBIOS[(v) + 1] << 8) | \ |
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75 | (VBIOS[(v) + 2] << 16) | \ |
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76 | (VBIOS[(v) + 3] << 24)) |
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77 | #endif |
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78 | |||
79 | #define OUTREGP(addr, val, mask) \ |
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80 | do { \ |
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81 | uint32_t tmp = INREG(addr); \ |
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82 | tmp &= (mask); \ |
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83 | tmp |= (val); \ |
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84 | OUTREG(addr, tmp); \ |
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85 | } while (0) |
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86 | |||
87 | #define INPLL(addr) R128INPLL(addr) |
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88 | |||
89 | #define OUTPLL(addr, val) \ |
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90 | do { \ |
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91 | OUTREG8(R128_CLOCK_CNTL_INDEX, ((addr) & 0x1f) | R128_PLL_WR_EN); \ |
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92 | OUTREG(R128_CLOCK_CNTL_DATA, val); \ |
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93 | } while (0) |
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94 | |||
95 | #define OUTPLLP(addr, val, mask) \ |
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96 | do { \ |
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97 | uint32_t tmp = INPLL(addr); \ |
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98 | tmp &= (mask); \ |
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99 | tmp |= (val); \ |
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100 | OUTPLL(addr, tmp); \ |
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101 | } while (0) |
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102 | |||
103 | #define OUTPAL_START(idx) \ |
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104 | do { \ |
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105 | OUTREG8(R128_PALETTE_INDEX, (idx)); \ |
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106 | } while (0) |
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107 | |||
108 | #define OUTPAL_NEXT(r, g, b) \ |
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109 | do { \ |
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110 | OUTREG(R128_PALETTE_DATA, ((r) << 16) | ((g) << 8) | (b)); \ |
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111 | } while (0) |
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112 | |||
113 | #define OUTPAL_NEXT_uint32_t(v) \ |
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114 | do { \ |
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115 | OUTREG(R128_PALETTE_DATA, (v & 0x00ffffff)); \ |
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116 | } while (0) |
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117 | |||
118 | #define OUTPAL(idx, r, g, b) \ |
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119 | do { \ |
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120 | OUTPAL_START((idx)); \ |
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121 | OUTPAL_NEXT((r), (g), (b)); \ |
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122 | } while (0) |
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123 | |||
124 | #define INPAL_START(idx) \ |
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125 | do { \ |
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126 | OUTREG(R128_PALETTE_INDEX, (idx) << 16); \ |
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127 | } while (0) |
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128 | |||
129 | #define INPAL_NEXT() INREG(R128_PALETTE_DATA) |
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130 | |||
131 | #define PAL_SELECT(idx) \ |
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132 | do { \ |
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133 | if (idx) { \ |
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134 | OUTREG(R128_DAC_CNTL, INREG(R128_DAC_CNTL) | \ |
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135 | R128_DAC_PALETTE_ACC_CTL); \ |
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136 | } else { \ |
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137 | OUTREG(R128_DAC_CNTL, INREG(R128_DAC_CNTL) & \ |
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138 | ~R128_DAC_PALETTE_ACC_CTL); \ |
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139 | } \ |
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140 | } while (0) |
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141 | |||
142 | #define R128_ADAPTER_ID 0x0f2c /* PCI */ |
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143 | #define R128_AGP_APER_OFFSET 0x0178 |
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144 | #define R128_AGP_BASE 0x0170 |
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145 | #define R128_AGP_CNTL 0x0174 |
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146 | # define R128_AGP_APER_SIZE_256MB (0x00 << 0) |
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147 | # define R128_AGP_APER_SIZE_128MB (0x20 << 0) |
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148 | # define R128_AGP_APER_SIZE_64MB (0x30 << 0) |
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149 | # define R128_AGP_APER_SIZE_32MB (0x38 << 0) |
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150 | # define R128_AGP_APER_SIZE_16MB (0x3c << 0) |
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151 | # define R128_AGP_APER_SIZE_8MB (0x3e << 0) |
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152 | # define R128_AGP_APER_SIZE_4MB (0x3f << 0) |
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153 | # define R128_AGP_APER_SIZE_MASK (0x3f << 0) |
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154 | #define R128_AGP_CNTL_B 0x0b44 |
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155 | #define R128_AGP_COMMAND 0x0f58 /* PCI */ |
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156 | #define R128_AGP_PLL_CNTL 0x0010 /* PLL */ |
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157 | #define R128_AGP_STATUS 0x0f54 /* PCI */ |
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158 | # define R128_AGP_1X_MODE 0x01 |
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159 | # define R128_AGP_2X_MODE 0x02 |
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160 | # define R128_AGP_4X_MODE 0x04 |
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161 | # define R128_AGP_MODE_MASK 0x07 |
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162 | #define R128_AMCGPIO_A_REG 0x01a0 |
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163 | #define R128_AMCGPIO_EN_REG 0x01a8 |
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164 | #define R128_AMCGPIO_MASK 0x0194 |
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165 | #define R128_AMCGPIO_Y_REG 0x01a4 |
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166 | #define R128_ATTRDR 0x03c1 /* VGA */ |
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167 | #define R128_ATTRDW 0x03c0 /* VGA */ |
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168 | #define R128_ATTRX 0x03c0 /* VGA */ |
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169 | #define R128_AUX_SC_CNTL 0x1660 |
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170 | # define R128_AUX1_SC_EN (1 << 0) |
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171 | # define R128_AUX1_SC_MODE_OR (0 << 1) |
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172 | # define R128_AUX1_SC_MODE_NAND (1 << 1) |
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173 | # define R128_AUX2_SC_EN (1 << 2) |
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174 | # define R128_AUX2_SC_MODE_OR (0 << 3) |
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175 | # define R128_AUX2_SC_MODE_NAND (1 << 3) |
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176 | # define R128_AUX3_SC_EN (1 << 4) |
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177 | # define R128_AUX3_SC_MODE_OR (0 << 5) |
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178 | # define R128_AUX3_SC_MODE_NAND (1 << 5) |
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179 | #define R128_AUX1_SC_BOTTOM 0x1670 |
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180 | #define R128_AUX1_SC_LEFT 0x1664 |
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181 | #define R128_AUX1_SC_RIGHT 0x1668 |
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182 | #define R128_AUX1_SC_TOP 0x166c |
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183 | #define R128_AUX2_SC_BOTTOM 0x1680 |
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184 | #define R128_AUX2_SC_LEFT 0x1674 |
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185 | #define R128_AUX2_SC_RIGHT 0x1678 |
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186 | #define R128_AUX2_SC_TOP 0x167c |
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187 | #define R128_AUX3_SC_BOTTOM 0x1690 |
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188 | #define R128_AUX3_SC_LEFT 0x1684 |
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189 | #define R128_AUX3_SC_RIGHT 0x1688 |
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190 | #define R128_AUX3_SC_TOP 0x168c |
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191 | #define R128_AUX_WINDOW_HORZ_CNTL 0x02d8 |
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192 | #define R128_AUX_WINDOW_VERT_CNTL 0x02dc |
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193 | |||
194 | #define R128_BASE_CODE 0x0f0b |
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195 | #define R128_BIOS_0_SCRATCH 0x0010 |
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196 | #define R128_BIOS_1_SCRATCH 0x0014 |
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197 | #define R128_BIOS_2_SCRATCH 0x0018 |
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198 | #define R128_BIOS_3_SCRATCH 0x001c |
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199 | #define R128_BIOS_ROM 0x0f30 /* PCI */ |
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200 | #define R128_BIST 0x0f0f /* PCI */ |
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201 | #define R128_BRUSH_DATA0 0x1480 |
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202 | #define R128_BRUSH_DATA1 0x1484 |
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203 | #define R128_BRUSH_DATA10 0x14a8 |
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204 | #define R128_BRUSH_DATA11 0x14ac |
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205 | #define R128_BRUSH_DATA12 0x14b0 |
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206 | #define R128_BRUSH_DATA13 0x14b4 |
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207 | #define R128_BRUSH_DATA14 0x14b8 |
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208 | #define R128_BRUSH_DATA15 0x14bc |
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209 | #define R128_BRUSH_DATA16 0x14c0 |
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210 | #define R128_BRUSH_DATA17 0x14c4 |
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211 | #define R128_BRUSH_DATA18 0x14c8 |
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212 | #define R128_BRUSH_DATA19 0x14cc |
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213 | #define R128_BRUSH_DATA2 0x1488 |
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214 | #define R128_BRUSH_DATA20 0x14d0 |
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215 | #define R128_BRUSH_DATA21 0x14d4 |
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216 | #define R128_BRUSH_DATA22 0x14d8 |
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217 | #define R128_BRUSH_DATA23 0x14dc |
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218 | #define R128_BRUSH_DATA24 0x14e0 |
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219 | #define R128_BRUSH_DATA25 0x14e4 |
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220 | #define R128_BRUSH_DATA26 0x14e8 |
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221 | #define R128_BRUSH_DATA27 0x14ec |
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222 | #define R128_BRUSH_DATA28 0x14f0 |
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223 | #define R128_BRUSH_DATA29 0x14f4 |
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224 | #define R128_BRUSH_DATA3 0x148c |
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225 | #define R128_BRUSH_DATA30 0x14f8 |
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226 | #define R128_BRUSH_DATA31 0x14fc |
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227 | #define R128_BRUSH_DATA32 0x1500 |
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228 | #define R128_BRUSH_DATA33 0x1504 |
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229 | #define R128_BRUSH_DATA34 0x1508 |
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230 | #define R128_BRUSH_DATA35 0x150c |
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231 | #define R128_BRUSH_DATA36 0x1510 |
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232 | #define R128_BRUSH_DATA37 0x1514 |
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233 | #define R128_BRUSH_DATA38 0x1518 |
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234 | #define R128_BRUSH_DATA39 0x151c |
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235 | #define R128_BRUSH_DATA4 0x1490 |
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236 | #define R128_BRUSH_DATA40 0x1520 |
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237 | #define R128_BRUSH_DATA41 0x1524 |
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238 | #define R128_BRUSH_DATA42 0x1528 |
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239 | #define R128_BRUSH_DATA43 0x152c |
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240 | #define R128_BRUSH_DATA44 0x1530 |
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241 | #define R128_BRUSH_DATA45 0x1534 |
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242 | #define R128_BRUSH_DATA46 0x1538 |
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243 | #define R128_BRUSH_DATA47 0x153c |
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244 | #define R128_BRUSH_DATA48 0x1540 |
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245 | #define R128_BRUSH_DATA49 0x1544 |
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246 | #define R128_BRUSH_DATA5 0x1494 |
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247 | #define R128_BRUSH_DATA50 0x1548 |
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248 | #define R128_BRUSH_DATA51 0x154c |
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249 | #define R128_BRUSH_DATA52 0x1550 |
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250 | #define R128_BRUSH_DATA53 0x1554 |
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251 | #define R128_BRUSH_DATA54 0x1558 |
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252 | #define R128_BRUSH_DATA55 0x155c |
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253 | #define R128_BRUSH_DATA56 0x1560 |
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254 | #define R128_BRUSH_DATA57 0x1564 |
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255 | #define R128_BRUSH_DATA58 0x1568 |
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256 | #define R128_BRUSH_DATA59 0x156c |
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257 | #define R128_BRUSH_DATA6 0x1498 |
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258 | #define R128_BRUSH_DATA60 0x1570 |
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259 | #define R128_BRUSH_DATA61 0x1574 |
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260 | #define R128_BRUSH_DATA62 0x1578 |
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261 | #define R128_BRUSH_DATA63 0x157c |
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262 | #define R128_BRUSH_DATA7 0x149c |
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263 | #define R128_BRUSH_DATA8 0x14a0 |
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264 | #define R128_BRUSH_DATA9 0x14a4 |
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265 | #define R128_BRUSH_SCALE 0x1470 |
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266 | #define R128_BRUSH_Y_X 0x1474 |
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267 | #define R128_BUS_CNTL 0x0030 |
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268 | # define R128_BUS_MASTER_DIS (1 << 6) |
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269 | # define R128_BUS_RD_DISCARD_EN (1 << 24) |
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270 | # define R128_BUS_RD_ABORT_EN (1 << 25) |
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271 | # define R128_BUS_MSTR_DISCONNECT_EN (1 << 28) |
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272 | # define R128_BUS_WRT_BURST (1 << 29) |
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273 | # define R128_BUS_READ_BURST (1 << 30) |
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274 | #define R128_BUS_CNTL1 0x0034 |
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275 | # define R128_BUS_WAIT_ON_LOCK_EN (1 << 4) |
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276 | |||
277 | #define R128_CACHE_CNTL 0x1724 |
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278 | #define R128_CACHE_LINE 0x0f0c /* PCI */ |
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279 | #define R128_CAP0_TRIG_CNTL 0x0950 /* ? */ |
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280 | #define R128_CAP1_TRIG_CNTL 0x09c0 /* ? */ |
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281 | #define R128_CAPABILITIES_ID 0x0f50 /* PCI */ |
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282 | #define R128_CAPABILITIES_PTR 0x0f34 /* PCI */ |
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283 | #define R128_CLK_PIN_CNTL 0x0001 /* PLL */ |
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284 | #define R128_CLOCK_CNTL_DATA 0x000c |
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285 | #define R128_CLOCK_CNTL_INDEX 0x0008 |
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286 | # define R128_PLL_WR_EN (1 << 7) |
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287 | # define R128_PLL_DIV_SEL (3 << 8) |
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288 | #define R128_CLR_CMP_CLR_3D 0x1a24 |
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289 | #define R128_CLR_CMP_CLR_DST 0x15c8 |
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290 | #define R128_CLR_CMP_CLR_SRC 0x15c4 |
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291 | #define R128_CLR_CMP_CNTL 0x15c0 |
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292 | # define R128_SRC_CMP_EQ_COLOR (4 << 0) |
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293 | # define R128_SRC_CMP_NEQ_COLOR (5 << 0) |
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294 | # define R128_CLR_CMP_SRC_SOURCE (1 << 24) |
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295 | #define R128_CLR_CMP_MASK 0x15cc |
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296 | # define R128_CLR_CMP_MSK 0xffffffff |
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297 | #define R128_CLR_CMP_MASK_3D 0x1A28 |
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298 | #define R128_COMMAND 0x0f04 /* PCI */ |
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299 | #define R128_COMPOSITE_SHADOW_ID 0x1a0c |
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300 | #define R128_CONFIG_APER_0_BASE 0x0100 |
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301 | #define R128_CONFIG_APER_1_BASE 0x0104 |
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302 | #define R128_CONFIG_APER_SIZE 0x0108 |
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303 | #define R128_CONFIG_BONDS 0x00e8 |
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304 | #define R128_CONFIG_CNTL 0x00e0 |
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305 | # define APER_0_BIG_ENDIAN_16BPP_SWAP (1 << 0) |
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306 | # define APER_0_BIG_ENDIAN_32BPP_SWAP (2 << 0) |
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307 | # define R128_CFG_VGA_RAM_EN (1 << 8) |
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308 | #define R128_CONFIG_MEMSIZE 0x00f8 |
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309 | #define R128_CONFIG_MEMSIZE_EMBEDDED 0x0114 |
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310 | #define R128_CONFIG_REG_1_BASE 0x010c |
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311 | #define R128_CONFIG_REG_APER_SIZE 0x0110 |
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312 | #define R128_CONFIG_XSTRAP 0x00e4 |
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313 | #define R128_CONSTANT_COLOR_C 0x1d34 |
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314 | # define R128_CONSTANT_COLOR_MASK 0x00ffffff |
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315 | # define R128_CONSTANT_COLOR_ONE 0x00ffffff |
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316 | # define R128_CONSTANT_COLOR_ZERO 0x00000000 |
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317 | #define R128_CRC_CMDFIFO_ADDR 0x0740 |
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318 | #define R128_CRC_CMDFIFO_DOUT 0x0744 |
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319 | #define R128_CRTC_CRNT_FRAME 0x0214 |
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320 | #define R128_CRTC_DEBUG 0x021c |
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321 | #define R128_CRTC_EXT_CNTL 0x0054 |
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322 | # define R128_CRTC_VGA_XOVERSCAN (1 << 0) |
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323 | # define R128_VGA_ATI_LINEAR (1 << 3) |
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324 | # define R128_XCRT_CNT_EN (1 << 6) |
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325 | # define R128_CRTC_HSYNC_DIS (1 << 8) |
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326 | # define R128_CRTC_VSYNC_DIS (1 << 9) |
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327 | # define R128_CRTC_DISPLAY_DIS (1 << 10) |
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328 | # define R128_CRTC_CRT_ON (1 << 15) |
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329 | # define R128_VGA_MEM_PS_EN (1 << 19) |
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330 | #define R128_CRTC_EXT_CNTL_DPMS_BYTE 0x0055 |
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331 | # define R128_CRTC_HSYNC_DIS_BYTE (1 << 0) |
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332 | # define R128_CRTC_VSYNC_DIS_BYTE (1 << 1) |
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333 | # define R128_CRTC_DISPLAY_DIS_BYTE (1 << 2) |
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334 | #define R128_CRTC_GEN_CNTL 0x0050 |
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335 | # define R128_CRTC_DBL_SCAN_EN (1 << 0) |
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336 | # define R128_CRTC_INTERLACE_EN (1 << 1) |
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337 | # define R128_CRTC_CSYNC_EN (1 << 4) |
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338 | # define R128_CRTC_CUR_EN (1 << 16) |
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339 | # define R128_CRTC_CUR_MODE_MASK (7 << 17) |
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340 | # define R128_CRTC_ICON_EN (1 << 20) |
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341 | # define R128_CRTC_EXT_DISP_EN (1 << 24) |
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342 | # define R128_CRTC_EN (1 << 25) |
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343 | # define R128_CRTC_DISP_REQ_EN_B (1 << 26) |
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344 | #define R128_CRTC_GUI_TRIG_VLINE 0x0218 |
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345 | #define R128_CRTC_H_SYNC_STRT_WID 0x0204 |
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346 | # define R128_CRTC_H_SYNC_STRT_PIX (0x07 << 0) |
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347 | # define R128_CRTC_H_SYNC_STRT_CHAR (0x1ff << 3) |
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348 | # define R128_CRTC_H_SYNC_STRT_CHAR_SHIFT 3 |
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349 | # define R128_CRTC_H_SYNC_WID (0x3f << 16) |
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350 | # define R128_CRTC_H_SYNC_WID_SHIFT 16 |
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351 | # define R128_CRTC_H_SYNC_POL (1 << 23) |
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352 | #define R128_CRTC_H_TOTAL_DISP 0x0200 |
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353 | # define R128_CRTC_H_TOTAL (0x01ff << 0) |
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354 | # define R128_CRTC_H_TOTAL_SHIFT 0 |
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355 | # define R128_CRTC_H_DISP (0x00ff << 16) |
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356 | # define R128_CRTC_H_DISP_SHIFT 16 |
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357 | #define R128_CRTC_OFFSET 0x0224 |
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358 | #define R128_CRTC_OFFSET_CNTL 0x0228 |
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359 | #define R128_CRTC_PITCH 0x022c |
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360 | #define R128_CRTC_STATUS 0x005c |
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361 | # define R128_CRTC_VBLANK_SAVE (1 << 1) |
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362 | #define R128_CRTC_V_SYNC_STRT_WID 0x020c |
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363 | # define R128_CRTC_V_SYNC_STRT (0x7ff << 0) |
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364 | # define R128_CRTC_V_SYNC_STRT_SHIFT 0 |
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365 | # define R128_CRTC_V_SYNC_WID (0x1f << 16) |
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366 | # define R128_CRTC_V_SYNC_WID_SHIFT 16 |
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367 | # define R128_CRTC_V_SYNC_POL (1 << 23) |
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368 | #define R128_CRTC_V_TOTAL_DISP 0x0208 |
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369 | # define R128_CRTC_V_TOTAL (0x07ff << 0) |
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370 | # define R128_CRTC_V_TOTAL_SHIFT 0 |
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371 | # define R128_CRTC_V_DISP (0x07ff << 16) |
||
372 | # define R128_CRTC_V_DISP_SHIFT 16 |
||
373 | #define R128_CRTC_VLINE_CRNT_VLINE 0x0210 |
||
374 | # define R128_CRTC_CRNT_VLINE_MASK (0x7ff << 16) |
||
375 | #define R128_CRTC2_CRNT_FRAME 0x0314 |
||
376 | #define R128_CRTC2_DEBUG 0x031c |
||
377 | #define R128_CRTC2_GEN_CNTL 0x03f8 |
||
378 | #define R128_CRTC2_GUI_TRIG_VLINE 0x0318 |
||
379 | #define R128_CRTC2_H_SYNC_STRT_WID 0x0304 |
||
380 | #define R128_CRTC2_H_TOTAL_DISP 0x0300 |
||
381 | #define R128_CRTC2_OFFSET 0x0324 |
||
382 | #define R128_CRTC2_OFFSET_CNTL 0x0328 |
||
383 | #define R128_CRTC2_PITCH 0x032c |
||
384 | #define R128_CRTC2_STATUS 0x03fc |
||
385 | #define R128_CRTC2_V_SYNC_STRT_WID 0x030c |
||
386 | #define R128_CRTC2_V_TOTAL_DISP 0x0308 |
||
387 | #define R128_CRTC2_VLINE_CRNT_VLINE 0x0310 |
||
388 | #define R128_CRTC8_DATA 0x03d5 /* VGA, 0x3b5 */ |
||
389 | #define R128_CRTC8_IDX 0x03d4 /* VGA, 0x3b4 */ |
||
390 | #define R128_CUR_CLR0 0x026c |
||
391 | #define R128_CUR_CLR1 0x0270 |
||
392 | #define R128_CUR_HORZ_VERT_OFF 0x0268 |
||
393 | #define R128_CUR_HORZ_VERT_POSN 0x0264 |
||
394 | #define R128_CUR_OFFSET 0x0260 |
||
395 | # define R128_CUR_LOCK (1 << 31) |
||
396 | |||
397 | #define R128_DAC_CNTL 0x0058 |
||
398 | # define R128_DAC_RANGE_CNTL (3 << 0) |
||
399 | # define R128_DAC_BLANKING (1 << 2) |
||
400 | # define R128_DAC_CRT_SEL_CRTC2 (1 << 4) |
||
401 | # define R128_DAC_PALETTE_ACC_CTL (1 << 5) |
||
402 | # define R128_DAC_8BIT_EN (1 << 8) |
||
403 | # define R128_DAC_VGA_ADR_EN (1 << 13) |
||
404 | # define R128_DAC_MASK_ALL (0xff << 24) |
||
405 | #define R128_DAC_CRC_SIG 0x02cc |
||
406 | #define R128_DAC_DATA 0x03c9 /* VGA */ |
||
407 | #define R128_DAC_MASK 0x03c6 /* VGA */ |
||
408 | #define R128_DAC_R_INDEX 0x03c7 /* VGA */ |
||
409 | #define R128_DAC_W_INDEX 0x03c8 /* VGA */ |
||
410 | #define R128_DDA_CONFIG 0x02e0 |
||
411 | #define R128_DDA_ON_OFF 0x02e4 |
||
412 | #define R128_DEFAULT_OFFSET 0x16e0 |
||
413 | #define R128_DEFAULT_PITCH 0x16e4 |
||
414 | #define R128_DEFAULT_SC_BOTTOM_RIGHT 0x16e8 |
||
415 | # define R128_DEFAULT_SC_RIGHT_MAX (0x1fff << 0) |
||
416 | # define R128_DEFAULT_SC_BOTTOM_MAX (0x1fff << 16) |
||
417 | #define R128_DESTINATION_3D_CLR_CMP_VAL 0x1820 |
||
418 | #define R128_DESTINATION_3D_CLR_CMP_MSK 0x1824 |
||
419 | #define R128_DEVICE_ID 0x0f02 /* PCI */ |
||
420 | #define R128_DP_BRUSH_BKGD_CLR 0x1478 |
||
421 | #define R128_DP_BRUSH_FRGD_CLR 0x147c |
||
422 | #define R128_DP_CNTL 0x16c0 |
||
423 | # define R128_DST_X_LEFT_TO_RIGHT (1 << 0) |
||
424 | # define R128_DST_Y_TOP_TO_BOTTOM (1 << 1) |
||
425 | #define R128_DP_CNTL_XDIR_YDIR_YMAJOR 0x16d0 |
||
426 | # define R128_DST_Y_MAJOR (1 << 2) |
||
427 | # define R128_DST_Y_DIR_TOP_TO_BOTTOM (1 << 15) |
||
428 | # define R128_DST_X_DIR_LEFT_TO_RIGHT (1 << 31) |
||
429 | #define R128_DP_DATATYPE 0x16c4 |
||
430 | # define R128_HOST_BIG_ENDIAN_EN (1 << 29) |
||
431 | #define R128_DP_GUI_MASTER_CNTL 0x146c |
||
432 | # define R128_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0) |
||
433 | # define R128_GMC_DST_PITCH_OFFSET_CNTL (1 << 1) |
||
434 | # define R128_GMC_SRC_CLIPPING (1 << 2) |
||
435 | # define R128_GMC_DST_CLIPPING (1 << 3) |
||
436 | # define R128_GMC_BRUSH_DATATYPE_MASK (0x0f << 4) |
||
437 | # define R128_GMC_BRUSH_8X8_MONO_FG_BG (0 << 4) |
||
438 | # define R128_GMC_BRUSH_8X8_MONO_FG_LA (1 << 4) |
||
439 | # define R128_GMC_BRUSH_1X8_MONO_FG_BG (4 << 4) |
||
440 | # define R128_GMC_BRUSH_1X8_MONO_FG_LA (5 << 4) |
||
441 | # define R128_GMC_BRUSH_32x1_MONO_FG_BG (6 << 4) |
||
442 | # define R128_GMC_BRUSH_32x1_MONO_FG_LA (7 << 4) |
||
443 | # define R128_GMC_BRUSH_32x32_MONO_FG_BG (8 << 4) |
||
444 | # define R128_GMC_BRUSH_32x32_MONO_FG_LA (9 << 4) |
||
445 | # define R128_GMC_BRUSH_8x8_COLOR (10 << 4) |
||
446 | # define R128_GMC_BRUSH_1X8_COLOR (12 << 4) |
||
447 | # define R128_GMC_BRUSH_SOLID_COLOR (13 << 4) |
||
448 | # define R128_GMC_BRUSH_NONE (15 << 4) |
||
449 | # define R128_GMC_DST_8BPP_CI (2 << 8) |
||
450 | # define R128_GMC_DST_15BPP (3 << 8) |
||
451 | # define R128_GMC_DST_16BPP (4 << 8) |
||
452 | # define R128_GMC_DST_24BPP (5 << 8) |
||
453 | # define R128_GMC_DST_32BPP (6 << 8) |
||
454 | # define R128_GMC_DST_8BPP_RGB (7 << 8) |
||
455 | # define R128_GMC_DST_Y8 (8 << 8) |
||
456 | # define R128_GMC_DST_RGB8 (9 << 8) |
||
457 | # define R128_GMC_DST_VYUY (11 << 8) |
||
458 | # define R128_GMC_DST_YVYU (12 << 8) |
||
459 | # define R128_GMC_DST_AYUV444 (14 << 8) |
||
460 | # define R128_GMC_DST_ARGB4444 (15 << 8) |
||
461 | # define R128_GMC_DST_DATATYPE_MASK (0x0f << 8) |
||
462 | # define R128_GMC_DST_DATATYPE_SHIFT 8 |
||
463 | # define R128_GMC_SRC_DATATYPE_MASK (3 << 12) |
||
464 | # define R128_GMC_SRC_DATATYPE_MONO_FG_BG (0 << 12) |
||
465 | # define R128_GMC_SRC_DATATYPE_MONO_FG_LA (1 << 12) |
||
466 | # define R128_GMC_SRC_DATATYPE_COLOR (3 << 12) |
||
467 | # define R128_GMC_BYTE_PIX_ORDER (1 << 14) |
||
468 | # define R128_GMC_BYTE_MSB_TO_LSB (0 << 14) |
||
469 | # define R128_GMC_BYTE_LSB_TO_MSB (1 << 14) |
||
470 | # define R128_GMC_CONVERSION_TEMP (1 << 15) |
||
471 | # define R128_GMC_CONVERSION_TEMP_6500 (0 << 15) |
||
472 | # define R128_GMC_CONVERSION_TEMP_9300 (1 << 15) |
||
473 | # define R128_GMC_ROP3_MASK (0xff << 16) |
||
474 | # define R128_DP_SRC_SOURCE_MASK (7 << 24) |
||
475 | # define R128_DP_SRC_SOURCE_MEMORY (2 << 24) |
||
476 | # define R128_DP_SRC_SOURCE_HOST_DATA (3 << 24) |
||
477 | # define R128_GMC_3D_FCN_EN (1 << 27) |
||
478 | # define R128_GMC_CLR_CMP_CNTL_DIS (1 << 28) |
||
479 | # define R128_GMC_AUX_CLIP_DIS (1 << 29) |
||
480 | # define R128_GMC_WR_MSK_DIS (1 << 30) |
||
481 | # define R128_GMC_LD_BRUSH_Y_X (1 << 31) |
||
482 | # define R128_ROP3_ZERO 0x00000000 |
||
483 | # define R128_ROP3_DSa 0x00880000 |
||
484 | # define R128_ROP3_SDna 0x00440000 |
||
485 | # define R128_ROP3_S 0x00cc0000 |
||
486 | # define R128_ROP3_DSna 0x00220000 |
||
487 | # define R128_ROP3_D 0x00aa0000 |
||
488 | # define R128_ROP3_DSx 0x00660000 |
||
489 | # define R128_ROP3_DSo 0x00ee0000 |
||
490 | # define R128_ROP3_DSon 0x00110000 |
||
491 | # define R128_ROP3_DSxn 0x00990000 |
||
492 | # define R128_ROP3_Dn 0x00550000 |
||
493 | # define R128_ROP3_SDno 0x00dd0000 |
||
494 | # define R128_ROP3_Sn 0x00330000 |
||
495 | # define R128_ROP3_DSno 0x00bb0000 |
||
496 | # define R128_ROP3_DSan 0x00770000 |
||
497 | # define R128_ROP3_ONE 0x00ff0000 |
||
498 | # define R128_ROP3_DPa 0x00a00000 |
||
499 | # define R128_ROP3_PDna 0x00500000 |
||
500 | # define R128_ROP3_P 0x00f00000 |
||
501 | # define R128_ROP3_DPna 0x000a0000 |
||
502 | # define R128_ROP3_D 0x00aa0000 |
||
503 | # define R128_ROP3_DPx 0x005a0000 |
||
504 | # define R128_ROP3_DPo 0x00fa0000 |
||
505 | # define R128_ROP3_DPon 0x00050000 |
||
506 | # define R128_ROP3_PDxn 0x00a50000 |
||
507 | # define R128_ROP3_PDno 0x00f50000 |
||
508 | # define R128_ROP3_Pn 0x000f0000 |
||
509 | # define R128_ROP3_DPno 0x00af0000 |
||
510 | # define R128_ROP3_DPan 0x005f0000 |
||
511 | |||
512 | |||
513 | #define R128_DP_GUI_MASTER_CNTL_C 0x1c84 |
||
514 | #define R128_DP_MIX 0x16c8 |
||
515 | #define R128_DP_SRC_BKGD_CLR 0x15dc |
||
516 | #define R128_DP_SRC_FRGD_CLR 0x15d8 |
||
517 | #define R128_DP_WRITE_MASK 0x16cc |
||
518 | #define R128_DST_BRES_DEC 0x1630 |
||
519 | #define R128_DST_BRES_ERR 0x1628 |
||
520 | #define R128_DST_BRES_INC 0x162c |
||
521 | #define R128_DST_BRES_LNTH 0x1634 |
||
522 | #define R128_DST_BRES_LNTH_SUB 0x1638 |
||
523 | #define R128_DST_HEIGHT 0x1410 |
||
524 | #define R128_DST_HEIGHT_WIDTH 0x143c |
||
525 | #define R128_DST_HEIGHT_WIDTH_8 0x158c |
||
526 | #define R128_DST_HEIGHT_WIDTH_BW 0x15b4 |
||
527 | #define R128_DST_HEIGHT_Y 0x15a0 |
||
528 | #define R128_DST_OFFSET 0x1404 |
||
529 | #define R128_DST_PITCH 0x1408 |
||
530 | #define R128_DST_PITCH_OFFSET 0x142c |
||
531 | #define R128_DST_PITCH_OFFSET_C 0x1c80 |
||
532 | # define R128_PITCH_SHIFT 21 |
||
533 | # define R128_DST_TILE (1 << 31) |
||
534 | #define R128_DST_WIDTH 0x140c |
||
535 | #define R128_DST_WIDTH_HEIGHT 0x1598 |
||
536 | #define R128_DST_WIDTH_X 0x1588 |
||
537 | #define R128_DST_WIDTH_X_INCY 0x159c |
||
538 | #define R128_DST_X 0x141c |
||
539 | #define R128_DST_X_SUB 0x15a4 |
||
540 | #define R128_DST_X_Y 0x1594 |
||
541 | #define R128_DST_Y 0x1420 |
||
542 | #define R128_DST_Y_SUB 0x15a8 |
||
543 | #define R128_DST_Y_X 0x1438 |
||
544 | |||
545 | #define R128_EXT_MEM_CNTL 0x0144 |
||
546 | |||
547 | #define R128_FCP_CNTL 0x0012 /* PLL */ |
||
548 | #define R128_FLUSH_1 0x1704 |
||
549 | #define R128_FLUSH_2 0x1708 |
||
550 | #define R128_FLUSH_3 0x170c |
||
551 | #define R128_FLUSH_4 0x1710 |
||
552 | #define R128_FLUSH_5 0x1714 |
||
553 | #define R128_FLUSH_6 0x1718 |
||
554 | #define R128_FLUSH_7 0x171c |
||
555 | #define R128_FOG_3D_TABLE_START 0x1810 |
||
556 | #define R128_FOG_3D_TABLE_END 0x1814 |
||
557 | #define R128_FOG_3D_TABLE_DENSITY 0x181c |
||
558 | #define R128_FOG_TABLE_INDEX 0x1a14 |
||
559 | #define R128_FOG_TABLE_DATA 0x1a18 |
||
560 | #define R128_FP_CRTC_H_TOTAL_DISP 0x0250 |
||
561 | #define R128_FP_CRTC_V_TOTAL_DISP 0x0254 |
||
562 | #define R128_FP_GEN_CNTL 0x0284 |
||
563 | # define R128_FP_FPON (1 << 0) |
||
564 | # define R128_FP_TDMS_EN (1 << 2) |
||
565 | # define R128_FP_DETECT_SENSE (1 << 8) |
||
566 | # define R128_FP_SEL_CRTC2 (1 << 13) |
||
567 | # define R128_FP_CRTC_DONT_SHADOW_VPAR (1 << 16) |
||
568 | # define R128_FP_CRTC_USE_SHADOW_VEND (1 << 18) |
||
569 | # define R128_FP_CRTC_HORZ_DIV2_EN (1 << 20) |
||
570 | # define R128_FP_CRTC_HOR_CRT_DIV2_DIS (1 << 21) |
||
571 | # define R128_FP_USE_SHADOW_EN (1 << 24) |
||
572 | #define R128_FP_H_SYNC_STRT_WID 0x02c4 |
||
573 | #define R128_FP_HORZ_STRETCH 0x028c |
||
574 | # define R128_HORZ_STRETCH_RATIO_MASK 0xffff |
||
575 | # define R128_HORZ_STRETCH_RATIO_SHIFT 0 |
||
576 | # define R128_HORZ_STRETCH_RATIO_MAX 4096 |
||
577 | # define R128_HORZ_PANEL_SIZE (0xff << 16) |
||
578 | # define R128_HORZ_PANEL_SHIFT 16 |
||
579 | # define R128_HORZ_STRETCH_PIXREP (0 << 25) |
||
580 | # define R128_HORZ_STRETCH_BLEND (1 << 25) |
||
581 | # define R128_HORZ_STRETCH_ENABLE (1 << 26) |
||
582 | # define R128_HORZ_FP_LOOP_STRETCH (0x7 << 27) |
||
583 | # define R128_HORZ_STRETCH_RESERVED (1 << 30) |
||
584 | # define R128_HORZ_AUTO_RATIO_FIX_EN (1 << 31) |
||
585 | |||
586 | #define R128_FP_PANEL_CNTL 0x0288 |
||
587 | # define R128_FP_DIGON (1 << 0) |
||
588 | # define R128_FP_BLON (1 << 1) |
||
589 | #define R128_FP_V_SYNC_STRT_WID 0x02c8 |
||
590 | #define R128_FP_VERT_STRETCH 0x0290 |
||
591 | # define R128_VERT_PANEL_SIZE (0x7ff << 0) |
||
592 | # define R128_VERT_PANEL_SHIFT 0 |
||
593 | # define R128_VERT_STRETCH_RATIO_MASK 0x3ff |
||
594 | # define R128_VERT_STRETCH_RATIO_SHIFT 11 |
||
595 | # define R128_VERT_STRETCH_RATIO_MAX 1024 |
||
596 | # define R128_VERT_STRETCH_ENABLE (1 << 24) |
||
597 | # define R128_VERT_STRETCH_LINEREP (0 << 25) |
||
598 | # define R128_VERT_STRETCH_BLEND (1 << 25) |
||
599 | # define R128_VERT_AUTO_RATIO_EN (1 << 26) |
||
600 | # define R128_VERT_STRETCH_RESERVED 0xf8e00000 |
||
601 | |||
602 | #define R128_GEN_INT_CNTL 0x0040 |
||
603 | #define R128_GEN_INT_STATUS 0x0044 |
||
604 | # define R128_VSYNC_INT_AK (1 << 2) |
||
605 | # define R128_VSYNC_INT (1 << 2) |
||
606 | #define R128_GEN_RESET_CNTL 0x00f0 |
||
607 | # define R128_SOFT_RESET_GUI (1 << 0) |
||
608 | # define R128_SOFT_RESET_VCLK (1 << 8) |
||
609 | # define R128_SOFT_RESET_PCLK (1 << 9) |
||
610 | # define R128_SOFT_RESET_DISPENG_XCLK (1 << 11) |
||
611 | # define R128_SOFT_RESET_MEMCTLR_XCLK (1 << 12) |
||
612 | #define R128_GENENB 0x03c3 /* VGA */ |
||
613 | #define R128_GENFC_RD 0x03ca /* VGA */ |
||
614 | #define R128_GENFC_WT 0x03da /* VGA, 0x03ba */ |
||
615 | #define R128_GENMO_RD 0x03cc /* VGA */ |
||
616 | #define R128_GENMO_WT 0x03c2 /* VGA */ |
||
617 | #define R128_GENS0 0x03c2 /* VGA */ |
||
618 | #define R128_GENS1 0x03da /* VGA, 0x03ba */ |
||
619 | #define R128_GPIO_MONID 0x0068 |
||
620 | # define R128_GPIO_MONID_A_0 (1 << 0) |
||
621 | # define R128_GPIO_MONID_A_1 (1 << 1) |
||
622 | # define R128_GPIO_MONID_A_2 (1 << 2) |
||
623 | # define R128_GPIO_MONID_A_3 (1 << 3) |
||
624 | # define R128_GPIO_MONID_Y_0 (1 << 8) |
||
625 | # define R128_GPIO_MONID_Y_1 (1 << 9) |
||
626 | # define R128_GPIO_MONID_Y_2 (1 << 10) |
||
627 | # define R128_GPIO_MONID_Y_3 (1 << 11) |
||
628 | # define R128_GPIO_MONID_EN_0 (1 << 16) |
||
629 | # define R128_GPIO_MONID_EN_1 (1 << 17) |
||
630 | # define R128_GPIO_MONID_EN_2 (1 << 18) |
||
631 | # define R128_GPIO_MONID_EN_3 (1 << 19) |
||
632 | # define R128_GPIO_MONID_MASK_0 (1 << 24) |
||
633 | # define R128_GPIO_MONID_MASK_1 (1 << 25) |
||
634 | # define R128_GPIO_MONID_MASK_2 (1 << 26) |
||
635 | # define R128_GPIO_MONID_MASK_3 (1 << 27) |
||
636 | #define R128_GPIO_MONIDB 0x006c |
||
637 | #define R128_GRPH8_DATA 0x03cf /* VGA */ |
||
638 | #define R128_GRPH8_IDX 0x03ce /* VGA */ |
||
639 | #define R128_GUI_DEBUG0 0x16a0 |
||
640 | #define R128_GUI_DEBUG1 0x16a4 |
||
641 | #define R128_GUI_DEBUG2 0x16a8 |
||
642 | #define R128_GUI_DEBUG3 0x16ac |
||
643 | #define R128_GUI_DEBUG4 0x16b0 |
||
644 | #define R128_GUI_DEBUG5 0x16b4 |
||
645 | #define R128_GUI_DEBUG6 0x16b8 |
||
646 | #define R128_GUI_PROBE 0x16bc |
||
647 | #define R128_GUI_SCRATCH_REG0 0x15e0 |
||
648 | #define R128_GUI_SCRATCH_REG1 0x15e4 |
||
649 | #define R128_GUI_SCRATCH_REG2 0x15e8 |
||
650 | #define R128_GUI_SCRATCH_REG3 0x15ec |
||
651 | #define R128_GUI_SCRATCH_REG4 0x15f0 |
||
652 | #define R128_GUI_SCRATCH_REG5 0x15f4 |
||
653 | #define R128_GUI_STAT 0x1740 |
||
654 | # define R128_GUI_FIFOCNT_MASK 0x0fff |
||
655 | # define R128_GUI_ACTIVE (1 << 31) |
||
656 | |||
657 | #define R128_HEADER 0x0f0e /* PCI */ |
||
658 | #define R128_HOST_DATA0 0x17c0 |
||
659 | #define R128_HOST_DATA1 0x17c4 |
||
660 | #define R128_HOST_DATA2 0x17c8 |
||
661 | #define R128_HOST_DATA3 0x17cc |
||
662 | #define R128_HOST_DATA4 0x17d0 |
||
663 | #define R128_HOST_DATA5 0x17d4 |
||
664 | #define R128_HOST_DATA6 0x17d8 |
||
665 | #define R128_HOST_DATA7 0x17dc |
||
666 | #define R128_HOST_DATA_LAST 0x17e0 |
||
667 | #define R128_HOST_PATH_CNTL 0x0130 |
||
668 | #define R128_HTOTAL_CNTL 0x0009 /* PLL */ |
||
669 | #define R128_HW_DEBUG 0x0128 |
||
670 | #define R128_HW_DEBUG2 0x011c |
||
671 | |||
672 | #define R128_I2C_CNTL_1 0x0094 /* ? */ |
||
673 | #define R128_INTERRUPT_LINE 0x0f3c /* PCI */ |
||
674 | #define R128_INTERRUPT_PIN 0x0f3d /* PCI */ |
||
675 | #define R128_IO_BASE 0x0f14 /* PCI */ |
||
676 | |||
677 | #define R128_LATENCY 0x0f0d /* PCI */ |
||
678 | #define R128_LEAD_BRES_DEC 0x1608 |
||
679 | #define R128_LEAD_BRES_ERR 0x1600 |
||
680 | #define R128_LEAD_BRES_INC 0x1604 |
||
681 | #define R128_LEAD_BRES_LNTH 0x161c |
||
682 | #define R128_LEAD_BRES_LNTH_SUB 0x1624 |
||
683 | #define R128_LVDS_GEN_CNTL 0x02d0 |
||
684 | # define R128_LVDS_ON (1 << 0) |
||
685 | # define R128_LVDS_BLON (1 << 19) |
||
686 | # define R128_LVDS_SEL_CRTC2 (1 << 23) |
||
687 | # define R128_HSYNC_DELAY_SHIFT 28 |
||
688 | # define R128_HSYNC_DELAY_MASK (0xf << 28) |
||
689 | |||
690 | #define R128_MAX_LATENCY 0x0f3f /* PCI */ |
||
691 | #define R128_MCLK_CNTL 0x000f /* PLL */ |
||
692 | # define R128_FORCE_GCP (1 << 16) |
||
693 | # define R128_FORCE_PIPE3D_CP (1 << 17) |
||
694 | # define R128_FORCE_RCP (1 << 18) |
||
695 | #define R128_MDGPIO_A_REG 0x01ac |
||
696 | #define R128_MDGPIO_EN_REG 0x01b0 |
||
697 | #define R128_MDGPIO_MASK 0x0198 |
||
698 | #define R128_MDGPIO_Y_REG 0x01b4 |
||
699 | #define R128_MEM_ADDR_CONFIG 0x0148 |
||
700 | #define R128_MEM_BASE 0x0f10 /* PCI */ |
||
701 | #define R128_MEM_CNTL 0x0140 |
||
702 | #define R128_MEM_INIT_LAT_TIMER 0x0154 |
||
703 | #define R128_MEM_INTF_CNTL 0x014c |
||
704 | #define R128_MEM_SDRAM_MODE_REG 0x0158 |
||
705 | #define R128_MEM_STR_CNTL 0x0150 |
||
706 | #define R128_MEM_VGA_RP_SEL 0x003c |
||
707 | #define R128_MEM_VGA_WP_SEL 0x0038 |
||
708 | #define R128_MIN_GRANT 0x0f3e /* PCI */ |
||
709 | #define R128_MM_DATA 0x0004 |
||
710 | #define R128_MM_INDEX 0x0000 |
||
711 | #define R128_MPLL_CNTL 0x000e /* PLL */ |
||
712 | #define R128_MPP_TB_CONFIG 0x01c0 /* ? */ |
||
713 | #define R128_MPP_GP_CONFIG 0x01c8 /* ? */ |
||
714 | |||
715 | #define R128_N_VIF_COUNT 0x0248 |
||
716 | |||
717 | #define R128_OVR_CLR 0x0230 |
||
718 | #define R128_OVR_WID_LEFT_RIGHT 0x0234 |
||
719 | #define R128_OVR_WID_TOP_BOTTOM 0x0238 |
||
720 | |||
721 | /* first overlay unit (there is only one) */ |
||
722 | |||
723 | #define R128_OV0_Y_X_START 0x0400 |
||
724 | #define R128_OV0_Y_X_END 0x0404 |
||
725 | #define R128_OV0_EXCLUSIVE_HORZ 0x0408 |
||
726 | # define R128_EXCL_HORZ_START_MASK 0x000000ff |
||
727 | # define R128_EXCL_HORZ_END_MASK 0x0000ff00 |
||
728 | # define R128_EXCL_HORZ_BACK_PORCH_MASK 0x00ff0000 |
||
729 | # define R128_EXCL_HORZ_EXCLUSIVE_EN 0x80000000 |
||
730 | #define R128_OV0_EXCLUSIVE_VERT 0x040C |
||
731 | # define R128_EXCL_VERT_START_MASK 0x000003ff |
||
732 | # define R128_EXCL_VERT_END_MASK 0x03ff0000 |
||
733 | #define R128_OV0_REG_LOAD_CNTL 0x0410 |
||
734 | # define R128_REG_LD_CTL_LOCK 0x00000001L |
||
735 | # define R128_REG_LD_CTL_VBLANK_DURING_LOCK 0x00000002L |
||
736 | # define R128_REG_LD_CTL_STALL_GUI_UNTIL_FLIP 0x00000004L |
||
737 | # define R128_REG_LD_CTL_LOCK_READBACK 0x00000008L |
||
738 | #define R128_OV0_SCALE_CNTL 0x0420 |
||
739 | # define R128_SCALER_PIX_EXPAND 0x00000001L |
||
740 | # define R128_SCALER_Y2R_TEMP 0x00000002L |
||
741 | # define R128_SCALER_HORZ_PICK_NEAREST 0x00000003L |
||
742 | # define R128_SCALER_VERT_PICK_NEAREST 0x00000004L |
||
743 | # define R128_SCALER_SIGNED_UV 0x00000010L |
||
744 | # define R128_SCALER_GAMMA_SEL_MASK 0x00000060L |
||
745 | # define R128_SCALER_GAMMA_SEL_BRIGHT 0x00000000L |
||
746 | # define R128_SCALER_GAMMA_SEL_G22 0x00000020L |
||
747 | # define R128_SCALER_GAMMA_SEL_G18 0x00000040L |
||
748 | # define R128_SCALER_GAMMA_SEL_G14 0x00000060L |
||
749 | # define R128_SCALER_COMCORE_SHIFT_UP_ONE 0x00000080L |
||
750 | # define R128_SCALER_SURFAC_FORMAT 0x00000f00L |
||
751 | # define R128_SCALER_SOURCE_15BPP 0x00000300L |
||
752 | # define R128_SCALER_SOURCE_16BPP 0x00000400L |
||
753 | # define R128_SCALER_SOURCE_32BPP 0x00000600L |
||
754 | # define R128_SCALER_SOURCE_YUV9 0x00000900L |
||
755 | # define R128_SCALER_SOURCE_YUV12 0x00000A00L |
||
756 | # define R128_SCALER_SOURCE_VYUY422 0x00000B00L |
||
757 | # define R128_SCALER_SOURCE_YVYU422 0x00000C00L |
||
758 | # define R128_SCALER_SMART_SWITCH 0x00008000L |
||
759 | # define R128_SCALER_BURST_PER_PLANE 0x00ff0000L |
||
760 | # define R128_SCALER_DOUBLE_BUFFER 0x01000000L |
||
761 | # define R128_SCALER_DIS_LIMIT 0x08000000L |
||
762 | # define R128_SCALER_PRG_LOAD_START 0x10000000L |
||
763 | # define R128_SCALER_INT_EMU 0x20000000L |
||
764 | # define R128_SCALER_ENABLE 0x40000000L |
||
765 | # define R128_SCALER_SOFT_RESET 0x80000000L |
||
766 | #define R128_OV0_V_INC 0x0424 |
||
767 | #define R128_OV0_P1_V_ACCUM_INIT 0x0428 |
||
768 | # define R128_OV0_P1_MAX_LN_IN_PER_LN_OUT 0x00000003L |
||
769 | # define R128_OV0_P1_V_ACCUM_INIT_MASK 0x01ff8000L |
||
770 | #define R128_OV0_P23_V_ACCUM_INIT 0x042C |
||
771 | #define R128_OV0_P1_BLANK_LINES_AT_TOP 0x0430 |
||
772 | # define R128_P1_BLNK_LN_AT_TOP_M1_MASK 0x00000fffL |
||
773 | # define R128_P1_ACTIVE_LINES_M1 0x0fff0000L |
||
774 | #define R128_OV0_P23_BLANK_LINES_AT_TOP 0x0434 |
||
775 | # define R128_P23_BLNK_LN_AT_TOP_M1_MASK 0x000007ffL |
||
776 | # define R128_P23_ACTIVE_LINES_M1 0x07ff0000L |
||
777 | #define R128_OV0_VID_BUF0_BASE_ADRS 0x0440 |
||
778 | # define R128_VIF_BUF0_PITCH_SEL 0x00000001L |
||
779 | # define R128_VIF_BUF0_TILE_ADRS 0x00000002L |
||
780 | # define R128_VIF_BUF0_BASE_ADRS_MASK 0x03fffff0L |
||
781 | # define R128_VIF_BUF0_1ST_LINE_LSBS_MASK 0x48000000L |
||
782 | #define R128_OV0_VID_BUF1_BASE_ADRS 0x0444 |
||
783 | # define R128_VIF_BUF1_PITCH_SEL 0x00000001L |
||
784 | # define R128_VIF_BUF1_TILE_ADRS 0x00000002L |
||
785 | # define R128_VIF_BUF1_BASE_ADRS_MASK 0x03fffff0L |
||
786 | # define R128_VIF_BUF1_1ST_LINE_LSBS_MASK 0x48000000L |
||
787 | #define R128_OV0_VID_BUF2_BASE_ADRS 0x0448 |
||
788 | # define R128_VIF_BUF2_PITCH_SEL 0x00000001L |
||
789 | # define R128_VIF_BUF2_TILE_ADRS 0x00000002L |
||
790 | # define R128_VIF_BUF2_BASE_ADRS_MASK 0x03fffff0L |
||
791 | # define R128_VIF_BUF2_1ST_LINE_LSBS_MASK 0x48000000L |
||
792 | #define R128_OV0_VID_BUF3_BASE_ADRS 0x044C |
||
793 | #define R128_OV0_VID_BUF4_BASE_ADRS 0x0450 |
||
794 | #define R128_OV0_VID_BUF5_BASE_ADRS 0x0454 |
||
795 | #define R128_OV0_VID_BUF_PITCH0_VALUE 0x0460 |
||
796 | #define R128_OV0_VID_BUF_PITCH1_VALUE 0x0464 |
||
797 | #define R128_OV0_AUTO_FLIP_CNTL 0x0470 |
||
798 | #define R128_OV0_DEINTERLACE_PATTERN 0x0474 |
||
799 | #define R128_OV0_H_INC 0x0480 |
||
800 | #define R128_OV0_STEP_BY 0x0484 |
||
801 | #define R128_OV0_P1_H_ACCUM_INIT 0x0488 |
||
802 | #define R128_OV0_P23_H_ACCUM_INIT 0x048C |
||
803 | #define R128_OV0_P1_X_START_END 0x0494 |
||
804 | #define R128_OV0_P2_X_START_END 0x0498 |
||
805 | #define R128_OV0_P3_X_START_END 0x049C |
||
806 | #define R128_OV0_FILTER_CNTL 0x04A0 |
||
807 | #define R128_OV0_FOUR_TAP_COEF_0 0x04B0 |
||
808 | #define R128_OV0_FOUR_TAP_COEF_1 0x04B4 |
||
809 | #define R128_OV0_FOUR_TAP_COEF_2 0x04B8 |
||
810 | #define R128_OV0_FOUR_TAP_COEF_3 0x04BC |
||
811 | #define R128_OV0_FOUR_TAP_COEF_4 0x04C0 |
||
812 | #define R128_OV0_COLOUR_CNTL 0x04E0 |
||
813 | #define R128_OV0_VIDEO_KEY_CLR 0x04E4 |
||
814 | #define R128_OV0_VIDEO_KEY_MSK 0x04E8 |
||
815 | #define R128_OV0_GRAPHICS_KEY_CLR 0x04EC |
||
816 | #define R128_OV0_GRAPHICS_KEY_MSK 0x04F0 |
||
817 | #define R128_OV0_KEY_CNTL 0x04F4 |
||
818 | # define R128_VIDEO_KEY_FN_MASK 0x00000007L |
||
819 | # define R128_VIDEO_KEY_FN_FALSE 0x00000000L |
||
820 | # define R128_VIDEO_KEY_FN_TRUE 0x00000001L |
||
821 | # define R128_VIDEO_KEY_FN_EQ 0x00000004L |
||
822 | # define R128_VIDEO_KEY_FN_NE 0x00000005L |
||
823 | # define R128_GRAPHIC_KEY_FN_MASK 0x00000070L |
||
824 | # define R128_GRAPHIC_KEY_FN_FALSE 0x00000000L |
||
825 | # define R128_GRAPHIC_KEY_FN_TRUE 0x00000010L |
||
826 | # define R128_GRAPHIC_KEY_FN_EQ 0x00000040L |
||
827 | # define R128_GRAPHIC_KEY_FN_NE 0x00000050L |
||
828 | # define R128_CMP_MIX_MASK 0x00000100L |
||
829 | # define R128_CMP_MIX_OR 0x00000000L |
||
830 | # define R128_CMP_MIX_AND 0x00000100L |
||
831 | #define R128_OV0_TEST 0x04F8 |
||
832 | |||
833 | |||
834 | #define R128_PALETTE_DATA 0x00b4 |
||
835 | #define R128_PALETTE_INDEX 0x00b0 |
||
836 | #define R128_PC_DEBUG_MODE 0x1760 |
||
837 | #define R128_PC_GUI_CTLSTAT 0x1748 |
||
838 | #define R128_PC_GUI_MODE 0x1744 |
||
839 | # define R128_PC_IGNORE_UNIFY (1 << 5) |
||
840 | #define R128_PC_MISC_CNTL 0x0188 |
||
841 | #define R128_PC_NGUI_CTLSTAT 0x0184 |
||
842 | # define R128_PC_FLUSH_GUI (3 << 0) |
||
843 | # define R128_PC_RI_GUI (1 << 2) |
||
844 | # define R128_PC_FLUSH_ALL 0x00ff |
||
845 | # define R128_PC_BUSY (1 << 31) |
||
846 | #define R128_PC_NGUI_MODE 0x0180 |
||
847 | #define R128_PCI_GART_PAGE 0x017c |
||
848 | #define R128_PLANE_3D_MASK_C 0x1d44 |
||
849 | #define R128_PLL_TEST_CNTL 0x0013 /* PLL */ |
||
850 | #define R128_PMI_CAP_ID 0x0f5c /* PCI */ |
||
851 | #define R128_PMI_DATA 0x0f63 /* PCI */ |
||
852 | #define R128_PMI_NXT_CAP_PTR 0x0f5d /* PCI */ |
||
853 | #define R128_PMI_PMC_REG 0x0f5e /* PCI */ |
||
854 | #define R128_PMI_PMCSR_REG 0x0f60 /* PCI */ |
||
855 | #define R128_PMI_REGISTER 0x0f5c /* PCI */ |
||
856 | #define R128_PPLL_CNTL 0x0002 /* PLL */ |
||
857 | # define R128_PPLL_RESET (1 << 0) |
||
858 | # define R128_PPLL_SLEEP (1 << 1) |
||
859 | # define R128_PPLL_ATOMIC_UPDATE_EN (1 << 16) |
||
860 | # define R128_PPLL_VGA_ATOMIC_UPDATE_EN (1 << 17) |
||
861 | #define R128_PPLL_DIV_0 0x0004 /* PLL */ |
||
862 | #define R128_PPLL_DIV_1 0x0005 /* PLL */ |
||
863 | #define R128_PPLL_DIV_2 0x0006 /* PLL */ |
||
864 | #define R128_PPLL_DIV_3 0x0007 /* PLL */ |
||
865 | # define R128_PPLL_FB3_DIV_MASK 0x07ff |
||
866 | # define R128_PPLL_POST3_DIV_MASK 0x00070000 |
||
867 | #define R128_PPLL_REF_DIV 0x0003 /* PLL */ |
||
868 | # define R128_PPLL_REF_DIV_MASK 0x03ff |
||
869 | # define R128_PPLL_ATOMIC_UPDATE_R (1 << 15) /* same as _W */ |
||
870 | # define R128_PPLL_ATOMIC_UPDATE_W (1 << 15) /* same as _R */ |
||
871 | #define R128_PWR_MNGMT_CNTL_STATUS 0x0f60 /* PCI */ |
||
872 | #define R128_REG_BASE 0x0f18 /* PCI */ |
||
873 | #define R128_REGPROG_INF 0x0f09 /* PCI */ |
||
874 | #define R128_REVISION_ID 0x0f08 /* PCI */ |
||
875 | |||
876 | #define R128_SC_BOTTOM 0x164c |
||
877 | #define R128_SC_BOTTOM_RIGHT 0x16f0 |
||
878 | #define R128_SC_BOTTOM_RIGHT_C 0x1c8c |
||
879 | #define R128_SC_LEFT 0x1640 |
||
880 | #define R128_SC_RIGHT 0x1644 |
||
881 | #define R128_SC_TOP 0x1648 |
||
882 | #define R128_SC_TOP_LEFT 0x16ec |
||
883 | #define R128_SC_TOP_LEFT_C 0x1c88 |
||
884 | #define R128_SEQ8_DATA 0x03c5 /* VGA */ |
||
885 | #define R128_SEQ8_IDX 0x03c4 /* VGA */ |
||
886 | #define R128_SNAPSHOT_F_COUNT 0x0244 |
||
887 | #define R128_SNAPSHOT_VH_COUNTS 0x0240 |
||
888 | #define R128_SNAPSHOT_VIF_COUNT 0x024c |
||
889 | #define R128_SRC_OFFSET 0x15ac |
||
890 | #define R128_SRC_PITCH 0x15b0 |
||
891 | #define R128_SRC_PITCH_OFFSET 0x1428 |
||
892 | #define R128_SRC_SC_BOTTOM 0x165c |
||
893 | #define R128_SRC_SC_BOTTOM_RIGHT 0x16f4 |
||
894 | #define R128_SRC_SC_RIGHT 0x1654 |
||
895 | #define R128_SRC_X 0x1414 |
||
896 | #define R128_SRC_X_Y 0x1590 |
||
897 | #define R128_SRC_Y 0x1418 |
||
898 | #define R128_SRC_Y_X 0x1434 |
||
899 | #define R128_STATUS 0x0f06 /* PCI */ |
||
900 | #define R128_SUBPIC_CNTL 0x0540 /* ? */ |
||
901 | #define R128_SUB_CLASS 0x0f0a /* PCI */ |
||
902 | #define R128_SURFACE_DELAY 0x0b00 |
||
903 | #define R128_SURFACE0_INFO 0x0b0c |
||
904 | #define R128_SURFACE0_LOWER_BOUND 0x0b04 |
||
905 | #define R128_SURFACE0_UPPER_BOUND 0x0b08 |
||
906 | #define R128_SURFACE1_INFO 0x0b1c |
||
907 | #define R128_SURFACE1_LOWER_BOUND 0x0b14 |
||
908 | #define R128_SURFACE1_UPPER_BOUND 0x0b18 |
||
909 | #define R128_SURFACE2_INFO 0x0b2c |
||
910 | #define R128_SURFACE2_LOWER_BOUND 0x0b24 |
||
911 | #define R128_SURFACE2_UPPER_BOUND 0x0b28 |
||
912 | #define R128_SURFACE3_INFO 0x0b3c |
||
913 | #define R128_SURFACE3_LOWER_BOUND 0x0b34 |
||
914 | #define R128_SURFACE3_UPPER_BOUND 0x0b38 |
||
915 | #define R128_SW_SEMAPHORE 0x013c |
||
916 | |||
917 | #define R128_TEST_DEBUG_CNTL 0x0120 |
||
918 | #define R128_TEST_DEBUG_MUX 0x0124 |
||
919 | #define R128_TEST_DEBUG_OUT 0x012c |
||
920 | #define R128_TMDS_CRC 0x02a0 |
||
921 | #define R128_TRAIL_BRES_DEC 0x1614 |
||
922 | #define R128_TRAIL_BRES_ERR 0x160c |
||
923 | #define R128_TRAIL_BRES_INC 0x1610 |
||
924 | #define R128_TRAIL_X 0x1618 |
||
925 | #define R128_TRAIL_X_SUB 0x1620 |
||
926 | |||
927 | #define R128_VCLK_ECP_CNTL 0x0008 /* PLL */ |
||
928 | #define R128_VENDOR_ID 0x0f00 /* PCI */ |
||
929 | #define R128_VGA_DDA_CONFIG 0x02e8 |
||
930 | #define R128_VGA_DDA_ON_OFF 0x02ec |
||
931 | #define R128_VID_BUFFER_CONTROL 0x0900 |
||
932 | #define R128_VIDEOMUX_CNTL 0x0190 |
||
933 | #define R128_VIPH_CONTROL 0x01D0 /* ? */ |
||
934 | |||
935 | #define R128_WAIT_UNTIL 0x1720 |
||
936 | |||
937 | #define R128_X_MPLL_REF_FB_DIV 0x000a /* PLL */ |
||
938 | #define R128_XCLK_CNTL 0x000d /* PLL */ |
||
939 | #define R128_XDLL_CNTL 0x000c /* PLL */ |
||
940 | #define R128_XPLL_CNTL 0x000b /* PLL */ |
||
941 | |||
942 | /* Registers for CCE and Microcode Engine */ |
||
943 | #define R128_PM4_MICROCODE_ADDR 0x07d4 |
||
944 | #define R128_PM4_MICROCODE_RADDR 0x07d8 |
||
945 | #define R128_PM4_MICROCODE_DATAH 0x07dc |
||
946 | #define R128_PM4_MICROCODE_DATAL 0x07e0 |
||
947 | |||
948 | #define R128_PM4_BUFFER_OFFSET 0x0700 |
||
949 | #define R128_PM4_BUFFER_CNTL 0x0704 |
||
950 | # define R128_PM4_NONPM4 (0 << 28) |
||
951 | # define R128_PM4_192PIO (1 << 28) |
||
952 | # define R128_PM4_192BM (2 << 28) |
||
953 | # define R128_PM4_128PIO_64INDBM (3 << 28) |
||
954 | # define R128_PM4_128BM_64INDBM (4 << 28) |
||
955 | # define R128_PM4_64PIO_128INDBM (5 << 28) |
||
956 | # define R128_PM4_64BM_128INDBM (6 << 28) |
||
957 | # define R128_PM4_64PIO_64VCBM_64INDBM (7 << 28) |
||
958 | # define R128_PM4_64BM_64VCBM_64INDBM (8 << 28) |
||
959 | # define R128_PM4_64PIO_64VCPIO_64INDPIO (15 << 28) |
||
960 | #define R128_PM4_BUFFER_WM_CNTL 0x0708 |
||
961 | # define R128_WMA_SHIFT 0 |
||
962 | # define R128_WMB_SHIFT 8 |
||
963 | # define R128_WMC_SHIFT 16 |
||
964 | # define R128_WB_WM_SHIFT 24 |
||
965 | #define R128_PM4_BUFFER_DL_RPTR_ADDR 0x070c |
||
966 | #define R128_PM4_BUFFER_DL_RPTR 0x0710 |
||
967 | #define R128_PM4_BUFFER_DL_WPTR 0x0714 |
||
968 | # define R128_PM4_BUFFER_DL_DONE (1 << 31) |
||
969 | #define R128_PM4_BUFFER_DL_WPTR_DELAY 0x0718 |
||
970 | # define R128_PRE_WRITE_TIMER_SHIFT 0 |
||
971 | # define R128_PRE_WRITE_LIMIT_SHIFT 23 |
||
972 | #define R128_PM4_VC_FPU_SETUP 0x071c |
||
973 | # define R128_FRONT_DIR_CW (0 << 0) |
||
974 | # define R128_FRONT_DIR_CCW (1 << 0) |
||
975 | # define R128_FRONT_DIR_MASK (1 << 0) |
||
976 | # define R128_BACKFACE_CULL (0 << 1) |
||
977 | # define R128_BACKFACE_POINTS (1 << 1) |
||
978 | # define R128_BACKFACE_LINES (2 << 1) |
||
979 | # define R128_BACKFACE_SOLID (3 << 1) |
||
980 | # define R128_BACKFACE_MASK (3 << 1) |
||
981 | # define R128_FRONTFACE_CULL (0 << 3) |
||
982 | # define R128_FRONTFACE_POINTS (1 << 3) |
||
983 | # define R128_FRONTFACE_LINES (2 << 3) |
||
984 | # define R128_FRONTFACE_SOLID (3 << 3) |
||
985 | # define R128_FRONTFACE_MASK (3 << 3) |
||
986 | # define R128_FPU_COLOR_SOLID (0 << 5) |
||
987 | # define R128_FPU_COLOR_FLAT (1 << 5) |
||
988 | # define R128_FPU_COLOR_GOURAUD (2 << 5) |
||
989 | # define R128_FPU_COLOR_GOURAUD2 (3 << 5) |
||
990 | # define R128_FPU_COLOR_MASK (3 << 5) |
||
991 | # define R128_FPU_SUB_PIX_2BITS (0 << 7) |
||
992 | # define R128_FPU_SUB_PIX_4BITS (1 << 7) |
||
993 | # define R128_FPU_MODE_2D (0 << 8) |
||
994 | # define R128_FPU_MODE_3D (1 << 8) |
||
995 | # define R128_TRAP_BITS_DISABLE (1 << 9) |
||
996 | # define R128_EDGE_ANTIALIAS (1 << 10) |
||
997 | # define R128_SUPERSAMPLE (1 << 11) |
||
998 | # define R128_XFACTOR_2 (0 << 12) |
||
999 | # define R128_XFACTOR_4 (1 << 12) |
||
1000 | # define R128_YFACTOR_2 (0 << 13) |
||
1001 | # define R128_YFACTOR_4 (1 << 13) |
||
1002 | # define R128_FLAT_SHADE_VERTEX_D3D (0 << 14) |
||
1003 | # define R128_FLAT_SHADE_VERTEX_OGL (1 << 14) |
||
1004 | # define R128_FPU_ROUND_TRUNCATE (0 << 15) |
||
1005 | # define R128_FPU_ROUND_NEAREST (1 << 15) |
||
1006 | # define R128_WM_SEL_8DW (0 << 16) |
||
1007 | # define R128_WM_SEL_16DW (1 << 16) |
||
1008 | # define R128_WM_SEL_32DW (2 << 16) |
||
1009 | #define R128_PM4_VC_DEBUG_CONFIG 0x07a4 |
||
1010 | #define R128_PM4_VC_STAT 0x07a8 |
||
1011 | #define R128_PM4_VC_TIMESTAMP0 0x07b0 |
||
1012 | #define R128_PM4_VC_TIMESTAMP1 0x07b4 |
||
1013 | #define R128_PM4_STAT 0x07b8 |
||
1014 | # define R128_PM4_FIFOCNT_MASK 0x0fff |
||
1015 | # define R128_PM4_BUSY (1 << 16) |
||
1016 | # define R128_PM4_GUI_ACTIVE (1 << 31) |
||
1017 | #define R128_PM4_BUFFER_ADDR 0x07f0 |
||
1018 | #define R128_PM4_MICRO_CNTL 0x07fc |
||
1019 | # define R128_PM4_MICRO_FREERUN (1 << 30) |
||
1020 | #define R128_PM4_FIFO_DATA_EVEN 0x1000 |
||
1021 | #define R128_PM4_FIFO_DATA_ODD 0x1004 |
||
1022 | |||
1023 | #define R128_SCALE_3D_CNTL 0x1a00 |
||
1024 | # define R128_SCALE_DITHER_ERR_DIFF (0 << 1) |
||
1025 | # define R128_SCALE_DITHER_TABLE (1 << 1) |
||
1026 | # define R128_TEX_CACHE_SIZE_FULL (0 << 2) |
||
1027 | # define R128_TEX_CACHE_SIZE_HALF (1 << 2) |
||
1028 | # define R128_DITHER_INIT_CURR (0 << 3) |
||
1029 | # define R128_DITHER_INIT_RESET (1 << 3) |
||
1030 | # define R128_ROUND_24BIT (1 << 4) |
||
1031 | # define R128_TEX_CACHE_DISABLE (1 << 5) |
||
1032 | # define R128_SCALE_3D_NOOP (0 << 6) |
||
1033 | # define R128_SCALE_3D_SCALE (1 << 6) |
||
1034 | # define R128_SCALE_3D_TEXMAP_SHADE (2 << 6) |
||
1035 | # define R128_SCALE_PIX_BLEND (0 << 8) |
||
1036 | # define R128_SCALE_PIX_REPLICATE (1 << 8) |
||
1037 | # define R128_TEX_CACHE_SPLIT (1 << 9) |
||
1038 | # define R128_APPLE_YUV_MODE (1 << 10) |
||
1039 | # define R128_TEX_CACHE_PALLETE_MODE (1 << 11) |
||
1040 | # define R128_ALPHA_COMB_ADD_CLAMP (0 << 12) |
||
1041 | # define R128_ALPHA_COMB_ADD_NCLAMP (1 << 12) |
||
1042 | # define R128_ALPHA_COMB_SUB_DST_SRC_CLAMP (2 << 12) |
||
1043 | # define R128_ALPHA_COMB_SUB_DST_SRC_NCLAMP (3 << 12) |
||
1044 | # define R128_FOG_TABLE (1 << 14) |
||
1045 | # define R128_SIGNED_DST_CLAMP (1 << 15) |
||
1046 | # define R128_ALPHA_BLEND_SRC_ZERO (0 << 16) |
||
1047 | # define R128_ALPHA_BLEND_SRC_ONE (1 << 16) |
||
1048 | # define R128_ALPHA_BLEND_SRC_SRCCOLOR (2 << 16) |
||
1049 | # define R128_ALPHA_BLEND_SRC_INVSRCCOLOR (3 << 16) |
||
1050 | # define R128_ALPHA_BLEND_SRC_SRCALPHA (4 << 16) |
||
1051 | # define R128_ALPHA_BLEND_SRC_INVSRCALPHA (5 << 16) |
||
1052 | # define R128_ALPHA_BLEND_SRC_DSTALPHA (6 << 16) |
||
1053 | # define R128_ALPHA_BLEND_SRC_INVDSTALPHA (7 << 16) |
||
1054 | # define R128_ALPHA_BLEND_SRC_DSTCOLOR (8 << 16) |
||
1055 | # define R128_ALPHA_BLEND_SRC_INVDSTCOLOR (9 << 16) |
||
1056 | # define R128_ALPHA_BLEND_SRC_SAT (10 << 16) |
||
1057 | # define R128_ALPHA_BLEND_SRC_BLEND (11 << 16) |
||
1058 | # define R128_ALPHA_BLEND_SRC_INVBLEND (12 << 16) |
||
1059 | # define R128_ALPHA_BLEND_DST_ZERO (0 << 20) |
||
1060 | # define R128_ALPHA_BLEND_DST_ONE (1 << 20) |
||
1061 | # define R128_ALPHA_BLEND_DST_SRCCOLOR (2 << 20) |
||
1062 | # define R128_ALPHA_BLEND_DST_INVSRCCOLOR (3 << 20) |
||
1063 | # define R128_ALPHA_BLEND_DST_SRCALPHA (4 << 20) |
||
1064 | # define R128_ALPHA_BLEND_DST_INVSRCALPHA (5 << 20) |
||
1065 | # define R128_ALPHA_BLEND_DST_DSTALPHA (6 << 20) |
||
1066 | # define R128_ALPHA_BLEND_DST_INVDSTALPHA (7 << 20) |
||
1067 | # define R128_ALPHA_BLEND_DST_DSTCOLOR (8 << 20) |
||
1068 | # define R128_ALPHA_BLEND_DST_INVDSTCOLOR (9 << 20) |
||
1069 | # define R128_ALPHA_TEST_NEVER (0 << 24) |
||
1070 | # define R128_ALPHA_TEST_LESS (1 << 24) |
||
1071 | # define R128_ALPHA_TEST_LESSEQUAL (2 << 24) |
||
1072 | # define R128_ALPHA_TEST_EQUAL (3 << 24) |
||
1073 | # define R128_ALPHA_TEST_GREATEREQUAL (4 << 24) |
||
1074 | # define R128_ALPHA_TEST_GREATER (5 << 24) |
||
1075 | # define R128_ALPHA_TEST_NEQUAL (6 << 24) |
||
1076 | # define R128_ALPHA_TEST_ALWAYS (7 << 24) |
||
1077 | # define R128_COMPOSITE_SHADOW_CMP_EQUAL (0 << 28) |
||
1078 | # define R128_COMPOSITE_SHADOW_CMP_NEQUAL (1 << 28) |
||
1079 | # define R128_COMPOSITE_SHADOW (1 << 29) |
||
1080 | # define R128_TEX_MAP_ALPHA_IN_TEXTURE (1 << 30) |
||
1081 | # define R128_TEX_CACHE_LINE_SIZE_8QW (0 << 31) |
||
1082 | # define R128_TEX_CACHE_LINE_SIZE_4QW (1 << 31) |
||
1083 | #define R128_SCALE_3D_DATATYPE 0x1a20 |
||
1084 | |||
1085 | #define R128_SETUP_CNTL 0x1bc4 |
||
1086 | # define R128_DONT_START_TRIANGLE (1 << 0) |
||
1087 | # define R128_Z_BIAS (0 << 1) |
||
1088 | # define R128_DONT_START_ANY_ON (1 << 2) |
||
1089 | # define R128_COLOR_SOLID_COLOR (0 << 3) |
||
1090 | # define R128_COLOR_FLAT_VERT_1 (1 << 3) |
||
1091 | # define R128_COLOR_FLAT_VERT_2 (2 << 3) |
||
1092 | # define R128_COLOR_FLAT_VERT_3 (3 << 3) |
||
1093 | # define R128_COLOR_GOURAUD (4 << 3) |
||
1094 | # define R128_PRIM_TYPE_TRI (0 << 7) |
||
1095 | # define R128_PRIM_TYPE_LINE (1 << 7) |
||
1096 | # define R128_PRIM_TYPE_POINT (2 << 7) |
||
1097 | # define R128_PRIM_TYPE_POLY_EDGE (3 << 7) |
||
1098 | # define R128_TEXTURE_ST_MULT_W (0 << 9) |
||
1099 | # define R128_TEXTURE_ST_DIRECT (1 << 9) |
||
1100 | # define R128_STARTING_VERTEX_1 (1 << 14) |
||
1101 | # define R128_STARTING_VERTEX_2 (2 << 14) |
||
1102 | # define R128_STARTING_VERTEX_3 (3 << 14) |
||
1103 | # define R128_ENDING_VERTEX_1 (1 << 16) |
||
1104 | # define R128_ENDING_VERTEX_2 (2 << 16) |
||
1105 | # define R128_ENDING_VERTEX_3 (3 << 16) |
||
1106 | # define R128_SU_POLY_LINE_LAST (0 << 18) |
||
1107 | # define R128_SU_POLY_LINE_NOT_LAST (1 << 18) |
||
1108 | # define R128_SUB_PIX_2BITS (0 << 19) |
||
1109 | # define R128_SUB_PIX_4BITS (1 << 19) |
||
1110 | # define R128_SET_UP_CONTINUE (1 << 31) |
||
1111 | |||
1112 | #define R128_WINDOW_XY_OFFSET 0x1bcc |
||
1113 | # define R128_WINDOW_Y_SHIFT 4 |
||
1114 | # define R128_WINDOW_X_SHIFT 20 |
||
1115 | |||
1116 | #define R128_Z_OFFSET_C 0x1c90 |
||
1117 | #define R128_Z_PITCH_C 0x1c94 |
||
1118 | # define R128_Z_TILE (1 << 16) |
||
1119 | #define R128_Z_STEN_CNTL_C 0x1c98 |
||
1120 | # define R128_Z_PIX_WIDTH_16 (0 << 1) |
||
1121 | # define R128_Z_PIX_WIDTH_24 (1 << 1) |
||
1122 | # define R128_Z_PIX_WIDTH_32 (2 << 1) |
||
1123 | # define R128_Z_PIX_WIDTH_MASK (3 << 1) |
||
1124 | # define R128_Z_TEST_NEVER (0 << 4) |
||
1125 | # define R128_Z_TEST_LESS (1 << 4) |
||
1126 | # define R128_Z_TEST_LESSEQUAL (2 << 4) |
||
1127 | # define R128_Z_TEST_EQUAL (3 << 4) |
||
1128 | # define R128_Z_TEST_GREATEREQUAL (4 << 4) |
||
1129 | # define R128_Z_TEST_GREATER (5 << 4) |
||
1130 | # define R128_Z_TEST_NEQUAL (6 << 4) |
||
1131 | # define R128_Z_TEST_ALWAYS (7 << 4) |
||
1132 | # define R128_Z_TEST_MASK (7 << 4) |
||
1133 | # define R128_STENCIL_TEST_NEVER (0 << 12) |
||
1134 | # define R128_STENCIL_TEST_LESS (1 << 12) |
||
1135 | # define R128_STENCIL_TEST_LESSEQUAL (2 << 12) |
||
1136 | # define R128_STENCIL_TEST_EQUAL (3 << 12) |
||
1137 | # define R128_STENCIL_TEST_GREATEREQUAL (4 << 12) |
||
1138 | # define R128_STENCIL_TEST_GREATER (5 << 12) |
||
1139 | # define R128_STENCIL_TEST_NEQUAL (6 << 12) |
||
1140 | # define R128_STENCIL_TEST_ALWAYS (7 << 12) |
||
1141 | # define R128_STENCIL_S_FAIL_KEEP (0 << 16) |
||
1142 | # define R128_STENCIL_S_FAIL_ZERO (1 << 16) |
||
1143 | # define R128_STENCIL_S_FAIL_REPLACE (2 << 16) |
||
1144 | # define R128_STENCIL_S_FAIL_INC (3 << 16) |
||
1145 | # define R128_STENCIL_S_FAIL_DEC (4 << 16) |
||
1146 | # define R128_STENCIL_S_FAIL_INV (5 << 16) |
||
1147 | # define R128_STENCIL_ZPASS_KEEP (0 << 20) |
||
1148 | # define R128_STENCIL_ZPASS_ZERO (1 << 20) |
||
1149 | # define R128_STENCIL_ZPASS_REPLACE (2 << 20) |
||
1150 | # define R128_STENCIL_ZPASS_INC (3 << 20) |
||
1151 | # define R128_STENCIL_ZPASS_DEC (4 << 20) |
||
1152 | # define R128_STENCIL_ZPASS_INV (5 << 20) |
||
1153 | # define R128_STENCIL_ZFAIL_KEEP (0 << 24) |
||
1154 | # define R128_STENCIL_ZFAIL_ZERO (1 << 24) |
||
1155 | # define R128_STENCIL_ZFAIL_REPLACE (2 << 24) |
||
1156 | # define R128_STENCIL_ZFAIL_INC (3 << 24) |
||
1157 | # define R128_STENCIL_ZFAIL_DEC (4 << 24) |
||
1158 | # define R128_STENCIL_ZFAIL_INV (5 << 24) |
||
1159 | #define R128_TEX_CNTL_C 0x1c9c |
||
1160 | # define R128_Z_ENABLE (1 << 0) |
||
1161 | # define R128_Z_WRITE_ENABLE (1 << 1) |
||
1162 | # define R128_STENCIL_ENABLE (1 << 3) |
||
1163 | # define R128_SHADE_ENABLE (0 << 4) |
||
1164 | # define R128_TEXMAP_ENABLE (1 << 4) |
||
1165 | # define R128_SEC_TEXMAP_ENABLE (1 << 5) |
||
1166 | # define R128_FOG_ENABLE (1 << 7) |
||
1167 | # define R128_DITHER_ENABLE (1 << 8) |
||
1168 | # define R128_ALPHA_ENABLE (1 << 9) |
||
1169 | # define R128_ALPHA_TEST_ENABLE (1 << 10) |
||
1170 | # define R128_SPEC_LIGHT_ENABLE (1 << 11) |
||
1171 | # define R128_TEX_CHROMA_KEY_ENABLE (1 << 12) |
||
1172 | # define R128_ALPHA_IN_TEX_COMPLETE_A (0 << 13) |
||
1173 | # define R128_ALPHA_IN_TEX_LSB_A (1 << 13) |
||
1174 | # define R128_LIGHT_DIS (0 << 14) |
||
1175 | # define R128_LIGHT_COPY (1 << 14) |
||
1176 | # define R128_LIGHT_MODULATE (2 << 14) |
||
1177 | # define R128_LIGHT_ADD (3 << 14) |
||
1178 | # define R128_LIGHT_BLEND_CONSTANT (4 << 14) |
||
1179 | # define R128_LIGHT_BLEND_TEXTURE (5 << 14) |
||
1180 | # define R128_LIGHT_BLEND_VERTEX (6 << 14) |
||
1181 | # define R128_LIGHT_BLEND_CONST_COLOR (7 << 14) |
||
1182 | # define R128_ALPHA_LIGHT_DIS (0 << 18) |
||
1183 | # define R128_ALPHA_LIGHT_COPY (1 << 18) |
||
1184 | # define R128_ALPHA_LIGHT_MODULATE (2 << 18) |
||
1185 | # define R128_ALPHA_LIGHT_ADD (3 << 18) |
||
1186 | # define R128_ANTI_ALIAS (1 << 21) |
||
1187 | # define R128_TEX_CACHE_FLUSH (1 << 23) |
||
1188 | # define R128_LOD_BIAS_SHIFT 24 |
||
1189 | # define R128_LOD_BIAS_MASK (0xff << 24) |
||
1190 | #define R128_MISC_3D_STATE_CNTL_REG 0x1ca0 |
||
1191 | # define R128_REF_ALPHA_MASK 0xff |
||
1192 | # define R128_MISC_SCALE_3D_NOOP (0 << 8) |
||
1193 | # define R128_MISC_SCALE_3D_SCALE (1 << 8) |
||
1194 | # define R128_MISC_SCALE_3D_TEXMAP_SHADE (2 << 8) |
||
1195 | # define R128_MISC_SCALE_PIX_BLEND (0 << 10) |
||
1196 | # define R128_MISC_SCALE_PIX_REPLICATE (1 << 10) |
||
1197 | # define R128_ALPHA_COMB_ADD_CLAMP (0 << 12) |
||
1198 | # define R128_ALPHA_COMB_ADD_NO_CLAMP (1 << 12) |
||
1199 | # define R128_ALPHA_COMB_SUB_SRC_DST_CLAMP (2 << 12) |
||
1200 | # define R128_ALPHA_COMB_SUB_SRC_DST_NO_CLAMP (3 << 12) |
||
1201 | # define R128_FOG_VERTEX (0 << 14) |
||
1202 | # define R128_FOG_TABLE (1 << 14) |
||
1203 | # define R128_ALPHA_BLEND_SRC_ZERO (0 << 16) |
||
1204 | # define R128_ALPHA_BLEND_SRC_ONE (1 << 16) |
||
1205 | # define R128_ALPHA_BLEND_SRC_SRCCOLOR (2 << 16) |
||
1206 | # define R128_ALPHA_BLEND_SRC_INVSRCCOLOR (3 << 16) |
||
1207 | # define R128_ALPHA_BLEND_SRC_SRCALPHA (4 << 16) |
||
1208 | # define R128_ALPHA_BLEND_SRC_INVSRCALPHA (5 << 16) |
||
1209 | # define R128_ALPHA_BLEND_SRC_DESTALPHA (6 << 16) |
||
1210 | # define R128_ALPHA_BLEND_SRC_INVDESTALPHA (7 << 16) |
||
1211 | # define R128_ALPHA_BLEND_SRC_DESTCOLOR (8 << 16) |
||
1212 | # define R128_ALPHA_BLEND_SRC_INVDESTCOLOR (9 << 16) |
||
1213 | # define R128_ALPHA_BLEND_SRC_SRCALPHASAT (10 << 16) |
||
1214 | # define R128_ALPHA_BLEND_SRC_BOTHSRCALPHA (11 << 16) |
||
1215 | # define R128_ALPHA_BLEND_SRC_BOTHINVSRCALPHA (12 << 16) |
||
1216 | # define R128_ALPHA_BLEND_SRC_MASK (15 << 16) |
||
1217 | # define R128_ALPHA_BLEND_DST_ZERO (0 << 20) |
||
1218 | # define R128_ALPHA_BLEND_DST_ONE (1 << 20) |
||
1219 | # define R128_ALPHA_BLEND_DST_SRCCOLOR (2 << 20) |
||
1220 | # define R128_ALPHA_BLEND_DST_INVSRCCOLOR (3 << 20) |
||
1221 | # define R128_ALPHA_BLEND_DST_SRCALPHA (4 << 20) |
||
1222 | # define R128_ALPHA_BLEND_DST_INVSRCALPHA (5 << 20) |
||
1223 | # define R128_ALPHA_BLEND_DST_DESTALPHA (6 << 20) |
||
1224 | # define R128_ALPHA_BLEND_DST_INVDESTALPHA (7 << 20) |
||
1225 | # define R128_ALPHA_BLEND_DST_DESTCOLOR (8 << 20) |
||
1226 | # define R128_ALPHA_BLEND_DST_INVDESTCOLOR (9 << 20) |
||
1227 | # define R128_ALPHA_BLEND_DST_SRCALPHASAT (10 << 20) |
||
1228 | # define R128_ALPHA_BLEND_DST_MASK (15 << 20) |
||
1229 | # define R128_ALPHA_TEST_NEVER (0 << 24) |
||
1230 | # define R128_ALPHA_TEST_LESS (1 << 24) |
||
1231 | # define R128_ALPHA_TEST_LESSEQUAL (2 << 24) |
||
1232 | # define R128_ALPHA_TEST_EQUAL (3 << 24) |
||
1233 | # define R128_ALPHA_TEST_GREATEREQUAL (4 << 24) |
||
1234 | # define R128_ALPHA_TEST_GREATER (5 << 24) |
||
1235 | # define R128_ALPHA_TEST_NEQUAL (6 << 24) |
||
1236 | # define R128_ALPHA_TEST_ALWAYS (7 << 24) |
||
1237 | # define R128_ALPHA_TEST_MASK (7 << 24) |
||
1238 | #define R128_TEXTURE_CLR_CMP_CLR_C 0x1ca4 |
||
1239 | #define R128_TEXTURE_CLR_CMP_MSK_C 0x1ca8 |
||
1240 | #define R128_FOG_COLOR_C 0x1cac |
||
1241 | # define R128_FOG_BLUE_SHIFT 0 |
||
1242 | # define R128_FOG_GREEN_SHIFT 8 |
||
1243 | # define R128_FOG_RED_SHIFT 16 |
||
1244 | #define R128_PRIM_TEX_CNTL_C 0x1cb0 |
||
1245 | # define R128_MIN_BLEND_NEAREST (0 << 1) |
||
1246 | # define R128_MIN_BLEND_LINEAR (1 << 1) |
||
1247 | # define R128_MIN_BLEND_MIPNEAREST (2 << 1) |
||
1248 | # define R128_MIN_BLEND_MIPLINEAR (3 << 1) |
||
1249 | # define R128_MIN_BLEND_LINEARMIPNEAREST (4 << 1) |
||
1250 | # define R128_MIN_BLEND_LINEARMIPLINEAR (5 << 1) |
||
1251 | # define R128_MIN_BLEND_MASK (7 << 1) |
||
1252 | # define R128_MAG_BLEND_NEAREST (0 << 4) |
||
1253 | # define R128_MAG_BLEND_LINEAR (1 << 4) |
||
1254 | # define R128_MAG_BLEND_MASK (7 << 4) |
||
1255 | # define R128_MIP_MAP_DISABLE (1 << 7) |
||
1256 | # define R128_TEX_CLAMP_S_WRAP (0 << 8) |
||
1257 | # define R128_TEX_CLAMP_S_MIRROR (1 << 8) |
||
1258 | # define R128_TEX_CLAMP_S_CLAMP (2 << 8) |
||
1259 | # define R128_TEX_CLAMP_S_BORDER_COLOR (3 << 8) |
||
1260 | # define R128_TEX_CLAMP_S_MASK (3 << 8) |
||
1261 | # define R128_TEX_WRAP_S (1 << 10) |
||
1262 | # define R128_TEX_CLAMP_T_WRAP (0 << 11) |
||
1263 | # define R128_TEX_CLAMP_T_MIRROR (1 << 11) |
||
1264 | # define R128_TEX_CLAMP_T_CLAMP (2 << 11) |
||
1265 | # define R128_TEX_CLAMP_T_BORDER_COLOR (3 << 11) |
||
1266 | # define R128_TEX_CLAMP_T_MASK (3 << 11) |
||
1267 | # define R128_TEX_WRAP_T (1 << 13) |
||
1268 | # define R128_TEX_PERSPECTIVE_DISABLE (1 << 14) |
||
1269 | # define R128_DATATYPE_VQ (0 << 16) |
||
1270 | # define R128_DATATYPE_CI4 (1 << 16) |
||
1271 | # define R128_DATATYPE_CI8 (2 << 16) |
||
1272 | # define R128_DATATYPE_ARGB1555 (3 << 16) |
||
1273 | # define R128_DATATYPE_RGB565 (4 << 16) |
||
1274 | # define R128_DATATYPE_RGB888 (5 << 16) |
||
1275 | # define R128_DATATYPE_ARGB8888 (6 << 16) |
||
1276 | # define R128_DATATYPE_RGB332 (7 << 16) |
||
1277 | # define R128_DATATYPE_Y8 (8 << 16) |
||
1278 | # define R128_DATATYPE_RGB8 (9 << 16) |
||
1279 | # define R128_DATATYPE_CI16 (10 << 16) |
||
1280 | # define R128_DATATYPE_YUV422 (11 << 16) |
||
1281 | # define R128_DATATYPE_YUV422_2 (12 << 16) |
||
1282 | # define R128_DATATYPE_AYUV444 (14 << 16) |
||
1283 | # define R128_DATATYPE_ARGB4444 (15 << 16) |
||
1284 | # define R128_PALLETE_EITHER (0 << 20) |
||
1285 | # define R128_PALLETE_1 (1 << 20) |
||
1286 | # define R128_PALLETE_2 (2 << 20) |
||
1287 | # define R128_PSEUDOCOLOR_DT_RGB565 (0 << 24) |
||
1288 | # define R128_PSEUDOCOLOR_DT_ARGB1555 (1 << 24) |
||
1289 | # define R128_PSEUDOCOLOR_DT_ARGB4444 (2 << 24) |
||
1290 | #define R128_PRIM_TEXTURE_COMBINE_CNTL_C 0x1cb4 |
||
1291 | # define R128_COMB_DIS (0 << 0) |
||
1292 | # define R128_COMB_COPY (1 << 0) |
||
1293 | # define R128_COMB_COPY_INP (2 << 0) |
||
1294 | # define R128_COMB_MODULATE (3 << 0) |
||
1295 | # define R128_COMB_MODULATE2X (4 << 0) |
||
1296 | # define R128_COMB_MODULATE4X (5 << 0) |
||
1297 | # define R128_COMB_ADD (6 << 0) |
||
1298 | # define R128_COMB_ADD_SIGNED (7 << 0) |
||
1299 | # define R128_COMB_BLEND_VERTEX (8 << 0) |
||
1300 | # define R128_COMB_BLEND_TEXTURE (9 << 0) |
||
1301 | # define R128_COMB_BLEND_CONST (10 << 0) |
||
1302 | # define R128_COMB_BLEND_PREMULT (11 << 0) |
||
1303 | # define R128_COMB_BLEND_PREV (12 << 0) |
||
1304 | # define R128_COMB_BLEND_PREMULT_INV (13 << 0) |
||
1305 | # define R128_COMB_ADD_SIGNED2X (14 << 0) |
||
1306 | # define R128_COMB_BLEND_CONST_COLOR (15 << 0) |
||
1307 | # define R128_COMB_MASK (15 << 0) |
||
1308 | # define R128_COLOR_FACTOR_TEX (4 << 4) |
||
1309 | # define R128_COLOR_FACTOR_NTEX (5 << 4) |
||
1310 | # define R128_COLOR_FACTOR_ALPHA (6 << 4) |
||
1311 | # define R128_COLOR_FACTOR_NALPHA (7 << 4) |
||
1312 | # define R128_COLOR_FACTOR_MASK (15 << 4) |
||
1313 | # define R128_INPUT_FACTOR_CONST_COLOR (2 << 10) |
||
1314 | # define R128_INPUT_FACTOR_CONST_ALPHA (3 << 10) |
||
1315 | # define R128_INPUT_FACTOR_INT_COLOR (4 << 10) |
||
1316 | # define R128_INPUT_FACTOR_INT_ALPHA (5 << 10) |
||
1317 | # define R128_INPUT_FACTOR_MASK (15 << 10) |
||
1318 | # define R128_COMB_ALPHA_DIS (0 << 14) |
||
1319 | # define R128_COMB_ALPHA_COPY (1 << 14) |
||
1320 | # define R128_COMB_ALPHA_COPY_INP (2 << 14) |
||
1321 | # define R128_COMB_ALPHA_MODULATE (3 << 14) |
||
1322 | # define R128_COMB_ALPHA_MODULATE2X (4 << 14) |
||
1323 | # define R128_COMB_ALPHA_MODULATE4X (5 << 14) |
||
1324 | # define R128_COMB_ALPHA_ADD (6 << 14) |
||
1325 | # define R128_COMB_ALPHA_ADD_SIGNED (7 << 14) |
||
1326 | # define R128_COMB_ALPHA_ADD_SIGNED2X (14 << 14) |
||
1327 | # define R128_COMB_ALPHA_MASK (15 << 14) |
||
1328 | # define R128_ALPHA_FACTOR_TEX_ALPHA (6 << 18) |
||
1329 | # define R128_ALPHA_FACTOR_NTEX_ALPHA (7 << 18) |
||
1330 | # define R128_ALPHA_FACTOR_MASK (15 << 18) |
||
1331 | # define R128_INP_FACTOR_A_CONST_ALPHA (1 << 25) |
||
1332 | # define R128_INP_FACTOR_A_INT_ALPHA (2 << 25) |
||
1333 | # define R128_INP_FACTOR_A_MASK (7 << 25) |
||
1334 | #define R128_TEX_SIZE_PITCH_C 0x1cb8 |
||
1335 | # define R128_TEX_PITCH_SHIFT 0 |
||
1336 | # define R128_TEX_SIZE_SHIFT 4 |
||
1337 | # define R128_TEX_HEIGHT_SHIFT 8 |
||
1338 | # define R128_TEX_MIN_SIZE_SHIFT 12 |
||
1339 | # define R128_SEC_TEX_PITCH_SHIFT 16 |
||
1340 | # define R128_SEC_TEX_SIZE_SHIFT 20 |
||
1341 | # define R128_SEC_TEX_HEIGHT_SHIFT 24 |
||
1342 | # define R128_SEC_TEX_MIN_SIZE_SHIFT 28 |
||
1343 | # define R128_TEX_PITCH_MASK (0x0f << 0) |
||
1344 | # define R128_TEX_SIZE_MASK (0x0f << 4) |
||
1345 | # define R128_TEX_HEIGHT_MASK (0x0f << 8) |
||
1346 | # define R128_TEX_MIN_SIZE_MASK (0x0f << 12) |
||
1347 | # define R128_SEC_TEX_PITCH_MASK (0x0f << 16) |
||
1348 | # define R128_SEC_TEX_SIZE_MASK (0x0f << 20) |
||
1349 | # define R128_SEC_TEX_HEIGHT_MASK (0x0f << 24) |
||
1350 | # define R128_SEC_TEX_MIN_SIZE_MASK (0x0f << 28) |
||
1351 | # define R128_TEX_SIZE_PITCH_SHIFT 0 |
||
1352 | # define R128_SEC_TEX_SIZE_PITCH_SHIFT 16 |
||
1353 | # define R128_TEX_SIZE_PITCH_MASK (0xffff << 0) |
||
1354 | # define R128_SEC_TEX_SIZE_PITCH_MASK (0xffff << 16) |
||
1355 | #define R128_PRIM_TEX_0_OFFSET_C 0x1cbc |
||
1356 | #define R128_PRIM_TEX_1_OFFSET_C 0x1cc0 |
||
1357 | #define R128_PRIM_TEX_2_OFFSET_C 0x1cc4 |
||
1358 | #define R128_PRIM_TEX_3_OFFSET_C 0x1cc8 |
||
1359 | #define R128_PRIM_TEX_4_OFFSET_C 0x1ccc |
||
1360 | #define R128_PRIM_TEX_5_OFFSET_C 0x1cd0 |
||
1361 | #define R128_PRIM_TEX_6_OFFSET_C 0x1cd4 |
||
1362 | #define R128_PRIM_TEX_7_OFFSET_C 0x1cd8 |
||
1363 | #define R128_PRIM_TEX_8_OFFSET_C 0x1cdc |
||
1364 | #define R128_PRIM_TEX_9_OFFSET_C 0x1ce0 |
||
1365 | #define R128_PRIM_TEX_10_OFFSET_C 0x1ce4 |
||
1366 | # define R128_TEX_NO_TILE (0 << 30) |
||
1367 | # define R128_TEX_TILED_BY_HOST (1 << 30) |
||
1368 | # define R128_TEX_TILED_BY_STORAGE (2 << 30) |
||
1369 | # define R128_TEX_TILED_BY_STORAGE2 (3 << 30) |
||
1370 | |||
1371 | #define R128_SEC_TEX_CNTL_C 0x1d00 |
||
1372 | # define R128_SEC_SELECT_PRIM_ST (0 << 0) |
||
1373 | # define R128_SEC_SELECT_SEC_ST (1 << 0) |
||
1374 | #define R128_SEC_TEX_COMBINE_CNTL_C 0x1d04 |
||
1375 | # define R128_INPUT_FACTOR_PREV_COLOR (8 << 10) |
||
1376 | # define R128_INPUT_FACTOR_PREV_ALPHA (9 << 10) |
||
1377 | # define R128_INP_FACTOR_A_PREV_ALPHA (4 << 25) |
||
1378 | #define R128_SEC_TEX_0_OFFSET_C 0x1d08 |
||
1379 | #define R128_SEC_TEX_1_OFFSET_C 0x1d0c |
||
1380 | #define R128_SEC_TEX_2_OFFSET_C 0x1d10 |
||
1381 | #define R128_SEC_TEX_3_OFFSET_C 0x1d14 |
||
1382 | #define R128_SEC_TEX_4_OFFSET_C 0x1d18 |
||
1383 | #define R128_SEC_TEX_5_OFFSET_C 0x1d1c |
||
1384 | #define R128_SEC_TEX_6_OFFSET_C 0x1d20 |
||
1385 | #define R128_SEC_TEX_7_OFFSET_C 0x1d24 |
||
1386 | #define R128_SEC_TEX_8_OFFSET_C 0x1d28 |
||
1387 | #define R128_SEC_TEX_9_OFFSET_C 0x1d2c |
||
1388 | #define R128_SEC_TEX_10_OFFSET_C 0x1d30 |
||
1389 | #define R128_CONSTANT_COLOR_C 0x1d34 |
||
1390 | # define R128_CONSTANT_BLUE_SHIFT 0 |
||
1391 | # define R128_CONSTANT_GREEN_SHIFT 8 |
||
1392 | # define R128_CONSTANT_RED_SHIFT 16 |
||
1393 | # define R128_CONSTANT_ALPHA_SHIFT 24 |
||
1394 | #define R128_PRIM_TEXTURE_BORDER_COLOR_C 0x1d38 |
||
1395 | # define R128_PRIM_TEX_BORDER_BLUE_SHIFT 0 |
||
1396 | # define R128_PRIM_TEX_BORDER_GREEN_SHIFT 8 |
||
1397 | # define R128_PRIM_TEX_BORDER_RED_SHIFT 16 |
||
1398 | # define R128_PRIM_TEX_BORDER_ALPHA_SHIFT 24 |
||
1399 | #define R128_SEC_TEXTURE_BORDER_COLOR_C 0x1d3c |
||
1400 | # define R128_SEC_TEX_BORDER_BLUE_SHIFT 0 |
||
1401 | # define R128_SEC_TEX_BORDER_GREEN_SHIFT 8 |
||
1402 | # define R128_SEC_TEX_BORDER_RED_SHIFT 16 |
||
1403 | # define R128_SEC_TEX_BORDER_ALPHA_SHIFT 24 |
||
1404 | #define R128_STEN_REF_MASK_C 0x1d40 |
||
1405 | # define R128_STEN_REFERENCE_SHIFT 0 |
||
1406 | # define R128_STEN_MASK_SHIFT 16 |
||
1407 | # define R128_STEN_WRITE_MASK_SHIFT 24 |
||
1408 | #define R128_PLANE_3D_MASK_C 0x1d44 |
||
1409 | #define R128_TEX_CACHE_STAT_COUNT 0x1974 |
||
1410 | |||
1411 | |||
1412 | /* Constants */ |
||
1413 | #define R128_AGP_TEX_OFFSET 0x02000000 |
||
1414 | |||
1415 | #define R128_LAST_FRAME_REG R128_GUI_SCRATCH_REG0 |
||
1416 | |||
1417 | /* CCE packet types */ |
||
1418 | #define R128_CCE_PACKET0 0x00000000 |
||
1419 | #define R128_CCE_PACKET0_ONE_REG_WR 0x00008000 |
||
1420 | #define R128_CCE_PACKET1 0x40000000 |
||
1421 | #define R128_CCE_PACKET2 0x80000000 |
||
1422 | #define R128_CCE_PACKET3 0xC0000000 |
||
1423 | #define R128_CCE_PACKET3_NOP 0xC0001000 |
||
1424 | #define R128_CCE_PACKET3_PAINT 0xC0001100 |
||
1425 | #define R128_CCE_PACKET3_BITBLT 0xC0001200 |
||
1426 | #define R128_CCE_PACKET3_SMALLTEXT 0xC0001300 |
||
1427 | #define R128_CCE_PACKET3_HOSTDATA_BLT 0xC0001400 |
||
1428 | #define R128_CCE_PACKET3_POLYLINE 0xC0001500 |
||
1429 | #define R128_CCE_PACKET3_SCALING 0xC0001600 |
||
1430 | #define R128_CCE_PACKET3_TRANS_SCALING 0xC0001700 |
||
1431 | #define R128_CCE_PACKET3_POLYSCANLINES 0xC0001800 |
||
1432 | #define R128_CCE_PACKET3_NEXT_CHAR 0xC0001900 |
||
1433 | #define R128_CCE_PACKET3_PAINT_MULTI 0xC0001A00 |
||
1434 | #define R128_CCE_PACKET3_BITBLT_MULTI 0xC0001B00 |
||
1435 | #define R128_CCE_PACKET3_PLY_NEXTSCAN 0xC0001D00 |
||
1436 | #define R128_CCE_PACKET3_SET_SCISSORS 0xC0001E00 |
||
1437 | #define R128_CCE_PACKET3_SET_MODE24BPP 0xC0001F00 |
||
1438 | #define R128_CCE_PACKET3_CNTL_PAINT 0xC0009100 |
||
1439 | #define R128_CCE_PACKET3_CNTL_BITBLT 0xC0009200 |
||
1440 | #define R128_CCE_PACKET3_CNTL_SMALLTEXT 0xC0009300 |
||
1441 | #define R128_CCE_PACKET3_CNTL_HOSTDATA_BLT 0xC0009400 |
||
1442 | #define R128_CCE_PACKET3_CNTL_POLYLINE 0xC0009500 |
||
1443 | #define R128_CCE_PACKET3_CNTL_SCALING 0xC0009600 |
||
1444 | #define R128_CCE_PACKET3_CNTL_TRANS_SCALING 0xC0009700 |
||
1445 | #define R128_CCE_PACKET3_CNTL_POLYSCANLINES 0xC0009800 |
||
1446 | #define R128_CCE_PACKET3_CNTL_NEXT_CHAR 0xC0009900 |
||
1447 | #define R128_CCE_PACKET3_CNTL_PAINT_MULTI 0xC0009A00 |
||
1448 | #define R128_CCE_PACKET3_CNTL_BITBLT_MULTI 0xC0009B00 |
||
1449 | #define R128_CCE_PACKET3_CNTL_TRANS_BITBLT 0xC0009C00 |
||
1450 | #define R128_CCE_PACKET3_3D_SAVE_CONTEXT 0xC0002000 |
||
1451 | #define R128_CCE_PACKET3_3D_PLAY_CONTEXT 0xC0002100 |
||
1452 | #define R128_CCE_PACKET3_3D_RNDR_GEN_INDX_PRIM 0xC0002300 |
||
1453 | #define R128_CCE_PACKET3_3D_RNDR_GEN_PRIM 0xC0002500 |
||
1454 | #define R128_CCE_PACKET3_LOAD_PALETTE 0xC0002C00 |
||
1455 | #define R128_CCE_PACKET3_PURGE 0xC0002D00 |
||
1456 | #define R128_CCE_PACKET3_NEXT_VERTEX_BUNDLE 0xC0002E00 |
||
1457 | # define R128_CCE_PACKET_MASK 0xC0000000 |
||
1458 | # define R128_CCE_PACKET_COUNT_MASK 0x3fff0000 |
||
1459 | # define R128_CCE_PACKET_MAX_DWORDS (1 << 12) |
||
1460 | # define R128_CCE_PACKET0_REG_MASK 0x000007ff |
||
1461 | # define R128_CCE_PACKET1_REG0_MASK 0x000007ff |
||
1462 | # define R128_CCE_PACKET1_REG1_MASK 0x003ff800 |
||
1463 | |||
1464 | #define R128_CCE_VC_FRMT_RHW 0x00000001 |
||
1465 | #define R128_CCE_VC_FRMT_DIFFUSE_BGR 0x00000002 |
||
1466 | #define R128_CCE_VC_FRMT_DIFFUSE_A 0x00000004 |
||
1467 | #define R128_CCE_VC_FRMT_DIFFUSE_ARGB 0x00000008 |
||
1468 | #define R128_CCE_VC_FRMT_SPEC_BGR 0x00000010 |
||
1469 | #define R128_CCE_VC_FRMT_SPEC_F 0x00000020 |
||
1470 | #define R128_CCE_VC_FRMT_SPEC_FRGB 0x00000040 |
||
1471 | #define R128_CCE_VC_FRMT_S_T 0x00000080 |
||
1472 | #define R128_CCE_VC_FRMT_S2_T2 0x00000100 |
||
1473 | #define R128_CCE_VC_FRMT_RHW2 0x00000200 |
||
1474 | |||
1475 | #define R128_CCE_VC_CNTL_PRIM_TYPE_NONE 0x00000000 |
||
1476 | #define R128_CCE_VC_CNTL_PRIM_TYPE_POINT 0x00000001 |
||
1477 | #define R128_CCE_VC_CNTL_PRIM_TYPE_LINE 0x00000002 |
||
1478 | #define R128_CCE_VC_CNTL_PRIM_TYPE_POLY_LINE 0x00000003 |
||
1479 | #define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_LIST 0x00000004 |
||
1480 | #define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_FAN 0x00000005 |
||
1481 | #define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_STRIP 0x00000006 |
||
1482 | #define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_TYPE2 0x00000007 |
||
1483 | #define R128_CCE_VC_CNTL_PRIM_WALK_IND 0x00000010 |
||
1484 | #define R128_CCE_VC_CNTL_PRIM_WALK_LIST 0x00000020 |
||
1485 | #define R128_CCE_VC_CNTL_PRIM_WALK_RING 0x00000030 |
||
1486 | #define R128_CCE_VC_CNTL_NUM_SHIFT 16 |
||
1487 | |||
1488 | #define RADEON_DAC_CNTL2 0x007c |
||
1489 | #define RADEON_CRTC_MORE_CNTL 0x027c |
||
1490 | #define RADEON_DAC_EXT_CNTL 0x0280 |
||
1491 | #define RADEON_GRPH_BUF_CNTL 0x02f0 |
||
1492 | #define RADEON_VGA_BUF_CNTL 0x02f4 |
||
1493 | |||
1494 | #define RADEON_SURFACE_CNTL 0x0b00 |
||
1495 | |||
1496 | #define RADEON_VCLK_SRC_SEL_MASK 0x0003 |
||
1497 | #define RADEON_VCLK_SRC_SEL_CPUCLK 0x0000 |
||
1498 | #define RADEON_VCLK_SRC_SEL_PPLLCLK 0x0003 |
||
1499 | |||
1500 | #define RADEON_BUS_READ_BURST (1<<30) |
||
1501 | #define RADEON_BUS_RD_DISCARD_EN (1<<24) |
||
1502 | |||
1503 | #define RADEON_SURF_TRANSLATION_DIS (1<<8) |
||
1504 | #endif |