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846 giacomo 1
/*
2
 * OHCI HCD (Host Controller Driver) for USB.
3
 *
4
 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
5
 * (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net>
6
 *
7
 * This file is licenced under the GPL.
8
 */
9
 
10
/*
11
 * OHCI Endpoint Descriptor (ED) ... holds TD queue
12
 * See OHCI spec, section 4.2
13
 *
14
 * This is a "Queue Head" for those transfers, which is why
15
 * both EHCI and UHCI call similar structures a "QH".
16
 */
17
struct ed {
18
        /* first fields are hardware-specified, le32 */
19
        __u32                   hwINFO;         /* endpoint config bitmap */
20
        /* info bits defined by hcd */
21
#define ED_DEQUEUE      __constant_cpu_to_le32(1 << 27)
22
        /* info bits defined by the hardware */
23
#define ED_ISO          __constant_cpu_to_le32(1 << 15)
24
#define ED_SKIP         __constant_cpu_to_le32(1 << 14)
25
#define ED_LOWSPEED     __constant_cpu_to_le32(1 << 13)
26
#define ED_OUT          __constant_cpu_to_le32(0x01 << 11)
27
#define ED_IN           __constant_cpu_to_le32(0x02 << 11)
28
        __u32                   hwTailP;        /* tail of TD list */
29
        __u32                   hwHeadP;        /* head of TD list (hc r/w) */
30
#define ED_C            __constant_cpu_to_le32(0x02)    /* toggle carry */
31
#define ED_H            __constant_cpu_to_le32(0x01)    /* halted */
32
        __u32                   hwNextED;       /* next ED in list */
33
 
34
        /* rest are purely for the driver's use */
35
        dma_addr_t              dma;            /* addr of ED */
36
        struct td               *dummy;         /* next TD to activate */
37
 
38
        /* host's view of schedule */
39
        struct ed               *ed_next;       /* on schedule or rm_list */
40
        struct ed               *ed_prev;       /* for non-interrupt EDs */
41
        struct list_head        td_list;        /* "shadow list" of our TDs */
42
 
43
        /* create --> IDLE --> OPER --> ... --> IDLE --> destroy
44
         * usually:  OPER --> UNLINK --> (IDLE | OPER) --> ...
45
         * some special cases :  OPER --> IDLE ...
46
         */
47
        u8                      state;          /* ED_{IDLE,UNLINK,OPER} */
48
#define ED_IDLE         0x00            /* NOT linked to HC */
49
#define ED_UNLINK       0x01            /* being unlinked from hc */
50
#define ED_OPER         0x02            /* IS linked to hc */
51
 
52
        u8                      type;           /* PIPE_{BULK,...} */
53
 
54
        /* periodic scheduling params (for intr and iso) */
55
        u8                      branch;
56
        u16                     interval;
57
        u16                     load;
58
        u16                     last_iso;       /* iso only */
59
 
60
        /* HC may see EDs on rm_list until next frame (frame_no == tick) */
61
        u16                     tick;
62
} __attribute__ ((aligned(16)));
63
 
64
#define ED_MASK ((u32)~0x0f)            /* strip hw status in low addr bits */
65
 
66
 
67
/*
68
 * OHCI Transfer Descriptor (TD) ... one per transfer segment
69
 * See OHCI spec, sections 4.3.1 (general = control/bulk/interrupt)
70
 * and 4.3.2 (iso)
71
 */
72
struct td {
73
        /* first fields are hardware-specified, le32 */
74
        __u32           hwINFO;         /* transfer info bitmask */
75
 
76
        /* hwINFO bits for both general and iso tds: */
77
#define TD_CC       0xf0000000                  /* condition code */
78
#define TD_CC_GET(td_p) ((td_p >>28) & 0x0f)
79
//#define TD_CC_SET(td_p, cc) (td_p) = ((td_p) & 0x0fffffff) | (((cc) & 0x0f) << 28)
80
#define TD_DI       0x00E00000                  /* frames before interrupt */
81
#define TD_DI_SET(X) (((X) & 0x07)<< 21)
82
        /* these two bits are available for definition/use by HCDs in both
83
         * general and iso tds ... others are available for only one type
84
         */
85
#define TD_DONE     0x00020000                  /* retired to donelist */
86
#define TD_ISO      0x00010000                  /* copy of ED_ISO */
87
 
88
        /* hwINFO bits for general tds: */
89
#define TD_EC       0x0C000000                  /* error count */
90
#define TD_T        0x03000000                  /* data toggle state */
91
#define TD_T_DATA0  0x02000000                          /* DATA0 */
92
#define TD_T_DATA1  0x03000000                          /* DATA1 */
93
#define TD_T_TOGGLE 0x00000000                          /* uses ED_C */
94
#define TD_DP       0x00180000                  /* direction/pid */
95
#define TD_DP_SETUP 0x00000000                  /* SETUP pid */
96
#define TD_DP_IN    0x00100000                          /* IN pid */
97
#define TD_DP_OUT   0x00080000                          /* OUT pid */
98
                                                        /* 0x00180000 rsvd */
99
#define TD_R        0x00040000                  /* round: short packets OK? */
100
 
101
        /* (no hwINFO #defines yet for iso tds) */
102
 
103
        __u32           hwCBP;          /* Current Buffer Pointer (or 0) */
104
        __u32           hwNextTD;       /* Next TD Pointer */
105
        __u32           hwBE;           /* Memory Buffer End Pointer */
106
 
107
        /* PSW is only for ISO */
108
#define MAXPSW 1                /* hardware allows 8 */
109
        __u16           hwPSW [MAXPSW];
110
 
111
        /* rest are purely for the driver's use */
112
        __u8            index;
113
        struct ed       *ed;
114
        struct td       *td_hash;       /* dma-->td hashtable */
115
        struct td       *next_dl_td;
116
        struct urb      *urb;
117
 
118
        dma_addr_t      td_dma;         /* addr of this TD */
119
        dma_addr_t      data_dma;       /* addr of data it points to */
120
 
121
        struct list_head td_list;       /* "shadow list", TDs on same ED */
122
} __attribute__ ((aligned(32)));        /* c/b/i need 16; only iso needs 32 */
123
 
124
#define TD_MASK ((u32)~0x1f)            /* strip hw status in low addr bits */
125
 
126
/*
127
 * Hardware transfer status codes -- CC from td->hwINFO or td->hwPSW
128
 */
129
#define TD_CC_NOERROR      0x00
130
#define TD_CC_CRC          0x01
131
#define TD_CC_BITSTUFFING  0x02
132
#define TD_CC_DATATOGGLEM  0x03
133
#define TD_CC_STALL        0x04
134
#define TD_DEVNOTRESP      0x05
135
#define TD_PIDCHECKFAIL    0x06
136
#define TD_UNEXPECTEDPID   0x07
137
#define TD_DATAOVERRUN     0x08
138
#define TD_DATAUNDERRUN    0x09
139
    /* 0x0A, 0x0B reserved for hardware */
140
#define TD_BUFFEROVERRUN   0x0C
141
#define TD_BUFFERUNDERRUN  0x0D
142
    /* 0x0E, 0x0F reserved for HCD */
143
#define TD_NOTACCESSED     0x0F
144
 
145
 
146
/* map OHCI TD status codes (CC) to errno values */
147
static const int cc_to_error [16] = {
148
        /* No  Error  */               0,
149
        /* CRC Error  */               -EILSEQ,
150
        /* Bit Stuff  */               -EPROTO,
151
        /* Data Togg  */               -EILSEQ,
152
        /* Stall      */               -EPIPE,
153
        /* DevNotResp */               -ETIMEDOUT,
154
        /* PIDCheck   */               -EPROTO,
155
        /* UnExpPID   */               -EPROTO,
156
        /* DataOver   */               -EOVERFLOW,
157
        /* DataUnder  */               -EREMOTEIO,
158
        /* (for hw)   */               -EIO,
159
        /* (for hw)   */               -EIO,
160
        /* BufferOver */               -ECOMM,
161
        /* BuffUnder  */               -ENOSR,
162
        /* (for HCD)  */               -EALREADY,
163
        /* (for HCD)  */               -EALREADY
164
};
165
 
166
 
167
/*
168
 * The HCCA (Host Controller Communications Area) is a 256 byte
169
 * structure defined section 4.4.1 of the OHCI spec. The HC is
170
 * told the base address of it.  It must be 256-byte aligned.
171
 */
172
struct ohci_hcca {
173
#define NUM_INTS 32
174
        __u32   int_table [NUM_INTS];   /* periodic schedule */
175
        __u16   frame_no;               /* current frame number */
176
        __u16   pad1;                   /* set to 0 on each frame_no change */
177
        __u32   done_head;              /* info returned for an interrupt */
178
        u8      reserved_for_hc [116];
179
        u8      what [4];               /* spec only identifies 252 bytes :) */
180
} __attribute__ ((aligned(256)));
181
 
182
 
183
/*
184
 * This is the structure of the OHCI controller's memory mapped I/O region.
185
 * You must use readl() and writel() (in <asm/io.h>) to access these fields!!
186
 * Layout is in section 7 (and appendix B) of the spec.
187
 */
188
struct ohci_regs {
189
        /* control and status registers (section 7.1) */
190
        __u32   revision;
191
        __u32   control;
192
        __u32   cmdstatus;
193
        __u32   intrstatus;
194
        __u32   intrenable;
195
        __u32   intrdisable;
196
 
197
        /* memory pointers (section 7.2) */
198
        __u32   hcca;
199
        __u32   ed_periodcurrent;
200
        __u32   ed_controlhead;
201
        __u32   ed_controlcurrent;
202
        __u32   ed_bulkhead;
203
        __u32   ed_bulkcurrent;
204
        __u32   donehead;
205
 
206
        /* frame counters (section 7.3) */
207
        __u32   fminterval;
208
        __u32   fmremaining;
209
        __u32   fmnumber;
210
        __u32   periodicstart;
211
        __u32   lsthresh;
212
 
213
        /* Root hub ports (section 7.4) */
214
        struct  ohci_roothub_regs {
215
                __u32   a;
216
                __u32   b;
217
                __u32   status;
218
#define MAX_ROOT_PORTS  15      /* maximum OHCI root hub ports (RH_A_NDP) */
219
                __u32   portstatus [MAX_ROOT_PORTS];
220
        } roothub;
221
 
222
        /* and optional "legacy support" registers (appendix B) at 0x0100 */
223
 
224
} __attribute__ ((aligned(32)));
225
 
226
 
227
/* OHCI CONTROL AND STATUS REGISTER MASKS */
228
 
229
/*
230
 * HcControl (control) register masks
231
 */
232
#define OHCI_CTRL_CBSR  (3 << 0)        /* control/bulk service ratio */
233
#define OHCI_CTRL_PLE   (1 << 2)        /* periodic list enable */
234
#define OHCI_CTRL_IE    (1 << 3)        /* isochronous enable */
235
#define OHCI_CTRL_CLE   (1 << 4)        /* control list enable */
236
#define OHCI_CTRL_BLE   (1 << 5)        /* bulk list enable */
237
#define OHCI_CTRL_HCFS  (3 << 6)        /* host controller functional state */
238
#define OHCI_CTRL_IR    (1 << 8)        /* interrupt routing */
239
#define OHCI_CTRL_RWC   (1 << 9)        /* remote wakeup connected */
240
#define OHCI_CTRL_RWE   (1 << 10)       /* remote wakeup enable */
241
 
242
/* pre-shifted values for HCFS */
243
#       define OHCI_USB_RESET   (0 << 6)
244
#       define OHCI_USB_RESUME  (1 << 6)
245
#       define OHCI_USB_OPER    (2 << 6)
246
#       define OHCI_USB_SUSPEND (3 << 6)
247
 
248
/*
249
 * HcCommandStatus (cmdstatus) register masks
250
 */
251
#define OHCI_HCR        (1 << 0)        /* host controller reset */
252
#define OHCI_CLF        (1 << 1)        /* control list filled */
253
#define OHCI_BLF        (1 << 2)        /* bulk list filled */
254
#define OHCI_OCR        (1 << 3)        /* ownership change request */
255
#define OHCI_SOC        (3 << 16)       /* scheduling overrun count */
256
 
257
/*
258
 * masks used with interrupt registers:
259
 * HcInterruptStatus (intrstatus)
260
 * HcInterruptEnable (intrenable)
261
 * HcInterruptDisable (intrdisable)
262
 */
263
#define OHCI_INTR_SO    (1 << 0)        /* scheduling overrun */
264
#define OHCI_INTR_WDH   (1 << 1)        /* writeback of done_head */
265
#define OHCI_INTR_SF    (1 << 2)        /* start frame */
266
#define OHCI_INTR_RD    (1 << 3)        /* resume detect */
267
#define OHCI_INTR_UE    (1 << 4)        /* unrecoverable error */
268
#define OHCI_INTR_FNO   (1 << 5)        /* frame number overflow */
269
#define OHCI_INTR_RHSC  (1 << 6)        /* root hub status change */
270
#define OHCI_INTR_OC    (1 << 30)       /* ownership change */
271
#define OHCI_INTR_MIE   (1 << 31)       /* master interrupt enable */
272
 
273
 
274
/* OHCI ROOT HUB REGISTER MASKS */
275
 
276
/* roothub.portstatus [i] bits */
277
#define RH_PS_CCS            0x00000001         /* current connect status */
278
#define RH_PS_PES            0x00000002         /* port enable status*/
279
#define RH_PS_PSS            0x00000004         /* port suspend status */
280
#define RH_PS_POCI           0x00000008         /* port over current indicator */
281
#define RH_PS_PRS            0x00000010         /* port reset status */
282
#define RH_PS_PPS            0x00000100         /* port power status */
283
#define RH_PS_LSDA           0x00000200         /* low speed device attached */
284
#define RH_PS_CSC            0x00010000         /* connect status change */
285
#define RH_PS_PESC           0x00020000         /* port enable status change */
286
#define RH_PS_PSSC           0x00040000         /* port suspend status change */
287
#define RH_PS_OCIC           0x00080000         /* over current indicator change */
288
#define RH_PS_PRSC           0x00100000         /* port reset status change */
289
 
290
/* roothub.status bits */
291
#define RH_HS_LPS            0x00000001         /* local power status */
292
#define RH_HS_OCI            0x00000002         /* over current indicator */
293
#define RH_HS_DRWE           0x00008000         /* device remote wakeup enable */
294
#define RH_HS_LPSC           0x00010000         /* local power status change */
295
#define RH_HS_OCIC           0x00020000         /* over current indicator change */
296
#define RH_HS_CRWE           0x80000000         /* clear remote wakeup enable */
297
 
298
/* roothub.b masks */
299
#define RH_B_DR         0x0000ffff              /* device removable flags */
300
#define RH_B_PPCM       0xffff0000              /* port power control mask */
301
 
302
/* roothub.a masks */
303
#define RH_A_NDP        (0xff << 0)             /* number of downstream ports */
304
#define RH_A_PSM        (1 << 8)                /* power switching mode */
305
#define RH_A_NPS        (1 << 9)                /* no power switching */
306
#define RH_A_DT         (1 << 10)               /* device type (mbz) */
307
#define RH_A_OCPM       (1 << 11)               /* over current protection mode */
308
#define RH_A_NOCP       (1 << 12)               /* no over current protection */
309
#define RH_A_POTPGT     (0xff << 24)            /* power on to power good time */
310
 
311
 
312
/* hcd-private per-urb state */
313
typedef struct urb_priv {
314
        struct ed               *ed;
315
        __u16                   length;         // # tds in this request
316
        __u16                   td_cnt;         // tds already serviced
317
        struct td               *td [0];        // all TDs in this request
318
 
319
} urb_priv_t;
320
 
321
#define TD_HASH_SIZE    64    /* power'o'two */
322
// sizeof (struct td) ~= 64 == 2^6 ... 
323
#define TD_HASH_FUNC(td_dma) ((td_dma ^ (td_dma >> 6)) % TD_HASH_SIZE)
324
 
325
 
326
/*
327
 * This is the full ohci controller description
328
 *
329
 * Note how the "proper" USB information is just
330
 * a subset of what the full implementation needs. (Linus)
331
 */
332
 
333
struct ohci_hcd {
334
        spinlock_t              lock;
335
 
336
        /*
337
         * I/O memory used to communicate with the HC (dma-consistent)
338
         */
339
        struct ohci_regs        *regs;
340
 
341
        /*
342
         * main memory used to communicate with the HC (dma-consistent).
343
         * hcd adds to schedule for a live hc any time, but removals finish
344
         * only at the start of the next frame.
345
         */
346
        struct ohci_hcca        *hcca;
347
        dma_addr_t              hcca_dma;
348
 
349
        struct ed               *ed_rm_list;            /* to be removed */
350
 
351
        struct ed               *ed_bulktail;           /* last in bulk list */
352
        struct ed               *ed_controltail;        /* last in ctrl list */
353
        struct ed               *periodic [NUM_INTS];   /* shadow int_table */
354
 
355
        /*
356
         * memory management for queue data structures
357
         */
358
        struct pci_pool         *td_cache;
359
        struct pci_pool         *ed_cache;
360
        struct td               *td_hash [TD_HASH_SIZE];
361
 
362
        /*
363
         * driver state
364
         */
365
        int                     load [NUM_INTS];
366
        u32                     hc_control;     /* copy of hc control reg */
367
 
368
        unsigned long           flags;          /* for HC bugs */
369
#define OHCI_QUIRK_AMD756       0x01                    /* erratum #4 */
370
#define OHCI_QUIRK_SUPERIO      0x02                    /* natsemi */
371
        // there are also chip quirks/bugs in init logic
372
 
373
        /*
374
         * framework state
375
         */
376
        struct usb_hcd          hcd;
377
};
378
 
379
#define hcd_to_ohci(hcd_ptr) container_of(hcd_ptr, struct ohci_hcd, hcd)
380
 
381
/*-------------------------------------------------------------------------*/
382
 
383
#ifndef DEBUG
384
#define STUB_DEBUG_FILES
385
#endif  /* DEBUG */
386
 
387
#define ohci_dbg(ohci, fmt, args...) \
388
        dev_dbg ((ohci)->hcd.controller , fmt , ## args )
389
#define ohci_err(ohci, fmt, args...) \
390
        dev_err ((ohci)->hcd.controller , fmt , ## args )
391
#define ohci_info(ohci, fmt, args...) \
392
        dev_info ((ohci)->hcd.controller , fmt , ## args )
393
#define ohci_warn(ohci, fmt, args...) \
394
        dev_warn ((ohci)->hcd.controller , fmt , ## args )
395
 
396
#ifdef OHCI_VERBOSE_DEBUG
397
#       define ohci_vdbg ohci_dbg
398
#else
399
#       define ohci_vdbg(ohci, fmt, args...) do { } while (0)
400
#endif
401