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120 giacomo 1
/* Project:     OSLib
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 * Description: The OS Construction Kit
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 * Date:                1.6.2000
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 * Idea by:             Luca Abeni & Gerardo Lamastra
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 *
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 * OSLib is an SO project aimed at developing a common, easy-to-use
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 * low-level infrastructure for developing OS kernels and Embedded
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 * Applications; it partially derives from the HARTIK project but it
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 * currently is independently developed.
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 *
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 * OSLib is distributed under GPL License, and some of its code has
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 * been derived from the Linux kernel source; also some important
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 * ideas come from studying the DJGPP go32 extender.
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 *
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 * We acknowledge the Linux Community, Free Software Foundation,
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 * D.J. Delorie and all the other developers who believe in the
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 * freedom of software and ideas.
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 *
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 * For legalese, check out the included GPL license.
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 */
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/*      Advanced Timer Managment
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 *      Author: Giacomo Guidi <giacomo@gandalf.sssup.it>
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 */
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#include <ll/i386/stdlib.h>
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#include <ll/i386/error.h>
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#include <ll/i386/advtimer.h>
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#include <ll/sys/ll/ll-data.h>
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#include <ll/sys/ll/ll-func.h>
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#include <ll/i386/pic.h>
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#include <ll/sys/ll/event.h>
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#include <ll/sys/ll/time.h>
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unsigned char use_tsc = 0; //Enable the TSC counter mode
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unsigned char use_cmos = 0; //Enable the RTC correction
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//Max single delta_clk_per_msec increment
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#define MAX_DELTA_INK 10 
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//Max delta_clk_per_msec before declare lost
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//the CMOS sync
121 giacomo 43
#define MAX_DELTA_TOT 1000
120 giacomo 44
 
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signed long long init_tsc;
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signed long long init_nsec; //Warp around 292 years !!
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signed long long clk_per_msec;
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signed long last_delta_clk_per_msec;
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signed long total_delta_clk_per_msec;
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unsigned char save_CMOS_regA;
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unsigned char save_CMOS_regB;
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void HandlerIRQ8(void *p)
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{
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   unsigned char set;
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   static unsigned long init_step = 0;
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   signed long long actual_tsc;
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   signed long long dt,dn;
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   signed long delta_clk_per_msec;
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   cli();
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   CMOS_READ(0x0C,set);
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   rdtscll(actual_tsc);
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   //Delta TSC
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   dt = actual_tsc - init_tsc;
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   init_tsc = actual_tsc;
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   UNSIGNED_TSC2NSEC(dt,&dn);
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   //Offset
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   init_nsec += dn;
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   if (init_step < 5) {
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           init_step++;
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           return;
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   }
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   dn = dn % 1000000000 - 500000000;
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   //Delta clk/msec
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   delta_clk_per_msec = dn * clk_per_msec / (500000000 - dn);
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   //clk_per_msec adjustment
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   if (delta_clk_per_msec < 0) {
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        if (delta_clk_per_msec > -MAX_DELTA_INK)
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                clk_per_msec += delta_clk_per_msec;
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        else
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                clk_per_msec -= MAX_DELTA_INK;
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   } else {
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        if (delta_clk_per_msec < MAX_DELTA_INK)
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                clk_per_msec += delta_clk_per_msec;
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        else
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                clk_per_msec += MAX_DELTA_INK;
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   }
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   if (delta_clk_per_msec > MAX_DELTA_TOT || delta_clk_per_msec < -MAX_DELTA_TOT) {
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           message("Error: Delta_clk_per_msec |%ld| > %ld\n",\
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                    (long)delta_clk_per_msec,(long)MAX_DELTA_TOT);
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           ll_abort(10);
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   }
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114
   last_delta_clk_per_msec = delta_clk_per_msec;
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   total_delta_clk_per_msec += delta_clk_per_msec;
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117
   sti();
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}
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#define HZ 100
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#ifdef CONFIG_MELAN
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#  define CLOCK_TICK_RATE 1189200 /* AMD Elan has different frequency! */
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#else
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#  define CLOCK_TICK_RATE 1193180 /* Underlying HZ */
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#endif
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#define LATCH  ((CLOCK_TICK_RATE + HZ/2) / HZ)
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#define CALIBRATE_LATCH (5 * LATCH)
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#define CALIBRATE_TIME  (5 * 1000020/HZ)
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//TSC Calibration (idea from the linux kernel code)
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void ll_calibrate_tsc(void)
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{
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        signed long long start;
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        signed long long end;
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        signed long long dtsc;
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        signed long start_8253, end_8253, delta_8253;
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        cli();
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        /* Set the Gate high, disable speaker */
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        outp(0x61, (inp(0x61) & ~0x02) | 0x01);
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        outp(0x43,0xB0);                        /* binary, mode 0, LSB/MSB, Ch 2 */
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        outp(0x42,CALIBRATE_LATCH & 0xff);      /* LSB of count */
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        outp(0x42,CALIBRATE_LATCH >> 8);        /* MSB of count */
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        rdtscll(start);
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        outp(0x43,0x00);
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        start_8253 = inp(0x42);
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        start_8253 |= inp(0x42) << 8;          
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        do {
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            outp(0x43,0x00);
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            end_8253 = inp(0x42);
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            end_8253 |= inp(0x42) << 8;
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        } while (end_8253 > 10);
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        rdtscll(end);
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        outp(0x43,0x00);
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        end_8253 = inp(0x42);
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        end_8253 |= inp(0x42) << 8;
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        //Delta TSC
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        dtsc = end - start;
173
 
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        //Delta PIT
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        delta_8253 = start_8253 - end_8253 + 1;
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        if (delta_8253 > 0xFFFF) {
178
                message("Error calculating Delta PIT\n");
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                ll_abort(10);
180
        }
181
 
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        message("Delta TSC               = %10ld\n",(long)dtsc);
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        message("Delta PIT               = %10ld\n",(long)delta_8253);
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186
        clk_per_msec = dtsc * CALIBRATE_LATCH * 1000 / delta_8253 / CALIBRATE_TIME;
187
 
188
        message("Calibrated Clk_per_msec = %10ld\n",(long)clk_per_msec);
189
 
190
        sti();
191
 
192
}
193
 
194
//Low level time read function
195
void read_timespec(struct timespec *tspec)
196
{
197
 
198
    signed long long actual_tsc;
199
    signed long long dt,dn;
200
 
201
    rdtscll(actual_tsc);
202
 
203
    tspec->tsc = actual_tsc;
204
 
205
    dt = actual_tsc - init_tsc;
206
 
207
    UNSIGNED_TSC2NSEC(dt,&dn);
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209
    tspec->tv_sec = (init_nsec + dn) / 1000000000;
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    tspec->tv_nsec = (init_nsec + dn) % 1000000000;
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212
}
213
 
214
void ll_init_advtimer()
215
{
216
 
217
    if (use_tsc) {
218
 
219
        ll_calibrate_tsc();
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221
        last_delta_clk_per_msec = 0;
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        total_delta_clk_per_msec = 0;
223
 
224
        rdtscll(init_tsc); // Read start TSC
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        init_nsec = 0;
226
 
227
        if (use_cmos) {
228
 
229
            message("CMOS adjustment enabled\n");
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231
            cli();         
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233
            irq_bind(8, HandlerIRQ8, INT_FORCE);
234
 
235
            CMOS_READ(0x0A,save_CMOS_regA);
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            CMOS_READ(0x0B,save_CMOS_regB);
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238
            CMOS_WRITE(0x0A,0x2F); // Set 2 Hz Periodic Interrupt
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            CMOS_WRITE(0x0B,0x42); // Enable Interrupt
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241
            irq_unmask(8);
242
 
243
            sti();
244
 
245
        }
246
 
247
    } else {
248
 
249
        use_cmos = 0;
250
 
251
   }
252
 
253
}
254
 
255
void restore_CMOS()
256
{
257
        if (use_cmos) {
258
                cli();
259
 
260
                irq_mask(8);
261
 
262
                CMOS_WRITE(0x0A,save_CMOS_regA);
263
                CMOS_WRITE(0x0B,save_CMOS_regB);
264
 
265
                sti();         
266
        }
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}