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Rev | Author | Line No. | Line |
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120 | giacomo | 1 | /* Project: OSLib |
2 | * Description: The OS Construction Kit |
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3 | * Date: 1.6.2000 |
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4 | * Idea by: Luca Abeni & Gerardo Lamastra |
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5 | * |
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6 | * OSLib is an SO project aimed at developing a common, easy-to-use |
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7 | * low-level infrastructure for developing OS kernels and Embedded |
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8 | * Applications; it partially derives from the HARTIK project but it |
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9 | * currently is independently developed. |
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10 | * |
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11 | * OSLib is distributed under GPL License, and some of its code has |
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12 | * been derived from the Linux kernel source; also some important |
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13 | * ideas come from studying the DJGPP go32 extender. |
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14 | * |
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15 | * We acknowledge the Linux Community, Free Software Foundation, |
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16 | * D.J. Delorie and all the other developers who believe in the |
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17 | * freedom of software and ideas. |
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18 | * |
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19 | * For legalese, check out the included GPL license. |
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20 | */ |
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21 | |||
22 | /* Advanced Timer Managment |
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23 | * Author: Giacomo Guidi <giacomo@gandalf.sssup.it> |
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24 | */ |
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25 | |||
26 | #include <ll/i386/stdlib.h> |
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27 | #include <ll/i386/error.h> |
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28 | #include <ll/i386/advtimer.h> |
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29 | #include <ll/sys/ll/ll-data.h> |
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30 | #include <ll/sys/ll/ll-func.h> |
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31 | #include <ll/i386/pic.h> |
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299 | giacomo | 32 | #include <ll/i386/apic.h> |
120 | giacomo | 33 | #include <ll/sys/ll/event.h> |
34 | #include <ll/sys/ll/time.h> |
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35 | |||
264 | giacomo | 36 | #define CALIBRATE_USING_CMOS |
37 | |||
130 | giacomo | 38 | unsigned char use_tsc = 1; //Enable the TSC counter mode |
120 | giacomo | 39 | unsigned char use_cmos = 0; //Enable the RTC correction |
304 | giacomo | 40 | unsigned char use_apic = 0; //Enable the APIC for P6 only |
120 | giacomo | 41 | |
126 | giacomo | 42 | //Max single delta_clk_per_msec increment = clk_per_msec / MAX_DIV_INK; |
43 | #define MAX_DIV_INK 30000 |
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120 | giacomo | 44 | |
45 | signed long long init_tsc; |
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194 | giacomo | 46 | signed long long * ptr_init_tsc = &init_tsc; |
47 | |||
238 | giacomo | 48 | signed long long init_nsec; //Wraparound 292 years |
194 | giacomo | 49 | signed long long * ptr_init_nsec = &init_nsec; |
50 | |||
120 | giacomo | 51 | signed long long clk_per_msec; |
194 | giacomo | 52 | signed long long * ptr_clk_per_msec = &clk_per_msec; |
120 | giacomo | 53 | |
299 | giacomo | 54 | signed long long apic_clk_per_msec; |
303 | giacomo | 55 | unsigned int apic_set_limit; |
299 | giacomo | 56 | |
120 | giacomo | 57 | signed long last_delta_clk_per_msec; |
58 | signed long total_delta_clk_per_msec; |
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59 | |||
60 | unsigned char save_CMOS_regA; |
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61 | unsigned char save_CMOS_regB; |
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62 | |||
242 | giacomo | 63 | //#define IRQ8_DEBUG |
64 | |||
120 | giacomo | 65 | void HandlerIRQ8(void *p) |
66 | { |
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67 | |||
68 | unsigned char set; |
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194 | giacomo | 69 | |
70 | static unsigned long Mconst = 1000000; |
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120 | giacomo | 71 | |
72 | static unsigned long init_step = 0; |
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73 | |||
126 | giacomo | 74 | signed long max_dcms = clk_per_msec / MAX_DIV_INK; |
120 | giacomo | 75 | |
194 | giacomo | 76 | static signed long long dn; |
77 | static signed long long * ptr_dn = &dn; |
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120 | giacomo | 78 | signed long delta_clk_per_msec; |
126 | giacomo | 79 | |
120 | giacomo | 80 | cli(); |
242 | giacomo | 81 | |
82 | #ifdef IRQ8_DEBUG |
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83 | message("(IRQ8"); |
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84 | #endif |
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85 | |||
120 | giacomo | 86 | CMOS_READ(0x0C,set); |
194 | giacomo | 87 | |
242 | giacomo | 88 | __asm__("xorl %%eax,%%eax\n\t" |
89 | "cpuid\n\t" |
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90 | "rdtsc\n\t" |
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194 | giacomo | 91 | "pushl %%eax\n\t" |
92 | "pushl %%edx\n\t" |
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242 | giacomo | 93 | "pushl %%eax\n\t" |
94 | "pushl %%edx\n\t" |
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95 | "xorl %%eax,%%eax\n\t" |
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96 | "cpuid\n\t" |
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97 | "popl %%edx\n\t" |
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98 | "popl %%eax\n\t" |
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194 | giacomo | 99 | "subl (%%edi),%%eax\n\t" |
100 | "sbbl 4(%%edi),%%edx\n\t" |
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101 | "popl 4(%%edi)\n\t" |
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102 | "popl (%%edi)\n\t" |
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103 | "movl %%edx,%%ecx\n\t" |
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104 | "mull %4\n\t" |
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105 | "pushl %%eax\n\t" |
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106 | "movl %%ecx,%%eax\n\t" |
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107 | "movl %%edx,%%ecx\n\t" |
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108 | "mull %4\n\t" |
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109 | "addl %%ecx,%%eax\n\t" |
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110 | "adcl $0,%%edx\n\t" |
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242 | giacomo | 111 | "movl %7,%%ebx\n\t" |
194 | giacomo | 112 | "divl (%%ebx)\n\t" |
113 | "movl %%eax,4(%%esi)\n\t" |
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114 | "popl %%eax\n\t" |
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115 | "divl (%%ebx)\n\t" |
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116 | "movl %%eax,(%%esi)\n\t" |
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117 | |||
118 | : |
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242 | giacomo | 119 | : "D" (ptr_init_tsc), "S" (ptr_dn), "b" (0), |
120 | "c" (0), "m" (Mconst), "a" (0), "d" (0), "m" (ptr_clk_per_msec)); |
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120 | giacomo | 121 | |
122 | //Offset |
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123 | init_nsec += dn; |
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194 | giacomo | 124 | |
120 | giacomo | 125 | if (init_step < 5) { |
126 | init_step++; |
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242 | giacomo | 127 | #ifdef IRQ8_DEBUG |
128 | message(")"); |
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129 | #endif |
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130 | |||
244 | giacomo | 131 | sti(); |
132 | |||
120 | giacomo | 133 | return; |
134 | } |
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135 | |||
136 | dn = dn % 1000000000 - 500000000; |
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137 | |||
138 | //Delta clk/msec |
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139 | delta_clk_per_msec = dn * clk_per_msec / (500000000 - dn); |
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140 | |||
141 | //clk_per_msec adjustment |
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142 | if (delta_clk_per_msec < 0) { |
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143 | |||
126 | giacomo | 144 | if (delta_clk_per_msec > -max_dcms) |
120 | giacomo | 145 | clk_per_msec += delta_clk_per_msec; |
146 | else |
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126 | giacomo | 147 | clk_per_msec -= max_dcms; |
120 | giacomo | 148 | } else { |
149 | |||
126 | giacomo | 150 | if (delta_clk_per_msec < max_dcms) |
120 | giacomo | 151 | clk_per_msec += delta_clk_per_msec; |
152 | else |
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126 | giacomo | 153 | clk_per_msec += max_dcms; |
120 | giacomo | 154 | } |
155 | |||
156 | last_delta_clk_per_msec = delta_clk_per_msec; |
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157 | total_delta_clk_per_msec += delta_clk_per_msec; |
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158 | |||
242 | giacomo | 159 | #ifdef IRQ8_DEBUG |
160 | message(")"); |
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161 | #endif |
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162 | |||
120 | giacomo | 163 | sti(); |
164 | |||
165 | } |
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166 | |||
167 | #ifdef CONFIG_MELAN |
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168 | # define CLOCK_TICK_RATE 1189200 /* AMD Elan has different frequency! */ |
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169 | #else |
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249 | giacomo | 170 | # define CLOCK_TICK_RATE 1193182 /* Underlying HZ */ |
120 | giacomo | 171 | #endif |
172 | |||
248 | giacomo | 173 | #define COUNTER_END 100 |
120 | giacomo | 174 | |
245 | giacomo | 175 | #define barrier() __asm__ __volatile__("" ::: "memory"); |
176 | |||
120 | giacomo | 177 | //TSC Calibration (idea from the linux kernel code) |
178 | void ll_calibrate_tsc(void) |
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179 | { |
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180 | |||
181 | signed long long start; |
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182 | signed long long end; |
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244 | giacomo | 183 | signed long long dtsc; |
120 | giacomo | 184 | |
244 | giacomo | 185 | signed long start_8253, end_8253, delta_8253; |
120 | giacomo | 186 | |
187 | cli(); |
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188 | |||
248 | giacomo | 189 | outp(0x61, (inp(0x61) & ~0x02) | 0x01); |
120 | giacomo | 190 | |
191 | outp(0x43,0xB0); /* binary, mode 0, LSB/MSB, Ch 2 */ |
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238 | giacomo | 192 | outp(0x42,0xFF); /* LSB of count */ |
193 | outp(0x42,0xFF); /* MSB of count */ |
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242 | giacomo | 194 | |
245 | giacomo | 195 | barrier(); |
196 | rdtscll(start); |
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197 | barrier(); |
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243 | giacomo | 198 | outp(0x43,0x00); |
199 | start_8253 = inp(0x42); |
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200 | start_8253 |= inp(0x42) << 8; |
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245 | giacomo | 201 | barrier(); |
264 | giacomo | 202 | rdtscll(start); |
203 | barrier(); |
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243 | giacomo | 204 | |
205 | do { |
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206 | |||
207 | outp(0x43,0x00); |
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208 | end_8253 = inp(0x42); |
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209 | end_8253 |= inp(0x42) << 8; |
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210 | |||
211 | } while (end_8253 > COUNTER_END); |
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212 | |||
245 | giacomo | 213 | barrier(); |
214 | rdtscll(end); |
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215 | barrier(); |
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243 | giacomo | 216 | outp(0x43,0x00); |
217 | end_8253 = inp(0x42); |
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218 | end_8253 |= inp(0x42) << 8; |
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245 | giacomo | 219 | barrier(); |
264 | giacomo | 220 | rdtscll(end); |
221 | barrier(); |
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243 | giacomo | 222 | |
223 | //Delta TSC |
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244 | giacomo | 224 | dtsc = end - start; |
243 | giacomo | 225 | |
226 | //Delta PIT |
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264 | giacomo | 227 | delta_8253 = start_8253 - end_8253; |
243 | giacomo | 228 | |
242 | giacomo | 229 | if (delta_8253 > 0x20000) { |
120 | giacomo | 230 | message("Error calculating Delta PIT\n"); |
231 | ll_abort(10); |
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232 | } |
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233 | |||
234 | message("Delta TSC = %10ld\n",(long)dtsc); |
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235 | |||
236 | message("Delta PIT = %10ld\n",(long)delta_8253); |
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237 | |||
252 | giacomo | 238 | clk_per_msec = dtsc * CLOCK_TICK_RATE / delta_8253 / 1000; |
120 | giacomo | 239 | |
240 | message("Calibrated Clk_per_msec = %10ld\n",(long)clk_per_msec); |
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241 | |||
242 | sti(); |
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243 | |||
244 | } |
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245 | |||
264 | giacomo | 246 | #define CMOS_INIT 0 |
247 | #define CMOS_BEGIN 1 |
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248 | #define CMOS_START 2 |
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249 | #define CMOS_END 3 |
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250 | |||
251 | int cmos_calibrate_status = CMOS_INIT; |
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252 | signed long long irq8_start; |
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253 | signed long long irq8_end; |
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254 | |||
299 | giacomo | 255 | void calibrate_tsc_IRQ8(void *p) |
264 | giacomo | 256 | { |
257 | |||
258 | unsigned char set; |
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259 | |||
260 | cli(); |
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261 | |||
262 | CMOS_READ(0x0C,set); |
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263 | |||
264 | barrier(); |
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265 | rdtscll(irq8_end); |
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266 | barrier(); |
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267 | |||
268 | if (cmos_calibrate_status == CMOS_START) { |
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269 | cmos_calibrate_status = CMOS_END; |
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270 | } |
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271 | |||
272 | if (cmos_calibrate_status == CMOS_BEGIN) { |
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273 | irq8_start = irq8_end; |
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274 | cmos_calibrate_status = CMOS_START; |
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275 | } |
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276 | |||
277 | if (cmos_calibrate_status == CMOS_INIT) { |
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278 | cmos_calibrate_status = CMOS_BEGIN; |
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279 | } |
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280 | |||
281 | sti(); |
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282 | |||
283 | } |
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284 | |||
285 | //TSC Calibration using RTC |
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286 | void ll_calibrate_tsc_cmos(void) |
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287 | { |
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288 | |||
289 | signed long long dtsc; |
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290 | |||
291 | cli(); |
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292 | |||
299 | giacomo | 293 | irq_bind(8, calibrate_tsc_IRQ8, INT_FORCE); |
264 | giacomo | 294 | |
295 | CMOS_READ(0x0A,save_CMOS_regA); |
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296 | CMOS_READ(0x0B,save_CMOS_regB); |
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297 | |||
298 | CMOS_WRITE(0x0A,0x2F); // Set 2 Hz Periodic Interrupt |
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299 | CMOS_WRITE(0x0B,0x42); // Enable Interrupt |
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300 | |||
301 | irq_unmask(8); |
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302 | |||
303 | sti(); |
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304 | |||
305 | while (cmos_calibrate_status != CMOS_END) { |
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306 | barrier(); |
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307 | } |
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308 | |||
309 | dtsc = irq8_end - irq8_start; |
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310 | |||
311 | clk_per_msec = dtsc / 500; |
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312 | |||
299 | giacomo | 313 | message("Calibrated CPU Clk/msec = %10ld\n",(long)clk_per_msec); |
264 | giacomo | 314 | |
315 | cli(); |
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316 | |||
317 | irq_mask(8); |
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318 | |||
319 | CMOS_WRITE(0x0A,save_CMOS_regA); |
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320 | CMOS_WRITE(0x0B,save_CMOS_regB); |
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321 | |||
322 | sti(); |
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323 | |||
324 | } |
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325 | |||
120 | giacomo | 326 | //Low level time read function |
131 | giacomo | 327 | void ll_read_timespec(struct timespec *tspec) |
120 | giacomo | 328 | { |
329 | |||
194 | giacomo | 330 | static unsigned long Gconst = 1000000000; |
331 | static unsigned long Mconst = 1000000; |
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120 | giacomo | 332 | |
124 | giacomo | 333 | if (clk_per_msec <= 0) { |
334 | NULL_TIMESPEC(tspec); |
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335 | return; |
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336 | } |
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337 | |||
242 | giacomo | 338 | __asm__("xorl %%eax,%%eax\n\t" |
339 | "cpuid\n\t" |
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340 | "rdtsc\n\t" |
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341 | "pushl %%eax\n\t" |
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342 | "pushl %%edx\n\t" |
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343 | "xorl %%eax,%%eax\n\t" |
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344 | "cpuid\n\t" |
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345 | "popl %%edx\n\t" |
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346 | "popl %%eax\n\t" |
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347 | "subl (%%edi),%%eax\n\t" |
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194 | giacomo | 348 | "sbbl 4(%%edi),%%edx\n\t" |
349 | "movl %%edx,%%ecx\n\t" |
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350 | "mull %6\n\t" |
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351 | "pushl %%eax\n\t" |
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352 | "movl %%ecx,%%eax\n\t" |
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353 | "movl %%edx,%%ecx\n\t" |
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354 | "mull %6\n\t" |
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355 | "addl %%ecx,%%eax\n\t" |
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356 | "adcl $0,%%edx\n\t" |
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242 | giacomo | 357 | "movl %8,%%ebx\n\t" |
194 | giacomo | 358 | "divl (%%ebx)\n\t" |
359 | "movl %%eax,%%ecx\n\t" |
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360 | "popl %%eax\n\t" |
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361 | "divl (%%ebx)\n\t" |
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362 | "movl %%ecx,%%edx\n\t" |
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363 | "addl (%%esi),%%eax\n\t" |
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364 | "adcl 4(%%esi),%%edx\n\t" |
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365 | "divl %7\n\t" |
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366 | |||
367 | : "=a" (tspec->tv_sec), "=d" (tspec->tv_nsec) |
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242 | giacomo | 368 | : "D" (ptr_init_tsc), "S" (ptr_init_nsec), "b" (0), |
369 | "c" (0), "m" (Mconst), "m" (Gconst), "m" (ptr_clk_per_msec)); |
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194 | giacomo | 370 | |
120 | giacomo | 371 | } |
372 | |||
299 | giacomo | 373 | int apic_get_maxlvt(void) |
374 | { |
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375 | unsigned int v, ver, maxlvt; |
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376 | |||
377 | v = apic_read(APIC_LVR); |
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378 | ver = GET_APIC_VERSION(v); |
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379 | /* 82489DXs do not report # of LVT entries. */ |
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380 | maxlvt = APIC_INTEGRATED(ver) ? GET_APIC_MAXLVT(v) : 2; |
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381 | return maxlvt; |
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382 | } |
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383 | |||
304 | giacomo | 384 | /* Clear local APIC, from Linux kernel */ |
299 | giacomo | 385 | void clear_local_APIC(void) |
386 | { |
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387 | int maxlvt; |
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388 | unsigned long v; |
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389 | |||
390 | maxlvt = apic_get_maxlvt(); |
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391 | |||
392 | /* |
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393 | * Masking an LVT entry on a P6 can trigger a local APIC error |
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394 | * if the vector is zero. Mask LVTERR first to prevent this. |
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395 | */ |
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396 | if (maxlvt >= 3) { |
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397 | v = 0xFF; /* any non-zero vector will do */ |
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398 | apic_write_around(APIC_LVTERR, v | APIC_LVT_MASKED); |
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399 | } |
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400 | /* |
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401 | * Careful: we have to set masks only first to deassert |
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402 | * any level-triggered sources. |
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403 | */ |
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404 | v = apic_read(APIC_LVTT); |
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405 | apic_write_around(APIC_LVTT, v | APIC_LVT_MASKED); |
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406 | v = apic_read(APIC_LVT0); |
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407 | apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED); |
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408 | v = apic_read(APIC_LVT1); |
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409 | apic_write_around(APIC_LVT1, v | APIC_LVT_MASKED); |
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410 | if (maxlvt >= 4) { |
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411 | v = apic_read(APIC_LVTPC); |
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412 | apic_write_around(APIC_LVTPC, v | APIC_LVT_MASKED); |
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413 | } |
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414 | |||
415 | /* |
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416 | * Clean APIC state for other OSs: |
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417 | */ |
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418 | apic_write_around(APIC_LVTT, APIC_LVT_MASKED); |
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419 | apic_write_around(APIC_LVT0, APIC_LVT_MASKED); |
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420 | apic_write_around(APIC_LVT1, APIC_LVT_MASKED); |
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421 | if (maxlvt >= 3) |
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422 | apic_write_around(APIC_LVTERR, APIC_LVT_MASKED); |
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423 | if (maxlvt >= 4) |
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424 | apic_write_around(APIC_LVTPC, APIC_LVT_MASKED); |
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425 | v = GET_APIC_VERSION(apic_read(APIC_LVR)); |
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426 | if (APIC_INTEGRATED(v)) { /* !82489DX */ |
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427 | if (maxlvt > 3) |
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428 | apic_write(APIC_ESR, 0); |
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429 | apic_read(APIC_ESR); |
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430 | } |
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431 | } |
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432 | |||
433 | void disable_local_APIC(void) |
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434 | { |
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435 | unsigned long value; |
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436 | |||
437 | clear_local_APIC(); |
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438 | |||
439 | /* |
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440 | * Disable APIC (implies clearing of registers |
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441 | * for 82489DX!). |
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442 | */ |
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443 | value = apic_read(APIC_SPIV); |
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444 | value &= ~APIC_SPIV_APIC_ENABLED; |
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445 | apic_write_around(APIC_SPIV, value); |
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446 | } |
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447 | |||
448 | #define SPURIOUS_APIC_VECTOR 0xFF |
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449 | |||
450 | /* |
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302 | giacomo | 451 | * Setup the local APIC, minimal code to run P6 APIC |
299 | giacomo | 452 | */ |
453 | void setup_local_APIC (void) |
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454 | { |
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301 | giacomo | 455 | unsigned long value; |
299 | giacomo | 456 | |
457 | /* Pound the ESR really hard over the head with a big hammer - mbligh */ |
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458 | |||
459 | apic_write(APIC_ESR, 0); |
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460 | apic_write(APIC_ESR, 0); |
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461 | apic_write(APIC_ESR, 0); |
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462 | apic_write(APIC_ESR, 0); |
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463 | |||
301 | giacomo | 464 | value = APIC_SPIV_FOCUS_DISABLED | APIC_SPIV_APIC_ENABLED | SPURIOUS_APIC_VECTOR; |
465 | apic_write_around(APIC_SPIV, value); |
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299 | giacomo | 466 | |
301 | giacomo | 467 | value = APIC_DM_EXTINT | APIC_LVT_LEVEL_TRIGGER; |
468 | apic_write_around(APIC_LVT0, value); |
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299 | giacomo | 469 | |
301 | giacomo | 470 | value = APIC_DM_NMI; |
471 | apic_write_around(APIC_LVT1, value); |
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299 | giacomo | 472 | |
301 | giacomo | 473 | apic_write(APIC_ESR, 0); |
299 | giacomo | 474 | |
475 | } |
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476 | |||
477 | void disable_APIC_timer(void) |
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478 | { |
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479 | unsigned long v; |
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480 | |||
481 | v = apic_read(APIC_LVTT); |
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482 | apic_write_around(APIC_LVTT, v | APIC_LVT_MASKED); |
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483 | |||
484 | } |
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485 | |||
486 | void enable_APIC_timer(void) |
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487 | { |
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488 | unsigned long v; |
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489 | |||
490 | v = apic_read(APIC_LVTT); |
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491 | apic_write_around(APIC_LVTT, v & ~APIC_LVT_MASKED); |
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492 | |||
493 | } |
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494 | |||
304 | giacomo | 495 | #define LOCAL_TIMER_VECTOR 0x39 |
302 | giacomo | 496 | |
303 | giacomo | 497 | /* Set APIC Timer... from Linux kernel */ |
498 | void setup_APIC_timer() |
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299 | giacomo | 499 | { |
500 | unsigned int lvtt1_value, tmp_value; |
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501 | |||
502 | lvtt1_value = SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV) | |
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503 | APIC_LVT_TIMER_PERIODIC | LOCAL_TIMER_VECTOR; |
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504 | apic_write_around(APIC_LVTT, lvtt1_value); |
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505 | |||
506 | /* |
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507 | * Divide PICLK by 1 |
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508 | */ |
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509 | tmp_value = apic_read(APIC_TDCR); |
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510 | apic_write_around(APIC_TDCR, (tmp_value |
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511 | & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) |
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512 | | APIC_TDR_DIV_1); |
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303 | giacomo | 513 | |
514 | apic_write_around(APIC_TMICT, 0xFFFFFFFF); |
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515 | |||
516 | disable_APIC_timer(); |
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299 | giacomo | 517 | } |
518 | |||
519 | #define APIC_LIMIT 0xFF000000 |
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303 | giacomo | 520 | #define APIC_SET_LIMIT 10 |
299 | giacomo | 521 | |
522 | void ll_calibrate_apic(void) |
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523 | { |
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524 | |||
525 | unsigned int apic_start = 0, apic_end = 0, dapic; |
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526 | signed long long tsc_start = 0, tsc_end = 0, dtsc; |
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527 | unsigned int tmp_value; |
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528 | |||
529 | cli(); |
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530 | |||
531 | tmp_value = apic_read(APIC_TDCR); |
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532 | apic_write_around(APIC_TDCR, (tmp_value |
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533 | & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) |
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534 | | APIC_TDR_DIV_1); |
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535 | |||
536 | apic_write(APIC_TMICT, MAX_DWORD); |
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537 | |||
538 | barrier(); |
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539 | rdtscll(tsc_start); |
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540 | barrier(); |
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541 | apic_start = apic_read(APIC_TMCCT); |
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542 | barrier(); |
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543 | |||
544 | while (apic_read(APIC_TMCCT) > APIC_LIMIT) { |
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545 | barrier(); |
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546 | rdtscll(tsc_end); |
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547 | } |
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548 | |||
549 | barrier(); |
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550 | rdtscll(tsc_end); |
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551 | barrier(); |
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552 | apic_end = apic_read(APIC_TMCCT); |
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553 | barrier(); |
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554 | |||
555 | sti(); |
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556 | |||
557 | dtsc = tsc_end - tsc_start; |
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558 | dapic = apic_start - apic_end; |
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559 | |||
560 | apic_clk_per_msec = clk_per_msec * (signed long long)(dapic) / dtsc; |
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303 | giacomo | 561 | apic_set_limit = ((apic_clk_per_msec / 100) == 0) ? (apic_clk_per_msec/100) : APIC_SET_LIMIT; |
562 | |||
299 | giacomo | 563 | message("Calibrated APIC Clk/msec = %10ld\n",(long)apic_clk_per_msec); |
564 | |||
565 | } |
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566 | |||
120 | giacomo | 567 | void ll_init_advtimer() |
568 | { |
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569 | |||
570 | if (use_tsc) { |
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571 | |||
264 | giacomo | 572 | #ifdef CALIBRATE_USING_CMOS |
573 | ll_calibrate_tsc_cmos(); |
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574 | #else |
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575 | ll_calibrate_tsc(); |
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576 | #endif |
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577 | |||
120 | giacomo | 578 | last_delta_clk_per_msec = 0; |
579 | total_delta_clk_per_msec = 0; |
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580 | |||
581 | rdtscll(init_tsc); // Read start TSC |
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582 | init_nsec = 0; |
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583 | |||
299 | giacomo | 584 | if (use_apic) { |
585 | unsigned long msr_low_orig, tmp; |
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586 | |||
587 | rdmsr(APIC_BASE_MSR, msr_low_orig, tmp); |
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588 | wrmsr(APIC_BASE_MSR, msr_low_orig|(1<<11), 0); |
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589 | |||
301 | giacomo | 590 | clear_local_APIC(); |
299 | giacomo | 591 | |
301 | giacomo | 592 | ll_calibrate_apic(); |
593 | |||
299 | giacomo | 594 | setup_local_APIC(); |
303 | giacomo | 595 | |
596 | setup_APIC_timer(); |
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299 | giacomo | 597 | |
598 | } |
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599 | |||
120 | giacomo | 600 | if (use_cmos) { |
601 | |||
131 | giacomo | 602 | message("CMOS adjustement enabled\n"); |
120 | giacomo | 603 | |
604 | cli(); |
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605 | |||
606 | irq_bind(8, HandlerIRQ8, INT_FORCE); |
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607 | |||
608 | CMOS_READ(0x0A,save_CMOS_regA); |
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609 | CMOS_READ(0x0B,save_CMOS_regB); |
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610 | |||
611 | CMOS_WRITE(0x0A,0x2F); // Set 2 Hz Periodic Interrupt |
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612 | CMOS_WRITE(0x0B,0x42); // Enable Interrupt |
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613 | |||
614 | irq_unmask(8); |
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615 | |||
616 | sti(); |
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617 | |||
618 | } |
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619 | |||
620 | } else { |
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621 | |||
622 | use_cmos = 0; |
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623 | |||
624 | } |
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625 | |||
626 | } |
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627 | |||
301 | giacomo | 628 | void ll_restore_adv() |
120 | giacomo | 629 | { |
302 | giacomo | 630 | /* Restore CMOS setting */ |
120 | giacomo | 631 | if (use_cmos) { |
632 | cli(); |
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633 | |||
634 | irq_mask(8); |
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635 | |||
636 | CMOS_WRITE(0x0A,save_CMOS_regA); |
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637 | CMOS_WRITE(0x0B,save_CMOS_regB); |
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638 | |||
639 | sti(); |
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640 | } |
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301 | giacomo | 641 | |
302 | giacomo | 642 | /* Disable APIC */ |
301 | giacomo | 643 | if (use_apic) { |
644 | unsigned int msr_low_orig, tmp; |
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645 | |||
646 | cli(); |
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647 | |||
648 | disable_APIC_timer(); |
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649 | |||
650 | rdmsr(APIC_BASE_MSR, msr_low_orig, tmp); |
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651 | wrmsr(APIC_BASE_MSR, msr_low_orig&~(1<<11), 0); |
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652 | |||
653 | sti(); |
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654 | |||
655 | } |
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656 | |||
120 | giacomo | 657 | } |