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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 42 | pj | 1 | /* Project: OSLib |
| 2 | * Description: The OS Construction Kit |
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| 3 | * Date: 1.6.2000 |
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| 4 | * Idea by: Luca Abeni & Gerardo Lamastra |
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| 5 | * |
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| 6 | * OSLib is an SO project aimed at developing a common, easy-to-use |
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| 7 | * low-level infrastructure for developing OS kernels and Embedded |
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| 8 | * Applications; it partially derives from the HARTIK project but it |
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| 9 | * currently is independently developed. |
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| 10 | * |
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| 11 | * OSLib is distributed under GPL License, and some of its code has |
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| 12 | * been derived from the Linux kernel source; also some important |
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| 13 | * ideas come from studying the DJGPP go32 extender. |
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| 14 | * |
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| 15 | * We acknowledge the Linux Community, Free Software Foundation, |
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| 16 | * D.J. Delorie and all the other developers who believe in the |
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| 17 | * freedom of software and ideas. |
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| 18 | * |
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| 19 | * For legalese, check out the included GPL license. |
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| 20 | */ |
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| 21 | |||
| 22 | /* The Programmable Interrupt Timer management code */ |
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| 23 | |||
| 24 | #ifndef __PIT_H__ |
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| 25 | #define __PIT_H__ |
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| 26 | |||
| 27 | #include <ll/i386/defs.h> |
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| 28 | BEGIN_DEF |
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| 29 | |||
| 30 | #include <ll/i386/hw-data.h> |
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| 31 | #include <ll/i386/hw-instr.h> |
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| 32 | |||
| 46 | trimarchi | 33 | #define MIN_INT 100 |
| 42 | pj | 34 | |
| 35 | #define TMR_CTRL 0x43 /* PIT Control port*/ |
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| 36 | #define TMR_CNT0 0x40 /* Counter 0 port */ |
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| 37 | #define TMR_CNT1 0x41 /* Counter 1 port */ |
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| 38 | #define TMR_CNT2 0x42 /* Counter 2 port */ |
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| 39 | |||
| 40 | #define TMR_SC0 0x00 /* Select Channel 0 */ |
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| 41 | #define TMR_SC1 0x40 /* Select Channel 1 */ |
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| 42 | #define TMR_SC2 0x80 /* Select Channel 2 */ |
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| 43 | |||
| 44 | #define TMR_LSB 0x10 /* R/W Least Significative Byte */ |
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| 45 | #define TMR_MSB 0x20 /* R/W Most Significative Byte */ |
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| 46 | #define TMR_BOTH 0x30 /* R/W Both Bytes */ |
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| 47 | #define TMR_LATCH 0x00 /* Latch Command */ |
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| 48 | #define TMR_READ 0xF0 /* Read Command */ |
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| 49 | #define TMR_CNT 0x20 /* Read Counter */ |
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| 50 | #define TMR_STAT 0x10 /* Read Status */ |
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| 51 | #define TMR_CH2 0x08 /* Read Channel 2 Counter/Status */ |
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| 52 | #define TMR_CH1 0x04 /* Read Channel 1 Counter/Status */ |
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| 53 | #define TMR_CH0 0x02 /* Read Channel 0 Counter/Status */ |
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| 54 | |||
| 55 | |||
| 56 | #define TMR_MD0 0x00 /* Mode 0 */ |
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| 57 | #define TMR_MD1 0x02 /* Mode 1 */ |
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| 58 | #define TMR_MD2 0x04 /* Mode 2 */ |
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| 59 | #define TMR_MD3 0x06 /* Mode 3 */ |
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| 60 | #define TMR_MD4 0x08 /* Mode 4 */ |
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| 61 | #define TMR_MD5 0x0A /* Mode 5 */ |
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| 62 | |||
| 63 | |||
| 64 | INLINE_OP int pit_init(BYTE channel, BYTE mode, WORD tconst) |
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| 65 | { |
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| 66 | BYTE v, ch; |
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| 67 | WORD cnt; |
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| 68 | |||
| 69 | switch (channel) { |
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| 70 | case 0: |
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| 71 | cnt = TMR_CNT0; |
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| 72 | ch = TMR_SC0; |
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| 73 | break; |
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| 74 | case 1: |
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| 75 | cnt = TMR_CNT1; |
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| 76 | ch = TMR_SC1; |
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| 77 | break; |
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| 78 | case 2: |
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| 79 | cnt = TMR_CNT2; |
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| 80 | ch = TMR_SC2; |
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| 81 | break; |
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| 82 | default: |
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| 83 | return -1; |
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| 84 | } |
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| 85 | |||
| 86 | /* VM_out(TMR_CTRL, 0x34); */ |
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| 87 | outp(TMR_CTRL, ch | TMR_BOTH | mode); |
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| 88 | /* Load Time_const with 2 access to CTR */ |
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| 89 | v = (BYTE)(tconst); |
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| 90 | outp(cnt, v); |
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| 91 | v = (BYTE)(tconst >> 8); |
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| 92 | outp(cnt, v); |
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| 93 | |||
| 94 | return 1; |
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| 95 | } |
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| 96 | |||
| 97 | INLINE_OP int pit_setconstant(BYTE channel, DWORD c) |
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| 98 | { |
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| 99 | BYTE v; |
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| 100 | WORD cnt; |
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| 101 | WORD tconst; |
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| 102 | |||
| 103 | if (c > 0xF000) { |
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| 104 | tconst = 0xF000; |
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| 105 | } else { |
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| 106 | if (c < MIN_INT) { |
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| 107 | tconst = MIN_INT; |
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| 108 | } else { |
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| 109 | tconst = c; |
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| 110 | } |
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| 111 | } |
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| 112 | |||
| 113 | switch (channel) { |
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| 114 | case 0: |
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| 115 | cnt = TMR_CNT0; |
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| 116 | break; |
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| 117 | case 1: |
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| 118 | cnt = TMR_CNT1; |
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| 119 | break; |
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| 120 | case 2: |
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| 121 | cnt = TMR_CNT2; |
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| 122 | break; |
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| 123 | default: |
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| 124 | return -1; |
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| 125 | } |
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| 126 | |||
| 127 | /* Load Time_const with 2 access to CTR */ |
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| 128 | v = (BYTE)(tconst); |
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| 129 | outp(cnt, v); |
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| 130 | v = (BYTE)(tconst >> 8); |
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| 131 | outp(cnt, v); |
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| 132 | |||
| 133 | return 1; |
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| 134 | } |
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| 135 | |||
| 136 | |||
| 137 | INLINE_OP WORD pit_read(BYTE channel) |
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| 138 | { |
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| 139 | WORD result; |
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| 140 | WORD cnt; |
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| 141 | BYTE ch; |
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| 142 | BYTE str_msb, str_lsb; |
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| 143 | |||
| 144 | switch (channel) { |
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| 145 | case 0: |
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| 146 | cnt = TMR_CNT0; |
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| 147 | ch = TMR_CH0; |
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| 148 | break; |
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| 149 | case 1: |
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| 150 | cnt = TMR_CNT1; |
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| 151 | ch = TMR_CH1; |
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| 152 | break; |
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| 153 | case 2: |
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| 154 | cnt = TMR_CNT2; |
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| 155 | ch = TMR_CH2; |
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| 156 | break; |
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| 157 | default: |
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| 158 | return 0; |
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| 159 | } |
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| 160 | |||
| 161 | /* Read Back Command on counter 0 */ |
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| 162 | #if 0 |
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| 163 | outp(TMR_CTRL, ch | TMR_LATCH | TMR_BOTH); |
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| 164 | #else |
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| 165 | outp(TMR_CTRL, TMR_READ - TMR_CNT + ch /*0xD2*/); |
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| 166 | #endif |
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| 167 | /* Read the latched value from STR */ |
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| 168 | str_lsb = inp(cnt); |
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| 169 | str_msb = inp(cnt); |
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| 170 | /* Combine the byte values to obtain a word */ |
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| 171 | result = ((WORD)str_msb << 8) | (WORD)str_lsb; |
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| 172 | return result; |
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| 173 | } |
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| 174 | |||
| 175 | struct pitspec { |
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| 176 | long units; |
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| 177 | long gigas; |
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| 178 | }; |
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| 179 | |||
| 180 | #define ADDPITSPEC(n, t) ((t)->units += (n), \ |
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| 330 | giacomo | 181 | (t)->gigas += (t)->units / 1423249, \ |
| 182 | (t)->units %= 1423249) |
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| 42 | pj | 183 | #define NULLPITSPEC(t) (t)->units = 0, (t)->gigas = 0 |
| 330 | giacomo | 184 | #define PITSPEC2USEC(t) ((((t)->units * 1000) / 1193) \ |
| 185 | + (((t)->gigas * 1000) * 1193)) |
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| 42 | pj | 186 | #define CPPITSPEC(a, b) (b)->units = (a)->units, (b)->gigas = (a)->gigas |
| 305 | giacomo | 187 | |
| 42 | pj | 188 | #endif /* __PIT_H__ */ |