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Rev | Author | Line No. | Line |
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2 | pj | 1 | /* Project: OSLib |
2 | * Description: The OS Construction Kit |
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3 | * Date: 1.6.2000 |
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4 | * Idea by: Luca Abeni & Gerardo Lamastra |
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5 | * |
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6 | * OSLib is an SO project aimed at developing a common, easy-to-use |
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7 | * low-level infrastructure for developing OS kernels and Embedded |
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8 | * Applications; it partially derives from the HARTIK project but it |
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9 | * currently is independently developed. |
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10 | * |
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11 | * OSLib is distributed under GPL License, and some of its code has |
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12 | * been derived from the Linux kernel source; also some important |
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13 | * ideas come from studying the DJGPP go32 extender. |
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14 | * |
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15 | * We acknowledge the Linux Community, Free Software Foundation, |
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16 | * D.J. Delorie and all the other developers who believe in the |
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17 | * freedom of software and ideas. |
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18 | * |
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19 | * For legalese, check out the included GPL license. |
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20 | */ |
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21 | |||
22 | /* File: Vm86.C |
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23 | * |
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24 | * VM86 mode switch routines! |
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25 | * This is basically an alternative way of invoking the |
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26 | * BIOS service routines; it is very useful to support |
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27 | * native VBE compliant Video card, without writing an explicit driver |
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28 | */ |
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29 | |||
40 | pj | 30 | #include <ll/i386/hw-data.h> |
31 | #include <ll/i386/hw-instr.h> |
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32 | #include <ll/i386/hw-func.h> |
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2 | pj | 33 | #include <ll/i386/mem.h> |
34 | #include <ll/i386/x-bios.h> |
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40 | pj | 35 | #include <ll/i386/x-dosmem.h> |
2 | pj | 36 | #include <ll/i386/cons.h> |
37 | #include <ll/i386/error.h> |
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38 | |||
40 | pj | 39 | FILE(VM-86); |
2 | pj | 40 | |
41 | /* |
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42 | #define __LL_DEBUG__ |
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43 | #define __DUMB_CODE__ |
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44 | #define __CHK_IO__ |
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45 | */ |
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46 | |||
313 | giacomo | 47 | #define __LL_DEBUG__ |
48 | |||
40 | pj | 49 | #define VM86_STACK_SIZE 1024 |
2 | pj | 50 | |
40 | pj | 51 | extern DWORD ll_irq_table[256]; |
52 | |||
2 | pj | 53 | /* TSS optional section */ |
40 | pj | 54 | static BYTE vm86_stack0[VM86_STACK_SIZE]; |
2 | pj | 55 | |
56 | static struct { |
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57 | TSS t; |
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58 | DWORD io_map[2048]; |
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59 | } vm86_TSS; |
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60 | static LIN_ADDR vm86_stack; |
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61 | static LIN_ADDR vm86_iretAddress; |
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62 | |||
63 | |||
40 | pj | 64 | struct registers *global_regs; |
2 | pj | 65 | |
66 | #ifdef __DUMB_CODE__ |
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67 | static LIN_ADDR vm86_code; |
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68 | static BYTE prova86[] = { |
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40 | pj | 69 | 0x1e, /* push ds */ |
70 | 0xb8,0x00,0xb8, /* mov ax,0xb800 */ |
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71 | 0x8e,0xd8, /* mov ds,ax */ |
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72 | 0xbf,0x9e,0x00, /* mov di,0x009e (158) */ |
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73 | 0xb0,0x2a, /* mov ax,'*' */ |
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74 | 0x88,0x05, /* mov ds:[di],al */ |
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75 | 0x1f, /* pop ds */ |
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76 | 0xcd, 0x40, /*???*/ |
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77 | #ifdef __CHK_IO__ |
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78 | 0xb0, 0x00, /* movb $0x0,%al*/ |
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79 | 0x66,0xba, 0x80, 0x00, /* movw $0x80,%dx */ |
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80 | 0x66,0xef, /* outw %ax, (%dx) */ |
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81 | #endif |
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82 | 0xcf, /* iret */ |
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83 | 0xf4, /* hlt */ |
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84 | 0}; |
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2 | pj | 85 | #endif |
86 | |||
87 | #ifdef __LL_DEBUG__ |
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88 | static BYTE vm86_retAddr[] = { |
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40 | pj | 89 | 0x1e, /* push ds */ |
90 | 0xb8,0x00,0xb8, /* mov ax,0xb800 */ |
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91 | 0x8e,0xd8, /* mov ds,ax */ |
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92 | 0xbf,0x3e,0x01, /* mov di,0x013c (316) */ |
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93 | 0xb0,'%', /* mov ax,'%' */ |
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94 | 0x88,0x05, /* mov ds:[di],al */ |
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95 | 0x1f, /* pop ds */ |
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96 | 0xcd, 0x48}; /* int 0x48 */ |
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2 | pj | 97 | #else |
40 | pj | 98 | static BYTE vm86_retAddr[] = {0xcd, 0x48}; /* int 48h */ |
2 | pj | 99 | #endif |
100 | |||
40 | pj | 101 | TSS *vm86_get_tss(void) |
102 | { |
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103 | return &(vm86_TSS.t); |
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104 | } |
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105 | |||
2 | pj | 106 | /* This is the return point from V86 mode, called through int 0x48 |
107 | * (see vm86-exc.s). We double check that this function is called in |
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108 | * the V86 TSS. Otherwise, Panic!!! |
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109 | */ |
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40 | pj | 110 | void vm86_return(DWORD n, struct registers r) |
2 | pj | 111 | { |
112 | CONTEXT c = get_TR(); |
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113 | #ifdef __LL_DEBUG__ |
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40 | pj | 114 | DWORD cs,eip; |
2 | pj | 115 | void *esp; |
116 | DWORD a; |
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117 | /* message("Gotta code=%d [0 called from GPF/1 int 0x48]\n",code);*/ |
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118 | #endif |
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119 | if (c == X_VM86_TSS) { |
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40 | pj | 120 | global_regs = &r; |
2 | pj | 121 | #ifdef __LL_DEBUG__ |
40 | pj | 122 | message("TSS CS=%x IP=%lx\n",vm86_TSS.t.cs,vm86_TSS.t.eip); |
123 | message("Switching to %x\n", vm86_TSS.t.back_link); |
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124 | a = (DWORD)(vm86_iretAddress); |
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125 | cs = (a & 0xFF000) >> 4; |
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126 | eip = (a & 0xFFF); |
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127 | message("Real-Mode Address is CS=%lx IP=%lx\nLinear=%lx\n",cs,eip,a); |
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313 | giacomo | 128 | esp = /* (void *)(tos)*/ (void *)0x69; |
40 | pj | 129 | message("Stack frame: %p %lx %lx\n", |
130 | esp, vm86_TSS.t.esp0, vm86_TSS.t.esp); |
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131 | message("%lx ",lmempeekd(esp)); /* bp */ |
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132 | message("%lx ",lmempeekd(esp+4)); /* eip */ |
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133 | message("%lx ",lmempeekd(esp+8)); /* 0x0d */ |
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134 | message("%lx\n",lmempeekd(esp+12)); /* error code */ |
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2 | pj | 135 | /* The error code is given by the selector causing shifted and or-ed with |
136 | 3 bits: [LDT/GDT | IDT | Ext/Int] |
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137 | If IDT == 1 -> the fault was provoked bu an interrupt (Internal if the |
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138 | Ext/Int bit is 0, External if the bit is 1) |
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139 | Else the LDT/GDT bit shows if the selector belongs to the LDT (if 1) |
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140 | or GDT (if 0) |
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141 | */ |
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40 | pj | 142 | message("%lx ",lmempeekd(esp+16)); /* EIP of faulting instr */ |
143 | message("%lx ",lmempeekd(esp+20)); /* CS of faulting instr*/ |
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144 | message("%lx ",lmempeekd(esp+24)); /* EFLAGS*/ |
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145 | message("%lx\n",lmempeekd(esp+28)); /* old ESP*/ |
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146 | message("%lx ",lmempeekd(esp+32)); /* old SS*/ |
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147 | message("%lx ",lmempeekd(esp+36)); /* old ES*/ |
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148 | message("%lx ",lmempeekd(esp+40)); /* old DS*/ |
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149 | message("%lx\n",lmempeekd(esp+44)); /* old FS*/ |
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2 | pj | 150 | #endif |
40 | pj | 151 | ll_context_load(vm86_TSS.t.back_link); |
2 | pj | 152 | } |
40 | pj | 153 | message("Here?\n"); |
2 | pj | 154 | halt(); |
155 | } |
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156 | |||
157 | extern void vm86_exc(void); |
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158 | |||
159 | /* Just a debugging function; it dumps the status of the TSS */ |
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160 | void vm86_dump_TSS(void) |
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161 | { |
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40 | pj | 162 | BYTE acc,gran; |
163 | DWORD base,lim; |
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2 | pj | 164 | message("vm86_TSS.t dump\n"); |
40 | pj | 165 | message("Flag: %lx\n",vm86_TSS.t.eflags); |
166 | message("SS: %hx SP:%lx\n", vm86_TSS.t.ss,vm86_TSS.t.esp); |
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167 | message("Stack0: %hx:%lx\n",vm86_TSS.t.ss0,vm86_TSS.t.esp0); |
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168 | message("Stack1: %hx:%lx\n",vm86_TSS.t.ss1,vm86_TSS.t.esp1); |
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169 | message("Stack2: %hx:%lx\n",vm86_TSS.t.ss2,vm86_TSS.t.esp2); |
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170 | message("CS: %hx IP: %lx",vm86_TSS.t.cs, vm86_TSS.t.eip); |
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171 | message("DS: %hx\n",vm86_TSS.t.ds); |
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172 | base = GDT_read(X_VM86_TSS,&lim,&acc,&gran); |
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2 | pj | 173 | message("Base : %lx Lim : %lx Acc : %x Gran %x\n", |
40 | pj | 174 | base,lim,(unsigned)(acc),(unsigned)(gran)); |
2 | pj | 175 | } |
176 | |||
177 | void vm86_init(void) |
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178 | { |
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179 | int register i; |
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40 | pj | 180 | |
2 | pj | 181 | /* Init the DOS memory allocator */ |
40 | pj | 182 | DOS_mem_init(); |
2 | pj | 183 | |
184 | /* First of all, we need to setup a GDT entries to |
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185 | * allow vm86 task execution. We just need a free 386 TSS, which |
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186 | * will be used to store the execution context of the virtual 8086 |
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187 | * task |
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188 | */ |
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40 | pj | 189 | GDT_place(X_VM86_TSS,(DWORD)(&vm86_TSS), |
190 | sizeof(vm86_TSS),FREE_TSS386,GRAN_16); |
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2 | pj | 191 | |
313 | giacomo | 192 | IDT_place(0x48, (void *)(vm86_return)); |
40 | pj | 193 | |
2 | pj | 194 | /* Prepare a real-mode stack, obtaining it from the |
195 | * DOS memory allocator! |
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196 | * 8K should be OK! Stack top is vm86_stack + SIZE! |
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197 | */ |
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40 | pj | 198 | vm86_stack = DOS_alloc(VM86_STACK_SIZE*2); |
199 | vm86_stack += VM86_STACK_SIZE/2; |
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200 | |||
2 | pj | 201 | /* Create a location of DOS memory containing the |
202 | * opcode sequence which will generate a GPF |
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203 | * We use the privileged instruction hlt to do it |
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204 | */ |
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205 | vm86_iretAddress = DOS_alloc(sizeof(vm86_retAddr)); |
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40 | pj | 206 | memcpy(vm86_iretAddress,vm86_retAddr,sizeof(vm86_retAddr)); |
2 | pj | 207 | #ifdef __LL_DEBUG__ |
40 | pj | 208 | message("PM reentry linear address=0x%lx\n", (DWORD)vm86_iretAddress); |
2 | pj | 209 | #endif |
210 | #ifdef __DUMB_CODE__ |
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211 | vm86_code = DOS_alloc(2048); |
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40 | pj | 212 | lmemcpy(vm86_code,prova86,sizeof(prova86)); |
2 | pj | 213 | #endif |
214 | /* Zero the PM/Ring[1,2] ss:esp; they're unused! */ |
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215 | vm86_TSS.t.esp1 = 0; |
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216 | vm86_TSS.t.esp2 = 0; |
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217 | vm86_TSS.t.ss1 = 0; |
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218 | vm86_TSS.t.ss2 = 0; |
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219 | /* Use only the GDT */ |
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220 | vm86_TSS.t.ldt = 0; |
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221 | /* No paging activated */ |
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222 | vm86_TSS.t.cr3 = 0; |
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223 | vm86_TSS.t.trap = 0; |
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224 | /* Yeah, free access to any I/O port; we trust BIOS anyway! */ |
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225 | /* Here is the explanation: we have 65536 I/O ports... each bit |
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226 | * in the io_map masks/unmasks the exception for the given I/O port |
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227 | * If the bit is set, an exception is generated; otherwise, if the bit |
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228 | * is clear, everythings works fine... |
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229 | * Because of alignment problem, we need to add an extra byte all set |
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230 | * to 1, according to Intel manuals |
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231 | */ |
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40 | pj | 232 | vm86_TSS.t.io_base = (DWORD)(&(vm86_TSS.io_map)) - |
233 | (DWORD)(&(vm86_TSS)); |
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234 | for (i = 0; i < 2047; i++) vm86_TSS.io_map[i] = 0; |
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2 | pj | 235 | vm86_TSS.io_map[2047] = 0xFF000000; |
236 | } |
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237 | |||
40 | pj | 238 | int vm86_callBIOS(int service,X_REGS16 *in,X_REGS16 *out,X_SREGS16 *s) |
2 | pj | 239 | { |
240 | DWORD vm86_tmpAddr; |
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40 | pj | 241 | DWORD vm86_flags, vm86_cs,vm86_ip; |
2 | pj | 242 | LIN_ADDR vm86_stackPtr; |
243 | DWORD *IRQTable_entry; |
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40 | pj | 244 | |
245 | if (service < 0x10 || in == NULL) return -1; |
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2 | pj | 246 | /* Setup the stack frame */ |
40 | pj | 247 | vm86_tmpAddr = (DWORD)(vm86_stack); |
2 | pj | 248 | vm86_TSS.t.ss = (vm86_tmpAddr & 0xFF000) >> 4; |
249 | vm86_TSS.t.ebp = vm86_TSS.t.esp = (vm86_tmpAddr & 0x0FFF) |
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40 | pj | 250 | + VM86_STACK_SIZE - 6; |
2 | pj | 251 | /* Build an iret stack frame which returns to vm86_iretAddress */ |
40 | pj | 252 | vm86_tmpAddr = (DWORD)(vm86_iretAddress); |
2 | pj | 253 | vm86_cs = (vm86_tmpAddr & 0xFF000) >> 4; |
254 | vm86_ip = (vm86_tmpAddr & 0xFFF); |
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40 | pj | 255 | vm86_flags = 0; /* CPU_FLAG_VM | CPU_FLAG_IOPL; */ |
2 | pj | 256 | vm86_stackPtr = vm86_stack + VM86_STACK_SIZE; |
40 | pj | 257 | lmempokew(vm86_stackPtr-6,vm86_ip); |
258 | lmempokew(vm86_stackPtr-4,vm86_cs); |
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259 | lmempokew(vm86_stackPtr-2,vm86_flags); |
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2 | pj | 260 | #ifdef __LL_DEBUG__ |
261 | message("Stack: %lx SS: %lx SP: %lx\n", |
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40 | pj | 262 | vm86_tmpAddr + VM86_STACK_SIZE,(DWORD)vm86_TSS.t.ss,vm86_TSS.t.esp); |
2 | pj | 263 | #endif |
264 | /* Wanted VM86 mode + IOPL = 3! */ |
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265 | vm86_TSS.t.eflags = CPU_FLAG_VM | CPU_FLAG_IOPL; |
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266 | /* Preload some standard values into the registers */ |
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267 | vm86_TSS.t.ss0 = X_FLATDATA_SEL; |
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40 | pj | 268 | vm86_TSS.t.esp0 = (DWORD)&(vm86_stack0[VM86_STACK_SIZE-1]); |
269 | |||
270 | |||
2 | pj | 271 | #ifdef __DUMB_CODE__ |
40 | pj | 272 | vm86_TSS.t.cs = ((DWORD)(vm86_code) & 0xFFFF0) >> 4; |
273 | vm86_TSS.t.eip = ((DWORD)(vm86_code) & 0x000F); |
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2 | pj | 274 | #ifdef __LL_DEBUG_ |
275 | message("(DUMB CODE) CS:%x IP:%x/%x\n", |
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40 | pj | 276 | (DWORD)vm86_TSS.t.cs,vm86_TSS.t.eip,&prova86); |
2 | pj | 277 | message("(DUMB CODE) Go...\n"); |
278 | #endif |
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279 | vm86_TSS.t.back_link = ll_context_save(); |
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280 | ll_context_load(X_VM86_TSS); |
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281 | |||
282 | #ifdef __LL_DEBUG_ |
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283 | message("(DUMB CODE) I am back...\n"); |
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284 | #endif |
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285 | #else |
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286 | /* Copy the parms from the X_*REGS structures in the vm86 TSS */ |
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40 | pj | 287 | vm86_TSS.t.eax = (DWORD)in->x.ax; |
288 | vm86_TSS.t.ebx = (DWORD)in->x.bx; |
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289 | vm86_TSS.t.ecx = (DWORD)in->x.cx; |
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290 | vm86_TSS.t.edx = (DWORD)in->x.dx; |
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291 | vm86_TSS.t.esi = (DWORD)in->x.si; |
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292 | vm86_TSS.t.edi = (DWORD)in->x.di; |
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2 | pj | 293 | /* IF Segment registers are required, copy them... */ |
294 | if (s != NULL) { |
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40 | pj | 295 | vm86_TSS.t.es = (WORD)s->es; |
296 | vm86_TSS.t.ds = (WORD)s->ds; |
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2 | pj | 297 | } else { |
40 | pj | 298 | vm86_TSS.t.ds = vm86_TSS.t.ss; |
299 | vm86_TSS.t.es = vm86_TSS.t.ss; |
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2 | pj | 300 | } |
40 | pj | 301 | vm86_TSS.t.gs = vm86_TSS.t.ss; |
302 | vm86_TSS.t.fs = vm86_TSS.t.ss; |
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2 | pj | 303 | /* Execute the BIOS call, fetching the CS:IP of the real interrupt |
304 | * handler from 0:0 (DOS irq table!) |
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305 | */ |
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40 | pj | 306 | IRQTable_entry = (void *)(0L); |
307 | vm86_TSS.t.cs= ((IRQTable_entry[service]) & 0xFFFF0000) >> 16; |
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2 | pj | 308 | vm86_TSS.t.eip = ((IRQTable_entry[service]) & 0x0000FFFF); |
40 | pj | 309 | #ifdef __LL_DEBUG__ |
310 | message("CS:%x IP:%lx\n", vm86_TSS.t.cs, vm86_TSS.t.eip); |
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2 | pj | 311 | #endif |
312 | /* Let's use the ll standard call... */ |
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313 | vm86_TSS.t.back_link = ll_context_save(); |
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314 | ll_context_load(X_VM86_TSS); |
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40 | pj | 315 | #ifdef __LL_DEBUG__ |
2 | pj | 316 | message("I am back...\n"); |
317 | message("TSS CS=%hx IP=%lx\n", vm86_TSS.t.cs, vm86_TSS.t.eip); |
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40 | pj | 318 | { char *xp = (char *)(vm86_iretAddress + 0xe); |
319 | message("PM reentry linear address=%p\n", vm86_iretAddress); |
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320 | message("Executing code: %x ",(unsigned char)(*xp)); xp++; |
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321 | message("%x\n",(unsigned char)(*xp));} |
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2 | pj | 322 | #endif |
323 | /* Send back in the X_*REGS structure the value obtained with |
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324 | * the real-mode interrupt call |
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325 | */ |
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326 | if (out != NULL) { |
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327 | /* |
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328 | out->x.ax = (WORD)vm86_TSS.t.eax; |
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329 | out->x.bx = (WORD)vm86_TSS.t.ebx; |
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330 | out->x.cx = (WORD)vm86_TSS.t.ecx; |
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331 | out->x.dx = (WORD)vm86_TSS.t.edx; |
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332 | out->x.si = (WORD)vm86_TSS.t.esi; |
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333 | out->x.di = (WORD)vm86_TSS.t.edi; |
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334 | out->x.cflag = (WORD)vm86_TSS.t.eflags; |
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335 | */ |
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40 | pj | 336 | out->x.ax = global_regs->eax; |
337 | out->x.bx = global_regs->ebx; |
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338 | out->x.cx = global_regs->ecx; |
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339 | out->x.dx = global_regs->edx; |
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340 | out->x.si = global_regs->esi; |
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341 | out->x.di = global_regs->edi; |
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342 | out->x.cflag = global_regs->flags; |
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2 | pj | 343 | } |
344 | if (s != NULL) { |
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40 | pj | 345 | s->es = vm86_TSS.t.es; |
346 | s->ds = vm86_TSS.t.ds; |
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2 | pj | 347 | } |
348 | #endif |
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349 | return 1; |
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350 | } |