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2 | pj | 1 | /* Project: OSLib |
2 | * Description: The OS Construction Kit |
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3 | * Date: 1.6.2000 |
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4 | * Idea by: Luca Abeni & Gerardo Lamastra |
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5 | * |
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6 | * OSLib is an SO project aimed at developing a common, easy-to-use |
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7 | * low-level infrastructure for developing OS kernels and Embedded |
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8 | * Applications; it partially derives from the HARTIK project but it |
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9 | * currently is independently developed. |
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10 | * |
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11 | * OSLib is distributed under GPL License, and some of its code has |
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12 | * been derived from the Linux kernel source; also some important |
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13 | * ideas come from studying the DJGPP go32 extender. |
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14 | * |
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15 | * We acknowledge the Linux Community, Free Software Foundation, |
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16 | * D.J. Delorie and all the other developers who believe in the |
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17 | * freedom of software and ideas. |
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18 | * |
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19 | * For legalese, check out the included GPL license. |
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20 | */ |
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21 | |||
22 | /* File: Vm86.C |
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23 | * |
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24 | * VM86 mode switch routines! |
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25 | * This is basically an alternative way of invoking the |
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26 | * BIOS service routines; it is very useful to support |
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27 | * native VBE compliant Video card, without writing an explicit driver |
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28 | */ |
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29 | |||
40 | pj | 30 | #include <ll/i386/hw-data.h> |
31 | #include <ll/i386/hw-instr.h> |
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32 | #include <ll/i386/hw-func.h> |
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2 | pj | 33 | #include <ll/i386/mem.h> |
34 | #include <ll/i386/x-bios.h> |
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40 | pj | 35 | #include <ll/i386/x-dosmem.h> |
2 | pj | 36 | #include <ll/i386/cons.h> |
37 | #include <ll/i386/error.h> |
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38 | |||
40 | pj | 39 | FILE(VM-86); |
2 | pj | 40 | |
41 | /* |
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42 | #define __LL_DEBUG__ |
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43 | #define __DUMB_CODE__ |
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44 | #define __CHK_IO__ |
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45 | */ |
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46 | |||
443 | giacomo | 47 | //#define __LL_DEBUG__ |
313 | giacomo | 48 | |
40 | pj | 49 | #define VM86_STACK_SIZE 1024 |
2 | pj | 50 | |
40 | pj | 51 | extern DWORD ll_irq_table[256]; |
52 | |||
2 | pj | 53 | /* TSS optional section */ |
40 | pj | 54 | static BYTE vm86_stack0[VM86_STACK_SIZE]; |
2 | pj | 55 | |
56 | static struct { |
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57 | TSS t; |
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58 | DWORD io_map[2048]; |
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59 | } vm86_TSS; |
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60 | static LIN_ADDR vm86_stack; |
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61 | static LIN_ADDR vm86_iretAddress; |
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62 | |||
40 | pj | 63 | struct registers *global_regs; |
443 | giacomo | 64 | WORD VM86_ret_ctx; |
2 | pj | 65 | |
443 | giacomo | 66 | |
2 | pj | 67 | #ifdef __DUMB_CODE__ |
68 | static LIN_ADDR vm86_code; |
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69 | static BYTE prova86[] = { |
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40 | pj | 70 | 0x1e, /* push ds */ |
71 | 0xb8,0x00,0xb8, /* mov ax,0xb800 */ |
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72 | 0x8e,0xd8, /* mov ds,ax */ |
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73 | 0xbf,0x9e,0x00, /* mov di,0x009e (158) */ |
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74 | 0xb0,0x2a, /* mov ax,'*' */ |
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75 | 0x88,0x05, /* mov ds:[di],al */ |
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76 | 0x1f, /* pop ds */ |
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77 | 0xcd, 0x40, /*???*/ |
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78 | #ifdef __CHK_IO__ |
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79 | 0xb0, 0x00, /* movb $0x0,%al*/ |
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80 | 0x66,0xba, 0x80, 0x00, /* movw $0x80,%dx */ |
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81 | 0x66,0xef, /* outw %ax, (%dx) */ |
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82 | #endif |
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83 | 0xcf, /* iret */ |
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84 | 0xf4, /* hlt */ |
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85 | 0}; |
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2 | pj | 86 | #endif |
87 | |||
40 | pj | 88 | static BYTE vm86_retAddr[] = {0xcd, 0x48}; /* int 48h */ |
2 | pj | 89 | |
40 | pj | 90 | TSS *vm86_get_tss(void) |
91 | { |
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92 | return &(vm86_TSS.t); |
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93 | } |
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94 | |||
2 | pj | 95 | /* Just a debugging function; it dumps the status of the TSS */ |
96 | void vm86_dump_TSS(void) |
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97 | { |
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40 | pj | 98 | BYTE acc,gran; |
99 | DWORD base,lim; |
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2 | pj | 100 | message("vm86_TSS.t dump\n"); |
40 | pj | 101 | message("Flag: %lx\n",vm86_TSS.t.eflags); |
102 | message("SS: %hx SP:%lx\n", vm86_TSS.t.ss,vm86_TSS.t.esp); |
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103 | message("Stack0: %hx:%lx\n",vm86_TSS.t.ss0,vm86_TSS.t.esp0); |
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104 | message("Stack1: %hx:%lx\n",vm86_TSS.t.ss1,vm86_TSS.t.esp1); |
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105 | message("Stack2: %hx:%lx\n",vm86_TSS.t.ss2,vm86_TSS.t.esp2); |
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106 | message("CS: %hx IP: %lx",vm86_TSS.t.cs, vm86_TSS.t.eip); |
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107 | message("DS: %hx\n",vm86_TSS.t.ds); |
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108 | base = GDT_read(X_VM86_TSS,&lim,&acc,&gran); |
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2 | pj | 109 | message("Base : %lx Lim : %lx Acc : %x Gran %x\n", |
40 | pj | 110 | base,lim,(unsigned)(acc),(unsigned)(gran)); |
2 | pj | 111 | } |
112 | |||
113 | void vm86_init(void) |
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114 | { |
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115 | int register i; |
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40 | pj | 116 | |
2 | pj | 117 | /* Init the DOS memory allocator */ |
40 | pj | 118 | DOS_mem_init(); |
2 | pj | 119 | |
120 | /* First of all, we need to setup a GDT entries to |
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121 | * allow vm86 task execution. We just need a free 386 TSS, which |
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122 | * will be used to store the execution context of the virtual 8086 |
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123 | * task |
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124 | */ |
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40 | pj | 125 | GDT_place(X_VM86_TSS,(DWORD)(&vm86_TSS), |
126 | sizeof(vm86_TSS),FREE_TSS386,GRAN_16); |
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2 | pj | 127 | |
443 | giacomo | 128 | /* Return Registers */ |
129 | global_regs = DOS_alloc(sizeof(struct registers)); |
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40 | pj | 130 | |
2 | pj | 131 | /* Prepare a real-mode stack, obtaining it from the |
132 | * DOS memory allocator! |
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133 | * 8K should be OK! Stack top is vm86_stack + SIZE! |
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134 | */ |
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40 | pj | 135 | vm86_stack = DOS_alloc(VM86_STACK_SIZE*2); |
136 | vm86_stack += VM86_STACK_SIZE/2; |
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137 | |||
2 | pj | 138 | /* Create a location of DOS memory containing the |
139 | * opcode sequence which will generate a GPF |
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140 | * We use the privileged instruction hlt to do it |
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141 | */ |
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142 | vm86_iretAddress = DOS_alloc(sizeof(vm86_retAddr)); |
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40 | pj | 143 | memcpy(vm86_iretAddress,vm86_retAddr,sizeof(vm86_retAddr)); |
2 | pj | 144 | #ifdef __LL_DEBUG__ |
40 | pj | 145 | message("PM reentry linear address=0x%lx\n", (DWORD)vm86_iretAddress); |
2 | pj | 146 | #endif |
147 | #ifdef __DUMB_CODE__ |
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148 | vm86_code = DOS_alloc(2048); |
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40 | pj | 149 | lmemcpy(vm86_code,prova86,sizeof(prova86)); |
2 | pj | 150 | #endif |
151 | /* Zero the PM/Ring[1,2] ss:esp; they're unused! */ |
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152 | vm86_TSS.t.esp1 = 0; |
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153 | vm86_TSS.t.esp2 = 0; |
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154 | vm86_TSS.t.ss1 = 0; |
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155 | vm86_TSS.t.ss2 = 0; |
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156 | /* Use only the GDT */ |
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157 | vm86_TSS.t.ldt = 0; |
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158 | /* No paging activated */ |
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159 | vm86_TSS.t.cr3 = 0; |
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160 | vm86_TSS.t.trap = 0; |
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161 | /* Yeah, free access to any I/O port; we trust BIOS anyway! */ |
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162 | /* Here is the explanation: we have 65536 I/O ports... each bit |
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163 | * in the io_map masks/unmasks the exception for the given I/O port |
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164 | * If the bit is set, an exception is generated; otherwise, if the bit |
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165 | * is clear, everythings works fine... |
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166 | * Because of alignment problem, we need to add an extra byte all set |
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167 | * to 1, according to Intel manuals |
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168 | */ |
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40 | pj | 169 | vm86_TSS.t.io_base = (DWORD)(&(vm86_TSS.io_map)) - |
170 | (DWORD)(&(vm86_TSS)); |
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171 | for (i = 0; i < 2047; i++) vm86_TSS.io_map[i] = 0; |
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2 | pj | 172 | vm86_TSS.io_map[2047] = 0xFF000000; |
173 | } |
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174 | |||
40 | pj | 175 | int vm86_callBIOS(int service,X_REGS16 *in,X_REGS16 *out,X_SREGS16 *s) |
2 | pj | 176 | { |
177 | DWORD vm86_tmpAddr; |
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40 | pj | 178 | DWORD vm86_flags, vm86_cs,vm86_ip; |
2 | pj | 179 | LIN_ADDR vm86_stackPtr; |
180 | DWORD *IRQTable_entry; |
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443 | giacomo | 181 | BYTE p1,p2; |
182 | |||
183 | SYS_FLAGS f; |
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184 | |||
185 | if (service < 0x10 || in == NULL) return -1; |
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40 | pj | 186 | |
443 | giacomo | 187 | f = ll_fsave(); |
188 | |||
2 | pj | 189 | /* Setup the stack frame */ |
40 | pj | 190 | vm86_tmpAddr = (DWORD)(vm86_stack); |
2 | pj | 191 | vm86_TSS.t.ss = (vm86_tmpAddr & 0xFF000) >> 4; |
192 | vm86_TSS.t.ebp = vm86_TSS.t.esp = (vm86_tmpAddr & 0x0FFF) |
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40 | pj | 193 | + VM86_STACK_SIZE - 6; |
2 | pj | 194 | /* Build an iret stack frame which returns to vm86_iretAddress */ |
40 | pj | 195 | vm86_tmpAddr = (DWORD)(vm86_iretAddress); |
2 | pj | 196 | vm86_cs = (vm86_tmpAddr & 0xFF000) >> 4; |
197 | vm86_ip = (vm86_tmpAddr & 0xFFF); |
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40 | pj | 198 | vm86_flags = 0; /* CPU_FLAG_VM | CPU_FLAG_IOPL; */ |
2 | pj | 199 | vm86_stackPtr = vm86_stack + VM86_STACK_SIZE; |
40 | pj | 200 | lmempokew(vm86_stackPtr-6,vm86_ip); |
201 | lmempokew(vm86_stackPtr-4,vm86_cs); |
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202 | lmempokew(vm86_stackPtr-2,vm86_flags); |
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2 | pj | 203 | #ifdef __LL_DEBUG__ |
204 | message("Stack: %lx SS: %lx SP: %lx\n", |
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40 | pj | 205 | vm86_tmpAddr + VM86_STACK_SIZE,(DWORD)vm86_TSS.t.ss,vm86_TSS.t.esp); |
2 | pj | 206 | #endif |
207 | /* Wanted VM86 mode + IOPL = 3! */ |
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443 | giacomo | 208 | vm86_TSS.t.eflags = CPU_FLAG_VM + CPU_FLAG_IOPL; |
2 | pj | 209 | /* Preload some standard values into the registers */ |
210 | vm86_TSS.t.ss0 = X_FLATDATA_SEL; |
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40 | pj | 211 | vm86_TSS.t.esp0 = (DWORD)&(vm86_stack0[VM86_STACK_SIZE-1]); |
212 | |||
2 | pj | 213 | #ifdef __DUMB_CODE__ |
40 | pj | 214 | vm86_TSS.t.cs = ((DWORD)(vm86_code) & 0xFFFF0) >> 4; |
215 | vm86_TSS.t.eip = ((DWORD)(vm86_code) & 0x000F); |
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2 | pj | 216 | #ifdef __LL_DEBUG_ |
217 | message("(DUMB CODE) CS:%x IP:%x/%x\n", |
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40 | pj | 218 | (DWORD)vm86_TSS.t.cs,vm86_TSS.t.eip,&prova86); |
2 | pj | 219 | message("(DUMB CODE) Go...\n"); |
220 | #endif |
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221 | vm86_TSS.t.back_link = ll_context_save(); |
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443 | giacomo | 222 | VM86_ret_ctx = vm86_TSS.t.back_link; |
223 | |||
224 | p1 = inp(0x21); |
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225 | p2 = inp(0xA1); |
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226 | outp(0x21,0xFF); |
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227 | outp(0xA1,0xFF); |
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228 | |||
229 | sti(); |
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2 | pj | 230 | ll_context_load(X_VM86_TSS); |
231 | |||
443 | giacomo | 232 | cli(); |
233 | outp(0x21,p1); |
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234 | outp(0xA1,p2); |
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235 | |||
2 | pj | 236 | #ifdef __LL_DEBUG_ |
237 | message("(DUMB CODE) I am back...\n"); |
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238 | #endif |
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239 | #else |
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240 | /* Copy the parms from the X_*REGS structures in the vm86 TSS */ |
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40 | pj | 241 | vm86_TSS.t.eax = (DWORD)in->x.ax; |
242 | vm86_TSS.t.ebx = (DWORD)in->x.bx; |
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243 | vm86_TSS.t.ecx = (DWORD)in->x.cx; |
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244 | vm86_TSS.t.edx = (DWORD)in->x.dx; |
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245 | vm86_TSS.t.esi = (DWORD)in->x.si; |
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246 | vm86_TSS.t.edi = (DWORD)in->x.di; |
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2 | pj | 247 | /* IF Segment registers are required, copy them... */ |
248 | if (s != NULL) { |
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40 | pj | 249 | vm86_TSS.t.es = (WORD)s->es; |
250 | vm86_TSS.t.ds = (WORD)s->ds; |
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2 | pj | 251 | } else { |
40 | pj | 252 | vm86_TSS.t.ds = vm86_TSS.t.ss; |
253 | vm86_TSS.t.es = vm86_TSS.t.ss; |
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2 | pj | 254 | } |
40 | pj | 255 | vm86_TSS.t.gs = vm86_TSS.t.ss; |
256 | vm86_TSS.t.fs = vm86_TSS.t.ss; |
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2 | pj | 257 | /* Execute the BIOS call, fetching the CS:IP of the real interrupt |
258 | * handler from 0:0 (DOS irq table!) |
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259 | */ |
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40 | pj | 260 | IRQTable_entry = (void *)(0L); |
261 | vm86_TSS.t.cs= ((IRQTable_entry[service]) & 0xFFFF0000) >> 16; |
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2 | pj | 262 | vm86_TSS.t.eip = ((IRQTable_entry[service]) & 0x0000FFFF); |
40 | pj | 263 | #ifdef __LL_DEBUG__ |
264 | message("CS:%x IP:%lx\n", vm86_TSS.t.cs, vm86_TSS.t.eip); |
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2 | pj | 265 | #endif |
266 | /* Let's use the ll standard call... */ |
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443 | giacomo | 267 | |
2 | pj | 268 | vm86_TSS.t.back_link = ll_context_save(); |
443 | giacomo | 269 | VM86_ret_ctx = vm86_TSS.t.back_link; |
270 | |||
271 | p1 = inp(0x21); |
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272 | p2 = inp(0xA1); |
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273 | outp(0x21,0xFF); |
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274 | outp(0xA1,0xFF); |
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275 | sti(); |
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276 | |||
2 | pj | 277 | ll_context_load(X_VM86_TSS); |
443 | giacomo | 278 | |
279 | |||
280 | cli(); |
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281 | outp(0x21,p1); |
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282 | outp(0xA1,p2); |
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283 | |||
40 | pj | 284 | #ifdef __LL_DEBUG__ |
2 | pj | 285 | message("I am back...\n"); |
286 | message("TSS CS=%hx IP=%lx\n", vm86_TSS.t.cs, vm86_TSS.t.eip); |
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287 | #endif |
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288 | /* Send back in the X_*REGS structure the value obtained with |
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289 | * the real-mode interrupt call |
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290 | */ |
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291 | if (out != NULL) { |
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443 | giacomo | 292 | |
40 | pj | 293 | out->x.ax = global_regs->eax; |
294 | out->x.bx = global_regs->ebx; |
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295 | out->x.cx = global_regs->ecx; |
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296 | out->x.dx = global_regs->edx; |
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297 | out->x.si = global_regs->esi; |
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298 | out->x.di = global_regs->edi; |
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299 | out->x.cflag = global_regs->flags; |
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443 | giacomo | 300 | |
301 | //message("ax = %d bx = %d cx = %d dx = %d\n",out->x.ax,out->x.bx,out->x.cx,out->x.dx); |
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302 | //message("si = %d di = %d\n",out->x.si,out->x.di); |
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303 | |||
2 | pj | 304 | } |
305 | if (s != NULL) { |
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40 | pj | 306 | s->es = vm86_TSS.t.es; |
307 | s->ds = vm86_TSS.t.ds; |
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2 | pj | 308 | } |
309 | #endif |
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443 | giacomo | 310 | |
311 | ll_frestore(f); |
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312 | |||
313 | return 1; |
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2 | pj | 314 | } |