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134 giacomo 1
/* $Id: asm_common_x86.s,v 1.1 2003-04-24 13:36:02 giacomo Exp $ */
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/*
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 * Mesa 3-D graphics library
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 * Version:  4.0.3
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 *
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 * Copyright (C) 1999-2002  Brian Paul   All Rights Reserved.
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 *
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 * Permission is hereby granted, free of charge, to any person obtaining a
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 * copy of this software and associated documentation files (the "Software"),
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 * to deal in the Software without restriction, including without limitation
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 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
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 * and/or sell copies of the Software, and to permit persons to whom the
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 * Software is furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice shall be included
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 * in all copies or substantial portions of the Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
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 * BRIAN PAUL BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
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 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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 */
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/*
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 * Check extended CPU capabilities.  Now justs returns the raw CPUID
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 * feature information, allowing the higher level code to interpret the
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 * results.
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 *
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 * Written by Holger Waechtler <holger@akaflieg.extern.tu-berlin.de>
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 *
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 * Cleaned up and simplified by Gareth Hughes <gareth@valinux.com>
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 */
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/*
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 * NOTE: Avoid using spaces in between '(' ')' and arguments, especially
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 * with macros like CONST, LLBL that expand to CONCAT(...).  Putting spaces
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 * in there will break the build on some platforms.
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 */
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#include "matypes.h"
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#include "features_common_x86.h"
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/* Intel vendor string
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 */
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#define GENU	0x756e6547	/* "Genu" */
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#define INEI	0x49656e69	/* "ineI" */
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#define NTEL	0x6c65746e	/* "ntel" */
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/* AMD vendor string
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 */
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#define AUTH	0x68747541	/* "Auth" */
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#define ENTI	0x69746e65	/* "enti" */
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#define CAMD	0x444d4163	/* "cAMD" */
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	SEG_DATA
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/* We might want to print out some useful messages.
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 */
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GLNAME( found_intel ):	STRING( "Genuine Intel processor found\n\0" )
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GLNAME( found_amd ):	STRING( "Authentic AMD processor found\n\0" )
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	SEG_TEXT
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ALIGNTEXT4
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GLOBL GLNAME( _mesa_identify_x86_cpu_features )
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GLNAME( _mesa_identify_x86_cpu_features ):
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	PUSH_L	( EBX )
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	PUSH_L	( ESI )
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	/* Test for the CPUID command.  If the ID Flag bit in EFLAGS
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	 * (bit 21) is writable, the CPUID command is present.
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	 */
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	PUSHF_L
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	POP_L	( EAX )
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	MOV_L	( EAX, ECX )
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	XOR_L	( CONST(0x00200000), EAX )
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	PUSH_L	( EAX )
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	POPF_L
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	PUSHF_L
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	POP_L	( EAX )
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	/* Verify the ID Flag bit has been written.
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	 */
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	CMP_L	( ECX, EAX )
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	JZ	( LLBL (cpuid_done) )
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	/* Get the CPU vendor info.
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	 */
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	XOR_L	( EAX, EAX )
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	CPUID
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	/* Test for Intel processors.  We must look for the
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	 * "GenuineIntel" string in EBX, ECX and EDX.
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	 */
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	CMP_L	( CONST(GENU), EBX )
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	JNE	( LLBL(cpuid_amd) )
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	CMP_L	( CONST(INEI), EDX )
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	JNE	( LLBL(cpuid_amd) )
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	CMP_L	( CONST(NTEL), ECX )
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	JNE	( LLBL(cpuid_amd) )
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	/* We have an Intel processor, so we can get the feature
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	 * information with an CPUID input value of 1.
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	 */
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	MOV_L	( CONST(0x1), EAX )
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	CPUID
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	MOV_L	( EDX, EAX )
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	/* Mask out highest bit, which is used by AMD for 3dnow
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         * Newer Intel have this bit set, but do not support 3dnow
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 	 */
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        AND_L   ( CONST(0X7FFFFFFF), EAX)
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	JMP	( LLBL(cpuid_done) )
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LLBL(cpuid_amd):
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	/* Test for AMD processors.  We must look for the
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	 * "AuthenticAMD" string in EBX, ECX and EDX.
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	 */
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	CMP_L	( CONST(AUTH), EBX )
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	JNE	( LLBL(cpuid_other) )
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	CMP_L	( CONST(ENTI), EDX )
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	JNE	( LLBL(cpuid_other) )
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	CMP_L	( CONST(CAMD), ECX )
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	JNE	( LLBL(cpuid_other) )
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	/* We have an AMD processor, so we can get the feature
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	 * information after we verify that the extended functions are
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	 * supported.
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	 */
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	/* The features we need are almost all in the extended set.  The
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	 * exception is SSE enable, which is in the standard set (0x1).
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	 */
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	MOV_L	( CONST(0x1), EAX )
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	CPUID
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	TEST_L	( EAX, EAX )
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	JZ	( LLBL (cpuid_failed) )
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	MOV_L	( EDX, ESI )
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	MOV_L	( CONST(0x80000000), EAX )
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	CPUID
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	TEST_L	( EAX, EAX )
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	JZ	( LLBL (cpuid_failed) )
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	MOV_L	( CONST(0x80000001), EAX )
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	CPUID
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	MOV_L	( EDX, EAX )
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	AND_L	( CONST(0x02000000), ESI )	/* OR in the SSE bit */
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	OR_L	( ESI, EAX )
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	JMP	( LLBL (cpuid_done) )
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LLBL(cpuid_other):
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	/* Test for other processors here when required.
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	 */
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LLBL(cpuid_failed):
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	/* If we can't determine the feature information, we must
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	 * return zero to indicate that no platform-specific
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	 * optimizations can be used.
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	 */
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	MOV_L	( CONST(0), EAX )
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LLBL (cpuid_done):
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	POP_L	( ESI )
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	POP_L	( EBX )
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	RET
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#ifdef USE_SSE_ASM
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/* Execute an SSE instruction to see if the operating system correctly
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 * supports SSE.  A signal handler for SIGILL should have been set
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 * before calling this function, otherwise this could kill the client
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 * application.
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 */
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ALIGNTEXT4
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GLOBL GLNAME( _mesa_test_os_sse_support )
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GLNAME( _mesa_test_os_sse_support ):
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	XORPS	( XMM0, XMM0 )
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	RET
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/* Perform an SSE divide-by-zero to see if the operating system
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 * correctly supports unmasked SIMD FPU exceptions.  Signal handlers for
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 * SIGILL and SIGFPE should have been set before calling this function,
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 * otherwise this could kill the client application.
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 */
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ALIGNTEXT4
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GLOBL GLNAME( _mesa_test_os_sse_exception_support )
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GLNAME( _mesa_test_os_sse_exception_support ):
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	PUSH_L	( EBP )
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	MOV_L	( ESP, EBP )
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	SUB_L	( CONST( 8 ), ESP )
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	/* Save the original MXCSR register value.
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	 */
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	STMXCSR	( REGOFF( -4, EBP ) )
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	/* Unmask the divide-by-zero exception and perform one.
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	 */
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	STMXCSR	( REGOFF( -8, EBP ) )
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	AND_L	( CONST( 0xfffffdff ), REGOFF( -8, EBP ) )
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	LDMXCSR	( REGOFF( -8, EBP ) )
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	XORPS	( XMM0, XMM0 )
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	PUSH_L	( CONST( 0x3f800000 ) )
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	PUSH_L	( CONST( 0x3f800000 ) )
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	PUSH_L	( CONST( 0x3f800000 ) )
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	PUSH_L	( CONST( 0x3f800000 ) )
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	MOVUPS	( REGIND( ESP ), XMM1 )
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	ADD_L	( CONST( 32 ), ESP )
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	DIVPS	( XMM0, XMM1 )
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	/* Restore the original MXCSR register value.
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	 */
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	LDMXCSR	( REGOFF( -4, EBP ) )
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	LEAVE
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	RET
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#endif