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773 giacomo 1
#include <linuxcomp.h>
2
 
425 giacomo 3
#include <media/saa7146_vv.h>
4
 
5
#define my_min(type,x,y) \
6
        ({ type __x = (x), __y = (y); __x < __y ? __x: __y; })
7
#define my_max(type,x,y) \
8
        ({ type __x = (x), __y = (y); __x > __y ? __x: __y; })
9
 
10
static void calculate_output_format_register(struct saa7146_dev* saa, u32 palette, u32* clip_format)
11
{
12
        /* clear out the necessary bits */
13
        *clip_format &= 0x0000ffff;    
14
        /* set these bits new */
15
        *clip_format |=  (( ((palette&0xf00)>>8) << 30) | ((palette&0x00f) << 24) | (((palette&0x0f0)>>4) << 16));
16
}
17
 
18
static void calculate_bcs_ctrl_register(struct saa7146_dev *dev, int brightness, int contrast, int colour, u32 *bcs_ctrl)
19
{
20
        *bcs_ctrl = ((brightness << 24) | (contrast << 16) | (colour <<  0));
21
}
22
 
23
static void calculate_hps_source_and_sync(struct saa7146_dev *dev, int source, int sync, u32* hps_ctrl)
24
{
25
        *hps_ctrl &= ~(MASK_30 | MASK_31 | MASK_28);
26
        *hps_ctrl |= (source << 30) | (sync << 28);
27
}
28
 
29
static void calculate_hxo_and_hyo(struct saa7146_vv *vv, u32* hps_h_scale, u32* hps_ctrl)
30
{
31
        int hyo = 0, hxo = 0;
32
 
33
        hyo = vv->standard->v_offset;
34
        hxo = vv->standard->h_offset;
35
 
36
        *hps_h_scale    &= ~(MASK_B0 | 0xf00);
37
        *hps_h_scale    |= (hxo <<  0);
38
 
39
        *hps_ctrl       &= ~(MASK_W0 | MASK_B2);
40
        *hps_ctrl       |= (hyo << 12);
41
}
42
 
43
/* helper functions for the calculation of the horizontal- and vertical
44
   scaling registers, clip-format-register etc ...
45
   these functions take pointers to the (most-likely read-out
46
   original-values) and manipulate them according to the requested
47
   changes.
48
*/
49
 
50
/* hps_coeff used for CXY and CXUV; scale 1/1 -> scale 1/64 */
51
static struct {
52
        u16 hps_coeff;
53
        u16 weight_sum;
54
} hps_h_coeff_tab [] = {
55
        {0x00,   2}, {0x02,   4}, {0x00,   4}, {0x06,   8}, {0x02,   8},
56
        {0x08,   8}, {0x00,   8}, {0x1E,  16}, {0x0E,   8}, {0x26,   8},
57
        {0x06,   8}, {0x42,   8}, {0x02,   8}, {0x80,   8}, {0x00,   8},
58
        {0xFE,  16}, {0xFE,   8}, {0x7E,   8}, {0x7E,   8}, {0x3E,   8},
59
        {0x3E,   8}, {0x1E,   8}, {0x1E,   8}, {0x0E,   8}, {0x0E,   8},
60
        {0x06,   8}, {0x06,   8}, {0x02,   8}, {0x02,   8}, {0x00,   8},
61
        {0x00,   8}, {0xFE,  16}, {0xFE,   8}, {0xFE,   8}, {0xFE,   8},
62
        {0xFE,   8}, {0xFE,   8}, {0xFE,   8}, {0xFE,   8}, {0xFE,   8},
63
        {0xFE,   8}, {0xFE,   8}, {0xFE,   8}, {0xFE,   8}, {0xFE,   8},
64
        {0xFE,   8}, {0xFE,   8}, {0xFE,   8}, {0xFE,   8}, {0x7E,   8},
65
        {0x7E,   8}, {0x3E,   8}, {0x3E,   8}, {0x1E,   8}, {0x1E,   8},
66
        {0x0E,   8}, {0x0E,   8}, {0x06,   8}, {0x06,   8}, {0x02,   8},
67
        {0x02,   8}, {0x00,   8}, {0x00,   8}, {0xFE,  16}
68
};
69
 
70
/* table of attenuation values for horizontal scaling */
71
u8 h_attenuation[] = { 1, 2, 4, 8, 2, 4, 8, 16, 0};
72
 
73
/* calculate horizontal scale registers */
74
static int calculate_h_scale_registers(struct saa7146_dev *dev,
75
        int in_x, int out_x, int flip_lr,
76
        u32* hps_ctrl, u32* hps_v_gain, u32* hps_h_prescale, u32* hps_h_scale)
77
{
78
        /* horizontal prescaler */
79
        u32 dcgx = 0, xpsc = 0, xacm = 0, cxy = 0, cxuv = 0;   
80
        /* horizontal scaler */
81
        u32 xim = 0, xp = 0, xsci =0;                          
82
        /* vertical scale & gain */
83
        u32 pfuv = 0;                                          
84
 
85
        /* helper variables */
86
        u32 h_atten = 0, i = 0;
87
 
88
        if ( 0 == out_x ) {
89
                return -EINVAL;
90
        }
91
 
92
        /* mask out vanity-bit */
93
        *hps_ctrl &= ~MASK_29;
94
 
95
        /* calculate prescale-(xspc)-value:     [n   .. 1/2) : 1
96
                                                [1/2 .. 1/3) : 2
97
                                                [1/3 .. 1/4) : 3
98
                                                ...             */
99
        if (in_x > out_x) {
100
                xpsc = in_x / out_x;
101
        }
102
        else {
103
                /* zooming */
104
                xpsc = 1;                                              
105
        }
106
 
107
        /* if flip_lr-bit is set, number of pixels after
108
           horizontal prescaling must be < 384 */
109
        if ( 0 != flip_lr ) {
110
 
111
                /* set vanity bit */
112
                *hps_ctrl |= MASK_29;
113
 
114
                while (in_x / xpsc >= 384 )
115
                        xpsc++;
116
        }
117
        /* if zooming is wanted, number of pixels after
118
           horizontal prescaling must be < 768 */
119
        else {
120
                while ( in_x / xpsc >= 768 )
121
                        xpsc++;
122
        }
123
 
124
        /* maximum prescale is 64 (p.69) */
125
        if ( xpsc > 64 )
126
                xpsc = 64;
127
 
128
        /* keep xacm clear*/
129
        xacm = 0;
130
 
131
        /* set horizontal filter parameters (CXY = CXUV) */
132
        cxy = hps_h_coeff_tab[( (xpsc - 1) < 63 ? (xpsc - 1) : 63 )].hps_coeff;
133
        cxuv = cxy;
134
 
135
        /* calculate and set horizontal fine scale (xsci) */
136
 
137
        /* bypass the horizontal scaler ? */
138
        if ( (in_x == out_x) && ( 1 == xpsc ) )
139
                xsci = 0x400;
140
        else   
141
                xsci = ( (1024 * in_x) / (out_x * xpsc) ) + xpsc;
142
 
143
        /* set start phase for horizontal fine scale (xp) to 0 */      
144
        xp = 0;
145
 
146
        /* set xim, if we bypass the horizontal scaler */
147
        if ( 0x400 == xsci )
148
                xim = 1;
149
        else
150
                xim = 0;
151
 
152
        /* if the prescaler is bypassed, enable horizontal
153
           accumulation mode (xacm) and clear dcgx */
154
        if( 1 == xpsc ) {
155
                xacm = 1;
156
                dcgx = 0;
157
        } else {
158
                xacm = 0;
159
                /* get best match in the table of attenuations
160
                   for horizontal scaling */
161
                h_atten = hps_h_coeff_tab[( (xpsc - 1) < 63 ? (xpsc - 1) : 63 )].weight_sum;
162
 
163
                for (i = 0; h_attenuation[i] != 0; i++) {
164
                        if (h_attenuation[i] >= h_atten)
165
                                break;
166
                }
167
 
168
                dcgx = i;
169
        }
170
 
171
        /* the horizontal scaling increment controls the UV filter
172
           to reduce the bandwith to improve the display quality,
173
           so set it ... */
174
        if ( xsci == 0x400)
175
                pfuv = 0x00;
176
        else if ( xsci < 0x600)
177
                pfuv = 0x01;
178
        else if ( xsci < 0x680)
179
                pfuv = 0x11;
180
        else if ( xsci < 0x700)
181
                pfuv = 0x22;
182
        else
183
                pfuv = 0x33;
184
 
185
 
186
        *hps_v_gain  &= MASK_W0|MASK_B2;
187
        *hps_v_gain  |= (pfuv << 24);  
188
 
189
        *hps_h_scale    &= ~(MASK_W1 | 0xf000);
190
        *hps_h_scale    |= (xim << 31) | (xp << 24) | (xsci << 12);
191
 
192
        *hps_h_prescale |= (dcgx << 27) | ((xpsc-1) << 18) | (xacm << 17) | (cxy << 8) | (cxuv << 0);
193
 
194
        return 0;
195
}
196
 
197
static struct {
198
        u16 hps_coeff;
199
        u16 weight_sum;
200
} hps_v_coeff_tab [] = {
201
 {0x0100,   2},  {0x0102,   4},  {0x0300,   4},  {0x0106,   8},  {0x0502,   8},
202
 {0x0708,   8},  {0x0F00,   8},  {0x011E,  16},  {0x110E,  16},  {0x1926,  16},
203
 {0x3906,  16},  {0x3D42,  16},  {0x7D02,  16},  {0x7F80,  16},  {0xFF00,  16},
204
 {0x01FE,  32},  {0x01FE,  32},  {0x817E,  32},  {0x817E,  32},  {0xC13E,  32},
205
 {0xC13E,  32},  {0xE11E,  32},  {0xE11E,  32},  {0xF10E,  32},  {0xF10E,  32},
206
 {0xF906,  32},  {0xF906,  32},  {0xFD02,  32},  {0xFD02,  32},  {0xFF00,  32},
207
 {0xFF00,  32},  {0x01FE,  64},  {0x01FE,  64},  {0x01FE,  64},  {0x01FE,  64},
208
 {0x01FE,  64},  {0x01FE,  64},  {0x01FE,  64},  {0x01FE,  64},  {0x01FE,  64},
209
 {0x01FE,  64},  {0x01FE,  64},  {0x01FE,  64},  {0x01FE,  64},  {0x01FE,  64},
210
 {0x01FE,  64},  {0x01FE,  64},  {0x01FE,  64},  {0x01FE,  64},  {0x817E,  64},
211
 {0x817E,  64},  {0xC13E,  64},  {0xC13E,  64},  {0xE11E,  64},  {0xE11E,  64},
212
 {0xF10E,  64},  {0xF10E,  64},  {0xF906,  64},  {0xF906,  64},  {0xFD02,  64},
213
 {0xFD02,  64},  {0xFF00,  64},  {0xFF00,  64},  {0x01FE, 128}
214
};
215
 
216
/* table of attenuation values for vertical scaling */
217
u16 v_attenuation[] = { 2, 4, 8, 16, 32, 64, 128, 256, 0};
218
 
219
/* calculate vertical scale registers */
220
static int calculate_v_scale_registers(struct saa7146_dev *dev, enum v4l2_field field,
221
        int in_y, int out_y, u32* hps_v_scale, u32* hps_v_gain)
222
{
223
        int lpi = 0;
224
 
225
        /* vertical scaling */
226
        u32 yacm = 0, ysci = 0, yacl = 0, ypo = 0, ype = 0;
227
        /* vertical scale & gain */
228
        u32 dcgy = 0, cya_cyb = 0;
229
 
230
        /* helper variables */
231
        u32 v_atten = 0, i = 0;
232
 
233
        /* error, if vertical zooming */
234
        if ( in_y < out_y ) {
235
                return -EINVAL;
236
        }
237
 
238
        /* linear phase interpolation may be used
239
           if scaling is between 1 and 1/2 (both fields used)
240
           or scaling is between 1/2 and 1/4 (if only one field is used) */
241
 
242
        if (V4L2_FIELD_HAS_BOTH(field)) {
243
                if( 2*out_y >= in_y) {
244
                        lpi = 1;
245
                }
246
        } else if (field == V4L2_FIELD_TOP
247
                || field == V4L2_FIELD_ALTERNATE
248
                || field == V4L2_FIELD_BOTTOM) {
249
                if( 4*out_y >= in_y ) {
250
                        lpi = 1;
251
                }
252
                out_y *= 2;
253
        }
254
        if( 0 != lpi ) {
255
 
256
                yacm = 0;
257
                yacl = 0;
258
                cya_cyb = 0x00ff;
259
 
260
                /* calculate scaling increment */
261
                if ( in_y > out_y )
262
                        ysci = ((1024 * in_y) / (out_y + 1)) - 1024;
263
                else
264
                        ysci = 0;
265
 
266
                dcgy = 0;
267
 
268
                /* calculate ype and ypo */
269
                ype = ysci / 16;
270
                ypo = ype + (ysci / 64);
271
 
272
        } else {
273
                yacm = 1;      
274
 
275
                /* calculate scaling increment */
276
                ysci = (((10 * 1024 * (in_y - out_y - 1)) / in_y) + 9) / 10;
277
 
278
                /* calculate ype and ypo */
279
                ypo = ype = ((ysci + 15) / 16);
280
 
281
                /* the sequence length interval (yacl) has to be set according
282
                   to the prescale value, e.g.  [n   .. 1/2) : 0
283
                                                [1/2 .. 1/3) : 1
284
                                                [1/3 .. 1/4) : 2
285
                                                ... */
286
                if ( ysci < 512) {
287
                        yacl = 0;
288
                } else {
289
                        yacl = ( ysci / (1024 - ysci) );
290
                }
291
 
292
                /* get filter coefficients for cya, cyb from table hps_v_coeff_tab */  
293
                cya_cyb = hps_v_coeff_tab[ (yacl < 63 ? yacl : 63 ) ].hps_coeff;
294
 
295
                /* get best match in the table of attenuations for vertical scaling */
296
                v_atten = hps_v_coeff_tab[ (yacl < 63 ? yacl : 63 ) ].weight_sum;
297
 
298
                for (i = 0; v_attenuation[i] != 0; i++) {
299
                        if (v_attenuation[i] >= v_atten)
300
                                break;
301
                }
302
 
303
                dcgy = i;
304
        }
305
 
306
        /* ypo and ype swapped in spec ? */
307
        *hps_v_scale    |= (yacm << 31) | (ysci << 21) | (yacl << 15) | (ypo << 8 ) | (ype << 1);
308
 
309
        *hps_v_gain     &= ~(MASK_W0|MASK_B2);
310
        *hps_v_gain     |= (dcgy << 16) | (cya_cyb << 0);
311
 
312
        return 0;
313
}
314
 
315
/* simple bubble-sort algorithm with duplicate elimination */
316
static int sort_and_eliminate(u32* values, int* count)
317
{
318
        int low = 0, high = 0, top = 0, temp = 0;
319
        int cur = 0, next = 0;
320
 
321
        /* sanity checks */
322
        if( (0 > *count) || (NULL == values) ) {
323
                return -EINVAL;
324
        }
325
 
326
        /* bubble sort the first ´count´ items of the array ´values´ */
327
        for( top = *count; top > 0; top--) {
328
                for( low = 0, high = 1; high < top; low++, high++) {
329
                        if( values[low] > values[high] ) {
330
                                temp = values[low];
331
                                values[low] = values[high];
332
                                values[high] = temp;
333
                        }
334
                }
335
        }
336
 
337
        /* remove duplicate items */
338
        for( cur = 0, next = 1; next < *count; next++) {
339
                if( values[cur] != values[next])
340
                        values[++cur] = values[next];
341
        }
342
 
343
        *count = cur + 1;
344
 
345
        return 0;
346
}
347
 
348
static void calculate_clipping_registers_rect(struct saa7146_dev *dev, struct saa7146_fh *fh,
349
        struct saa7146_video_dma *vdma2, u32* clip_format, u32* arbtr_ctrl, enum v4l2_field field)
350
{
351
        struct saa7146_vv *vv = dev->vv_data;
352
        u32 *clipping = vv->d_clipping.cpu_addr;
353
 
354
        int width = fh->ov.win.w.width;
355
        int height =  fh->ov.win.w.height;
356
        int clipcount = fh->ov.nclips;
357
 
358
        u32 line_list[32];                     
359
        u32 pixel_list[32];
360
        int numdwords = 0;
361
 
362
        int i = 0, j = 0;
363
        int cnt_line = 0, cnt_pixel = 0;
364
 
365
        int x[32], y[32], w[32], h[32];
366
 
367
        /* clear out memory */
368
        memset(&line_list[0],  0x00, sizeof(u32)*32);
369
        memset(&pixel_list[0], 0x00, sizeof(u32)*32);
370
        memset(clipping,  0x00, SAA7146_CLIPPING_MEM);
371
 
372
        /* fill the line and pixel-lists */
373
        for(i = 0; i < clipcount; i++) {
374
                int l = 0, r = 0, t = 0, b = 0;
375
 
376
                x[i] = fh->ov.clips[i].c.left;
377
                y[i] = fh->ov.clips[i].c.top;
378
                w[i] = fh->ov.clips[i].c.width;
379
                h[i] = fh->ov.clips[i].c.height;
380
 
381
                if( w[i] < 0) {
382
                        x[i] += w[i]; w[i] = -w[i];
383
                }
384
                if( h[i] < 0) {
385
                        y[i] += h[i]; h[i] = -h[i];
386
                }
387
                if( x[i] < 0) {
388
                        w[i] += x[i]; x[i] = 0;
389
                }
390
                if( y[i] < 0) {
391
                        h[i] += y[i]; y[i] = 0;
392
                }      
393
                if( 0 != vv->vflip ) {
394
                        y[i] = height - y[i] - h[i];
395
                }
396
 
397
                l = x[i];
398
                r = x[i]+w[i];
399
                t = y[i];
400
                b = y[i]+h[i];
401
 
402
                /* insert left/right coordinates */
403
                pixel_list[ 2*i   ] = my_min(int, l, width);
404
                pixel_list[(2*i)+1] = my_min(int, r, width);
405
                /* insert top/bottom coordinates */
406
                line_list[ 2*i   ] = my_min(int, t, height);
407
                line_list[(2*i)+1] = my_min(int, b, height);
408
        }
409
 
410
        /* sort and eliminate lists */
411
        cnt_line = cnt_pixel = 2*clipcount;
412
        sort_and_eliminate( &pixel_list[0], &cnt_pixel );
413
        sort_and_eliminate( &line_list[0], &cnt_line );
414
 
415
        /* calculate the number of used u32s */
416
        numdwords = my_max(int, (cnt_line+1), (cnt_pixel+1))*2;
417
        numdwords = my_max(int, 4, numdwords);
418
        numdwords = my_min(int, 64, numdwords);
419
 
420
        /* fill up cliptable */
421
        for(i = 0; i < cnt_pixel; i++) {
422
                clipping[2*i] |= (pixel_list[i] << 16);
423
        }
424
        for(i = 0; i < cnt_line; i++) {
425
                clipping[(2*i)+1] |= (line_list[i] << 16);
426
        }
427
 
428
        /* fill up cliptable with the display infos */
429
        for(j = 0; j < clipcount; j++) {
430
 
431
                for(i = 0; i < cnt_pixel; i++) {
432
 
433
                        if( x[j] < 0)
434
                                x[j] = 0;
435
 
436
                        if( pixel_list[i] < (x[j] + w[j])) {
437
 
438
                                if ( pixel_list[i] >= x[j] ) {
439
                                        clipping[2*i] |= (1 << j);                     
440
                                }
441
                        }
442
                }
443
                for(i = 0; i < cnt_line; i++) {
444
 
445
                        if( y[j] < 0)
446
                                y[j] = 0;
447
 
448
                        if( line_list[i] < (y[j] + h[j]) ) {
449
 
450
                                if( line_list[i] >= y[j] ) {
451
                                        clipping[(2*i)+1] |= (1 << j);                 
452
                                }
453
                        }
454
                }
455
        }
456
 
457
        /* adjust arbitration control register */
458
        *arbtr_ctrl &= 0xffff00ff;
459
        *arbtr_ctrl |= 0x00001c00;     
460
 
461
        vdma2->base_even        = vv->d_clipping.dma_handle;
462
        vdma2->base_odd         = vv->d_clipping.dma_handle;
463
        vdma2->prot_addr        = vv->d_clipping.dma_handle+((sizeof(u32))*(numdwords));
464
        vdma2->base_page        = 0x04;
465
        vdma2->pitch            = 0x00;
466
        vdma2->num_line_byte    = (0 << 16 | (sizeof(u32))*(numdwords-1) );
467
 
468
        /* set clipping-mode. this depends on the field(s) used */
469
        *clip_format &= 0xfffffff7;
470
        if (V4L2_FIELD_HAS_BOTH(field)) {
471
                *clip_format |= 0x00000008;
472
        } else {
473
                *clip_format |= 0x00000000;
474
        }
475
}
476
 
477
/* disable clipping */
478
static void saa7146_disable_clipping(struct saa7146_dev *dev)
479
{
480
        u32 clip_format = saa7146_read(dev, CLIP_FORMAT_CTRL);
481
 
482
        /* mask out relevant bits (=lower word)*/
483
        clip_format &= MASK_W1;
484
 
485
        /* upload clipping-registers*/
486
        saa7146_write(dev, CLIP_FORMAT_CTRL,clip_format);
487
        saa7146_write(dev, MC2, (MASK_05 | MASK_21));
488
 
489
        /* disable video dma2 */
490
        saa7146_write(dev, MC1, MASK_21);
491
}
492
 
493
static void saa7146_set_clipping_rect(struct saa7146_fh *fh)
494
{
495
        struct saa7146_dev *dev = fh->dev;
496
        enum v4l2_field field = fh->ov.win.field;
497
        struct  saa7146_video_dma vdma2;
498
        u32 clip_format;
499
        u32 arbtr_ctrl;
500
 
501
        /* check clipcount, disable clipping if clipcount == 0*/
502
        if( fh->ov.nclips == 0 ) {
503
                saa7146_disable_clipping(dev);
504
                return;
505
        }
506
 
507
        clip_format = saa7146_read(dev, CLIP_FORMAT_CTRL);
508
        arbtr_ctrl = saa7146_read(dev, PCI_BT_V1);
509
 
510
        calculate_clipping_registers_rect(dev, fh, &vdma2, &clip_format, &arbtr_ctrl, field);
511
 
512
        /* set clipping format */
513
        clip_format &= 0xffff0008;
514
        clip_format |= (SAA7146_CLIPPING_RECT << 4);
515
 
516
        /* prepare video dma2 */
517
        saa7146_write(dev, BASE_EVEN2,          vdma2.base_even);
518
        saa7146_write(dev, BASE_ODD2,           vdma2.base_odd);
519
        saa7146_write(dev, PROT_ADDR2,          vdma2.prot_addr);
520
        saa7146_write(dev, BASE_PAGE2,          vdma2.base_page);
521
        saa7146_write(dev, PITCH2,              vdma2.pitch);
522
        saa7146_write(dev, NUM_LINE_BYTE2,      vdma2.num_line_byte);
523
 
524
        /* prepare the rest */
525
        saa7146_write(dev, CLIP_FORMAT_CTRL,clip_format);
526
        saa7146_write(dev, PCI_BT_V1, arbtr_ctrl);     
527
 
528
        /* upload clip_control-register, clipping-registers, enable video dma2 */
529
        saa7146_write(dev, MC2, (MASK_05 | MASK_21 | MASK_03 | MASK_19));
530
        saa7146_write(dev, MC1, (MASK_05 | MASK_21));
531
}
532
 
533
static void saa7146_set_window(struct saa7146_dev *dev, int width, int height, enum v4l2_field field)
534
{
535
        struct saa7146_vv *vv = dev->vv_data;
536
 
537
        int source = vv->current_hps_source;
538
        int sync = vv->current_hps_sync;
539
 
540
        u32 hps_v_scale = 0, hps_v_gain  = 0, hps_ctrl = 0, hps_h_prescale = 0, hps_h_scale = 0;
541
 
542
        /* set vertical scale */
543
        hps_v_scale = 0; /* all bits get set by the function-call */
544
        hps_v_gain  = 0; /* fixme: saa7146_read(dev, HPS_V_GAIN);*/
545
        calculate_v_scale_registers(dev, field, vv->standard->v_calc, height, &hps_v_scale, &hps_v_gain);
546
 
547
        /* set horizontal scale */
548
        hps_ctrl        = 0;
549
        hps_h_prescale  = 0; /* all bits get set in the function */
550
        hps_h_scale     = 0;
551
        calculate_h_scale_registers(dev, vv->standard->h_calc, width, vv->hflip, &hps_ctrl, &hps_v_gain, &hps_h_prescale, &hps_h_scale);
552
 
553
        /* set hyo and hxo */
554
        calculate_hxo_and_hyo(vv, &hps_h_scale, &hps_ctrl);
555
        calculate_hps_source_and_sync(dev, source, sync, &hps_ctrl);
556
 
557
        /* write out new register contents */
558
        saa7146_write(dev, HPS_V_SCALE, hps_v_scale);
559
        saa7146_write(dev, HPS_V_GAIN,  hps_v_gain);
560
        saa7146_write(dev, HPS_CTRL,    hps_ctrl);
561
        saa7146_write(dev, HPS_H_PRESCALE,hps_h_prescale);
562
        saa7146_write(dev, HPS_H_SCALE, hps_h_scale);
563
 
564
        /* upload shadow-ram registers */
565
        saa7146_write(dev, MC2, (MASK_05 | MASK_06 | MASK_21 | MASK_22) );
566
}
567
 
568
/* calculate the new memory offsets for a desired position */
569
static void saa7146_set_position(struct saa7146_dev *dev, int w_x, int w_y, int w_height, enum v4l2_field field)
570
{      
571
        struct saa7146_vv *vv = dev->vv_data;
572
 
573
        int b_depth = vv->ov_fmt->depth;
574
        int b_bpl = vv->ov_fb.fmt.bytesperline;
575
        u32 base = (u32)vv->ov_fb.base;
576
 
577
        struct  saa7146_video_dma vdma1;
578
 
579
        /* calculate memory offsets for picture, look if we shall top-down-flip */
580
        vdma1.pitch     = 2*b_bpl;
581
        if ( 0 == vv->vflip ) {
582
                vdma1.base_even = (u32)base + (w_y * (vdma1.pitch/2)) + (w_x * (b_depth / 8));
583
                vdma1.base_odd  = vdma1.base_even + (vdma1.pitch / 2);
584
                vdma1.prot_addr = vdma1.base_even + (w_height * (vdma1.pitch / 2));
585
        }
586
        else {
587
                vdma1.base_even = (u32)base + ((w_y+w_height) * (vdma1.pitch/2)) + (w_x * (b_depth / 8));
588
                vdma1.base_odd  = vdma1.base_even - (vdma1.pitch / 2);
589
                vdma1.prot_addr = vdma1.base_odd - (w_height * (vdma1.pitch / 2));
590
        }
591
 
592
        if (V4L2_FIELD_HAS_BOTH(field)) {
593
        } else if (field == V4L2_FIELD_ALTERNATE) {
594
                /* fixme */
595
                vdma1.base_odd = vdma1.prot_addr;
596
                vdma1.pitch /= 2;
597
        } else if (field == V4L2_FIELD_TOP) {
598
                vdma1.base_odd = vdma1.prot_addr;
599
                vdma1.pitch /= 2;
600
        } else if (field == V4L2_FIELD_BOTTOM) {
601
                vdma1.base_odd = vdma1.base_even;
602
                vdma1.base_even = vdma1.prot_addr;
603
                vdma1.pitch /= 2;
604
        }
605
 
606
        if ( 0 != vv->vflip ) {
607
                vdma1.pitch *= -1;
608
        }
609
 
610
        vdma1.base_page = 0;
611
        vdma1.num_line_byte = (vv->standard->v_field<<16)+vv->standard->h_pixels;
612
 
613
        saa7146_write_out_dma(dev, 1, &vdma1);
614
}
615
 
616
static void saa7146_set_output_format(struct saa7146_dev *dev, unsigned long palette)
617
{
618
        u32 clip_format = saa7146_read(dev, CLIP_FORMAT_CTRL);
619
 
620
        /* call helper function */
621
        calculate_output_format_register(dev,palette,&clip_format);
622
 
623
        /* update the hps registers */
624
        saa7146_write(dev, CLIP_FORMAT_CTRL, clip_format);
625
        saa7146_write(dev, MC2, (MASK_05 | MASK_21));
626
}
627
 
628
void saa7146_set_picture_prop(struct saa7146_dev *dev, int brightness, int contrast, int colour)
629
{
630
        u32 bcs_ctrl = 0;
631
 
632
        calculate_bcs_ctrl_register(dev, brightness, contrast, colour, &bcs_ctrl);
633
        saa7146_write(dev, BCS_CTRL, bcs_ctrl);
634
 
635
        /* update the bcs register */
636
        saa7146_write(dev, MC2, (MASK_06 | MASK_22));
637
}
638
 
639
 
640
/* select input-source */
641
void saa7146_set_hps_source_and_sync(struct saa7146_dev *dev, int source, int sync)
642
{
643
        struct saa7146_vv *vv = dev->vv_data;
644
        u32 hps_ctrl = 0;
645
 
646
        /* read old state */
647
        hps_ctrl = saa7146_read(dev, HPS_CTRL);
648
 
649
        hps_ctrl &= ~( MASK_31 | MASK_30 | MASK_28 );
650
        hps_ctrl |= (source << 30) | (sync << 28);
651
 
652
        /* write back & upload register */
653
        saa7146_write(dev, HPS_CTRL, hps_ctrl);
654
        saa7146_write(dev, MC2, (MASK_05 | MASK_21));
655
 
656
        vv->current_hps_source = source;
657
        vv->current_hps_sync = sync;
658
}
659
 
660
int saa7146_enable_overlay(struct saa7146_fh *fh)
661
{
662
        struct saa7146_dev *dev = fh->dev;
663
        struct saa7146_vv *vv = dev->vv_data;
664
 
665
        saa7146_set_window(dev, fh->ov.win.w.width, fh->ov.win.w.height, fh->ov.win.field);
666
        saa7146_set_position(dev, fh->ov.win.w.left, fh->ov.win.w.top, fh->ov.win.w.height, fh->ov.win.field);
667
        saa7146_set_output_format(dev, vv->ov_fmt->trans);
668
        saa7146_set_clipping_rect(fh);
669
 
670
        /* enable video dma1 */
671
        saa7146_write(dev, MC1, (MASK_06 | MASK_22));
672
        return 0;
673
}              
674
 
675
void saa7146_disable_overlay(struct saa7146_fh *fh)
676
{
677
        struct saa7146_dev *dev = fh->dev;
678
 
679
        /* disable clipping + video dma1 */
680
        saa7146_disable_clipping(dev);
681
        saa7146_write(dev, MC1, MASK_22);
682
}              
683
 
684
void saa7146_write_out_dma(struct saa7146_dev* dev, int which, struct saa7146_video_dma* vdma)
685
{
686
        int where = 0;
687
 
688
        if( which < 1 || which > 3) {
689
                return;
690
        }
691
 
692
        /* calculate starting address */
693
        where  = (which-1)*0x18;
694
 
695
        saa7146_write(dev, where,       vdma->base_odd);
696
        saa7146_write(dev, where+0x04,  vdma->base_even);
697
        saa7146_write(dev, where+0x08,  vdma->prot_addr);
698
        saa7146_write(dev, where+0x0c,  vdma->pitch);
699
        saa7146_write(dev, where+0x10,  vdma->base_page);
700
        saa7146_write(dev, where+0x14,  vdma->num_line_byte);
701
 
702
        /* upload */
703
        saa7146_write(dev, MC2, (MASK_02<<(which-1))|(MASK_18<<(which-1)));            
704
/*             
705
        printk("vdma%d.base_even:     0x%08x\n", which,vdma->base_even);
706
        printk("vdma%d.base_odd:      0x%08x\n", which,vdma->base_odd);
707
        printk("vdma%d.prot_addr:     0x%08x\n", which,vdma->prot_addr);
708
        printk("vdma%d.base_page:     0x%08x\n", which,vdma->base_page);
709
        printk("vdma%d.pitch:         0x%08x\n", which,vdma->pitch);
710
        printk("vdma%d.num_line_byte: 0x%08x\n", which,vdma->num_line_byte);
711
*/
712
}
713
 
714
static int calculate_video_dma_grab_packed(struct saa7146_dev* dev, struct saa7146_buf *buf)
715
{
716
        struct saa7146_vv *vv = dev->vv_data;
717
        struct saa7146_video_dma vdma1;
718
 
719
        struct saa7146_format *sfmt = format_by_fourcc(dev,buf->fmt->pixelformat);
720
 
721
        int width = buf->fmt->width;
722
        int height = buf->fmt->height;
723
        int bytesperline = buf->fmt->bytesperline;
724
        enum v4l2_field field = buf->fmt->field;
725
 
726
        int depth = sfmt->depth;
727
 
728
        DEB_CAP(("[size=%dx%d,fields=%s]\n",
729
                width,height,v4l2_field_names[field]));
730
 
731
        if( bytesperline != 0) {
732
                vdma1.pitch = bytesperline*2;
733
        } else {
734
                vdma1.pitch = (width*depth*2)/8;
735
        }
736
        vdma1.num_line_byte     = ((vv->standard->v_field<<16) + vv->standard->h_pixels);
737
        vdma1.base_page         = buf->pt[0].dma | ME1;
738
 
739
        if( 0 != vv->vflip ) {
740
                vdma1.prot_addr = buf->pt[0].offset;
741
                vdma1.base_even = buf->pt[0].offset+(vdma1.pitch/2)*height;
742
                vdma1.base_odd  = vdma1.base_even - (vdma1.pitch/2);
743
        } else {
744
                vdma1.base_even = buf->pt[0].offset;
745
                vdma1.base_odd  = vdma1.base_even + (vdma1.pitch/2);
746
                vdma1.prot_addr = buf->pt[0].offset+(vdma1.pitch/2)*height;
747
        }
748
 
749
        if (V4L2_FIELD_HAS_BOTH(field)) {
750
        } else if (field == V4L2_FIELD_ALTERNATE) {
751
                /* fixme */
752
                if ( vv->last_field == V4L2_FIELD_TOP ) {
753
                        vdma1.base_odd  = vdma1.prot_addr;
754
                        vdma1.pitch /= 2;
755
                } else if ( vv->last_field == V4L2_FIELD_BOTTOM ) {
756
                        vdma1.base_odd  = vdma1.base_even;
757
                        vdma1.base_even = vdma1.prot_addr;
758
                        vdma1.pitch /= 2;
759
                }
760
        } else if (field == V4L2_FIELD_TOP) {
761
                vdma1.base_odd  = vdma1.prot_addr;
762
                vdma1.pitch /= 2;
763
        } else if (field == V4L2_FIELD_BOTTOM) {
764
                vdma1.base_odd  = vdma1.base_even;
765
                vdma1.base_even = vdma1.prot_addr;
766
                vdma1.pitch /= 2;
767
        }
768
 
769
        if( 0 != vv->vflip ) {
770
                vdma1.pitch *= -1;
771
        }      
772
 
773
        saa7146_write_out_dma(dev, 1, &vdma1);
774
        return 0;
775
}
776
 
777
static int calc_planar_422(struct saa7146_vv *vv, struct saa7146_buf *buf, struct saa7146_video_dma *vdma2, struct saa7146_video_dma *vdma3)
778
{
779
        int height = buf->fmt->height;
780
        int width = buf->fmt->width;
781
 
782
        vdma2->pitch    = width;
783
        vdma3->pitch    = width;
784
 
785
        /* fixme: look at bytesperline! */
786
 
787
        if( 0 != vv->vflip ) {
788
                vdma2->prot_addr        = buf->pt[1].offset;
789
                vdma2->base_even        = ((vdma2->pitch/2)*height)+buf->pt[1].offset;
790
                vdma2->base_odd         = vdma2->base_even - (vdma2->pitch/2);
791
 
792
                vdma3->prot_addr        = buf->pt[2].offset;
793
                vdma3->base_even        = ((vdma3->pitch/2)*height)+buf->pt[2].offset;
794
                vdma3->base_odd         = vdma3->base_even - (vdma3->pitch/2);
795
        } else {
796
                vdma3->base_even        = buf->pt[2].offset;
797
                vdma3->base_odd         = vdma3->base_even + (vdma3->pitch/2);
798
                vdma3->prot_addr        = (vdma3->pitch/2)*height+buf->pt[2].offset;
799
 
800
                vdma2->base_even        = buf->pt[1].offset;
801
                vdma2->base_odd         = vdma2->base_even + (vdma2->pitch/2);
802
                vdma2->prot_addr        = (vdma2->pitch/2)*height+buf->pt[1].offset;
803
        }
804
 
805
        return 0;
806
}
807
 
808
static int calc_planar_420(struct saa7146_vv *vv, struct saa7146_buf *buf, struct saa7146_video_dma *vdma2, struct saa7146_video_dma *vdma3)
809
{
810
        int height = buf->fmt->height;
811
        int width = buf->fmt->width;
812
 
813
        vdma2->pitch    = width/2;
814
        vdma3->pitch    = width/2;
815
 
816
        if( 0 != vv->vflip ) {
817
                vdma2->prot_addr        = buf->pt[2].offset;
818
                vdma2->base_even        = ((vdma2->pitch/2)*height)+buf->pt[2].offset;
819
                vdma2->base_odd         = vdma2->base_even - (vdma2->pitch/2);
820
 
821
                vdma3->prot_addr        = buf->pt[1].offset;
822
                vdma3->base_even        = ((vdma3->pitch/2)*height)+buf->pt[1].offset;
823
                vdma3->base_odd         = vdma3->base_even - (vdma3->pitch/2);
824
 
825
        } else {
826
                vdma3->base_even        = buf->pt[2].offset;
827
                vdma3->base_odd         = vdma3->base_even + (vdma3->pitch);
828
                vdma3->prot_addr        = (vdma3->pitch/2)*height+buf->pt[2].offset;
829
 
830
                vdma2->base_even        = buf->pt[1].offset;
831
                vdma2->base_odd         = vdma2->base_even + (vdma2->pitch);
832
                vdma2->prot_addr        = (vdma2->pitch/2)*height+buf->pt[1].offset;
833
        }
834
        return 0;
835
}
836
 
837
 
838
static int calculate_video_dma_grab_planar(struct saa7146_dev* dev, struct saa7146_buf *buf)
839
{
840
        struct saa7146_vv *vv = dev->vv_data;
841
        struct saa7146_video_dma vdma1;
842
        struct saa7146_video_dma vdma2;
843
        struct saa7146_video_dma vdma3;
844
 
845
        struct saa7146_format *sfmt = format_by_fourcc(dev,buf->fmt->pixelformat);
846
 
847
        int width = buf->fmt->width;
848
        int height = buf->fmt->height;
849
        enum v4l2_field field = buf->fmt->field;
850
 
851
        BUG_ON(0 == buf->pt[0].dma);
852
        BUG_ON(0 == buf->pt[1].dma);
853
        BUG_ON(0 == buf->pt[2].dma);
854
 
855
        DEB_CAP(("[size=%dx%d,fields=%s]\n",
856
                width,height,v4l2_field_names[field]));
857
 
858
        /* fixme: look at bytesperline! */
859
 
860
        /* fixme: what happens for user space buffers here?. The offsets are
861
           most likely wrong, this version here only works for page-aligned
862
           buffers, modifications to the pagetable-functions are necessary...*/
863
 
864
        vdma1.pitch             = width*2;
865
        vdma1.num_line_byte     = ((vv->standard->v_field<<16) + vv->standard->h_pixels);
866
        vdma1.base_page         = buf->pt[0].dma | ME1;
867
 
868
        if( 0 != vv->vflip ) {
869
                vdma1.prot_addr = buf->pt[0].offset;
870
                vdma1.base_even = ((vdma1.pitch/2)*height)+buf->pt[0].offset;
871
                vdma1.base_odd  = vdma1.base_even - (vdma1.pitch/2);
872
        } else {
873
                vdma1.base_even = buf->pt[0].offset;
874
                vdma1.base_odd  = vdma1.base_even + (vdma1.pitch/2);
875
                vdma1.prot_addr = (vdma1.pitch/2)*height+buf->pt[0].offset;
876
        }
877
 
878
        vdma2.num_line_byte     = 0; /* unused */
879
        vdma2.base_page         = buf->pt[1].dma | ME1;
880
 
881
        vdma3.num_line_byte     = 0; /* unused */
882
        vdma3.base_page         = buf->pt[2].dma | ME1;
883
 
884
        switch( sfmt->depth ) {
885
                case 12: {
886
                        calc_planar_420(vv,buf,&vdma2,&vdma3);
887
                        break;
888
                }
889
                case 16: {
890
                        calc_planar_422(vv,buf,&vdma2,&vdma3);
891
                        break;
892
                }
893
                default: {
894
                        return -1;
895
                }
896
        }
897
 
898
        if (V4L2_FIELD_HAS_BOTH(field)) {
899
        } else if (field == V4L2_FIELD_ALTERNATE) {
900
                /* fixme */
901
                vdma1.base_odd  = vdma1.prot_addr;
902
                vdma1.pitch /= 2;
903
                vdma2.base_odd  = vdma2.prot_addr;
904
                vdma2.pitch /= 2;
905
                vdma3.base_odd  = vdma3.prot_addr;
906
                vdma3.pitch /= 2;
907
        } else if (field == V4L2_FIELD_TOP) {
908
                vdma1.base_odd  = vdma1.prot_addr;
909
                vdma1.pitch /= 2;
910
                vdma2.base_odd  = vdma2.prot_addr;
911
                vdma2.pitch /= 2;
912
                vdma3.base_odd  = vdma3.prot_addr;
913
                vdma3.pitch /= 2;
914
        } else if (field == V4L2_FIELD_BOTTOM) {
915
                vdma1.base_odd  = vdma1.base_even;
916
                vdma1.base_even = vdma1.prot_addr;
917
                vdma1.pitch /= 2;
918
                vdma2.base_odd  = vdma2.base_even;
919
                vdma2.base_even = vdma2.prot_addr;
920
                vdma2.pitch /= 2;
921
                vdma3.base_odd  = vdma3.base_even;
922
                vdma3.base_even = vdma3.prot_addr;
923
                vdma3.pitch /= 2;
924
        }
925
 
926
        if( 0 != vv->vflip ) {
927
                vdma1.pitch *= -1;
928
                vdma2.pitch *= -1;
929
                vdma3.pitch *= -1;
930
        }      
931
 
932
        saa7146_write_out_dma(dev, 1, &vdma1);
933
        if( (sfmt->flags & FORMAT_BYTE_SWAP) != 0 ) {
934
                saa7146_write_out_dma(dev, 3, &vdma2);
935
                saa7146_write_out_dma(dev, 2, &vdma3);
936
        } else {
937
                saa7146_write_out_dma(dev, 2, &vdma2);
938
                saa7146_write_out_dma(dev, 3, &vdma3);
939
        }
940
        return 0;
941
}
942
 
943
static void program_capture_engine(struct saa7146_dev *dev, int planar)
944
{
945
        struct saa7146_vv *vv = dev->vv_data;
946
        int count = 0;
947
 
948
        unsigned long e_wait = vv->current_hps_sync == SAA7146_HPS_SYNC_PORT_A ? CMD_E_FID_A : CMD_E_FID_B;
949
        unsigned long o_wait = vv->current_hps_sync == SAA7146_HPS_SYNC_PORT_A ? CMD_O_FID_A : CMD_O_FID_B;
950
 
951
        /* wait for o_fid_a/b / e_fid_a/b toggle only if rps register 0 is not set*/
952
        WRITE_RPS0(CMD_PAUSE | CMD_OAN | CMD_SIG0 | o_wait);
953
        WRITE_RPS0(CMD_PAUSE | CMD_OAN | CMD_SIG0 | e_wait);
954
 
955
        /* set rps register 0 */
956
        WRITE_RPS0(CMD_WR_REG | (1 << 8) | (MC2/4));    
957
        WRITE_RPS0(MASK_27 | MASK_11);
958
 
959
        /* turn on video-dma1 */
960
        WRITE_RPS0(CMD_WR_REG_MASK | (MC1/4));         
961
        WRITE_RPS0(MASK_06 | MASK_22);                  /* => mask */
962
        WRITE_RPS0(MASK_06 | MASK_22);                  /* => values */
963
        if( 0 != planar ) {
964
                /* turn on video-dma2 */
965
                WRITE_RPS0(CMD_WR_REG_MASK | (MC1/4));         
966
                WRITE_RPS0(MASK_05 | MASK_21);                  /* => mask */
967
                WRITE_RPS0(MASK_05 | MASK_21);                  /* => values */
968
 
969
                /* turn on video-dma3 */
970
                WRITE_RPS0(CMD_WR_REG_MASK | (MC1/4));         
971
                WRITE_RPS0(MASK_04 | MASK_20);                  /* => mask */
972
                WRITE_RPS0(MASK_04 | MASK_20);                  /* => values */
973
        }
974
 
975
        /* wait for o_fid_a/b / e_fid_a/b toggle */
976
        if ( vv->last_field == V4L2_FIELD_INTERLACED ) {
977
                WRITE_RPS0(CMD_PAUSE | o_wait);
978
                WRITE_RPS0(CMD_PAUSE | e_wait);
979
        } else if ( vv->last_field == V4L2_FIELD_TOP ) {
980
                WRITE_RPS0(CMD_PAUSE | (vv->current_hps_sync == SAA7146_HPS_SYNC_PORT_A ? MASK_10 : MASK_09));
981
                WRITE_RPS0(CMD_PAUSE | o_wait);
982
        } else if ( vv->last_field == V4L2_FIELD_BOTTOM ) {
983
                WRITE_RPS0(CMD_PAUSE | (vv->current_hps_sync == SAA7146_HPS_SYNC_PORT_A ? MASK_10 : MASK_09));
984
                WRITE_RPS0(CMD_PAUSE | e_wait);
985
        }
986
 
987
        /* turn off video-dma1 */
988
        WRITE_RPS0(CMD_WR_REG_MASK | (MC1/4));
989
        WRITE_RPS0(MASK_22 | MASK_06);                  /* => mask */
990
        WRITE_RPS0(MASK_22);                                    /* => values */
991
        if( 0 != planar ) {
992
                /* turn off video-dma2 */
993
                WRITE_RPS0(CMD_WR_REG_MASK | (MC1/4));         
994
                WRITE_RPS0(MASK_05 | MASK_21);                  /* => mask */
995
                WRITE_RPS0(MASK_21);                                    /* => values */
996
 
997
                /* turn off video-dma3 */
998
                WRITE_RPS0(CMD_WR_REG_MASK | (MC1/4));         
999
                WRITE_RPS0(MASK_04 | MASK_20);                  /* => mask */
1000
                WRITE_RPS0(MASK_20);                                    /* => values */
1001
        }
1002
 
1003
        /* generate interrupt */
1004
        WRITE_RPS0(CMD_INTERRUPT);                                     
1005
 
1006
        /* stop */
1007
        WRITE_RPS0(CMD_STOP);                                  
1008
}
1009
 
1010
void saa7146_set_capture(struct saa7146_dev *dev, struct saa7146_buf *buf, struct saa7146_buf *next)
1011
{
1012
        struct saa7146_format *sfmt = format_by_fourcc(dev,buf->fmt->pixelformat);
1013
        struct saa7146_vv *vv = dev->vv_data;
1014
        u32 vdma1_prot_addr;
1015
 
1016
        DEB_CAP(("buf:%p, next:%p\n",buf,next));
1017
 
1018
        vdma1_prot_addr = saa7146_read(dev, PROT_ADDR1);
1019
        if( 0 == vdma1_prot_addr ) {
1020
                /* clear out beginning of streaming bit (rps register 0)*/
1021
                DEB_CAP(("forcing sync to new frame\n"));
1022
                saa7146_write(dev, MC2, MASK_27 );
1023
        }
1024
 
1025
        saa7146_set_window(dev, buf->fmt->width, buf->fmt->height, buf->fmt->field);
1026
        saa7146_set_output_format(dev, sfmt->trans);
1027
 
1028
        if ( vv->last_field == V4L2_FIELD_INTERLACED ) {
1029
        } else if ( vv->last_field == V4L2_FIELD_TOP ) {
1030
                vv->last_field = V4L2_FIELD_BOTTOM;
1031
        } else if ( vv->last_field == V4L2_FIELD_BOTTOM ) {
1032
                vv->last_field = V4L2_FIELD_TOP;
1033
        }
1034
 
1035
        if( 0 != IS_PLANAR(sfmt->trans)) {
1036
                calculate_video_dma_grab_planar(dev, buf);
1037
                program_capture_engine(dev,1);
1038
        } else {
1039
                calculate_video_dma_grab_packed(dev, buf);
1040
                program_capture_engine(dev,0);
1041
        }
1042
 
1043
/*
1044
        printk("vdma%d.base_even:     0x%08x\n", 1,saa7146_read(dev,BASE_EVEN1));
1045
        printk("vdma%d.base_odd:      0x%08x\n", 1,saa7146_read(dev,BASE_ODD1));
1046
        printk("vdma%d.prot_addr:     0x%08x\n", 1,saa7146_read(dev,PROT_ADDR1));
1047
        printk("vdma%d.base_page:     0x%08x\n", 1,saa7146_read(dev,BASE_PAGE1));
1048
        printk("vdma%d.pitch:         0x%08x\n", 1,saa7146_read(dev,PITCH1));
1049
        printk("vdma%d.num_line_byte: 0x%08x\n", 1,saa7146_read(dev,NUM_LINE_BYTE1));
1050
        printk("vdma%d => vptr      : 0x%08x\n", 1,saa7146_read(dev,PCI_VDP1));
1051
*/
1052
 
1053
        /* write the address of the rps-program */
1054
        saa7146_write(dev, RPS_ADDR0, dev->d_rps0.dma_handle);
1055
 
1056
        /* turn on rps */
1057
        saa7146_write(dev, MC1, (MASK_12 | MASK_28));  
1058
}
1059