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684 giacomo 1
/*
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 * Project: S.Ha.R.K.
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 *
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 * Coordinators:
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 *   Giorgio Buttazzo    <giorgio@sssup.it>
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 *   Paolo Gai           <pj@gandalf.sssup.it>
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 *
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 * Authors     :
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 *   Paolo Gai           <pj@gandalf.sssup.it>
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 *   Massimiliano Giorgi <massy@gandalf.sssup.it>
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 *   Luca Abeni          <luca@gandalf.sssup.it>
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 *   (see the web pages for full authors list)
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 *
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 * ReTiS Lab (Scuola Superiore S.Anna - Pisa - Italy)
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 *
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 * http://www.sssup.it
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 * http://retis.sssup.it
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 * http://shark.sssup.it
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 */
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/**
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 ------------
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 CVS :        $Id: rtc.h,v 1.1 2004-05-26 10:12:41 giacomo Exp $
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 File:        $File$
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 Revision:    $Revision: 1.1 $
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 Last update: $Date: 2004-05-26 10:12:41 $
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 ------------
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 Author:      Massimiliano Giorgi
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 A source from Linux 2.2.9 modified to work with S.Ha.R.K.
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 mc146818rtc.h - register definitions for the Real-Time-Clock / CMOS RAM
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 Copyright Torsten Duwe <duwe@informatik.uni-erlangen.de> 1993
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 derived from Data Sheet, Copyright Motorola 1984 (!).
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 It was written to be part of the Linux operating system.
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**/
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/*
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 * Copyright (C) 2000 Paolo Gai
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 *
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 * You should have received a copy of the GNU General Public License
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 * along with this program; if not, write to the Free Software
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 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
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 *
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 */
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#ifndef _MC146818RTC_H
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#define _MC146818RTC_H
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#include <rtcfunc.h>
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#ifndef RTC_PORT
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#define RTC_PORT(x)     (0x70 + (x))
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#define RTC_ALWAYS_BCD  1
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#endif
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/**********************************************************************
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 * register summary
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 **********************************************************************/
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#define RTC_SECONDS             0
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#define RTC_SECONDS_ALARM       1
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#define RTC_MINUTES             2
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#define RTC_MINUTES_ALARM       3
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#define RTC_HOURS               4
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#define RTC_HOURS_ALARM         5
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/* RTC_*_alarm is always true if 2 MSBs are set */
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# define RTC_ALARM_DONT_CARE    0xC0
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#define RTC_DAY_OF_WEEK         6
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#define RTC_DAY_OF_MONTH        7
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#define RTC_MONTH               8
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#define RTC_YEAR                9
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/* control registers - Moto names
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 */
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#define RTC_REG_A               10
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#define RTC_REG_B               11
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#define RTC_REG_C               12
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#define RTC_REG_D               13
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/**********************************************************************
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 * register details
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 **********************************************************************/
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#define RTC_FREQ_SELECT RTC_REG_A
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/* update-in-progress  - set to "1" 244 microsecs before RTC goes off the bus,
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 * reset after update (may take 1.984ms @ 32768Hz RefClock) is complete,
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 * totalling to a max high interval of 2.228 ms.
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 */
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# define RTC_UIP                0x80
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# define RTC_DIV_CTL            0x70
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   /* divider control: refclock values 4.194 / 1.049 MHz / 32.768 kHz */
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#  define RTC_REF_CLCK_4MHZ     0x00
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#  define RTC_REF_CLCK_1MHZ     0x10
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#  define RTC_REF_CLCK_32KHZ    0x20
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   /* 2 values for divider stage reset, others for "testing purposes only" */
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#  define RTC_DIV_RESET1        0x60
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#  define RTC_DIV_RESET2        0x70
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  /* Periodic intr. / Square wave rate select. 0=none, 1=32.8kHz,... 15=2Hz */
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# define RTC_RATE_SELECT        0x0F
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/**********************************************************************/
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#define RTC_CONTROL     RTC_REG_B
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# define RTC_SET 0x80           /* disable updates for clock setting */
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# define RTC_PIE 0x40           /* periodic interrupt enable */
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# define RTC_AIE 0x20           /* alarm interrupt enable */
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# define RTC_UIE 0x10           /* update-finished interrupt enable */
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# define RTC_SQWE 0x08          /* enable square-wave output */
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# define RTC_DM_BINARY 0x04     /* all time/date values are BCD if clear */
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# define RTC_24H 0x02           /* 24 hour mode - else hours bit 7 means pm */
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# define RTC_DST_EN 0x01        /* auto switch DST - works f. USA only */
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/**********************************************************************/
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#define RTC_INTR_FLAGS  RTC_REG_C
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/* caution - cleared by read */
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# define RTC_IRQF 0x80          /* any of the following 3 is active */
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# define RTC_PF 0x40
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# define RTC_AF 0x20
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# define RTC_UF 0x10
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/**********************************************************************/
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#define RTC_VALID       RTC_REG_D
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# define RTC_VRT 0x80           /* valid RAM and time */
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/**********************************************************************/
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/* example: !(CMOS_READ(RTC_CONTROL) & RTC_DM_BINARY)
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 * determines if the following two #defines are needed
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 */
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#ifndef BCD_TO_BIN
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#define BCD_TO_BIN(val) ((val)=((val)&15) + ((val)>>4)*10)
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#endif
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#ifndef BIN_TO_BCD
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#define BIN_TO_BCD(val) ((val)=(((val)/10)<<4) + (val)%10)
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#endif
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/*
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 * ioctl calls that are permitted to the /dev/rtc interface, if
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 * CONFIG_RTC was enabled.
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 */
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#define RTC_AIE_ON      _IO('p', 0x01)  /* Alarm int. enable on         */
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#define RTC_AIE_OFF     _IO('p', 0x02)  /* ... off                      */
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#define RTC_UIE_ON      _IO('p', 0x03)  /* Update int. enable on        */
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#define RTC_UIE_OFF     _IO('p', 0x04)  /* ... off                      */
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#define RTC_PIE_ON      _IO('p', 0x05)  /* Periodic int. enable on      */
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#define RTC_PIE_OFF     _IO('p', 0x06)  /* ... off                      */
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#define RTC_ALM_SET     _IOW('p', 0x07, struct rtc_time) /* Set alarm time  */
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#define RTC_ALM_READ    _IOR('p', 0x08, struct rtc_time) /* Read alarm time */
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#define RTC_RD_TIME     _IOR('p', 0x09, struct rtc_time) /* Read RTC time   */
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#define RTC_SET_TIME    _IOW('p', 0x0a, struct rtc_time) /* Set RTC time    */
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#define RTC_IRQP_READ   _IOR('p', 0x0b, unsigned long)   /* Read IRQ rate   */
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#define RTC_IRQP_SET    _IOW('p', 0x0c, unsigned long)   /* Set IRQ rate    */
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#define RTC_EPOCH_READ  _IOR('p', 0x0d, unsigned long)   /* Read epoch      */
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#define RTC_EPOCH_SET   _IOW('p', 0x0e, unsigned long)   /* Set epoch       */
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#endif /* _MC146818RTC_H */