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| Rev | Author | Line No. | Line |
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| 2 | pj | 1 | /* Project: OSLib |
| 2 | * Description: The OS Construction Kit |
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| 3 | * Date: 1.6.2000 |
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| 4 | * Idea by: Luca Abeni & Gerardo Lamastra |
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| 5 | * |
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| 6 | * OSLib is an SO project aimed at developing a common, easy-to-use |
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| 7 | * low-level infrastructure for developing OS kernels and Embedded |
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| 8 | * Applications; it partially derives from the HARTIK project but it |
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| 9 | * currently is independently developed. |
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| 10 | * |
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| 11 | * OSLib is distributed under GPL License, and some of its code has |
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| 12 | * been derived from the Linux kernel source; also some important |
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| 13 | * ideas come from studying the DJGPP go32 extender. |
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| 14 | * |
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| 15 | * We acknowledge the Linux Community, Free Software Foundation, |
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| 16 | * D.J. Delorie and all the other developers who believe in the |
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| 17 | * freedom of software and ideas. |
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| 18 | * |
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| 19 | * For legalese, check out the included GPL license. |
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| 20 | */ |
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| 21 | |||
| 22 | /* PIC management code & data */ |
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| 23 | |||
| 24 | #include <ll/i386/hw-instr.h> |
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| 25 | |||
| 26 | FILE(IRQ); |
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| 27 | |||
| 28 | #define ICW1_M 0x020 /* Master PIC (8259) register settings */ |
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| 29 | #define ICW2_M 0x021 |
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| 30 | #define ICW3_M 0x021 |
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| 31 | #define ICW4_M 0x021 |
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| 32 | #define OCW1_M 0x021 |
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| 33 | #define OCW2_M 0x020 |
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| 34 | #define OCW3_M 0x020 |
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| 35 | |||
| 36 | #define ICW1_S 0x0A0 /* Slave PIC register setting */ |
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| 37 | #define ICW2_S 0x0A1 |
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| 38 | #define ICW3_S 0x0A1 |
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| 39 | #define ICW4_S 0x0A1 |
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| 40 | #define OCW1_S 0x0A1 |
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| 41 | #define OCW2_S 0x0A0 |
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| 42 | #define OCW3_S 0x0A0 |
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| 43 | |||
| 44 | #define PIC1_BASE 0x040 /* Interrupt base for each PIC in HARTIK 3.0 */ |
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| 45 | #define PIC2_BASE 0x070 |
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| 46 | #define EOI 0x020 /* End Of Interrupt code for PIC! */ |
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| 47 | |||
| 48 | #define bit_on(v,b) ((v) |= (1 << (b))) |
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| 49 | #define bit_off(v,b) ((v) &= ~(1 << (b))) |
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| 50 | |||
| 51 | /* PIC interrupt mask */ |
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| 52 | BYTE ll_PIC_master_mask = 0xFE; |
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| 53 | BYTE ll_PIC_slave_mask = 0xFE; |
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| 54 | |||
| 55 | |||
| 56 | void PIC_init(void) |
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| 57 | { |
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| 58 | outp(ICW1_M, 0x11); |
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| 59 | outp(ICW2_M, PIC1_BASE); |
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| 60 | outp(ICW3_M, 0x04); |
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| 61 | outp(ICW4_M, 0x01); |
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| 62 | outp(OCW1_M, 0xFF); |
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| 63 | |||
| 64 | outp(ICW1_S, 0x11); |
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| 65 | outp(ICW2_S, PIC2_BASE); |
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| 66 | outp(ICW3_S, 0x02); |
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| 67 | outp(ICW4_S, 0x01); |
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| 68 | outp(OCW1_S, 0xFF); |
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| 69 | } |
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| 70 | |||
| 71 | void PIC_end(void) |
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| 72 | { |
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| 73 | outp(ICW1_M, 0x11); |
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| 74 | outp(ICW2_M, 0x08); |
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| 75 | outp(ICW3_M, 0x04); |
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| 76 | outp(ICW4_M, 0x01); |
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| 77 | outp(OCW1_M, 0xFF); |
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| 78 | |||
| 79 | outp(ICW1_S, 0x11); |
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| 80 | outp(ICW2_S, 0x70); |
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| 81 | outp(ICW3_S, 0x02); |
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| 82 | outp(ICW4_S, 0x01); |
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| 83 | outp(OCW1_S, 0xFF); |
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| 84 | } |
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| 85 | |||
| 86 | void irq_mask(WORD irqno) |
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| 87 | { |
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| 88 | /* Cannot mask timer interrupt! */ |
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| 89 | if (irqno == 0) |
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| 90 | return; |
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| 91 | /* Interrupt is on master PIC */ |
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| 92 | if (irqno < 8) { |
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| 93 | bit_on(ll_PIC_master_mask, irqno); |
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| 94 | outp(0x21, ll_PIC_master_mask); |
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| 95 | } else if (irqno < 16) { |
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| 96 | /* Interrupt on slave PIC */ |
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| 97 | bit_on(ll_PIC_slave_mask, irqno - 8); |
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| 98 | outp(0xA1, ll_PIC_slave_mask); |
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| 99 | /* If the slave PIC is completely off */ |
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| 100 | /* Then turn off cascading line (Irq #2) */ |
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| 101 | if (ll_PIC_slave_mask == 0xFF && !(ll_PIC_master_mask & 0x04)) { |
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| 102 | bit_on(ll_PIC_master_mask, 2); |
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| 103 | outp(0x21, ll_PIC_master_mask); |
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| 104 | } |
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| 105 | } |
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| 106 | } |
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| 107 | |||
| 108 | void irq_unmask(WORD irqno) |
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| 109 | { |
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| 110 | /* It is a nonsense to unmask the timer interrupt */ |
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| 111 | if (irqno == 0) |
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| 112 | return; |
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| 113 | /* Interrupt is on master PIC */ |
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| 114 | if (irqno < 8) { |
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| 115 | bit_off(ll_PIC_master_mask, irqno); |
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| 116 | outp(0x21, ll_PIC_master_mask); |
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| 117 | } else if (irqno < 16) { |
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| 118 | /* Interrupt on slave PIC */ |
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| 119 | bit_off(ll_PIC_slave_mask, irqno - 8); |
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| 120 | outp(0xA1, ll_PIC_slave_mask); |
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| 121 | /* If the cascading irq line was off */ |
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| 122 | /* Then activate it also! */ |
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| 123 | if (ll_PIC_master_mask & 0x04) { |
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| 124 | bit_off(ll_PIC_master_mask, 2); |
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| 125 | outp(0x21, ll_PIC_master_mask); |
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| 126 | } |
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| 127 | } |
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| 128 | } |