WebSVN - shark - Blame - Rev 582 - /shark/trunk/drivers/cpu/amd.c

Rev	Author	Line No.	Line
582	mauro	1	#include <linuxcomp.h>
		2
		3	#include <linux/init.h>
		4	#include <linux/bitops.h>
		5	#include <linux/mm.h>
		6	#include <asm/io.h>
		7	#include <asm/processor.h>
		8
		9	#include "cpu.h"
		10
		11	/*
		12	* B step AMD K6 before B 9730xxxx have hardware bugs that can cause
		13	* misexecution of code under Linux. Owners of such processors should
		14	* contact AMD for precise details and a CPU swap.
		15	*
		16	* See http://www.multimania.com/poulot/k6bug.html
		17	* http://www.amd.com/K6/k6docs/revgd.html
		18	*
		19	* The following test is erm.. interesting. AMD neglected to up
		20	* the chip setting when fixing the bug but they also tweaked some
		21	* performance at the same time..
		22	*/
		23
		24	extern void vide(void);
		25	__asm__(".align 4\nvide: ret");
		26
		27	static void __init init_amd(struct cpuinfo_x86 *c)
		28	{
		29	u32 l, h;
		30	int mbytes = 1; //!!!num_physpages >> (20-PAGE_SHIFT);
		31	int r;
		32
		33	/*
		34	* FIXME: We should handle the K5 here. Set up the write
		35	* range and also turn on MSR 83 bits 4 and 31 (write alloc,
		36	* no bus pipeline)
		37	*/
		38
		39	/* Bit 31 in normal CPUID used for nonstandard 3DNow ID;
		40	3DNow is IDd by bit 31 in extended CPUID (132+31) anyway /
		41	clear_bit(0*32+31, c->x86_capability);
		42
		43	r = get_model_name(c);
		44
		45	switch(c->x86)
		46	{
		47	case 4:
		48	/*
		49	* General Systems BIOSen alias the cpu frequency registers
		50	* of the Elan at 0x000df000. Unfortuantly, one of the Linux
		51	* drivers subsequently pokes it, and changes the CPU speed.
		52	* Workaround : Remove the unneeded alias.
		53	*/
		54	#define CBAR (0xfffc) /* Configuration Base Address (32-bit) */
		55	#define CBAR_ENB (0x80000000)
		56	#define CBAR_KEY (0X000000CB)
		57	if (c->x86_model==9 \|\| c->x86_model == 10) {
		58	if (inl (CBAR) & CBAR_ENB)
		59	outl (0 \| CBAR_KEY, CBAR);
		60	}
		61	break;
		62	case 5:
		63	if( c->x86_model < 6 )
		64	{
		65	/* Based on AMD doc 20734R - June 2000 */
		66	if ( c->x86_model == 0 ) {
		67	clear_bit(X86_FEATURE_APIC, c->x86_capability);
		68	set_bit(X86_FEATURE_PGE, c->x86_capability);
		69	}
		70	break;
		71	}
		72
		73	if ( c->x86_model == 6 && c->x86_mask == 1 ) {
		74	const int K6_BUG_LOOP = 1000000;
		75	int n;
		76	void (*f_vide)(void);
		77	unsigned long d, d2;
		78
		79	printk(KERN_INFO "AMD K6 stepping B detected - ");
		80
		81	/*
		82	* It looks like AMD fixed the 2.6.2 bug and improved indirect
		83	* calls at the same time.
		84	*/
		85
		86	n = K6_BUG_LOOP;
		87	f_vide = vide;
		88	rdtscl(d);
		89	while (n--)
		90	f_vide();
		91	rdtscl(d2);
		92	d = d2-d;
		93
		94	/* Knock these two lines out if it debugs out ok */
		95	printk(KERN_INFO "AMD K6 stepping B detected - ");
		96	/* -- cut here -- */
		97	if (d > 20*K6_BUG_LOOP)
		98	printk("system stability may be impaired when more than 32 MB are used.\n");
		99	else
		100	printk("probably OK (after B9730xxxx).\n");
		101	printk(KERN_INFO "Please see http://membres.lycos.fr/poulot/k6bug.html\n");
		102	}
		103
		104	/* K6 with old style WHCR */
		105	if (c->x86_model < 8 \|\|
		106	(c->x86_model== 8 && c->x86_mask < 8)) {
		107	/* We can only write allocate on the low 508Mb */
		108	if(mbytes>508)
		109	mbytes=508;
		110
		111	rdmsr(MSR_K6_WHCR, l, h);
		112	if ((l&0x0000FFFF)==0) {
		113	unsigned long flags;
		114	l=(1<<0)\|((mbytes/4)<<1);
		115	local_irq_save(flags);
		116	wbinvd();
		117	wrmsr(MSR_K6_WHCR, l, h);
		118	local_irq_restore(flags);
		119	printk(KERN_INFO "Enabling old style K6 write allocation for %d Mb\n",
		120	mbytes);
		121	}
		122	break;
		123	}
		124
		125	if ((c->x86_model == 8 && c->x86_mask >7) \|\|
		126	c->x86_model == 9 \|\| c->x86_model == 13) {
		127	/* The more serious chips .. */
		128
		129	if(mbytes>4092)
		130	mbytes=4092;
		131
		132	rdmsr(MSR_K6_WHCR, l, h);
		133	if ((l&0xFFFF0000)==0) {
		134	unsigned long flags;
		135	l=((mbytes>>2)<<22)\|(1<<16);
		136	local_irq_save(flags);
		137	wbinvd();
		138	wrmsr(MSR_K6_WHCR, l, h);
		139	local_irq_restore(flags);
		140	printk(KERN_INFO "Enabling new style K6 write allocation for %d Mb\n",
		141	mbytes);
		142	}
		143
		144	/* Set MTRR capability flag if appropriate */
		145	if (c->x86_model == 13 \|\| c->x86_model == 9 \|\|
		146	(c->x86_model == 8 && c->x86_mask >= 8))
		147	set_bit(X86_FEATURE_K6_MTRR, c->x86_capability);
		148	break;
		149	}
		150	break;
		151
		152	case 6: /* An Athlon/Duron */
		153
		154	/* Bit 15 of Athlon specific MSR 15, needs to be 0
		155	* to enable SSE on Palomino/Morgan/Barton CPU's.
		156	* If the BIOS didn't enable it already, enable it here.
		157	*/
		158	if (c->x86_model >= 6 && c->x86_model <= 10) {
		159	if (!cpu_has(c, X86_FEATURE_XMM)) {
		160	printk(KERN_INFO "Enabling disabled K7/SSE Support.\n");
		161	rdmsr(MSR_K7_HWCR, l, h);
		162	l &= ~0x00008000;
		163	wrmsr(MSR_K7_HWCR, l, h);
		164	set_bit(X86_FEATURE_XMM, c->x86_capability);
		165	}
		166	}
		167
		168	/* It's been determined by AMD that Athlons since model 8 stepping 1
		169	* are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx
		170	* As per AMD technical note 27212 0.2
		171	*/
		172	if ((c->x86_model == 8 && c->x86_mask>=1) \|\| (c->x86_model > 8)) {
		173	rdmsr(MSR_K7_CLK_CTL, l, h);
		174	if ((l & 0xfff00000) != 0x20000000) {
		175	printk ("CPU: CLK_CTL MSR was %x. Reprogramming to %x\n", l,
		176	((l & 0x000fffff)\|0x20000000));
		177	wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)\|0x20000000, h);
		178	}
		179	}
		180	break;
		181	}
		182
		183	switch (c->x86) {
		184	case 15:
		185	set_bit(X86_FEATURE_K8, c->x86_capability);
		186	break;
		187	case 6:
		188	set_bit(X86_FEATURE_K7, c->x86_capability);
		189	break;
		190	}
		191
		192	display_cacheinfo(c);
		193	}
		194
		195	static unsigned int amd_size_cache(struct cpuinfo_x86 * c, unsigned int size)
		196	{
		197	/* AMD errata T13 (order #21922) */
		198	if ((c->x86 == 6)) {
		199	if (c->x86_model == 3 && c->x86_mask == 0) /* Duron Rev A0 */
		200	size = 64;
		201	if (c->x86_model == 4 &&
		202	(c->x86_mask==0 \|\| c->x86_mask==1)) /* Tbird rev A1/A2 */
		203	size = 256;
		204	}
		205	return size;
		206	}
		207
		208	static struct cpu_dev amd_cpu_dev __initdata = {
		209	.c_vendor = "AMD",
		210	.c_ident = { "AuthenticAMD" },
		211	.c_models = {
		212	{ .vendor = X86_VENDOR_AMD, .family = 4, .model_names =
		213	{
		214	[3] = "486 DX/2",
		215	[7] = "486 DX/2-WB",
		216	[8] = "486 DX/4",
		217	[9] = "486 DX/4-WB",
		218	[14] = "Am5x86-WT",
		219	[15] = "Am5x86-WB"
		220	}
		221	},
		222	},
		223	.c_init = init_amd,
		224	.c_identify = generic_identify,
		225	.c_size_cache = amd_size_cache,
		226	};
		227
		228	int __init amd_init_cpu(void)
		229	{
		230	cpu_devs[X86_VENDOR_AMD] = &amd_cpu_dev;
		231	return 0;
		232	}
		233
		234	//early_arch_initcall(amd_init_cpu);

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(root)/shark/trunk/drivers/cpu/amd.c @ 597 - Rev 582