Rev 582 | Details | Compare with Previous | Last modification | View Log | RSS feed
| Rev | Author | Line No. | Line |
|---|---|---|---|
| 582 | mauro | 1 | /* |
| 2 | * Pentium 4/Xeon CPU on demand clock modulation/speed scaling |
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| 3 | * (C) 2002 - 2003 Dominik Brodowski <linux@brodo.de> |
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| 4 | * (C) 2002 Zwane Mwaikambo <zwane@commfireservices.com> |
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| 5 | * (C) 2002 Arjan van de Ven <arjanv@redhat.com> |
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| 6 | * (C) 2002 Tora T. Engstad |
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| 7 | * All Rights Reserved |
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| 8 | * |
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| 9 | * This program is free software; you can redistribute it and/or |
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| 10 | * modify it under the terms of the GNU General Public License |
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| 11 | * as published by the Free Software Foundation; either version |
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| 12 | * 2 of the License, or (at your option) any later version. |
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| 13 | * |
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| 14 | * The author(s) of this software shall not be held liable for damages |
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| 15 | * of any nature resulting due to the use of this software. This |
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| 16 | * software is provided AS-IS with no warranties. |
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| 17 | * |
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| 18 | * Date Errata Description |
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| 19 | * 20020525 N44, O17 12.5% or 25% DC causes lockup |
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| 20 | * |
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| 21 | */ |
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| 22 | |||
| 23 | #include <linuxcomp.h> |
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| 24 | |||
| 25 | #include <linux/config.h> |
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| 26 | #include <linux/kernel.h> |
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| 27 | #include <linux/module.h> |
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| 28 | #include <linux/init.h> |
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| 29 | #include <linux/smp.h> |
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| 30 | #include <linux/cpufreq.h> |
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| 31 | #include <linux/slab.h> |
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| 32 | #include <linux/sched.h> |
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| 33 | |||
| 34 | #include <asm/processor.h> |
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| 35 | #include <asm/msr.h> |
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| 36 | #include <asm/timex.h> |
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| 37 | |||
| 38 | #define PFX "cpufreq: " |
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| 39 | |||
| 40 | /* |
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| 41 | * Duty Cycle (3bits), note DC_DISABLE is not specified in |
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| 42 | * intel docs i just use it to mean disable |
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| 43 | */ |
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| 44 | enum { |
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| 45 | DC_RESV, DC_DFLT, DC_25PT, DC_38PT, DC_50PT, |
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| 46 | DC_64PT, DC_75PT, DC_88PT, DC_DISABLE |
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| 47 | }; |
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| 48 | |||
| 49 | #define DC_ENTRIES 8 |
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| 50 | |||
| 51 | |||
| 52 | static int has_N44_O17_errata[NR_CPUS]; |
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| 53 | static int stock_freq; |
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| 54 | |||
| 55 | |||
| 56 | static int cpufreq_p4_setdc(unsigned int cpu, unsigned int newstate) |
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| 57 | { |
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| 58 | u32 l, h; |
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| 59 | cpumask_t cpus_allowed, affected_cpu_map; |
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| 60 | struct cpufreq_freqs freqs; |
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| 61 | int hyperthreading = 0; |
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| 62 | int sibling = 0; |
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| 63 | |||
| 64 | if (!cpu_online(cpu) || (newstate > DC_DISABLE) || |
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| 65 | (newstate == DC_RESV)) |
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| 66 | return -EINVAL; |
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| 67 | |||
| 68 | /* switch to physical CPU where state is to be changed*/ |
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| 69 | cpus_allowed = current->cpus_allowed; |
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| 70 | |||
| 71 | /* only run on CPU to be set, or on its sibling */ |
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| 72 | affected_cpu_map = cpumask_of_cpu(cpu); |
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| 73 | #ifdef CONFIG_X86_HT |
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| 74 | hyperthreading = ((cpu_has_ht) && (smp_num_siblings == 2)); |
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| 75 | if (hyperthreading) { |
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| 76 | sibling = cpu_sibling_map[cpu]; |
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| 77 | cpu_set(sibling, affected_cpu_map); |
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| 78 | } |
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| 79 | #endif |
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| 80 | set_cpus_allowed(current, affected_cpu_map); |
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| 81 | BUG_ON(!cpu_isset(smp_processor_id(), affected_cpu_map)); |
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| 82 | |||
| 83 | /* get current state */ |
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| 84 | rdmsr(MSR_IA32_THERM_CONTROL, l, h); |
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| 85 | if (l & 0x10) { |
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| 86 | l = l >> 1; |
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| 87 | l &= 0x7; |
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| 88 | } else |
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| 89 | l = DC_DISABLE; |
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| 90 | |||
| 91 | if (l == newstate) { |
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| 92 | set_cpus_allowed(current, cpus_allowed); |
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| 93 | return 0; |
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| 94 | } else if (l == DC_RESV) { |
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| 95 | printk(KERN_ERR PFX "BIG FAT WARNING: currently in invalid setting\n"); |
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| 96 | } |
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| 97 | |||
| 98 | /* notifiers */ |
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| 99 | freqs.old = stock_freq * l / 8; |
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| 100 | freqs.new = stock_freq * newstate / 8; |
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| 101 | freqs.cpu = cpu; |
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| 600 | mauro | 102 | cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); |
| 582 | mauro | 103 | if (hyperthreading) { |
| 104 | freqs.cpu = sibling; |
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| 600 | mauro | 105 | cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); |
| 582 | mauro | 106 | } |
| 107 | |||
| 108 | rdmsr(MSR_IA32_THERM_STATUS, l, h); |
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| 109 | #if 0 |
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| 110 | if (l & 0x01) |
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| 111 | printk(KERN_DEBUG PFX "CPU#%d currently thermal throttled\n", cpu); |
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| 112 | #endif |
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| 113 | if (has_N44_O17_errata[cpu] && (newstate == DC_25PT || newstate == DC_DFLT)) |
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| 114 | newstate = DC_38PT; |
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| 115 | |||
| 116 | rdmsr(MSR_IA32_THERM_CONTROL, l, h); |
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| 117 | if (newstate == DC_DISABLE) { |
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| 118 | /* printk(KERN_INFO PFX "CPU#%d disabling modulation\n", cpu); */ |
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| 119 | wrmsr(MSR_IA32_THERM_CONTROL, l & ~(1<<4), h); |
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| 120 | } else { |
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| 121 | /* printk(KERN_INFO PFX "CPU#%d setting duty cycle to %d%%\n", |
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| 122 | cpu, ((125 * newstate) / 10)); */ |
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| 123 | /* bits 63 - 5 : reserved |
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| 124 | * bit 4 : enable/disable |
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| 125 | * bits 3-1 : duty cycle |
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| 126 | * bit 0 : reserved |
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| 127 | */ |
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| 128 | l = (l & ~14); |
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| 129 | l = l | (1<<4) | ((newstate & 0x7)<<1); |
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| 130 | wrmsr(MSR_IA32_THERM_CONTROL, l, h); |
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| 131 | } |
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| 132 | |||
| 133 | set_cpus_allowed(current, cpus_allowed); |
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| 134 | |||
| 135 | /* notifiers */ |
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| 600 | mauro | 136 | cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); |
| 582 | mauro | 137 | if (hyperthreading) { |
| 138 | freqs.cpu = cpu; |
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| 600 | mauro | 139 | cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); |
| 582 | mauro | 140 | } |
| 141 | |||
| 142 | return 0; |
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| 143 | } |
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| 144 | |||
| 145 | |||
| 146 | static struct cpufreq_frequency_table p4clockmod_table[] = { |
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| 147 | {DC_RESV, CPUFREQ_ENTRY_INVALID}, |
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| 148 | {DC_DFLT, 0}, |
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| 149 | {DC_25PT, 0}, |
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| 150 | {DC_38PT, 0}, |
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| 151 | {DC_50PT, 0}, |
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| 152 | {DC_64PT, 0}, |
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| 153 | {DC_75PT, 0}, |
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| 154 | {DC_88PT, 0}, |
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| 155 | {DC_DISABLE, 0}, |
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| 156 | {DC_RESV, CPUFREQ_TABLE_END}, |
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| 157 | }; |
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| 158 | |||
| 159 | |||
| 160 | static int cpufreq_p4_target(struct cpufreq_policy *policy, |
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| 161 | unsigned int target_freq, |
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| 162 | unsigned int relation) |
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| 163 | { |
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| 164 | unsigned int newstate = DC_RESV; |
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| 165 | |||
| 166 | if (cpufreq_frequency_table_target(policy, &p4clockmod_table[0], target_freq, relation, &newstate)) |
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| 167 | return -EINVAL; |
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| 168 | |||
| 169 | cpufreq_p4_setdc(policy->cpu, p4clockmod_table[newstate].index); |
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| 170 | |||
| 171 | return 0; |
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| 172 | } |
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| 173 | |||
| 174 | |||
| 175 | static int cpufreq_p4_verify(struct cpufreq_policy *policy) |
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| 176 | { |
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| 177 | return cpufreq_frequency_table_verify(policy, &p4clockmod_table[0]); |
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| 178 | } |
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| 179 | |||
| 180 | |||
| 181 | static int cpufreq_p4_cpu_init(struct cpufreq_policy *policy) |
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| 182 | { |
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| 183 | struct cpuinfo_x86 *c = &cpu_data[policy->cpu]; |
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| 184 | int cpuid = 0; |
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| 185 | unsigned int i; |
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| 186 | |||
| 187 | /* Errata workaround */ |
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| 188 | cpuid = (c->x86 << 8) | (c->x86_model << 4) | c->x86_mask; |
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| 189 | switch (cpuid) { |
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| 190 | case 0x0f07: |
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| 191 | case 0x0f0a: |
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| 192 | case 0x0f11: |
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| 193 | case 0x0f12: |
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| 194 | has_N44_O17_errata[policy->cpu] = 1; |
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| 195 | } |
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| 196 | |||
| 197 | /* get frequency */ |
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| 198 | if (!stock_freq) { |
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| 199 | if (cpu_khz) |
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| 200 | stock_freq = cpu_khz; |
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| 201 | else { |
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| 202 | printk(KERN_INFO PFX "unknown core frequency - please use module parameter 'stock_freq'\n"); |
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| 203 | return -EINVAL; |
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| 204 | } |
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| 205 | } |
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| 206 | |||
| 207 | /* table init */ |
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| 208 | for (i=1; (p4clockmod_table[i].frequency != CPUFREQ_TABLE_END); i++) { |
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| 209 | if ((i<2) && (has_N44_O17_errata[policy->cpu])) |
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| 210 | p4clockmod_table[i].frequency = CPUFREQ_ENTRY_INVALID; |
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| 211 | else |
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| 212 | p4clockmod_table[i].frequency = (stock_freq * i)/8; |
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| 213 | } |
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| 214 | cpufreq_frequency_table_get_attr(p4clockmod_table, policy->cpu); |
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| 215 | |||
| 216 | /* cpuinfo and default policy values */ |
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| 217 | policy->governor = 0; //!!!CPUFREQ_DEFAULT_GOVERNOR; |
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| 218 | policy->cpuinfo.transition_latency = 1000; |
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| 219 | policy->cur = stock_freq; |
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| 220 | |||
| 221 | return cpufreq_frequency_table_cpuinfo(policy, &p4clockmod_table[0]); |
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| 222 | } |
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| 223 | |||
| 224 | |||
| 225 | static int cpufreq_p4_cpu_exit(struct cpufreq_policy *policy) |
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| 226 | { |
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| 227 | cpufreq_frequency_table_put_attr(policy->cpu); |
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| 228 | return cpufreq_p4_setdc(policy->cpu, DC_DISABLE); |
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| 229 | } |
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| 230 | |||
| 231 | static struct freq_attr* p4clockmod_attr[] = { |
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| 232 | &cpufreq_freq_attr_scaling_available_freqs, |
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| 233 | NULL, |
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| 234 | }; |
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| 235 | |||
| 236 | static struct cpufreq_driver p4clockmod_driver = { |
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| 237 | .verify = cpufreq_p4_verify, |
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| 238 | .target = cpufreq_p4_target, |
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| 239 | .init = cpufreq_p4_cpu_init, |
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| 240 | .exit = cpufreq_p4_cpu_exit, |
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| 241 | .name = "p4-clockmod", |
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| 242 | .owner = THIS_MODULE, |
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| 243 | .attr = p4clockmod_attr, |
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| 244 | }; |
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| 245 | |||
| 246 | |||
| 247 | /*static*/ int __init cpufreq_p4_init(void) |
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| 248 | { |
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| 249 | struct cpuinfo_x86 *c = cpu_data; |
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| 250 | |||
| 251 | /* |
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| 252 | * THERM_CONTROL is architectural for IA32 now, so |
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| 253 | * we can rely on the capability checks |
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| 254 | */ |
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| 255 | if (c->x86_vendor != X86_VENDOR_INTEL) |
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| 256 | return -ENODEV; |
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| 257 | |||
| 258 | if (!test_bit(X86_FEATURE_ACPI, c->x86_capability) || |
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| 259 | !test_bit(X86_FEATURE_ACC, c->x86_capability)) |
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| 260 | return -ENODEV; |
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| 261 | |||
| 262 | printk(KERN_INFO PFX "P4/Xeon(TM) CPU On-Demand Clock Modulation available\n"); |
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| 263 | |||
| 264 | return cpufreq_register_driver(&p4clockmod_driver); |
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| 265 | } |
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| 266 | |||
| 267 | |||
| 268 | /*static*/ void __exit cpufreq_p4_exit(void) |
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| 269 | { |
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| 270 | cpufreq_unregister_driver(&p4clockmod_driver); |
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| 271 | } |
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| 272 | |||
| 273 | |||
| 274 | MODULE_PARM(stock_freq, "i"); |
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| 275 | |||
| 276 | MODULE_AUTHOR ("Zwane Mwaikambo <zwane@commfireservices.com>"); |
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| 277 | MODULE_DESCRIPTION ("cpufreq driver for Pentium(TM) 4/Xeon(TM)"); |
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| 278 | MODULE_LICENSE ("GPL"); |
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| 279 | |||
| 280 | module_init(cpufreq_p4_init); |
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| 281 | module_exit(cpufreq_p4_exit); |
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| 282 |