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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 489 | giacomo | 1 | /* |
| 2 | * |
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| 3 | * Hardware accelerated Matrox Millennium I, II, Mystique, G100, G200, G400 and G450 |
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| 4 | * |
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| 5 | * (c) 1998-2002 Petr Vandrovec <vandrove@vc.cvut.cz> |
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| 6 | * |
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| 7 | */ |
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| 8 | #ifndef __MATROXFB_H__ |
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| 9 | #define __MATROXFB_H__ |
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| 10 | |||
| 11 | /* general, but fairly heavy, debugging */ |
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| 12 | #undef MATROXFB_DEBUG |
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| 13 | |||
| 14 | /* heavy debugging: */ |
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| 15 | /* -- logs putc[s], so everytime a char is displayed, it's logged */ |
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| 16 | #undef MATROXFB_DEBUG_HEAVY |
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| 17 | |||
| 18 | /* This one _could_ cause infinite loops */ |
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| 19 | /* It _does_ cause lots and lots of messages during idle loops */ |
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| 20 | #undef MATROXFB_DEBUG_LOOP |
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| 21 | |||
| 22 | /* Debug register calls, too? */ |
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| 23 | #undef MATROXFB_DEBUG_REG |
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| 24 | |||
| 25 | /* Guard accelerator accesses with spin_lock_irqsave... */ |
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| 26 | #undef MATROXFB_USE_SPINLOCKS |
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| 27 | |||
| 28 | #include <linux/config.h> |
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| 29 | #include <linux/module.h> |
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| 30 | #include <linux/kernel.h> |
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| 31 | #include <linux/errno.h> |
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| 32 | #include <linux/string.h> |
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| 33 | #include <linux/mm.h> |
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| 34 | #include <linux/tty.h> |
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| 35 | #include <linux/slab.h> |
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| 36 | #include <linux/delay.h> |
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| 37 | #include <linux/fb.h> |
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| 38 | #include <linux/selection.h> |
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| 39 | #include <linux/ioport.h> |
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| 40 | #include <linux/init.h> |
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| 41 | #include <linux/timer.h> |
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| 42 | #include <linux/pci.h> |
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| 43 | #include <linux/spinlock.h> |
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| 44 | #include <linux/kd.h> |
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| 45 | |||
| 46 | #include <asm/io.h> |
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| 47 | #include <asm/unaligned.h> |
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| 48 | #ifdef CONFIG_MTRR |
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| 49 | #include <asm/mtrr.h> |
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| 50 | #endif |
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| 51 | |||
| 52 | #if defined(CONFIG_PPC_PMAC) |
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| 53 | #include <asm/prom.h> |
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| 54 | #include <asm/pci-bridge.h> |
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| 55 | #include "../macmodes.h" |
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| 56 | #endif |
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| 57 | |||
| 58 | /* always compile support for 32MB... It cost almost nothing */ |
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| 59 | #define CONFIG_FB_MATROX_32MB |
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| 60 | |||
| 61 | #ifdef MATROXFB_DEBUG |
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| 62 | |||
| 63 | #define DEBUG |
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| 64 | #define DBG(x) printk(KERN_DEBUG "matroxfb: %s\n", (x)); |
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| 65 | |||
| 66 | #ifdef MATROXFB_DEBUG_HEAVY |
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| 67 | #define DBG_HEAVY(x) DBG(x) |
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| 68 | #else /* MATROXFB_DEBUG_HEAVY */ |
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| 69 | #define DBG_HEAVY(x) /* DBG_HEAVY */ |
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| 70 | #endif /* MATROXFB_DEBUG_HEAVY */ |
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| 71 | |||
| 72 | #ifdef MATROXFB_DEBUG_LOOP |
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| 73 | #define DBG_LOOP(x) DBG(x) |
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| 74 | #else /* MATROXFB_DEBUG_LOOP */ |
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| 75 | #define DBG_LOOP(x) /* DBG_LOOP */ |
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| 76 | #endif /* MATROXFB_DEBUG_LOOP */ |
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| 77 | |||
| 78 | #ifdef MATROXFB_DEBUG_REG |
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| 79 | #define DBG_REG(x) DBG(x) |
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| 80 | #else /* MATROXFB_DEBUG_REG */ |
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| 81 | #define DBG_REG(x) /* DBG_REG */ |
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| 82 | #endif /* MATROXFB_DEBUG_REG */ |
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| 83 | |||
| 84 | #else /* MATROXFB_DEBUG */ |
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| 85 | |||
| 86 | #define DBG(x) /* DBG */ |
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| 87 | #define DBG_HEAVY(x) /* DBG_HEAVY */ |
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| 88 | #define DBG_REG(x) /* DBG_REG */ |
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| 89 | #define DBG_LOOP(x) /* DBG_LOOP */ |
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| 90 | |||
| 91 | #endif /* MATROXFB_DEBUG */ |
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| 92 | |||
| 93 | #if !defined(__i386__) && !defined(__x86_64__) |
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| 94 | #ifndef ioremap_nocache |
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| 95 | #define ioremap_nocache(X,Y) ioremap(X,Y) |
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| 96 | #endif |
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| 97 | #endif |
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| 98 | |||
| 99 | #if defined(__alpha__) || defined(__mc68000__) |
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| 100 | #define READx_WORKS |
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| 101 | #define MEMCPYTOIO_WORKS |
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| 102 | #else |
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| 103 | #define READx_FAILS |
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| 104 | /* recheck __ppc__, maybe that __ppc__ needs MEMCPYTOIO_WRITEL */ |
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| 105 | /* I benchmarked PII/350MHz with G200... MEMCPY, MEMCPYTOIO and WRITEL are on same speed ( <2% diff) */ |
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| 106 | /* so that means that G200 speed (or AGP speed?) is our limit... I do not have benchmark to test, how */ |
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| 107 | /* much of PCI bandwidth is used during transfers... */ |
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| 108 | #if defined(__i386__) || defined(__x86_64__) |
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| 109 | #define MEMCPYTOIO_MEMCPY |
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| 110 | #else |
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| 111 | #define MEMCPYTOIO_WRITEL |
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| 112 | #endif |
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| 113 | #endif |
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| 114 | |||
| 115 | #if defined(__mc68000__) |
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| 116 | #define MAP_BUSTOVIRT |
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| 117 | #else |
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| 118 | #define MAP_IOREMAP |
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| 119 | #endif |
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| 120 | |||
| 121 | #ifdef DEBUG |
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| 122 | #define dprintk(X...) printk(X) |
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| 123 | #else |
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| 124 | #define dprintk(X...) |
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| 125 | #endif |
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| 126 | |||
| 127 | #ifndef PCI_SS_VENDOR_ID_SIEMENS_NIXDORF |
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| 128 | #define PCI_SS_VENDOR_ID_SIEMENS_NIXDORF 0x110A |
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| 129 | #endif |
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| 130 | #ifndef PCI_SS_VENDOR_ID_MATROX |
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| 131 | #define PCI_SS_VENDOR_ID_MATROX PCI_VENDOR_ID_MATROX |
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| 132 | #endif |
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| 133 | |||
| 134 | #ifndef PCI_SS_ID_MATROX_PRODUCTIVA_G100_AGP |
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| 135 | #define PCI_SS_ID_MATROX_GENERIC 0xFF00 |
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| 136 | #define PCI_SS_ID_MATROX_PRODUCTIVA_G100_AGP 0xFF01 |
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| 137 | #define PCI_SS_ID_MATROX_MYSTIQUE_G200_AGP 0xFF02 |
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| 138 | #define PCI_SS_ID_MATROX_MILLENIUM_G200_AGP 0xFF03 |
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| 139 | #define PCI_SS_ID_MATROX_MARVEL_G200_AGP 0xFF04 |
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| 140 | #define PCI_SS_ID_MATROX_MGA_G100_PCI 0xFF05 |
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| 141 | #define PCI_SS_ID_MATROX_MGA_G100_AGP 0x1001 |
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| 142 | #define PCI_SS_ID_MATROX_MILLENNIUM_G400_MAX_AGP 0x2179 |
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| 143 | #define PCI_SS_ID_SIEMENS_MGA_G100_AGP 0x001E /* 30 */ |
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| 144 | #define PCI_SS_ID_SIEMENS_MGA_G200_AGP 0x0032 /* 50 */ |
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| 145 | #endif |
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| 146 | |||
| 147 | #define MX_VISUAL_TRUECOLOR FB_VISUAL_DIRECTCOLOR |
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| 148 | #define MX_VISUAL_DIRECTCOLOR FB_VISUAL_TRUECOLOR |
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| 149 | #define MX_VISUAL_PSEUDOCOLOR FB_VISUAL_PSEUDOCOLOR |
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| 150 | |||
| 151 | #define CNVT_TOHW(val,width) ((((val)<<(width))+0x7FFF-(val))>>16) |
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| 152 | |||
| 153 | /* G-series and Mystique have (almost) same DAC */ |
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| 154 | #undef NEED_DAC1064 |
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| 155 | #if defined(CONFIG_FB_MATROX_MYSTIQUE) || defined(CONFIG_FB_MATROX_G100) |
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| 156 | #define NEED_DAC1064 1 |
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| 157 | #endif |
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| 158 | |||
| 159 | typedef struct { |
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| 160 | u_int8_t* vaddr; |
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| 161 | } vaddr_t; |
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| 162 | |||
| 163 | #ifdef READx_WORKS |
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| 164 | static inline unsigned int mga_readb(vaddr_t va, unsigned int offs) { |
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| 165 | return readb(va.vaddr + offs); |
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| 166 | } |
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| 167 | |||
| 168 | static inline unsigned int mga_readw(vaddr_t va, unsigned int offs) { |
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| 169 | return readw(va.vaddr + offs); |
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| 170 | } |
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| 171 | |||
| 172 | static inline u_int32_t mga_readl(vaddr_t va, unsigned int offs) { |
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| 173 | return readl(va.vaddr + offs); |
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| 174 | } |
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| 175 | |||
| 176 | static inline void mga_writeb(vaddr_t va, unsigned int offs, u_int8_t value) { |
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| 177 | writeb(value, va.vaddr + offs); |
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| 178 | } |
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| 179 | |||
| 180 | static inline void mga_writew(vaddr_t va, unsigned int offs, u_int16_t value) { |
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| 181 | writew(value, va.vaddr + offs); |
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| 182 | } |
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| 183 | |||
| 184 | static inline void mga_writel(vaddr_t va, unsigned int offs, u_int32_t value) { |
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| 185 | writel(value, va.vaddr + offs); |
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| 186 | } |
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| 187 | #else |
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| 188 | static inline unsigned int mga_readb(vaddr_t va, unsigned int offs) { |
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| 189 | return *(volatile u_int8_t*)(va.vaddr + offs); |
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| 190 | } |
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| 191 | |||
| 192 | static inline unsigned int mga_readw(vaddr_t va, unsigned int offs) { |
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| 193 | return *(volatile u_int16_t*)(va.vaddr + offs); |
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| 194 | } |
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| 195 | |||
| 196 | static inline u_int32_t mga_readl(vaddr_t va, unsigned int offs) { |
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| 197 | return *(volatile u_int32_t*)(va.vaddr + offs); |
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| 198 | } |
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| 199 | |||
| 200 | static inline void mga_writeb(vaddr_t va, unsigned int offs, u_int8_t value) { |
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| 201 | *(volatile u_int8_t*)(va.vaddr + offs) = value; |
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| 202 | } |
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| 203 | |||
| 204 | static inline void mga_writew(vaddr_t va, unsigned int offs, u_int16_t value) { |
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| 205 | *(volatile u_int16_t*)(va.vaddr + offs) = value; |
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| 206 | } |
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| 207 | |||
| 208 | static inline void mga_writel(vaddr_t va, unsigned int offs, u_int32_t value) { |
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| 209 | *(volatile u_int32_t*)(va.vaddr + offs) = value; |
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| 210 | } |
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| 211 | #endif |
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| 212 | |||
| 213 | static inline void mga_memcpy_toio(vaddr_t va, unsigned int offs, const void* src, int len) { |
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| 214 | #ifdef MEMCPYTOIO_WORKS |
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| 215 | memcpy_toio(va.vaddr + offs, src, len); |
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| 216 | #elif defined(MEMCPYTOIO_WRITEL) |
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| 217 | #define srcd ((const u_int32_t*)src) |
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| 218 | if (offs & 3) { |
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| 219 | while (len >= 4) { |
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| 220 | mga_writel(va, offs, get_unaligned(srcd++)); |
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| 221 | offs += 4; |
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| 222 | len -= 4; |
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| 223 | } |
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| 224 | } else { |
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| 225 | while (len >= 4) { |
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| 226 | mga_writel(va, offs, *srcd++); |
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| 227 | offs += 4; |
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| 228 | len -= 4; |
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| 229 | } |
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| 230 | } |
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| 231 | #undef srcd |
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| 232 | if (len) { |
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| 233 | u_int32_t tmp; |
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| 234 | |||
| 235 | memcpy(&tmp, src, len); |
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| 236 | mga_writel(va, offs, tmp); |
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| 237 | } |
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| 238 | #elif defined(MEMCPYTOIO_MEMCPY) |
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| 239 | memcpy(va.vaddr + offs, src, len); |
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| 240 | #else |
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| 241 | #error "Sorry, do not know how to write block of data to device" |
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| 242 | #endif |
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| 243 | } |
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| 244 | |||
| 245 | static inline void vaddr_add(vaddr_t* va, unsigned long offs) { |
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| 246 | va->vaddr += offs; |
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| 247 | } |
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| 248 | |||
| 249 | static inline void* vaddr_va(vaddr_t va) { |
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| 250 | return va.vaddr; |
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| 251 | } |
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| 252 | |||
| 253 | #define MGA_IOREMAP_NORMAL 0 |
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| 254 | #define MGA_IOREMAP_NOCACHE 1 |
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| 255 | |||
| 256 | #define MGA_IOREMAP_FB MGA_IOREMAP_NOCACHE |
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| 257 | #define MGA_IOREMAP_MMIO MGA_IOREMAP_NOCACHE |
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| 258 | static inline int mga_ioremap(unsigned long phys, unsigned long size, int flags, vaddr_t* virt) { |
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| 259 | #ifdef MAP_IOREMAP |
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| 260 | if (flags & MGA_IOREMAP_NOCACHE) |
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| 261 | virt->vaddr = ioremap(phys, size); |
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| 262 | else |
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| 263 | virt->vaddr = ioremap(phys, size); |
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| 264 | #else |
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| 265 | #ifdef MAP_BUSTOVIRT |
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| 266 | virt->vaddr = bus_to_virt(phys); |
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| 267 | #else |
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| 268 | #error "Your architecture does not have neither ioremap nor bus_to_virt... Giving up" |
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| 269 | #endif |
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| 270 | #endif |
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| 271 | return (virt->vaddr == 0); /* 0, !0... 0, error_code in future */ |
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| 272 | } |
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| 273 | |||
| 274 | static inline void mga_iounmap(vaddr_t va) { |
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| 275 | #ifdef MAP_IOREMAP |
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| 276 | iounmap(va.vaddr); |
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| 277 | #endif |
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| 278 | } |
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| 279 | |||
| 280 | struct my_timming { |
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| 281 | unsigned int pixclock; |
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| 282 | int mnp; |
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| 283 | unsigned int crtc; |
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| 284 | unsigned int HDisplay; |
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| 285 | unsigned int HSyncStart; |
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| 286 | unsigned int HSyncEnd; |
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| 287 | unsigned int HTotal; |
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| 288 | unsigned int VDisplay; |
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| 289 | unsigned int VSyncStart; |
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| 290 | unsigned int VSyncEnd; |
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| 291 | unsigned int VTotal; |
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| 292 | unsigned int sync; |
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| 293 | int dblscan; |
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| 294 | int interlaced; |
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| 295 | unsigned int delay; /* CRTC delay */ |
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| 296 | }; |
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| 297 | |||
| 298 | enum { M_SYSTEM_PLL, M_PIXEL_PLL_A, M_PIXEL_PLL_B, M_PIXEL_PLL_C, M_VIDEO_PLL }; |
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| 299 | |||
| 300 | struct matrox_pll_cache { |
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| 301 | unsigned int valid; |
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| 302 | struct { |
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| 303 | unsigned int mnp_key; |
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| 304 | unsigned int mnp_value; |
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| 305 | } data[4]; |
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| 306 | }; |
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| 307 | |||
| 308 | struct matrox_pll_limits { |
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| 309 | unsigned int vcomin; |
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| 310 | unsigned int vcomax; |
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| 311 | }; |
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| 312 | |||
| 313 | struct matrox_pll_features { |
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| 314 | unsigned int vco_freq_min; |
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| 315 | unsigned int ref_freq; |
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| 316 | unsigned int feed_div_min; |
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| 317 | unsigned int feed_div_max; |
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| 318 | unsigned int in_div_min; |
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| 319 | unsigned int in_div_max; |
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| 320 | unsigned int post_shift_max; |
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| 321 | }; |
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| 322 | |||
| 323 | struct matroxfb_par |
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| 324 | { |
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| 325 | unsigned int final_bppShift; |
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| 326 | unsigned int cmap_len; |
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| 327 | struct { |
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| 328 | unsigned int bytes; |
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| 329 | unsigned int pixels; |
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| 330 | unsigned int chunks; |
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| 331 | } ydstorg; |
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| 332 | }; |
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| 333 | |||
| 334 | struct matrox_fb_info; |
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| 335 | |||
| 336 | struct matrox_DAC1064_features { |
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| 337 | u_int8_t xvrefctrl; |
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| 338 | u_int8_t xmiscctrl; |
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| 339 | }; |
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| 340 | |||
| 341 | struct matrox_accel_features { |
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| 342 | int has_cacheflush; |
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| 343 | }; |
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| 344 | |||
| 345 | /* current hardware status */ |
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| 346 | struct mavenregs { |
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| 347 | u_int8_t regs[256]; |
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| 348 | int mode; |
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| 349 | int vlines; |
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| 350 | int xtal; |
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| 351 | int fv; |
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| 352 | |||
| 353 | u_int16_t htotal; |
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| 354 | u_int16_t hcorr; |
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| 355 | }; |
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| 356 | |||
| 357 | struct matrox_crtc2 { |
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| 358 | u_int32_t ctl; |
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| 359 | }; |
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| 360 | |||
| 361 | struct matrox_hw_state { |
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| 362 | u_int32_t MXoptionReg; |
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| 363 | unsigned char DACclk[6]; |
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| 364 | unsigned char DACreg[80]; |
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| 365 | unsigned char MiscOutReg; |
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| 366 | unsigned char DACpal[768]; |
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| 367 | unsigned char CRTC[25]; |
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| 368 | unsigned char CRTCEXT[9]; |
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| 369 | unsigned char SEQ[5]; |
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| 370 | /* unused for MGA mode, but who knows... */ |
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| 371 | unsigned char GCTL[9]; |
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| 372 | /* unused for MGA mode, but who knows... */ |
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| 373 | unsigned char ATTR[21]; |
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| 374 | |||
| 375 | /* TVOut only */ |
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| 376 | struct mavenregs maven; |
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| 377 | |||
| 378 | struct matrox_crtc2 crtc2; |
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| 379 | }; |
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| 380 | |||
| 381 | struct matrox_accel_data { |
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| 382 | #ifdef CONFIG_FB_MATROX_MILLENIUM |
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| 383 | unsigned char ramdac_rev; |
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| 384 | #endif |
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| 385 | u_int32_t m_dwg_rect; |
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| 386 | u_int32_t m_opmode; |
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| 387 | }; |
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| 388 | |||
| 389 | struct v4l2_queryctrl; |
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| 390 | struct v4l2_control; |
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| 391 | |||
| 392 | struct matrox_altout { |
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| 393 | const char *name; |
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| 394 | int (*compute)(void* altout_dev, struct my_timming* input); |
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| 395 | int (*program)(void* altout_dev); |
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| 396 | int (*start)(void* altout_dev); |
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| 397 | int (*verifymode)(void* altout_dev, u_int32_t mode); |
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| 398 | int (*getqueryctrl)(void* altout_dev, |
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| 399 | struct v4l2_queryctrl* ctrl); |
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| 400 | int (*getctrl)(void* altout_dev, |
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| 401 | struct v4l2_control* ctrl); |
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| 402 | int (*setctrl)(void* altout_dev, |
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| 403 | struct v4l2_control* ctrl); |
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| 404 | }; |
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| 405 | |||
| 406 | #define MATROXFB_SRC_NONE 0 |
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| 407 | #define MATROXFB_SRC_CRTC1 1 |
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| 408 | #define MATROXFB_SRC_CRTC2 2 |
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| 409 | |||
| 410 | enum mga_chip { MGA_2064, MGA_2164, MGA_1064, MGA_1164, MGA_G100, MGA_G200, MGA_G400, MGA_G450, MGA_G550 }; |
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| 411 | |||
| 412 | struct matrox_bios { |
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| 413 | unsigned int bios_valid : 1; |
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| 414 | unsigned int pins_len; |
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| 415 | unsigned char pins[128]; |
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| 416 | struct { |
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| 417 | unsigned char vMaj, vMin, vRev; |
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| 418 | } version; |
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| 419 | struct { |
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| 420 | unsigned char state, tvout; |
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| 421 | } output; |
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| 422 | }; |
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| 423 | |||
| 424 | extern struct display fb_display[]; |
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| 425 | |||
| 426 | struct matrox_switch; |
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| 427 | struct matroxfb_driver; |
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| 428 | struct matroxfb_dh_fb_info; |
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| 429 | |||
| 430 | struct matrox_vsync { |
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| 431 | wait_queue_head_t wait; |
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| 432 | unsigned int cnt; |
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| 433 | }; |
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| 434 | |||
| 435 | struct matrox_fb_info { |
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| 436 | struct fb_info fbcon; |
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| 437 | |||
| 438 | struct list_head next_fb; |
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| 439 | |||
| 440 | int dead; |
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| 441 | unsigned int usecount; |
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| 442 | |||
| 443 | unsigned int userusecount; |
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| 444 | unsigned long irq_flags; |
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| 445 | |||
| 446 | struct matroxfb_par curr; |
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| 447 | struct matrox_hw_state hw; |
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| 448 | |||
| 449 | struct matrox_accel_data accel; |
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| 450 | |||
| 451 | struct pci_dev* pcidev; |
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| 452 | |||
| 453 | struct { |
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| 454 | struct matrox_vsync vsync; |
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| 455 | unsigned int pixclock; |
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| 456 | int mnp; |
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| 457 | int panpos; |
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| 458 | } crtc1; |
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| 459 | struct { |
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| 460 | struct matrox_vsync vsync; |
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| 461 | unsigned int pixclock; |
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| 462 | int mnp; |
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| 463 | struct matroxfb_dh_fb_info* info; |
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| 464 | struct rw_semaphore lock; |
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| 465 | } crtc2; |
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| 466 | struct { |
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| 467 | struct rw_semaphore lock; |
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| 468 | struct { |
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| 469 | int brightness, contrast, saturation, hue, gamma; |
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| 470 | int testout, deflicker; |
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| 471 | } tvo_params; |
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| 472 | } altout; |
||
| 473 | #define MATROXFB_MAX_OUTPUTS 3 |
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| 474 | struct { |
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| 475 | unsigned int src; |
||
| 476 | struct matrox_altout* output; |
||
| 477 | void* data; |
||
| 478 | unsigned int mode; |
||
| 479 | } outputs[MATROXFB_MAX_OUTPUTS]; |
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| 480 | |||
| 481 | #define MATROXFB_MAX_FB_DRIVERS 5 |
||
| 482 | struct matroxfb_driver* (drivers[MATROXFB_MAX_FB_DRIVERS]); |
||
| 483 | void* (drivers_data[MATROXFB_MAX_FB_DRIVERS]); |
||
| 484 | unsigned int drivers_count; |
||
| 485 | |||
| 486 | struct { |
||
| 487 | unsigned long base; /* physical */ |
||
| 488 | vaddr_t vbase; /* CPU view */ |
||
| 489 | unsigned int len; |
||
| 490 | unsigned int len_usable; |
||
| 491 | unsigned int len_maximum; |
||
| 492 | } video; |
||
| 493 | |||
| 494 | struct { |
||
| 495 | unsigned long base; /* physical */ |
||
| 496 | vaddr_t vbase; /* CPU view */ |
||
| 497 | unsigned int len; |
||
| 498 | } mmio; |
||
| 499 | |||
| 500 | unsigned int max_pixel_clock; |
||
| 501 | |||
| 502 | struct matrox_switch* hw_switch; |
||
| 503 | |||
| 504 | struct { |
||
| 505 | struct matrox_pll_features pll; |
||
| 506 | struct matrox_DAC1064_features DAC1064; |
||
| 507 | struct matrox_accel_features accel; |
||
| 508 | } features; |
||
| 509 | struct { |
||
| 510 | spinlock_t DAC; |
||
| 511 | spinlock_t accel; |
||
| 512 | } lock; |
||
| 513 | |||
| 514 | enum mga_chip chip; |
||
| 515 | |||
| 516 | int interleave; |
||
| 517 | int millenium; |
||
| 518 | int milleniumII; |
||
| 519 | struct { |
||
| 520 | int cfb4; |
||
| 521 | const int* vxres; |
||
| 522 | int cross4MB; |
||
| 523 | int text; |
||
| 524 | int plnwt; |
||
| 525 | int srcorg; |
||
| 526 | } capable; |
||
| 527 | #ifdef CONFIG_MTRR |
||
| 528 | struct { |
||
| 529 | int vram; |
||
| 530 | int vram_valid; |
||
| 531 | } mtrr; |
||
| 532 | #endif |
||
| 533 | struct { |
||
| 534 | int precise_width; |
||
| 535 | int mga_24bpp_fix; |
||
| 536 | int novga; |
||
| 537 | int nobios; |
||
| 538 | int nopciretry; |
||
| 539 | int noinit; |
||
| 540 | int sgram; |
||
| 541 | #ifdef CONFIG_FB_MATROX_32MB |
||
| 542 | int support32MB; |
||
| 543 | #endif |
||
| 544 | |||
| 545 | int accelerator; |
||
| 546 | int text_type_aux; |
||
| 547 | int video64bits; |
||
| 548 | int crtc2; |
||
| 549 | int maven_capable; |
||
| 550 | unsigned int vgastep; |
||
| 551 | unsigned int textmode; |
||
| 552 | unsigned int textstep; |
||
| 553 | unsigned int textvram; /* character cells */ |
||
| 554 | unsigned int ydstorg; /* offset in bytes from video start to usable memory */ |
||
| 555 | /* 0 except for 6MB Millenium */ |
||
| 556 | int memtype; |
||
| 557 | int g450dac; |
||
| 558 | int dfp_type; |
||
| 559 | int panellink; /* G400 DFP possible (not G450/G550) */ |
||
| 560 | int dualhead; |
||
| 561 | unsigned int fbResource; |
||
| 562 | } devflags; |
||
| 563 | struct fb_ops fbops; |
||
| 564 | struct matrox_bios bios; |
||
| 565 | struct { |
||
| 566 | struct matrox_pll_limits pixel; |
||
| 567 | struct matrox_pll_limits system; |
||
| 568 | struct matrox_pll_limits video; |
||
| 569 | } limits; |
||
| 570 | struct { |
||
| 571 | struct matrox_pll_cache pixel; |
||
| 572 | struct matrox_pll_cache system; |
||
| 573 | struct matrox_pll_cache video; |
||
| 574 | } cache; |
||
| 575 | struct { |
||
| 576 | struct { |
||
| 577 | unsigned int video; |
||
| 578 | unsigned int system; |
||
| 579 | } pll; |
||
| 580 | struct { |
||
| 581 | u_int32_t opt; |
||
| 582 | u_int32_t opt2; |
||
| 583 | u_int32_t opt3; |
||
| 584 | u_int32_t mctlwtst; |
||
| 585 | u_int32_t mctlwtst_core; |
||
| 586 | u_int32_t memmisc; |
||
| 587 | u_int32_t memrdbk; |
||
| 588 | u_int32_t maccess; |
||
| 589 | } reg; |
||
| 590 | struct { |
||
| 591 | unsigned int ddr:1, |
||
| 592 | emrswen:1, |
||
| 593 | dll:1; |
||
| 594 | } memory; |
||
| 595 | } values; |
||
| 596 | u_int32_t cmap[17]; |
||
| 597 | }; |
||
| 598 | |||
| 599 | #define info2minfo(info) container_of(info, struct matrox_fb_info, fbcon) |
||
| 600 | |||
| 601 | #ifdef CONFIG_FB_MATROX_MULTIHEAD |
||
| 602 | #define ACCESS_FBINFO2(info, x) (info->x) |
||
| 603 | #define ACCESS_FBINFO(x) ACCESS_FBINFO2(minfo,x) |
||
| 604 | |||
| 605 | #define MINFO minfo |
||
| 606 | |||
| 607 | #define WPMINFO2 struct matrox_fb_info* minfo |
||
| 608 | #define WPMINFO WPMINFO2 , |
||
| 609 | #define CPMINFO2 const struct matrox_fb_info* minfo |
||
| 610 | #define CPMINFO CPMINFO2 , |
||
| 611 | #define PMINFO2 minfo |
||
| 612 | #define PMINFO PMINFO2 , |
||
| 613 | |||
| 614 | #define MINFO_FROM(x) struct matrox_fb_info* minfo = x |
||
| 615 | #else |
||
| 616 | |||
| 617 | extern struct matrox_fb_info matroxfb_global_mxinfo; |
||
| 618 | |||
| 619 | #define ACCESS_FBINFO(x) (matroxfb_global_mxinfo.x) |
||
| 620 | #define ACCESS_FBINFO2(info, x) (matroxfb_global_mxinfo.x) |
||
| 621 | |||
| 622 | #define MINFO (&matroxfb_global_mxinfo) |
||
| 623 | |||
| 624 | #define WPMINFO2 void |
||
| 625 | #define WPMINFO |
||
| 626 | #define CPMINFO2 void |
||
| 627 | #define CPMINFO |
||
| 628 | #define PMINFO2 |
||
| 629 | #define PMINFO |
||
| 630 | |||
| 631 | #define MINFO_FROM(x) |
||
| 632 | |||
| 633 | #endif |
||
| 634 | |||
| 635 | #define MINFO_FROM_INFO(x) MINFO_FROM(info2minfo(x)) |
||
| 636 | |||
| 637 | struct matrox_switch { |
||
| 638 | int (*preinit)(WPMINFO2); |
||
| 639 | void (*reset)(WPMINFO2); |
||
| 640 | int (*init)(WPMINFO struct my_timming*); |
||
| 641 | void (*restore)(WPMINFO2); |
||
| 642 | }; |
||
| 643 | |||
| 644 | struct matroxfb_driver { |
||
| 645 | struct list_head node; |
||
| 646 | char* name; |
||
| 647 | void* (*probe)(struct matrox_fb_info* info); |
||
| 648 | void (*remove)(struct matrox_fb_info* info, void* data); |
||
| 649 | }; |
||
| 650 | |||
| 651 | int matroxfb_register_driver(struct matroxfb_driver* drv); |
||
| 652 | void matroxfb_unregister_driver(struct matroxfb_driver* drv); |
||
| 653 | |||
| 654 | #define PCI_OPTION_REG 0x40 |
||
| 655 | #define PCI_OPTION_ENABLE_ROM 0x40000000 |
||
| 656 | |||
| 657 | #define PCI_MGA_INDEX 0x44 |
||
| 658 | #define PCI_MGA_DATA 0x48 |
||
| 659 | #define PCI_OPTION2_REG 0x50 |
||
| 660 | #define PCI_OPTION3_REG 0x54 |
||
| 661 | #define PCI_MEMMISC_REG 0x58 |
||
| 662 | |||
| 663 | #define M_DWGCTL 0x1C00 |
||
| 664 | #define M_MACCESS 0x1C04 |
||
| 665 | #define M_CTLWTST 0x1C08 |
||
| 666 | |||
| 667 | #define M_PLNWT 0x1C1C |
||
| 668 | |||
| 669 | #define M_BCOL 0x1C20 |
||
| 670 | #define M_FCOL 0x1C24 |
||
| 671 | |||
| 672 | #define M_SGN 0x1C58 |
||
| 673 | #define M_LEN 0x1C5C |
||
| 674 | #define M_AR0 0x1C60 |
||
| 675 | #define M_AR1 0x1C64 |
||
| 676 | #define M_AR2 0x1C68 |
||
| 677 | #define M_AR3 0x1C6C |
||
| 678 | #define M_AR4 0x1C70 |
||
| 679 | #define M_AR5 0x1C74 |
||
| 680 | #define M_AR6 0x1C78 |
||
| 681 | |||
| 682 | #define M_CXBNDRY 0x1C80 |
||
| 683 | #define M_FXBNDRY 0x1C84 |
||
| 684 | #define M_YDSTLEN 0x1C88 |
||
| 685 | #define M_PITCH 0x1C8C |
||
| 686 | #define M_YDST 0x1C90 |
||
| 687 | #define M_YDSTORG 0x1C94 |
||
| 688 | #define M_YTOP 0x1C98 |
||
| 689 | #define M_YBOT 0x1C9C |
||
| 690 | |||
| 691 | /* mystique only */ |
||
| 692 | #define M_CACHEFLUSH 0x1FFF |
||
| 693 | |||
| 694 | #define M_EXEC 0x0100 |
||
| 695 | |||
| 696 | #define M_DWG_TRAP 0x04 |
||
| 697 | #define M_DWG_BITBLT 0x08 |
||
| 698 | #define M_DWG_ILOAD 0x09 |
||
| 699 | |||
| 700 | #define M_DWG_LINEAR 0x0080 |
||
| 701 | #define M_DWG_SOLID 0x0800 |
||
| 702 | #define M_DWG_ARZERO 0x1000 |
||
| 703 | #define M_DWG_SGNZERO 0x2000 |
||
| 704 | #define M_DWG_SHIFTZERO 0x4000 |
||
| 705 | |||
| 706 | #define M_DWG_REPLACE 0x000C0000 |
||
| 707 | #define M_DWG_REPLACE2 (M_DWG_REPLACE | 0x40) |
||
| 708 | #define M_DWG_XOR 0x00060010 |
||
| 709 | |||
| 710 | #define M_DWG_BFCOL 0x04000000 |
||
| 711 | #define M_DWG_BMONOWF 0x08000000 |
||
| 712 | |||
| 713 | #define M_DWG_TRANSC 0x40000000 |
||
| 714 | |||
| 715 | #define M_FIFOSTATUS 0x1E10 |
||
| 716 | #define M_STATUS 0x1E14 |
||
| 717 | #define M_ICLEAR 0x1E18 |
||
| 718 | #define M_IEN 0x1E1C |
||
| 719 | |||
| 720 | #define M_VCOUNT 0x1E20 |
||
| 721 | |||
| 722 | #define M_RESET 0x1E40 |
||
| 723 | #define M_MEMRDBK 0x1E44 |
||
| 724 | |||
| 725 | #define M_AGP2PLL 0x1E4C |
||
| 726 | |||
| 727 | #define M_OPMODE 0x1E54 |
||
| 728 | #define M_OPMODE_DMA_GEN_WRITE 0x00 |
||
| 729 | #define M_OPMODE_DMA_BLIT 0x04 |
||
| 730 | #define M_OPMODE_DMA_VECTOR_WRITE 0x08 |
||
| 731 | #define M_OPMODE_DMA_LE 0x0000 /* little endian - no transformation */ |
||
| 732 | #define M_OPMODE_DMA_BE_8BPP 0x0000 |
||
| 733 | #define M_OPMODE_DMA_BE_16BPP 0x0100 |
||
| 734 | #define M_OPMODE_DMA_BE_32BPP 0x0200 |
||
| 735 | #define M_OPMODE_DIR_LE 0x000000 /* little endian - no transformation */ |
||
| 736 | #define M_OPMODE_DIR_BE_8BPP 0x000000 |
||
| 737 | #define M_OPMODE_DIR_BE_16BPP 0x010000 |
||
| 738 | #define M_OPMODE_DIR_BE_32BPP 0x020000 |
||
| 739 | |||
| 740 | #define M_ATTR_INDEX 0x1FC0 |
||
| 741 | #define M_ATTR_DATA 0x1FC1 |
||
| 742 | |||
| 743 | #define M_MISC_REG 0x1FC2 |
||
| 744 | #define M_3C2_RD 0x1FC2 |
||
| 745 | |||
| 746 | #define M_SEQ_INDEX 0x1FC4 |
||
| 747 | #define M_SEQ_DATA 0x1FC5 |
||
| 748 | |||
| 749 | #define M_MISC_REG_READ 0x1FCC |
||
| 750 | |||
| 751 | #define M_GRAPHICS_INDEX 0x1FCE |
||
| 752 | #define M_GRAPHICS_DATA 0x1FCF |
||
| 753 | |||
| 754 | #define M_CRTC_INDEX 0x1FD4 |
||
| 755 | |||
| 756 | #define M_ATTR_RESET 0x1FDA |
||
| 757 | #define M_3DA_WR 0x1FDA |
||
| 758 | #define M_INSTS1 0x1FDA |
||
| 759 | |||
| 760 | #define M_EXTVGA_INDEX 0x1FDE |
||
| 761 | #define M_EXTVGA_DATA 0x1FDF |
||
| 762 | |||
| 763 | /* G200 only */ |
||
| 764 | #define M_SRCORG 0x2CB4 |
||
| 765 | #define M_DSTORG 0x2CB8 |
||
| 766 | |||
| 767 | #define M_RAMDAC_BASE 0x3C00 |
||
| 768 | |||
| 769 | /* fortunately, same on TVP3026 and MGA1064 */ |
||
| 770 | #define M_DAC_REG (M_RAMDAC_BASE+0) |
||
| 771 | #define M_DAC_VAL (M_RAMDAC_BASE+1) |
||
| 772 | #define M_PALETTE_MASK (M_RAMDAC_BASE+2) |
||
| 773 | |||
| 774 | #define M_X_INDEX 0x00 |
||
| 775 | #define M_X_DATAREG 0x0A |
||
| 776 | |||
| 777 | #define DAC_XGENIOCTRL 0x2A |
||
| 778 | #define DAC_XGENIODATA 0x2B |
||
| 779 | |||
| 780 | #define M_C2CTL 0x3E10 |
||
| 781 | |||
| 782 | #ifdef __LITTLE_ENDIAN |
||
| 783 | #define MX_OPTION_BSWAP 0x00000000 |
||
| 784 | |||
| 785 | #define M_OPMODE_4BPP (M_OPMODE_DMA_LE | M_OPMODE_DIR_LE | M_OPMODE_DMA_BLIT) |
||
| 786 | #define M_OPMODE_8BPP (M_OPMODE_DMA_LE | M_OPMODE_DIR_LE | M_OPMODE_DMA_BLIT) |
||
| 787 | #define M_OPMODE_16BPP (M_OPMODE_DMA_LE | M_OPMODE_DIR_LE | M_OPMODE_DMA_BLIT) |
||
| 788 | #define M_OPMODE_24BPP (M_OPMODE_DMA_LE | M_OPMODE_DIR_LE | M_OPMODE_DMA_BLIT) |
||
| 789 | #define M_OPMODE_32BPP (M_OPMODE_DMA_LE | M_OPMODE_DIR_LE | M_OPMODE_DMA_BLIT) |
||
| 790 | #else |
||
| 791 | #ifdef __BIG_ENDIAN |
||
| 792 | #define MX_OPTION_BSWAP 0x80000000 |
||
| 793 | |||
| 794 | #define M_OPMODE_4BPP (M_OPMODE_DMA_LE | M_OPMODE_DIR_LE | M_OPMODE_DMA_BLIT) /* TODO */ |
||
| 795 | #define M_OPMODE_8BPP (M_OPMODE_DMA_BE_8BPP | M_OPMODE_DIR_BE_8BPP | M_OPMODE_DMA_BLIT) |
||
| 796 | #define M_OPMODE_16BPP (M_OPMODE_DMA_BE_16BPP | M_OPMODE_DIR_BE_16BPP | M_OPMODE_DMA_BLIT) |
||
| 797 | #define M_OPMODE_24BPP (M_OPMODE_DMA_BE_8BPP | M_OPMODE_DIR_BE_8BPP | M_OPMODE_DMA_BLIT) /* TODO, ?32 */ |
||
| 798 | #define M_OPMODE_32BPP (M_OPMODE_DMA_BE_32BPP | M_OPMODE_DIR_BE_32BPP | M_OPMODE_DMA_BLIT) |
||
| 799 | #else |
||
| 800 | #error "Byte ordering have to be defined. Cannot continue." |
||
| 801 | #endif |
||
| 802 | #endif |
||
| 803 | |||
| 804 | #define mga_inb(addr) mga_readb(ACCESS_FBINFO(mmio.vbase), (addr)) |
||
| 805 | #define mga_inl(addr) mga_readl(ACCESS_FBINFO(mmio.vbase), (addr)) |
||
| 806 | #define mga_outb(addr,val) mga_writeb(ACCESS_FBINFO(mmio.vbase), (addr), (val)) |
||
| 807 | #define mga_outw(addr,val) mga_writew(ACCESS_FBINFO(mmio.vbase), (addr), (val)) |
||
| 808 | #define mga_outl(addr,val) mga_writel(ACCESS_FBINFO(mmio.vbase), (addr), (val)) |
||
| 809 | #define mga_readr(port,idx) (mga_outb((port),(idx)), mga_inb((port)+1)) |
||
| 810 | #ifdef __LITTLE_ENDIAN |
||
| 811 | #define mga_setr(addr,port,val) mga_outw(addr, ((val)<<8) | (port)) |
||
| 812 | #else |
||
| 813 | #define mga_setr(addr,port,val) do { mga_outb(addr, port); mga_outb((addr)+1, val); } while (0) |
||
| 814 | #endif |
||
| 815 | |||
| 816 | #define mga_fifo(n) do {} while ((mga_inl(M_FIFOSTATUS) & 0xFF) < (n)) |
||
| 817 | |||
| 818 | #define WaitTillIdle() do {} while (mga_inl(M_STATUS) & 0x10000) |
||
| 819 | |||
| 820 | /* code speedup */ |
||
| 821 | #ifdef CONFIG_FB_MATROX_MILLENIUM |
||
| 822 | #define isInterleave(x) (x->interleave) |
||
| 823 | #define isMillenium(x) (x->millenium) |
||
| 824 | #define isMilleniumII(x) (x->milleniumII) |
||
| 825 | #else |
||
| 826 | #define isInterleave(x) (0) |
||
| 827 | #define isMillenium(x) (0) |
||
| 828 | #define isMilleniumII(x) (0) |
||
| 829 | #endif |
||
| 830 | |||
| 831 | #define matroxfb_DAC_lock() spin_lock(&ACCESS_FBINFO(lock.DAC)) |
||
| 832 | #define matroxfb_DAC_unlock() spin_unlock(&ACCESS_FBINFO(lock.DAC)) |
||
| 833 | #define matroxfb_DAC_lock_irqsave(flags) spin_lock_irqsave(&ACCESS_FBINFO(lock.DAC),flags) |
||
| 834 | #define matroxfb_DAC_unlock_irqrestore(flags) spin_unlock_irqrestore(&ACCESS_FBINFO(lock.DAC),flags) |
||
| 835 | extern void matroxfb_DAC_out(CPMINFO int reg, int val); |
||
| 836 | extern int matroxfb_DAC_in(CPMINFO int reg); |
||
| 837 | extern struct list_head matroxfb_list; |
||
| 838 | extern void matroxfb_var2my(struct fb_var_screeninfo* fvsi, struct my_timming* mt); |
||
| 839 | extern int matroxfb_wait_for_sync(WPMINFO u_int32_t crtc); |
||
| 840 | extern int matroxfb_enable_irq(WPMINFO int reenable); |
||
| 841 | |||
| 842 | #ifdef MATROXFB_USE_SPINLOCKS |
||
| 843 | #define CRITBEGIN spin_lock_irqsave(&ACCESS_FBINFO(lock.accel), critflags); |
||
| 844 | #define CRITEND spin_unlock_irqrestore(&ACCESS_FBINFO(lock.accel), critflags); |
||
| 845 | #define CRITFLAGS unsigned long critflags; |
||
| 846 | #else |
||
| 847 | #define CRITBEGIN |
||
| 848 | #define CRITEND |
||
| 849 | #define CRITFLAGS |
||
| 850 | #endif |
||
| 851 | |||
| 852 | #endif /* __MATROXFB_H__ */ |