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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 422 | giacomo | 1 | /* |
| 2 | * cpufeature.h |
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| 3 | * |
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| 4 | * Defines x86 CPU feature bits |
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| 5 | */ |
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| 6 | |||
| 7 | #ifndef __ASM_I386_CPUFEATURE_H |
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| 8 | #define __ASM_I386_CPUFEATURE_H |
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| 9 | |||
| 10 | #include <linux/bitops.h> |
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| 11 | |||
| 12 | #define NCAPINTS 6 /* Currently we have 6 32-bit words worth of info */ |
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| 13 | |||
| 14 | /* Intel-defined CPU features, CPUID level 0x00000001 (edx), word 0 */ |
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| 15 | #define X86_FEATURE_FPU (0*32+ 0) /* Onboard FPU */ |
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| 16 | #define X86_FEATURE_VME (0*32+ 1) /* Virtual Mode Extensions */ |
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| 17 | #define X86_FEATURE_DE (0*32+ 2) /* Debugging Extensions */ |
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| 18 | #define X86_FEATURE_PSE (0*32+ 3) /* Page Size Extensions */ |
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| 19 | #define X86_FEATURE_TSC (0*32+ 4) /* Time Stamp Counter */ |
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| 20 | #define X86_FEATURE_MSR (0*32+ 5) /* Model-Specific Registers, RDMSR, WRMSR */ |
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| 21 | #define X86_FEATURE_PAE (0*32+ 6) /* Physical Address Extensions */ |
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| 22 | #define X86_FEATURE_MCE (0*32+ 7) /* Machine Check Architecture */ |
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| 23 | #define X86_FEATURE_CX8 (0*32+ 8) /* CMPXCHG8 instruction */ |
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| 24 | #define X86_FEATURE_APIC (0*32+ 9) /* Onboard APIC */ |
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| 25 | #define X86_FEATURE_SEP (0*32+11) /* SYSENTER/SYSEXIT */ |
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| 26 | #define X86_FEATURE_MTRR (0*32+12) /* Memory Type Range Registers */ |
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| 27 | #define X86_FEATURE_PGE (0*32+13) /* Page Global Enable */ |
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| 28 | #define X86_FEATURE_MCA (0*32+14) /* Machine Check Architecture */ |
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| 29 | #define X86_FEATURE_CMOV (0*32+15) /* CMOV instruction (FCMOVCC and FCOMI too if FPU present) */ |
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| 30 | #define X86_FEATURE_PAT (0*32+16) /* Page Attribute Table */ |
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| 31 | #define X86_FEATURE_PSE36 (0*32+17) /* 36-bit PSEs */ |
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| 32 | #define X86_FEATURE_PN (0*32+18) /* Processor serial number */ |
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| 33 | #define X86_FEATURE_CLFLSH (0*32+19) /* Supports the CLFLUSH instruction */ |
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| 34 | #define X86_FEATURE_DTES (0*32+21) /* Debug Trace Store */ |
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| 35 | #define X86_FEATURE_ACPI (0*32+22) /* ACPI via MSR */ |
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| 36 | #define X86_FEATURE_MMX (0*32+23) /* Multimedia Extensions */ |
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| 37 | #define X86_FEATURE_FXSR (0*32+24) /* FXSAVE and FXRSTOR instructions (fast save and restore */ |
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| 38 | /* of FPU context), and CR4.OSFXSR available */ |
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| 39 | #define X86_FEATURE_XMM (0*32+25) /* Streaming SIMD Extensions */ |
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| 40 | #define X86_FEATURE_XMM2 (0*32+26) /* Streaming SIMD Extensions-2 */ |
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| 41 | #define X86_FEATURE_SELFSNOOP (0*32+27) /* CPU self snoop */ |
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| 42 | #define X86_FEATURE_HT (0*32+28) /* Hyper-Threading */ |
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| 43 | #define X86_FEATURE_ACC (0*32+29) /* Automatic clock control */ |
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| 44 | #define X86_FEATURE_IA64 (0*32+30) /* IA-64 processor */ |
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| 45 | |||
| 46 | /* AMD-defined CPU features, CPUID level 0x80000001, word 1 */ |
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| 47 | /* Don't duplicate feature flags which are redundant with Intel! */ |
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| 48 | #define X86_FEATURE_SYSCALL (1*32+11) /* SYSCALL/SYSRET */ |
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| 49 | #define X86_FEATURE_MP (1*32+19) /* MP Capable. */ |
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| 50 | #define X86_FEATURE_MMXEXT (1*32+22) /* AMD MMX extensions */ |
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| 51 | #define X86_FEATURE_LM (1*32+29) /* Long Mode (x86-64) */ |
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| 52 | #define X86_FEATURE_3DNOWEXT (1*32+30) /* AMD 3DNow! extensions */ |
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| 53 | #define X86_FEATURE_3DNOW (1*32+31) /* 3DNow! */ |
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| 54 | |||
| 55 | /* Transmeta-defined CPU features, CPUID level 0x80860001, word 2 */ |
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| 56 | #define X86_FEATURE_RECOVERY (2*32+ 0) /* CPU in recovery mode */ |
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| 57 | #define X86_FEATURE_LONGRUN (2*32+ 1) /* Longrun power control */ |
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| 58 | #define X86_FEATURE_LRTI (2*32+ 3) /* LongRun table interface */ |
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| 59 | |||
| 60 | /* Other features, Linux-defined mapping, word 3 */ |
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| 61 | /* This range is used for feature bits which conflict or are synthesized */ |
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| 62 | #define X86_FEATURE_CXMMX (3*32+ 0) /* Cyrix MMX extensions */ |
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| 63 | #define X86_FEATURE_K6_MTRR (3*32+ 1) /* AMD K6 nonstandard MTRRs */ |
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| 64 | #define X86_FEATURE_CYRIX_ARR (3*32+ 2) /* Cyrix ARRs (= MTRRs) */ |
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| 65 | #define X86_FEATURE_CENTAUR_MCR (3*32+ 3) /* Centaur MCRs (= MTRRs) */ |
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| 66 | /* cpu types for specific tunings: */ |
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| 67 | #define X86_FEATURE_K8 (3*32+ 4) /* Opteron, Athlon64 */ |
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| 68 | #define X86_FEATURE_K7 (3*32+ 5) /* Athlon */ |
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| 69 | #define X86_FEATURE_P3 (3*32+ 6) /* P3 */ |
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| 70 | #define X86_FEATURE_P4 (3*32+ 7) /* P4 */ |
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| 71 | |||
| 72 | /* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */ |
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| 73 | #define X86_FEATURE_EST (4*32+ 7) /* Enhanced SpeedStep */ |
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| 74 | #define X86_FEATURE_MWAIT (4*32+ 3) /* Monitor/Mwait support */ |
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| 75 | |||
| 76 | |||
| 77 | /* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */ |
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| 78 | #define X86_FEATURE_XSTORE (5*32+ 2) /* on-CPU RNG present (xstore insn) */ |
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| 79 | |||
| 80 | |||
| 81 | #define cpu_has(c, bit) test_bit(bit, (c)->x86_capability) |
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| 82 | #define boot_cpu_has(bit) test_bit(bit, boot_cpu_data.x86_capability) |
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| 83 | |||
| 84 | #define cpu_has_fpu boot_cpu_has(X86_FEATURE_FPU) |
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| 85 | #define cpu_has_vme boot_cpu_has(X86_FEATURE_VME) |
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| 86 | #define cpu_has_de boot_cpu_has(X86_FEATURE_DE) |
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| 87 | #define cpu_has_pse boot_cpu_has(X86_FEATURE_PSE) |
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| 88 | #define cpu_has_tsc boot_cpu_has(X86_FEATURE_TSC) |
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| 89 | #define cpu_has_pae boot_cpu_has(X86_FEATURE_PAE) |
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| 90 | #define cpu_has_pge boot_cpu_has(X86_FEATURE_PGE) |
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| 91 | #define cpu_has_sse2 boot_cpu_has(X86_FEATURE_XMM2) |
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| 92 | #define cpu_has_apic boot_cpu_has(X86_FEATURE_APIC) |
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| 93 | #define cpu_has_sep boot_cpu_has(X86_FEATURE_SEP) |
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| 94 | #define cpu_has_mtrr boot_cpu_has(X86_FEATURE_MTRR) |
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| 95 | #define cpu_has_mmx boot_cpu_has(X86_FEATURE_MMX) |
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| 96 | #define cpu_has_fxsr boot_cpu_has(X86_FEATURE_FXSR) |
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| 97 | #define cpu_has_xmm boot_cpu_has(X86_FEATURE_XMM) |
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| 98 | #define cpu_has_ht boot_cpu_has(X86_FEATURE_HT) |
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| 99 | #define cpu_has_mp boot_cpu_has(X86_FEATURE_MP) |
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| 100 | #define cpu_has_k6_mtrr boot_cpu_has(X86_FEATURE_K6_MTRR) |
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| 101 | #define cpu_has_cyrix_arr boot_cpu_has(X86_FEATURE_CYRIX_ARR) |
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| 102 | #define cpu_has_centaur_mcr boot_cpu_has(X86_FEATURE_CENTAUR_MCR) |
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| 103 | #define cpu_has_xstore boot_cpu_has(X86_FEATURE_XSTORE) |
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| 104 | |||
| 105 | #endif /* __ASM_I386_CPUFEATURE_H */ |
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| 106 | |||
| 107 | /* |
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| 108 | * Local Variables: |
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| 109 | * mode:c |
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| 110 | * comment-column:42 |
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| 111 | * End: |
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| 112 | */ |