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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 422 | giacomo | 1 | #ifndef __ASM_SPINLOCK_H |
| 2 | #define __ASM_SPINLOCK_H |
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| 3 | |||
| 4 | #include <asm/atomic.h> |
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| 5 | #include <asm/rwlock.h> |
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| 6 | #include <asm/page.h> |
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| 7 | #include <linux/config.h> |
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| 8 | #include <linux/compiler.h> |
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| 9 | |||
| 10 | extern int printk(const char * fmt, ...) |
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| 11 | __attribute__ ((format (printf, 1, 2))); |
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| 12 | |||
| 13 | /* |
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| 14 | * Your basic SMP spinlocks, allowing only a single CPU anywhere |
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| 15 | */ |
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| 16 | |||
| 17 | typedef struct { |
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| 18 | volatile unsigned int lock; |
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| 19 | #ifdef CONFIG_DEBUG_SPINLOCK |
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| 20 | unsigned magic; |
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| 21 | #endif |
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| 22 | } spinlock_t; |
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| 23 | |||
| 24 | #define SPINLOCK_MAGIC 0xdead4ead |
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| 25 | |||
| 26 | #ifdef CONFIG_DEBUG_SPINLOCK |
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| 27 | #define SPINLOCK_MAGIC_INIT , SPINLOCK_MAGIC |
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| 28 | #else |
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| 29 | #define SPINLOCK_MAGIC_INIT /* */ |
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| 30 | #endif |
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| 31 | |||
| 32 | #define SPIN_LOCK_UNLOCKED (spinlock_t) { 1 SPINLOCK_MAGIC_INIT } |
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| 33 | |||
| 34 | #define spin_lock_init(x) do { *(x) = SPIN_LOCK_UNLOCKED; } while(0) |
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| 35 | |||
| 36 | /* |
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| 37 | * Simple spin lock operations. There are two variants, one clears IRQ's |
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| 38 | * on the local processor, one does not. |
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| 39 | * |
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| 40 | * We make no fairness assumptions. They have a cost. |
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| 41 | */ |
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| 42 | |||
| 43 | #define spin_is_locked(x) (*(volatile signed char *)(&(x)->lock) <= 0) |
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| 44 | #define spin_unlock_wait(x) do { barrier(); } while(spin_is_locked(x)) |
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| 45 | |||
| 46 | #define spin_lock_string \ |
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| 47 | "\n1:\t" \ |
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| 48 | "lock ; decb %0\n\t" \ |
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| 49 | "js 2f\n" \ |
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| 50 | LOCK_SECTION_START("") \ |
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| 51 | "2:\t" \ |
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| 52 | "rep;nop\n\t" \ |
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| 53 | "cmpb $0,%0\n\t" \ |
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| 54 | "jle 2b\n\t" \ |
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| 55 | "jmp 1b\n" \ |
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| 56 | LOCK_SECTION_END |
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| 57 | |||
| 58 | /* |
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| 59 | * This works. Despite all the confusion. |
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| 60 | * (except on PPro SMP or if we are using OOSTORE) |
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| 61 | * (PPro errata 66, 92) |
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| 62 | */ |
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| 63 | |||
| 64 | #if !defined(CONFIG_X86_OOSTORE) && !defined(CONFIG_X86_PPRO_FENCE) |
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| 65 | |||
| 66 | #define spin_unlock_string \ |
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| 67 | "movb $1,%0" \ |
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| 68 | :"=m" (lock->lock) : : "memory" |
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| 69 | |||
| 70 | |||
| 71 | static inline void _raw_spin_unlock(spinlock_t *lock) |
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| 72 | { |
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| 73 | #ifdef CONFIG_DEBUG_SPINLOCK |
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| 74 | BUG_ON(lock->magic != SPINLOCK_MAGIC); |
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| 75 | BUG_ON(!spin_is_locked(lock)); |
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| 76 | #endif |
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| 77 | __asm__ __volatile__( |
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| 78 | spin_unlock_string |
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| 79 | ); |
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| 80 | } |
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| 81 | |||
| 82 | #else |
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| 83 | |||
| 84 | #define spin_unlock_string \ |
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| 85 | "xchgb %b0, %1" \ |
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| 86 | :"=q" (oldval), "=m" (lock->lock) \ |
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| 87 | :"0" (oldval) : "memory" |
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| 88 | |||
| 89 | static inline void _raw_spin_unlock(spinlock_t *lock) |
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| 90 | { |
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| 91 | char oldval = 1; |
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| 92 | #ifdef CONFIG_DEBUG_SPINLOCK |
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| 93 | BUG_ON(lock->magic != SPINLOCK_MAGIC); |
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| 94 | BUG_ON(!spin_is_locked(lock)); |
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| 95 | #endif |
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| 96 | __asm__ __volatile__( |
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| 97 | spin_unlock_string |
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| 98 | ); |
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| 99 | } |
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| 100 | |||
| 101 | #endif |
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| 102 | |||
| 103 | static inline int _raw_spin_trylock(spinlock_t *lock) |
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| 104 | { |
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| 105 | char oldval; |
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| 106 | __asm__ __volatile__( |
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| 107 | "xchgb %b0,%1" |
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| 108 | :"=q" (oldval), "=m" (lock->lock) |
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| 109 | :"0" (0) : "memory"); |
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| 110 | return oldval > 0; |
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| 111 | } |
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| 112 | |||
| 113 | static inline void _raw_spin_lock(spinlock_t *lock) |
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| 114 | { |
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| 115 | #ifdef CONFIG_DEBUG_SPINLOCK |
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| 116 | __label__ here; |
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| 117 | here: |
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| 118 | if (unlikely(lock->magic != SPINLOCK_MAGIC)) { |
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| 119 | printk("eip: %p\n", &&here); |
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| 120 | BUG(); |
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| 121 | } |
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| 122 | #endif |
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| 123 | __asm__ __volatile__( |
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| 124 | spin_lock_string |
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| 125 | :"=m" (lock->lock) : : "memory"); |
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| 126 | } |
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| 127 | |||
| 128 | |||
| 129 | /* |
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| 130 | * Read-write spinlocks, allowing multiple readers |
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| 131 | * but only one writer. |
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| 132 | * |
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| 133 | * NOTE! it is quite common to have readers in interrupts |
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| 134 | * but no interrupt writers. For those circumstances we |
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| 135 | * can "mix" irq-safe locks - any writer needs to get a |
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| 136 | * irq-safe write-lock, but readers can get non-irqsafe |
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| 137 | * read-locks. |
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| 138 | */ |
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| 139 | typedef struct { |
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| 140 | volatile unsigned int lock; |
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| 141 | #ifdef CONFIG_DEBUG_SPINLOCK |
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| 142 | unsigned magic; |
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| 143 | #endif |
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| 144 | } rwlock_t; |
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| 145 | |||
| 146 | #define RWLOCK_MAGIC 0xdeaf1eed |
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| 147 | |||
| 148 | #ifdef CONFIG_DEBUG_SPINLOCK |
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| 149 | #define RWLOCK_MAGIC_INIT , RWLOCK_MAGIC |
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| 150 | #else |
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| 151 | #define RWLOCK_MAGIC_INIT /* */ |
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| 152 | #endif |
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| 153 | |||
| 154 | #define RW_LOCK_UNLOCKED (rwlock_t) { RW_LOCK_BIAS RWLOCK_MAGIC_INIT } |
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| 155 | |||
| 156 | #define rwlock_init(x) do { *(x) = RW_LOCK_UNLOCKED; } while(0) |
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| 157 | |||
| 158 | #define rwlock_is_locked(x) ((x)->lock != RW_LOCK_BIAS) |
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| 159 | |||
| 160 | /* |
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| 161 | * On x86, we implement read-write locks as a 32-bit counter |
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| 162 | * with the high bit (sign) being the "contended" bit. |
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| 163 | * |
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| 164 | * The inline assembly is non-obvious. Think about it. |
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| 165 | * |
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| 166 | * Changed to use the same technique as rw semaphores. See |
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| 167 | * semaphore.h for details. -ben |
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| 168 | */ |
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| 169 | /* the spinlock helpers are in arch/i386/kernel/semaphore.c */ |
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| 170 | |||
| 171 | static inline void _raw_read_lock(rwlock_t *rw) |
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| 172 | { |
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| 173 | #ifdef CONFIG_DEBUG_SPINLOCK |
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| 174 | BUG_ON(rw->magic != RWLOCK_MAGIC); |
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| 175 | #endif |
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| 176 | __build_read_lock(rw, "__read_lock_failed"); |
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| 177 | } |
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| 178 | |||
| 179 | static inline void _raw_write_lock(rwlock_t *rw) |
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| 180 | { |
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| 181 | #ifdef CONFIG_DEBUG_SPINLOCK |
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| 182 | BUG_ON(rw->magic != RWLOCK_MAGIC); |
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| 183 | #endif |
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| 184 | __build_write_lock(rw, "__write_lock_failed"); |
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| 185 | } |
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| 186 | |||
| 187 | #define _raw_read_unlock(rw) asm volatile("lock ; incl %0" :"=m" ((rw)->lock) : : "memory") |
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| 188 | #define _raw_write_unlock(rw) asm volatile("lock ; addl $" RW_LOCK_BIAS_STR ",%0":"=m" ((rw)->lock) : : "memory") |
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| 189 | |||
| 190 | static inline int _raw_write_trylock(rwlock_t *lock) |
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| 191 | { |
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| 192 | atomic_t *count = (atomic_t *)lock; |
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| 193 | if (atomic_sub_and_test(RW_LOCK_BIAS, count)) |
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| 194 | return 1; |
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| 195 | atomic_add(RW_LOCK_BIAS, count); |
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| 196 | return 0; |
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| 197 | } |
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| 198 | |||
| 199 | #endif /* __ASM_SPINLOCK_H */ |