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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 422 | giacomo | 1 | /* Copyright (C) 1999,2001 |
| 2 | * |
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| 3 | * Author: J.E.J.Bottomley@HansenPartnership.com |
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| 4 | * |
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| 5 | * Standard include definitions for the NCR Voyager system */ |
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| 6 | |||
| 7 | #undef VOYAGER_DEBUG |
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| 8 | #undef VOYAGER_CAT_DEBUG |
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| 9 | |||
| 10 | #ifdef VOYAGER_DEBUG |
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| 11 | #define VDEBUG(x) printk x |
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| 12 | #else |
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| 13 | #define VDEBUG(x) |
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| 14 | #endif |
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| 15 | |||
| 16 | /* There are three levels of voyager machine: 3,4 and 5. The rule is |
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| 17 | * if it's less than 3435 it's a Level 3 except for a 3360 which is |
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| 18 | * a level 4. A 3435 or above is a Level 5 */ |
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| 19 | #define VOYAGER_LEVEL5_AND_ABOVE 0x3435 |
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| 20 | #define VOYAGER_LEVEL4 0x3360 |
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| 21 | |||
| 22 | /* The L4 DINO ASIC */ |
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| 23 | #define VOYAGER_DINO 0x43 |
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| 24 | |||
| 25 | /* voyager ports in standard I/O space */ |
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| 26 | #define VOYAGER_MC_SETUP 0x96 |
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| 27 | |||
| 28 | |||
| 29 | #define VOYAGER_CAT_CONFIG_PORT 0x97 |
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| 30 | # define VOYAGER_CAT_DESELECT 0xff |
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| 31 | #define VOYAGER_SSPB_RELOCATION_PORT 0x98 |
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| 32 | |||
| 33 | /* Valid CAT controller commands */ |
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| 34 | /* start instruction register cycle */ |
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| 35 | #define VOYAGER_CAT_IRCYC 0x01 |
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| 36 | /* start data register cycle */ |
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| 37 | #define VOYAGER_CAT_DRCYC 0x02 |
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| 38 | /* move to execute state */ |
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| 39 | #define VOYAGER_CAT_RUN 0x0F |
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| 40 | /* end operation */ |
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| 41 | #define VOYAGER_CAT_END 0x80 |
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| 42 | /* hold in idle state */ |
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| 43 | #define VOYAGER_CAT_HOLD 0x90 |
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| 44 | /* single step an "intest" vector */ |
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| 45 | #define VOYAGER_CAT_STEP 0xE0 |
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| 46 | /* return cat controller to CLEMSON mode */ |
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| 47 | #define VOYAGER_CAT_CLEMSON 0xFF |
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| 48 | |||
| 49 | /* the default cat command header */ |
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| 50 | #define VOYAGER_CAT_HEADER 0x7F |
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| 51 | |||
| 52 | /* the range of possible CAT module ids in the system */ |
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| 53 | #define VOYAGER_MIN_MODULE 0x10 |
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| 54 | #define VOYAGER_MAX_MODULE 0x1f |
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| 55 | |||
| 56 | /* The voyager registers per asic */ |
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| 57 | #define VOYAGER_ASIC_ID_REG 0x00 |
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| 58 | #define VOYAGER_ASIC_TYPE_REG 0x01 |
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| 59 | /* the sub address registers can be made auto incrementing on reads */ |
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| 60 | #define VOYAGER_AUTO_INC_REG 0x02 |
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| 61 | # define VOYAGER_AUTO_INC 0x04 |
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| 62 | # define VOYAGER_NO_AUTO_INC 0xfb |
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| 63 | #define VOYAGER_SUBADDRDATA 0x03 |
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| 64 | #define VOYAGER_SCANPATH 0x05 |
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| 65 | # define VOYAGER_CONNECT_ASIC 0x01 |
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| 66 | # define VOYAGER_DISCONNECT_ASIC 0xfe |
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| 67 | #define VOYAGER_SUBADDRLO 0x06 |
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| 68 | #define VOYAGER_SUBADDRHI 0x07 |
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| 69 | #define VOYAGER_SUBMODSELECT 0x08 |
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| 70 | #define VOYAGER_SUBMODPRESENT 0x09 |
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| 71 | |||
| 72 | #define VOYAGER_SUBADDR_LO 0xff |
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| 73 | #define VOYAGER_SUBADDR_HI 0xffff |
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| 74 | |||
| 75 | /* the maximum size of a scan path -- used to form instructions */ |
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| 76 | #define VOYAGER_MAX_SCAN_PATH 0x100 |
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| 77 | /* the biggest possible register size (in bytes) */ |
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| 78 | #define VOYAGER_MAX_REG_SIZE 4 |
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| 79 | |||
| 80 | /* Total number of possible modules (including submodules) */ |
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| 81 | #define VOYAGER_MAX_MODULES 16 |
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| 82 | /* Largest number of asics per module */ |
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| 83 | #define VOYAGER_MAX_ASICS_PER_MODULE 7 |
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| 84 | |||
| 85 | /* the CAT asic of each module is always the first one */ |
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| 86 | #define VOYAGER_CAT_ID 0 |
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| 87 | #define VOYAGER_PSI 0x1a |
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| 88 | |||
| 89 | /* voyager instruction operations and registers */ |
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| 90 | #define VOYAGER_READ_CONFIG 0x1 |
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| 91 | #define VOYAGER_WRITE_CONFIG 0x2 |
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| 92 | #define VOYAGER_BYPASS 0xff |
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| 93 | |||
| 94 | typedef struct voyager_asic |
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| 95 | { |
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| 96 | __u8 asic_addr; /* ASIC address; Level 4 */ |
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| 97 | __u8 asic_type; /* ASIC type */ |
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| 98 | __u8 asic_id; /* ASIC id */ |
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| 99 | __u8 jtag_id[4]; /* JTAG id */ |
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| 100 | __u8 asic_location; /* Location within scan path; start w/ 0 */ |
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| 101 | __u8 bit_location; /* Location within bit stream; start w/ 0 */ |
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| 102 | __u8 ireg_length; /* Instruction register length */ |
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| 103 | __u16 subaddr; /* Amount of sub address space */ |
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| 104 | struct voyager_asic *next; /* Next asic in linked list */ |
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| 105 | } voyager_asic_t; |
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| 106 | |||
| 107 | typedef struct voyager_module { |
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| 108 | __u8 module_addr; /* Module address */ |
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| 109 | __u8 scan_path_connected; /* Scan path connected */ |
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| 110 | __u16 ee_size; /* Size of the EEPROM */ |
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| 111 | __u16 num_asics; /* Number of Asics */ |
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| 112 | __u16 inst_bits; /* Instruction bits in the scan path */ |
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| 113 | __u16 largest_reg; /* Largest register in the scan path */ |
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| 114 | __u16 smallest_reg; /* Smallest register in the scan path */ |
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| 115 | voyager_asic_t *asic; /* First ASIC in scan path (CAT_I) */ |
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| 116 | struct voyager_module *submodule; /* Submodule pointer */ |
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| 117 | struct voyager_module *next; /* Next module in linked list */ |
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| 118 | } voyager_module_t; |
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| 119 | |||
| 120 | typedef struct voyager_eeprom_hdr { |
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| 121 | __u8 module_id[4] __attribute__((packed)); |
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| 122 | __u8 version_id __attribute__((packed)); |
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| 123 | __u8 config_id __attribute__((packed)); |
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| 124 | __u16 boundry_id __attribute__((packed)); /* boundary scan id */ |
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| 125 | __u16 ee_size __attribute__((packed)); /* size of EEPROM */ |
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| 126 | __u8 assembly[11] __attribute__((packed)); /* assembly # */ |
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| 127 | __u8 assembly_rev __attribute__((packed)); /* assembly rev */ |
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| 128 | __u8 tracer[4] __attribute__((packed)); /* tracer number */ |
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| 129 | __u16 assembly_cksum __attribute__((packed)); /* asm checksum */ |
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| 130 | __u16 power_consump __attribute__((packed)); /* pwr requirements */ |
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| 131 | __u16 num_asics __attribute__((packed)); /* number of asics */ |
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| 132 | __u16 bist_time __attribute__((packed)); /* min. bist time */ |
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| 133 | __u16 err_log_offset __attribute__((packed)); /* error log offset */ |
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| 134 | __u16 scan_path_offset __attribute__((packed));/* scan path offset */ |
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| 135 | __u16 cct_offset __attribute__((packed)); |
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| 136 | __u16 log_length __attribute__((packed)); /* length of err log */ |
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| 137 | __u16 xsum_end __attribute__((packed)); /* offset to end of |
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| 138 | checksum */ |
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| 139 | __u8 reserved[4] __attribute__((packed)); |
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| 140 | __u8 sflag __attribute__((packed)); /* starting sentinal */ |
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| 141 | __u8 part_number[13] __attribute__((packed)); /* prom part number */ |
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| 142 | __u8 version[10] __attribute__((packed)); /* version number */ |
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| 143 | __u8 signature[8] __attribute__((packed)); |
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| 144 | __u16 eeprom_chksum __attribute__((packed)); |
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| 145 | __u32 data_stamp_offset __attribute__((packed)); |
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| 146 | __u8 eflag __attribute__((packed)); /* ending sentinal */ |
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| 147 | } voyager_eprom_hdr_t; |
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| 148 | |||
| 149 | |||
| 150 | |||
| 151 | #define VOYAGER_EPROM_SIZE_OFFSET ((__u16)(&(((voyager_eprom_hdr_t *)0)->ee_size))) |
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| 152 | #define VOYAGER_XSUM_END_OFFSET 0x2a |
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| 153 | |||
| 154 | /* the following three definitions are for internal table layouts |
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| 155 | * in the module EPROMs. We really only care about the IDs and |
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| 156 | * offsets */ |
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| 157 | typedef struct voyager_sp_table { |
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| 158 | __u8 asic_id __attribute__((packed)); |
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| 159 | __u8 bypass_flag __attribute__((packed)); |
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| 160 | __u16 asic_data_offset __attribute__((packed)); |
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| 161 | __u16 config_data_offset __attribute__((packed)); |
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| 162 | } voyager_sp_table_t; |
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| 163 | |||
| 164 | typedef struct voyager_jtag_table { |
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| 165 | __u8 icode[4] __attribute__((packed)); |
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| 166 | __u8 runbist[4] __attribute__((packed)); |
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| 167 | __u8 intest[4] __attribute__((packed)); |
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| 168 | __u8 samp_preld[4] __attribute__((packed)); |
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| 169 | __u8 ireg_len __attribute__((packed)); |
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| 170 | } voyager_jtt_t; |
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| 171 | |||
| 172 | typedef struct voyager_asic_data_table { |
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| 173 | __u8 jtag_id[4] __attribute__((packed)); |
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| 174 | __u16 length_bsr __attribute__((packed)); |
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| 175 | __u16 length_bist_reg __attribute__((packed)); |
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| 176 | __u32 bist_clk __attribute__((packed)); |
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| 177 | __u16 subaddr_bits __attribute__((packed)); |
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| 178 | __u16 seed_bits __attribute__((packed)); |
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| 179 | __u16 sig_bits __attribute__((packed)); |
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| 180 | __u16 jtag_offset __attribute__((packed)); |
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| 181 | } voyager_at_t; |
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| 182 | |||
| 183 | /* Voyager Interrupt Controller (VIC) registers */ |
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| 184 | |||
| 185 | /* Base to add to Cross Processor Interrupts (CPIs) when triggering |
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| 186 | * the CPU IRQ line */ |
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| 187 | /* register defines for the WCBICs (one per processor) */ |
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| 188 | #define VOYAGER_WCBIC0 0x41 /* bus A node P1 processor 0 */ |
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| 189 | #define VOYAGER_WCBIC1 0x49 /* bus A node P1 processor 1 */ |
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| 190 | #define VOYAGER_WCBIC2 0x51 /* bus A node P2 processor 0 */ |
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| 191 | #define VOYAGER_WCBIC3 0x59 /* bus A node P2 processor 1 */ |
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| 192 | #define VOYAGER_WCBIC4 0x61 /* bus B node P1 processor 0 */ |
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| 193 | #define VOYAGER_WCBIC5 0x69 /* bus B node P1 processor 1 */ |
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| 194 | #define VOYAGER_WCBIC6 0x71 /* bus B node P2 processor 0 */ |
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| 195 | #define VOYAGER_WCBIC7 0x79 /* bus B node P2 processor 1 */ |
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| 196 | |||
| 197 | |||
| 198 | /* top of memory registers */ |
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| 199 | #define VOYAGER_WCBIC_TOM_L 0x4 |
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| 200 | #define VOYAGER_WCBIC_TOM_H 0x5 |
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| 201 | |||
| 202 | /* register defines for Voyager Memory Contol (VMC) |
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| 203 | * these are present on L4 machines only */ |
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| 204 | #define VOYAGER_VMC1 0x81 |
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| 205 | #define VOYAGER_VMC2 0x91 |
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| 206 | #define VOYAGER_VMC3 0xa1 |
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| 207 | #define VOYAGER_VMC4 0xb1 |
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| 208 | |||
| 209 | /* VMC Ports */ |
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| 210 | #define VOYAGER_VMC_MEMORY_SETUP 0x9 |
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| 211 | # define VMC_Interleaving 0x01 |
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| 212 | # define VMC_4Way 0x02 |
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| 213 | # define VMC_EvenCacheLines 0x04 |
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| 214 | # define VMC_HighLine 0x08 |
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| 215 | # define VMC_Start0_Enable 0x20 |
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| 216 | # define VMC_Start1_Enable 0x40 |
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| 217 | # define VMC_Vremap 0x80 |
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| 218 | #define VOYAGER_VMC_BANK_DENSITY 0xa |
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| 219 | # define VMC_BANK_EMPTY 0 |
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| 220 | # define VMC_BANK_4MB 1 |
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| 221 | # define VMC_BANK_16MB 2 |
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| 222 | # define VMC_BANK_64MB 3 |
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| 223 | # define VMC_BANK0_MASK 0x03 |
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| 224 | # define VMC_BANK1_MASK 0x0C |
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| 225 | # define VMC_BANK2_MASK 0x30 |
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| 226 | # define VMC_BANK3_MASK 0xC0 |
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| 227 | |||
| 228 | /* Magellan Memory Controller (MMC) defines - present on L5 */ |
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| 229 | #define VOYAGER_MMC_ASIC_ID 1 |
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| 230 | /* the two memory modules corresponding to memory cards in the system */ |
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| 231 | #define VOYAGER_MMC_MEMORY0_MODULE 0x14 |
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| 232 | #define VOYAGER_MMC_MEMORY1_MODULE 0x15 |
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| 233 | /* the Magellan Memory Address (MMA) defines */ |
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| 234 | #define VOYAGER_MMA_ASIC_ID 2 |
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| 235 | |||
| 236 | /* Submodule number for the Quad Baseboard */ |
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| 237 | #define VOYAGER_QUAD_BASEBOARD 1 |
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| 238 | |||
| 239 | /* ASIC defines for the Quad Baseboard */ |
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| 240 | #define VOYAGER_QUAD_QDATA0 1 |
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| 241 | #define VOYAGER_QUAD_QDATA1 2 |
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| 242 | #define VOYAGER_QUAD_QABC 3 |
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| 243 | |||
| 244 | /* Useful areas in extended CMOS */ |
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| 245 | #define VOYAGER_PROCESSOR_PRESENT_MASK 0x88a |
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| 246 | #define VOYAGER_MEMORY_CLICKMAP 0xa23 |
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| 247 | #define VOYAGER_DUMP_LOCATION 0xb1a |
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| 248 | |||
| 249 | /* SUS In Control bit - used to tell SUS that we don't need to be |
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| 250 | * babysat anymore */ |
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| 251 | #define VOYAGER_SUS_IN_CONTROL_PORT 0x3ff |
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| 252 | # define VOYAGER_IN_CONTROL_FLAG 0x80 |
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| 253 | |||
| 254 | /* Voyager PSI defines */ |
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| 255 | #define VOYAGER_PSI_STATUS_REG 0x08 |
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| 256 | # define PSI_DC_FAIL 0x01 |
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| 257 | # define PSI_MON 0x02 |
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| 258 | # define PSI_FAULT 0x04 |
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| 259 | # define PSI_ALARM 0x08 |
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| 260 | # define PSI_CURRENT 0x10 |
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| 261 | # define PSI_DVM 0x20 |
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| 262 | # define PSI_PSCFAULT 0x40 |
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| 263 | # define PSI_STAT_CHG 0x80 |
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| 264 | |||
| 265 | #define VOYAGER_PSI_SUPPLY_REG 0x8000 |
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| 266 | /* read */ |
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| 267 | # define PSI_FAIL_DC 0x01 |
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| 268 | # define PSI_FAIL_AC 0x02 |
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| 269 | # define PSI_MON_INT 0x04 |
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| 270 | # define PSI_SWITCH_OFF 0x08 |
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| 271 | # define PSI_HX_OFF 0x10 |
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| 272 | # define PSI_SECURITY 0x20 |
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| 273 | # define PSI_CMOS_BATT_LOW 0x40 |
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| 274 | # define PSI_CMOS_BATT_FAIL 0x80 |
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| 275 | /* write */ |
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| 276 | # define PSI_CLR_SWITCH_OFF 0x13 |
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| 277 | # define PSI_CLR_HX_OFF 0x14 |
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| 278 | # define PSI_CLR_CMOS_BATT_FAIL 0x17 |
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| 279 | |||
| 280 | #define VOYAGER_PSI_MASK 0x8001 |
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| 281 | # define PSI_MASK_MASK 0x10 |
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| 282 | |||
| 283 | #define VOYAGER_PSI_AC_FAIL_REG 0x8004 |
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| 284 | #define AC_FAIL_STAT_CHANGE 0x80 |
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| 285 | |||
| 286 | #define VOYAGER_PSI_GENERAL_REG 0x8007 |
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| 287 | /* read */ |
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| 288 | # define PSI_SWITCH_ON 0x01 |
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| 289 | # define PSI_SWITCH_ENABLED 0x02 |
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| 290 | # define PSI_ALARM_ENABLED 0x08 |
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| 291 | # define PSI_SECURE_ENABLED 0x10 |
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| 292 | # define PSI_COLD_RESET 0x20 |
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| 293 | # define PSI_COLD_START 0x80 |
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| 294 | /* write */ |
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| 295 | # define PSI_POWER_DOWN 0x10 |
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| 296 | # define PSI_SWITCH_DISABLE 0x01 |
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| 297 | # define PSI_SWITCH_ENABLE 0x11 |
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| 298 | # define PSI_CLEAR 0x12 |
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| 299 | # define PSI_ALARM_DISABLE 0x03 |
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| 300 | # define PSI_ALARM_ENABLE 0x13 |
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| 301 | # define PSI_CLEAR_COLD_RESET 0x05 |
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| 302 | # define PSI_SET_COLD_RESET 0x15 |
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| 303 | # define PSI_CLEAR_COLD_START 0x07 |
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| 304 | # define PSI_SET_COLD_START 0x17 |
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| 305 | |||
| 306 | |||
| 307 | |||
| 308 | struct voyager_bios_info { |
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| 309 | __u8 len; |
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| 310 | __u8 major; |
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| 311 | __u8 minor; |
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| 312 | __u8 debug; |
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| 313 | __u8 num_classes; |
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| 314 | __u8 class_1; |
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| 315 | __u8 class_2; |
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| 316 | }; |
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| 317 | |||
| 318 | /* The following structures and definitions are for the Kernel/SUS |
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| 319 | * interface these are needed to find out how SUS initialised any Quad |
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| 320 | * boards in the system */ |
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| 321 | |||
| 322 | #define NUMBER_OF_MC_BUSSES 2 |
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| 323 | #define SLOTS_PER_MC_BUS 8 |
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| 324 | #define MAX_CPUS 16 /* 16 way CPU system */ |
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| 325 | #define MAX_PROCESSOR_BOARDS 4 /* 4 processor slot system */ |
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| 326 | #define MAX_CACHE_LEVELS 4 /* # of cache levels supported */ |
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| 327 | #define MAX_SHARED_CPUS 4 /* # of CPUs that can share a LARC */ |
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| 328 | #define NUMBER_OF_POS_REGS 8 |
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| 329 | |||
| 330 | typedef struct { |
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| 331 | __u8 MC_Slot __attribute__((packed)); |
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| 332 | __u8 POS_Values[NUMBER_OF_POS_REGS] __attribute__((packed)); |
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| 333 | } MC_SlotInformation_t; |
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| 334 | |||
| 335 | struct QuadDescription { |
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| 336 | __u8 Type __attribute__((packed)); /* for type 0 (DYADIC or MONADIC) all fields |
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| 337 | * will be zero except for slot */ |
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| 338 | __u8 StructureVersion __attribute__((packed)); |
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| 339 | __u32 CPI_BaseAddress __attribute__((packed)); |
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| 340 | __u32 LARC_BankSize __attribute__((packed)); |
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| 341 | __u32 LocalMemoryStateBits __attribute__((packed)); |
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| 342 | __u8 Slot __attribute__((packed)); /* Processor slots 1 - 4 */ |
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| 343 | }; |
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| 344 | |||
| 345 | struct ProcBoardInfo { |
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| 346 | __u8 Type __attribute__((packed)); |
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| 347 | __u8 StructureVersion __attribute__((packed)); |
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| 348 | __u8 NumberOfBoards __attribute__((packed)); |
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| 349 | struct QuadDescription QuadData[MAX_PROCESSOR_BOARDS] __attribute__((packed)); |
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| 350 | }; |
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| 351 | |||
| 352 | struct CacheDescription { |
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| 353 | __u8 Level __attribute__((packed)); |
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| 354 | __u32 TotalSize __attribute__((packed)); |
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| 355 | __u16 LineSize __attribute__((packed)); |
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| 356 | __u8 Associativity __attribute__((packed)); |
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| 357 | __u8 CacheType __attribute__((packed)); |
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| 358 | __u8 WriteType __attribute__((packed)); |
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| 359 | __u8 Number_CPUs_SharedBy __attribute__((packed)); |
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| 360 | __u8 Shared_CPUs_Hardware_IDs[MAX_SHARED_CPUS] __attribute__((packed)); |
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| 361 | |||
| 362 | }; |
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| 363 | |||
| 364 | struct CPU_Description { |
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| 365 | __u8 CPU_HardwareId __attribute__((packed)); |
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| 366 | char *FRU_String __attribute__((packed)); |
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| 367 | __u8 NumberOfCacheLevels __attribute__((packed)); |
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| 368 | struct CacheDescription CacheLevelData[MAX_CACHE_LEVELS] __attribute__((packed)); |
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| 369 | }; |
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| 370 | |||
| 371 | struct CPU_Info { |
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| 372 | __u8 Type __attribute__((packed)); |
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| 373 | __u8 StructureVersion __attribute__((packed)); |
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| 374 | __u8 NumberOf_CPUs __attribute__((packed)); |
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| 375 | struct CPU_Description CPU_Data[MAX_CPUS] __attribute__((packed)); |
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| 376 | }; |
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| 377 | |||
| 378 | |||
| 379 | /* |
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| 380 | * This structure will be used by SUS and the OS. |
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| 381 | * The assumption about this structure is that no blank space is |
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| 382 | * packed in it by our friend the compiler. |
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| 383 | */ |
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| 384 | typedef struct { |
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| 385 | __u8 Mailbox_SUS; /* Written to by SUS to give commands/response to the OS */ |
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| 386 | __u8 Mailbox_OS; /* Written to by the OS to give commands/response to SUS */ |
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| 387 | __u8 SUS_MailboxVersion; /* Tells the OS which iteration of the interface SUS supports */ |
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| 388 | __u8 OS_MailboxVersion; /* Tells SUS which iteration of the interface the OS supports */ |
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| 389 | __u32 OS_Flags; /* Flags set by the OS as info for SUS */ |
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| 390 | __u32 SUS_Flags; /* Flags set by SUS as info for the OS */ |
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| 391 | __u32 WatchDogPeriod; /* Watchdog period (in seconds) which the DP uses to see if the OS is dead */ |
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| 392 | __u32 WatchDogCount; /* Updated by the OS on every tic. */ |
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| 393 | __u32 MemoryFor_SUS_ErrorLog; /* Flat 32 bit address which tells SUS where to stuff the SUS error log on a dump */ |
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| 394 | MC_SlotInformation_t MC_SlotInfo[NUMBER_OF_MC_BUSSES*SLOTS_PER_MC_BUS]; /* Storage for MCA POS data */ |
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| 395 | /* All new SECOND_PASS_INTERFACE fields added from this point */ |
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| 396 | struct ProcBoardInfo *BoardData; |
||
| 397 | struct CPU_Info *CPU_Data; |
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| 398 | /* All new fields must be added from this point */ |
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| 399 | } Voyager_KernelSUS_Mbox_t; |
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| 400 | |||
| 401 | /* structure for finding the right memory address to send a QIC CPI to */ |
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| 402 | struct voyager_qic_cpi { |
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| 403 | /* Each cache line (32 bytes) can trigger a cpi. The cpi |
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| 404 | * read/write may occur anywhere in the cache line---pick the |
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| 405 | * middle to be safe */ |
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| 406 | struct { |
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| 407 | __u32 pad1[3]; |
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| 408 | __u32 cpi; |
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| 409 | __u32 pad2[4]; |
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| 410 | } qic_cpi[8]; |
||
| 411 | }; |
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| 412 | |||
| 413 | struct voyager_status { |
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| 414 | __u32 power_fail:1; |
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| 415 | __u32 switch_off:1; |
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| 416 | __u32 request_from_kernel:1; |
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| 417 | }; |
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| 418 | |||
| 419 | struct voyager_psi_regs { |
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| 420 | __u8 cat_id; |
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| 421 | __u8 cat_dev; |
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| 422 | __u8 cat_control; |
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| 423 | __u8 subaddr; |
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| 424 | __u8 dummy4; |
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| 425 | __u8 checkbit; |
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| 426 | __u8 subaddr_low; |
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| 427 | __u8 subaddr_high; |
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| 428 | __u8 intstatus; |
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| 429 | __u8 stat1; |
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| 430 | __u8 stat3; |
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| 431 | __u8 fault; |
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| 432 | __u8 tms; |
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| 433 | __u8 gen; |
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| 434 | __u8 sysconf; |
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| 435 | __u8 dummy15; |
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| 436 | }; |
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| 437 | |||
| 438 | struct voyager_psi_subregs { |
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| 439 | __u8 supply; |
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| 440 | __u8 mask; |
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| 441 | __u8 present; |
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| 442 | __u8 DCfail; |
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| 443 | __u8 ACfail; |
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| 444 | __u8 fail; |
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| 445 | __u8 UPSfail; |
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| 446 | __u8 genstatus; |
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| 447 | }; |
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| 448 | |||
| 449 | struct voyager_psi { |
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| 450 | struct voyager_psi_regs regs; |
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| 451 | struct voyager_psi_subregs subregs; |
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| 452 | }; |
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| 453 | |||
| 454 | struct voyager_SUS { |
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| 455 | #define VOYAGER_DUMP_BUTTON_NMI 0x1 |
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| 456 | #define VOYAGER_SUS_VALID 0x2 |
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| 457 | #define VOYAGER_SYSINT_COMPLETE 0x3 |
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| 458 | __u8 SUS_mbox; |
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| 459 | #define VOYAGER_NO_COMMAND 0x0 |
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| 460 | #define VOYAGER_IGNORE_DUMP 0x1 |
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| 461 | #define VOYAGER_DO_DUMP 0x2 |
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| 462 | #define VOYAGER_SYSINT_HANDSHAKE 0x3 |
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| 463 | #define VOYAGER_DO_MEM_DUMP 0x4 |
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| 464 | #define VOYAGER_SYSINT_WAS_RECOVERED 0x5 |
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| 465 | __u8 kernel_mbox; |
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| 466 | #define VOYAGER_MAILBOX_VERSION 0x10 |
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| 467 | __u8 SUS_version; |
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| 468 | __u8 kernel_version; |
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| 469 | #define VOYAGER_OS_HAS_SYSINT 0x1 |
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| 470 | #define VOYAGER_OS_IN_PROGRESS 0x2 |
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| 471 | #define VOYAGER_UPDATING_WDPERIOD 0x4 |
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| 472 | __u32 kernel_flags; |
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| 473 | #define VOYAGER_SUS_BOOTING 0x1 |
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| 474 | #define VOYAGER_SUS_IN_PROGRESS 0x2 |
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| 475 | __u32 SUS_flags; |
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| 476 | __u32 watchdog_period; |
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| 477 | __u32 watchdog_count; |
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| 478 | __u32 SUS_errorlog; |
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| 479 | /* lots of system configuration stuff under here */ |
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| 480 | }; |
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| 481 | |||
| 482 | /* Variables exported by voyager_smp */ |
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| 483 | extern __u32 voyager_extended_vic_processors; |
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| 484 | extern __u32 voyager_allowed_boot_processors; |
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| 485 | extern __u32 voyager_quad_processors; |
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| 486 | extern struct voyager_qic_cpi *voyager_quad_cpi_addr[NR_CPUS]; |
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| 487 | extern struct voyager_SUS *voyager_SUS; |
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| 488 | |||
| 489 | /* variables exported always */ |
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| 490 | extern int voyager_level; |
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| 491 | extern int kvoyagerd_running; |
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| 492 | extern struct semaphore kvoyagerd_sem; |
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| 493 | extern struct voyager_status voyager_status; |
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| 494 | |||
| 495 | |||
| 496 | |||
| 497 | /* functions exported by the voyager and voyager_smp modules */ |
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| 498 | |||
| 499 | extern int voyager_cat_readb(__u8 module, __u8 asic, int reg); |
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| 500 | extern void voyager_cat_init(void); |
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| 501 | extern void voyager_detect(struct voyager_bios_info *); |
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| 502 | extern void voyager_trap_init(void); |
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| 503 | extern void voyager_setup_irqs(void); |
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| 504 | extern int voyager_memory_detect(int region, __u32 *addr, __u32 *length); |
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| 505 | extern void voyager_smp_intr_init(void); |
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| 506 | extern __u8 voyager_extended_cmos_read(__u16 cmos_address); |
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| 507 | extern void voyager_smp_dump(void); |
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| 508 | extern void voyager_timer_interrupt(struct pt_regs *regs); |
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| 509 | extern void smp_local_timer_interrupt(struct pt_regs * regs); |
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| 510 | extern void voyager_power_off(void); |
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| 511 | extern void smp_voyager_power_off(void *dummy); |
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| 512 | extern void voyager_restart(void); |
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| 513 | extern void voyager_cat_power_off(void); |
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| 514 | extern void voyager_cat_do_common_interrupt(void); |
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| 515 | extern void voyager_handle_nmi(void); |
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| 516 | /* Commands for the following are */ |
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| 517 | #define VOYAGER_PSI_READ 0 |
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| 518 | #define VOYAGER_PSI_WRITE 1 |
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| 519 | #define VOYAGER_PSI_SUBREAD 2 |
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| 520 | #define VOYAGER_PSI_SUBWRITE 3 |
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| 521 | extern void voyager_cat_psi(__u8, __u16, __u8 *); |