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422 giacomo 1
/*
1047 mauro 2
 *      $Id: pci.h,v 1.4 2006-07-04 15:21:01 mauro Exp $
422 giacomo 3
 *
4
 *      PCI defines and function prototypes
5
 *      Copyright 1994, Drew Eckhardt
6
 *      Copyright 1997--1999 Martin Mares <mj@ucw.cz>
7
 *
8
 *      For more information, please consult the following manuals (look at
9
 *      http://www.pcisig.com/ for how to get them):
10
 *
11
 *      PCI BIOS Specification
12
 *      PCI Local Bus Specification
13
 *      PCI to PCI Bridge Specification
14
 *      PCI System Design Guide
15
 */
16
 
17
#ifndef LINUX_PCI_H
18
#define LINUX_PCI_H
19
 
20
#include <linux/mod_devicetable.h>
21
 
22
/*
23
 * Under PCI, each device has 256 bytes of configuration address space,
24
 * of which the first 64 bytes are standardized as follows:
25
 */
26
#define PCI_VENDOR_ID           0x00    /* 16 bits */
27
#define PCI_DEVICE_ID           0x02    /* 16 bits */
28
#define PCI_COMMAND             0x04    /* 16 bits */
29
#define  PCI_COMMAND_IO         0x1     /* Enable response in I/O space */
30
#define  PCI_COMMAND_MEMORY     0x2     /* Enable response in Memory space */
31
#define  PCI_COMMAND_MASTER     0x4     /* Enable bus mastering */
32
#define  PCI_COMMAND_SPECIAL    0x8     /* Enable response to special cycles */
33
#define  PCI_COMMAND_INVALIDATE 0x10    /* Use memory write and invalidate */
34
#define  PCI_COMMAND_VGA_PALETTE 0x20   /* Enable palette snooping */
35
#define  PCI_COMMAND_PARITY     0x40    /* Enable parity checking */
36
#define  PCI_COMMAND_WAIT       0x80    /* Enable address/data stepping */
37
#define  PCI_COMMAND_SERR       0x100   /* Enable SERR */
38
#define  PCI_COMMAND_FAST_BACK  0x200   /* Enable back-to-back writes */
39
 
40
#define PCI_STATUS              0x06    /* 16 bits */
41
#define  PCI_STATUS_CAP_LIST    0x10    /* Support Capability List */
42
#define  PCI_STATUS_66MHZ       0x20    /* Support 66 Mhz PCI 2.1 bus */
43
#define  PCI_STATUS_UDF         0x40    /* Support User Definable Features [obsolete] */
44
#define  PCI_STATUS_FAST_BACK   0x80    /* Accept fast-back to back */
45
#define  PCI_STATUS_PARITY      0x100   /* Detected parity error */
46
#define  PCI_STATUS_DEVSEL_MASK 0x600   /* DEVSEL timing */
47
#define  PCI_STATUS_DEVSEL_FAST 0x000   
48
#define  PCI_STATUS_DEVSEL_MEDIUM 0x200
49
#define  PCI_STATUS_DEVSEL_SLOW 0x400
50
#define  PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */
51
#define  PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */
52
#define  PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */
53
#define  PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */
54
#define  PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */
55
 
56
#define PCI_CLASS_REVISION      0x08    /* High 24 bits are class, low 8
57
                                           revision */
58
#define PCI_REVISION_ID         0x08    /* Revision ID */
59
#define PCI_CLASS_PROG          0x09    /* Reg. Level Programming Interface */
60
#define PCI_CLASS_DEVICE        0x0a    /* Device class */
61
 
62
#define PCI_CACHE_LINE_SIZE     0x0c    /* 8 bits */
63
#define PCI_LATENCY_TIMER       0x0d    /* 8 bits */
64
#define PCI_HEADER_TYPE         0x0e    /* 8 bits */
65
#define  PCI_HEADER_TYPE_NORMAL 0
66
#define  PCI_HEADER_TYPE_BRIDGE 1
67
#define  PCI_HEADER_TYPE_CARDBUS 2
68
 
69
#define PCI_BIST                0x0f    /* 8 bits */
70
#define  PCI_BIST_CODE_MASK     0x0f    /* Return result */
71
#define  PCI_BIST_START         0x40    /* 1 to start BIST, 2 secs or less */
72
#define  PCI_BIST_CAPABLE       0x80    /* 1 if BIST capable */
73
 
74
/*
75
 * Base addresses specify locations in memory or I/O space.
76
 * Decoded size can be determined by writing a value of
77
 * 0xffffffff to the register, and reading it back.  Only
78
 * 1 bits are decoded.
79
 */
80
#define PCI_BASE_ADDRESS_0      0x10    /* 32 bits */
81
#define PCI_BASE_ADDRESS_1      0x14    /* 32 bits [htype 0,1 only] */
82
#define PCI_BASE_ADDRESS_2      0x18    /* 32 bits [htype 0 only] */
83
#define PCI_BASE_ADDRESS_3      0x1c    /* 32 bits */
84
#define PCI_BASE_ADDRESS_4      0x20    /* 32 bits */
85
#define PCI_BASE_ADDRESS_5      0x24    /* 32 bits */
86
#define  PCI_BASE_ADDRESS_SPACE 0x01    /* 0 = memory, 1 = I/O */
87
#define  PCI_BASE_ADDRESS_SPACE_IO 0x01
88
#define  PCI_BASE_ADDRESS_SPACE_MEMORY 0x00
89
#define  PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06
90
#define  PCI_BASE_ADDRESS_MEM_TYPE_32   0x00    /* 32 bit address */
91
#define  PCI_BASE_ADDRESS_MEM_TYPE_1M   0x02    /* Below 1M [obsolete] */
92
#define  PCI_BASE_ADDRESS_MEM_TYPE_64   0x04    /* 64 bit address */
93
#define  PCI_BASE_ADDRESS_MEM_PREFETCH  0x08    /* prefetchable? */
94
#define  PCI_BASE_ADDRESS_MEM_MASK      (~0x0fUL)
95
#define  PCI_BASE_ADDRESS_IO_MASK       (~0x03UL)
96
/* bit 1 is reserved if address_space = 1 */
97
 
98
/* Header type 0 (normal devices) */
99
#define PCI_CARDBUS_CIS         0x28
100
#define PCI_SUBSYSTEM_VENDOR_ID 0x2c
101
#define PCI_SUBSYSTEM_ID        0x2e  
102
#define PCI_ROM_ADDRESS         0x30    /* Bits 31..11 are address, 10..1 reserved */
103
#define  PCI_ROM_ADDRESS_ENABLE 0x01
104
#define PCI_ROM_ADDRESS_MASK    (~0x7ffUL)
105
 
106
#define PCI_CAPABILITY_LIST     0x34    /* Offset of first capability list entry */
107
 
108
/* 0x35-0x3b are reserved */
109
#define PCI_INTERRUPT_LINE      0x3c    /* 8 bits */
110
#define PCI_INTERRUPT_PIN       0x3d    /* 8 bits */
111
#define PCI_MIN_GNT             0x3e    /* 8 bits */
112
#define PCI_MAX_LAT             0x3f    /* 8 bits */
113
 
114
/* Header type 1 (PCI-to-PCI bridges) */
115
#define PCI_PRIMARY_BUS         0x18    /* Primary bus number */
116
#define PCI_SECONDARY_BUS       0x19    /* Secondary bus number */
117
#define PCI_SUBORDINATE_BUS     0x1a    /* Highest bus number behind the bridge */
118
#define PCI_SEC_LATENCY_TIMER   0x1b    /* Latency timer for secondary interface */
119
#define PCI_IO_BASE             0x1c    /* I/O range behind the bridge */
120
#define PCI_IO_LIMIT            0x1d
121
#define  PCI_IO_RANGE_TYPE_MASK 0x0fUL  /* I/O bridging type */
122
#define  PCI_IO_RANGE_TYPE_16   0x00
123
#define  PCI_IO_RANGE_TYPE_32   0x01
124
#define  PCI_IO_RANGE_MASK      (~0x0fUL)
125
#define PCI_SEC_STATUS          0x1e    /* Secondary status register, only bit 14 used */
126
#define PCI_MEMORY_BASE         0x20    /* Memory range behind */
127
#define PCI_MEMORY_LIMIT        0x22
128
#define  PCI_MEMORY_RANGE_TYPE_MASK 0x0fUL
129
#define  PCI_MEMORY_RANGE_MASK  (~0x0fUL)
130
#define PCI_PREF_MEMORY_BASE    0x24    /* Prefetchable memory range behind */
131
#define PCI_PREF_MEMORY_LIMIT   0x26
132
#define  PCI_PREF_RANGE_TYPE_MASK 0x0fUL
133
#define  PCI_PREF_RANGE_TYPE_32 0x00
134
#define  PCI_PREF_RANGE_TYPE_64 0x01
135
#define  PCI_PREF_RANGE_MASK    (~0x0fUL)
136
#define PCI_PREF_BASE_UPPER32   0x28    /* Upper half of prefetchable memory range */
137
#define PCI_PREF_LIMIT_UPPER32  0x2c
138
#define PCI_IO_BASE_UPPER16     0x30    /* Upper half of I/O addresses */
139
#define PCI_IO_LIMIT_UPPER16    0x32
140
/* 0x34 same as for htype 0 */
141
/* 0x35-0x3b is reserved */
142
#define PCI_ROM_ADDRESS1        0x38    /* Same as PCI_ROM_ADDRESS, but for htype 1 */
143
/* 0x3c-0x3d are same as for htype 0 */
144
#define PCI_BRIDGE_CONTROL      0x3e
145
#define  PCI_BRIDGE_CTL_PARITY  0x01    /* Enable parity detection on secondary interface */
146
#define  PCI_BRIDGE_CTL_SERR    0x02    /* The same for SERR forwarding */
147
#define  PCI_BRIDGE_CTL_NO_ISA  0x04    /* Disable bridging of ISA ports */
148
#define  PCI_BRIDGE_CTL_VGA     0x08    /* Forward VGA addresses */
149
#define  PCI_BRIDGE_CTL_MASTER_ABORT 0x20  /* Report master aborts */
150
#define  PCI_BRIDGE_CTL_BUS_RESET 0x40  /* Secondary bus reset */
151
#define  PCI_BRIDGE_CTL_FAST_BACK 0x80  /* Fast Back2Back enabled on secondary interface */
152
 
153
/* Header type 2 (CardBus bridges) */
154
#define PCI_CB_CAPABILITY_LIST  0x14
155
/* 0x15 reserved */
156
#define PCI_CB_SEC_STATUS       0x16    /* Secondary status */
157
#define PCI_CB_PRIMARY_BUS      0x18    /* PCI bus number */
158
#define PCI_CB_CARD_BUS         0x19    /* CardBus bus number */
159
#define PCI_CB_SUBORDINATE_BUS  0x1a    /* Subordinate bus number */
160
#define PCI_CB_LATENCY_TIMER    0x1b    /* CardBus latency timer */
161
#define PCI_CB_MEMORY_BASE_0    0x1c
162
#define PCI_CB_MEMORY_LIMIT_0   0x20
163
#define PCI_CB_MEMORY_BASE_1    0x24
164
#define PCI_CB_MEMORY_LIMIT_1   0x28
165
#define PCI_CB_IO_BASE_0        0x2c
166
#define PCI_CB_IO_BASE_0_HI     0x2e
167
#define PCI_CB_IO_LIMIT_0       0x30
168
#define PCI_CB_IO_LIMIT_0_HI    0x32
169
#define PCI_CB_IO_BASE_1        0x34
170
#define PCI_CB_IO_BASE_1_HI     0x36
171
#define PCI_CB_IO_LIMIT_1       0x38
172
#define PCI_CB_IO_LIMIT_1_HI    0x3a
173
#define  PCI_CB_IO_RANGE_MASK   (~0x03UL)
174
/* 0x3c-0x3d are same as for htype 0 */
175
#define PCI_CB_BRIDGE_CONTROL   0x3e
176
#define  PCI_CB_BRIDGE_CTL_PARITY       0x01    /* Similar to standard bridge control register */
177
#define  PCI_CB_BRIDGE_CTL_SERR         0x02
178
#define  PCI_CB_BRIDGE_CTL_ISA          0x04
179
#define  PCI_CB_BRIDGE_CTL_VGA          0x08
180
#define  PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20
181
#define  PCI_CB_BRIDGE_CTL_CB_RESET     0x40    /* CardBus reset */
182
#define  PCI_CB_BRIDGE_CTL_16BIT_INT    0x80    /* Enable interrupt for 16-bit cards */
183
#define  PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100  /* Prefetch enable for both memory regions */
184
#define  PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200
185
#define  PCI_CB_BRIDGE_CTL_POST_WRITES  0x400
186
#define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40
187
#define PCI_CB_SUBSYSTEM_ID     0x42
188
#define PCI_CB_LEGACY_MODE_BASE 0x44    /* 16-bit PC Card legacy mode base address (ExCa) */
189
/* 0x48-0x7f reserved */
190
 
191
/* Capability lists */
192
 
193
#define PCI_CAP_LIST_ID         0       /* Capability ID */
194
#define  PCI_CAP_ID_PM          0x01    /* Power Management */
195
#define  PCI_CAP_ID_AGP         0x02    /* Accelerated Graphics Port */
196
#define  PCI_CAP_ID_VPD         0x03    /* Vital Product Data */
197
#define  PCI_CAP_ID_SLOTID      0x04    /* Slot Identification */
198
#define  PCI_CAP_ID_MSI         0x05    /* Message Signalled Interrupts */
199
#define  PCI_CAP_ID_CHSWP       0x06    /* CompactPCI HotSwap */
200
#define  PCI_CAP_ID_PCIX        0x07    /* PCI-X */
201
#define PCI_CAP_LIST_NEXT       1       /* Next capability in the list */
202
#define PCI_CAP_FLAGS           2       /* Capability defined flags (16 bits) */
203
#define PCI_CAP_SIZEOF          4
204
 
205
/* Power Management Registers */
206
 
207
#define PCI_PM_PMC              2       /* PM Capabilities Register */
208
#define  PCI_PM_CAP_VER_MASK    0x0007  /* Version */
209
#define  PCI_PM_CAP_PME_CLOCK   0x0008  /* PME clock required */
210
#define  PCI_PM_CAP_RESERVED    0x0010  /* Reserved field */
211
#define  PCI_PM_CAP_DSI         0x0020  /* Device specific initialization */
212
#define  PCI_PM_CAP_AUX_POWER   0x01C0  /* Auxilliary power support mask */
213
#define  PCI_PM_CAP_D1          0x0200  /* D1 power state support */
214
#define  PCI_PM_CAP_D2          0x0400  /* D2 power state support */
215
#define  PCI_PM_CAP_PME         0x0800  /* PME pin supported */
216
#define  PCI_PM_CAP_PME_MASK    0xF800  /* PME Mask of all supported states */
217
#define  PCI_PM_CAP_PME_D0      0x0800  /* PME# from D0 */
218
#define  PCI_PM_CAP_PME_D1      0x1000  /* PME# from D1 */
219
#define  PCI_PM_CAP_PME_D2      0x2000  /* PME# from D2 */
220
#define  PCI_PM_CAP_PME_D3      0x4000  /* PME# from D3 (hot) */
221
#define  PCI_PM_CAP_PME_D3cold  0x8000  /* PME# from D3 (cold) */
222
#define PCI_PM_CTRL             4       /* PM control and status register */
223
#define  PCI_PM_CTRL_STATE_MASK 0x0003  /* Current power state (D0 to D3) */
224
#define  PCI_PM_CTRL_PME_ENABLE 0x0100  /* PME pin enable */
225
#define  PCI_PM_CTRL_DATA_SEL_MASK      0x1e00  /* Data select (??) */
226
#define  PCI_PM_CTRL_DATA_SCALE_MASK    0x6000  /* Data scale (??) */
227
#define  PCI_PM_CTRL_PME_STATUS 0x8000  /* PME pin status */
228
#define PCI_PM_PPB_EXTENSIONS   6       /* PPB support extensions (??) */
229
#define  PCI_PM_PPB_B2_B3       0x40    /* Stop clock when in D3hot (??) */
230
#define  PCI_PM_BPCC_ENABLE     0x80    /* Bus power/clock control enable (??) */
231
#define PCI_PM_DATA_REGISTER    7       /* (??) */
232
#define PCI_PM_SIZEOF           8
233
 
234
/* AGP registers */
235
 
236
#define PCI_AGP_VERSION         2       /* BCD version number */
237
#define PCI_AGP_RFU             3       /* Rest of capability flags */
238
#define PCI_AGP_STATUS          4       /* Status register */
239
#define  PCI_AGP_STATUS_RQ_MASK 0xff000000      /* Maximum number of requests - 1 */
240
#define  PCI_AGP_STATUS_SBA     0x0200  /* Sideband addressing supported */
241
#define  PCI_AGP_STATUS_64BIT   0x0020  /* 64-bit addressing supported */
242
#define  PCI_AGP_STATUS_FW      0x0010  /* FW transfers supported */
243
#define  PCI_AGP_STATUS_RATE4   0x0004  /* 4x transfer rate supported */
244
#define  PCI_AGP_STATUS_RATE2   0x0002  /* 2x transfer rate supported */
245
#define  PCI_AGP_STATUS_RATE1   0x0001  /* 1x transfer rate supported */
246
#define PCI_AGP_COMMAND         8       /* Control register */
247
#define  PCI_AGP_COMMAND_RQ_MASK 0xff000000  /* Master: Maximum number of requests */
248
#define  PCI_AGP_COMMAND_SBA    0x0200  /* Sideband addressing enabled */
249
#define  PCI_AGP_COMMAND_AGP    0x0100  /* Allow processing of AGP transactions */
250
#define  PCI_AGP_COMMAND_64BIT  0x0020  /* Allow processing of 64-bit addresses */
251
#define  PCI_AGP_COMMAND_FW     0x0010  /* Force FW transfers */
252
#define  PCI_AGP_COMMAND_RATE4  0x0004  /* Use 4x rate */
253
#define  PCI_AGP_COMMAND_RATE2  0x0002  /* Use 2x rate */
254
#define  PCI_AGP_COMMAND_RATE1  0x0001  /* Use 1x rate */
255
#define PCI_AGP_SIZEOF          12
256
 
257
/* Vital Product Data */
258
 
259
#define PCI_VPD_ADDR            2       /* Address to access (15 bits!) */
260
#define  PCI_VPD_ADDR_MASK      0x7fff  /* Address mask */
261
#define  PCI_VPD_ADDR_F         0x8000  /* Write 0, 1 indicates completion */
262
#define PCI_VPD_DATA            4       /* 32-bits of data returned here */
263
 
264
/* Slot Identification */
265
 
266
#define PCI_SID_ESR             2       /* Expansion Slot Register */
267
#define  PCI_SID_ESR_NSLOTS     0x1f    /* Number of expansion slots available */
268
#define  PCI_SID_ESR_FIC        0x20    /* First In Chassis Flag */
269
#define PCI_SID_CHASSIS_NR      3       /* Chassis Number */
270
 
271
/* Message Signalled Interrupts registers */
272
 
273
#define PCI_MSI_FLAGS           2       /* Various flags */
274
#define  PCI_MSI_FLAGS_64BIT    0x80    /* 64-bit addresses allowed */
275
#define  PCI_MSI_FLAGS_QSIZE    0x70    /* Message queue size configured */
276
#define  PCI_MSI_FLAGS_QMASK    0x0e    /* Maximum queue size available */
277
#define  PCI_MSI_FLAGS_ENABLE   0x01    /* MSI feature enabled */
278
#define PCI_MSI_RFU             3       /* Rest of capability flags */
279
#define PCI_MSI_ADDRESS_LO      4       /* Lower 32 bits */
280
#define PCI_MSI_ADDRESS_HI      8       /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */
281
#define PCI_MSI_DATA_32         8       /* 16 bits of data for 32-bit devices */
282
#define PCI_MSI_DATA_64         12      /* 16 bits of data for 64-bit devices */
283
 
284
/* CompactPCI Hotswap Register */
285
 
286
#define PCI_CHSWP_CSR           2       /* Control and Status Register */
287
#define  PCI_CHSWP_DHA          0x01    /* Device Hiding Arm */
288
#define  PCI_CHSWP_EIM          0x02    /* ENUM# Signal Mask */
289
#define  PCI_CHSWP_PIE          0x04    /* Pending Insert or Extract */
290
#define  PCI_CHSWP_LOO          0x08    /* LED On / Off */
291
#define  PCI_CHSWP_PI           0x30    /* Programming Interface */
292
#define  PCI_CHSWP_EXT          0x40    /* ENUM# status - extraction */
293
#define  PCI_CHSWP_INS          0x80    /* ENUM# status - insertion */
294
 
295
/* PCI-X registers */
296
 
297
#define PCI_X_CMD               2       /* Modes & Features */
298
#define  PCI_X_CMD_DPERR_E      0x0001  /* Data Parity Error Recovery Enable */
299
#define  PCI_X_CMD_ERO          0x0002  /* Enable Relaxed Ordering */
300
#define  PCI_X_CMD_MAX_READ     0x000c  /* Max Memory Read Byte Count */
301
#define  PCI_X_CMD_MAX_SPLIT    0x0070  /* Max Outstanding Split Transactions */
302
#define PCI_X_DEVFN             4       /* A copy of devfn. */
303
#define PCI_X_BUSNR             5       /* Bus segment number */
304
#define PCI_X_STATUS            6       /* PCI-X capabilities */
305
#define  PCI_X_STATUS_64BIT     0x0001  /* 64-bit device */
306
#define  PCI_X_STATUS_133MHZ    0x0002  /* 133 MHz capable */
307
#define  PCI_X_STATUS_SPL_DISC  0x0004  /* Split Completion Discarded */
308
#define  PCI_X_STATUS_UNX_SPL   0x0008  /* Unexpected Split Completion */
309
#define  PCI_X_STATUS_COMPLEX   0x0010  /* Device Complexity */
310
#define  PCI_X_STATUS_MAX_READ  0x0060  /* Designed Maximum Memory Read Count */
311
#define  PCI_X_STATUS_MAX_SPLIT 0x0380  /* Design Max Outstanding Split Trans */
312
#define  PCI_X_STATUS_MAX_CUM   0x1c00  /* Designed Max Cumulative Read Size */
313
#define  PCI_X_STATUS_SPL_ERR   0x2000  /* Rcvd Split Completion Error Msg */
314
 
315
/* Include the ID list */
316
 
317
#include <linux/pci_ids.h>
318
 
319
/*
320
 * The PCI interface treats multi-function devices as independent
321
 * devices.  The slot/function address of each device is encoded
322
 * in a single byte as follows:
323
 *
324
 *      7:3 = slot
325
 *      2:0 = function
326
 */
327
#define PCI_DEVFN(slot,func)    ((((slot) & 0x1f) << 3) | ((func) & 0x07))
328
#define PCI_SLOT(devfn)         (((devfn) >> 3) & 0x1f)
329
#define PCI_FUNC(devfn)         ((devfn) & 0x07)
330
 
331
/* Ioctls for /proc/bus/pci/X/Y nodes. */
332
#define PCIIOC_BASE             ('P' << 24 | 'C' << 16 | 'I' << 8)
333
#define PCIIOC_CONTROLLER       (PCIIOC_BASE | 0x00)    /* Get controller for PCI device. */
334
#define PCIIOC_MMAP_IS_IO       (PCIIOC_BASE | 0x01)    /* Set mmap state to I/O space. */
335
#define PCIIOC_MMAP_IS_MEM      (PCIIOC_BASE | 0x02)    /* Set mmap state to MEM space. */
336
#define PCIIOC_WRITE_COMBINE    (PCIIOC_BASE | 0x03)    /* Enable/disable write-combining. */
337
 
338
#ifdef __KERNEL__
339
 
340
#include <linux/types.h>
341
#include <linux/config.h>
342
#include <linux/ioport.h>
343
#include <linux/list.h>
344
#include <linux/errno.h>
345
#include <linux/device.h>
346
 
347
/* File state for mmap()s on /proc/bus/pci/X/Y */
348
enum pci_mmap_state {
349
        pci_mmap_io,
350
        pci_mmap_mem
351
};
352
 
353
/* This defines the direction arg to the DMA mapping routines. */
354
#define PCI_DMA_BIDIRECTIONAL   0
355
#define PCI_DMA_TODEVICE        1
356
#define PCI_DMA_FROMDEVICE      2
357
#define PCI_DMA_NONE            3
358
 
359
#define DEVICE_COUNT_COMPATIBLE 4
360
#define DEVICE_COUNT_IRQ        2
361
#define DEVICE_COUNT_DMA        2
362
#define DEVICE_COUNT_RESOURCE   12
363
 
364
/*
365
 * The pci_dev structure is used to describe PCI devices.
366
 */
367
struct pci_dev {
368
        struct list_head global_list;   /* node in list of all PCI devices */
369
        struct list_head bus_list;      /* node in per-bus list */
370
        struct pci_bus  *bus;           /* bus this device is on */
371
        struct pci_bus  *subordinate;   /* bus this device bridges to */
372
 
373
        void            *sysdata;       /* hook for sys-specific extension */
374
        struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */
375
 
376
        unsigned int    devfn;          /* encoded device & function index */
377
        unsigned short  vendor;
378
        unsigned short  device;
379
        unsigned short  subsystem_vendor;
380
        unsigned short  subsystem_device;
381
        unsigned int    class;          /* 3 bytes: (base,sub,prog-if) */
382
        u8              hdr_type;       /* PCI header type (`multi' flag masked out) */
383
        u8              rom_base_reg;   /* which config register controls the ROM */
384
 
385
        struct pci_driver *driver;      /* which driver has allocated this device */
386
        u64             dma_mask;       /* Mask of the bits of bus address this
387
                                           device implements.  Normally this is
388
                                           0xffffffff.  You only need to change
389
                                           this if your device has broken DMA
390
                                           or supports 64-bit transfers.  */
391
        struct list_head pools;         /* pci_pools tied to this device */
392
 
393
        u64             consistent_dma_mask;/* Like dma_mask, but for
394
                                               pci_alloc_consistent mappings as
395
                                               not all hardware supports
396
                                               64 bit addresses for consistent
397
                                               allocations such descriptors. */
398
        u32             current_state;  /* Current operating state. In ACPI-speak,
399
                                           this is D0-D3, D0 being fully functional,
400
                                           and D3 being off. */
401
 
402
        struct  device  dev;            /* Generic device interface */
403
 
404
        /* device is compatible with these IDs */
405
        unsigned short vendor_compatible[DEVICE_COUNT_COMPATIBLE];
406
        unsigned short device_compatible[DEVICE_COUNT_COMPATIBLE];
407
 
408
        /*
409
         * Instead of touching interrupt line and base address registers
410
         * directly, use the values stored here. They might be different!
411
         */
412
        unsigned int    irq;
413
        struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
414
        struct resource dma_resource[DEVICE_COUNT_DMA];
415
        struct resource irq_resource[DEVICE_COUNT_IRQ];
416
 
417
        char *          slot_name;      /* pointer to dev.bus_id */
418
 
419
        /* These fields are used by common fixups */
420
        unsigned int    transparent:1;  /* Transparent PCI bridge */
421
        unsigned int    multifunction:1;/* Part of multi-function device */
422
#ifdef CONFIG_PCI_NAMES
423
#define PCI_NAME_SIZE   50
424
#define PCI_NAME_HALF   __stringify(20) /* less than half to handle slop */
425
        char            pretty_name[PCI_NAME_SIZE];     /* pretty name for users to see */
426
#endif
427
};
428
 
429
#define pci_dev_g(n) list_entry(n, struct pci_dev, global_list)
430
#define pci_dev_b(n) list_entry(n, struct pci_dev, bus_list)
431
#define to_pci_dev(n) container_of(n, struct pci_dev, dev)
432
 
433
/*
434
 *  For PCI devices, the region numbers are assigned this way:
435
 *
436
 *      0-5     standard PCI regions
437
 *      6       expansion ROM
438
 *      7-10    bridges: address space assigned to buses behind the bridge
439
 */
440
 
441
#define PCI_ROM_RESOURCE 6
442
#define PCI_BRIDGE_RESOURCES 7
443
#define PCI_NUM_RESOURCES 11
444
 
445
#ifndef PCI_BUS_NUM_RESOURCES
446
#define PCI_BUS_NUM_RESOURCES 4
447
#endif
448
 
449
#define PCI_REGION_FLAG_MASK 0x0fU      /* These bits of resource flags tell us the PCI region flags */
450
 
451
struct pci_bus {
452
        struct list_head node;          /* node in list of buses */
453
        struct pci_bus  *parent;        /* parent bus this bridge is on */
454
        struct list_head children;      /* list of child buses */
455
        struct list_head devices;       /* list of devices on this bus */
456
        struct pci_dev  *self;          /* bridge device as seen by parent */
457
        struct resource *resource[PCI_BUS_NUM_RESOURCES];
458
                                        /* address space routed to this bus */
459
 
460
        struct pci_ops  *ops;           /* configuration access functions */
461
        void            *sysdata;       /* hook for sys-specific extension */
462
        struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */
463
 
464
        unsigned char   number;         /* bus number */
465
        unsigned char   primary;        /* number of primary bridge */
466
        unsigned char   secondary;      /* number of secondary bridge */
467
        unsigned char   subordinate;    /* max number of subordinate buses */
468
 
469
        char            name[48];
470
 
471
        struct  device  * dev;
472
};
473
 
474
#define pci_bus_b(n) list_entry(n, struct pci_bus, node)
475
 
476
/*
477
 * Error values that may be returned by PCI functions.
478
 */
479
#define PCIBIOS_SUCCESSFUL              0x00
480
#define PCIBIOS_FUNC_NOT_SUPPORTED      0x81
481
#define PCIBIOS_BAD_VENDOR_ID           0x83
482
#define PCIBIOS_DEVICE_NOT_FOUND        0x86
483
#define PCIBIOS_BAD_REGISTER_NUMBER     0x87
484
#define PCIBIOS_SET_FAILED              0x88
485
#define PCIBIOS_BUFFER_TOO_SMALL        0x89
486
 
487
/* Low-level architecture-dependent routines */
488
 
489
struct pci_ops {
490
        int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
491
        int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
492
};
493
 
494
struct pci_raw_ops {
495
        int (*read)(int dom, int bus, int devfn, int reg, int len, u32 *val);
496
        int (*write)(int dom, int bus, int devfn, int reg, int len, u32 val);
497
};
498
 
499
extern struct pci_raw_ops *raw_pci_ops;
500
 
501
struct pci_bus_region {
502
        unsigned long start;
503
        unsigned long end;
504
};
505
 
506
struct pci_dynids {
507
        spinlock_t lock;            /* protects list, index */
508
        struct list_head list;      /* for IDs added at runtime */
509
        unsigned int use_driver_data:1; /* pci_driver->driver_data is used */
510
};
511
 
512
struct pci_driver {
513
        struct list_head node;
514
        char *name;
515
        const struct pci_device_id *id_table;   /* must be non-NULL for probe to be called */
516
        int  (*probe)  (struct pci_dev *dev, const struct pci_device_id *id);   /* New device inserted */
517
        void (*remove) (struct pci_dev *dev);   /* Device removed (NULL if not a hot-plug capable driver) */
518
        int  (*suspend) (struct pci_dev *dev, u32 state);       /* Device suspended */
519
        int  (*resume) (struct pci_dev *dev);                   /* Device woken up */
520
        int  (*enable_wake) (struct pci_dev *dev, u32 state, int enable);   /* Enable wake event */
521
 
522
        struct device_driver    driver;
523
        struct pci_dynids dynids;
524
};
525
 
526
#define to_pci_driver(drv) container_of(drv,struct pci_driver, driver)
527
 
528
/**
529
 * PCI_DEVICE - macro used to describe a specific pci device
530
 * @vend: the 16 bit PCI Vendor ID
531
 * @dev: the 16 bit PCI Device ID
532
 *
533
 * This macro is used to create a struct pci_device_id that matches a
534
 * specific device.  The subvendor and subdevice fields will be set to
535
 * PCI_ANY_ID.
536
 */
537
#define PCI_DEVICE(vend,dev) \
538
        .vendor = (vend), .device = (dev), \
539
        .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
540
 
541
/**
542
 * PCI_DEVICE_CLASS - macro used to describe a specific pci device class
543
 * @dev_class: the class, subclass, prog-if triple for this device
544
 * @dev_class_mask: the class mask for this device
545
 *
546
 * This macro is used to create a struct pci_device_id that matches a
547
 * specific PCI class.  The vendor, device, subvendor, and subdevice
548
 * fields will be set to PCI_ANY_ID.
549
 */
550
#define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
551
        .class = (dev_class), .class_mask = (dev_class_mask), \
552
        .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
553
        .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
554
 
555
/* these external functions are only available when PCI support is enabled */
556
#ifdef CONFIG_PCI
557
 
558
extern struct bus_type pci_bus_type;
559
 
560
/* Do NOT directly access these two variables, unless you are arch specific pci
561
 * code, or pci core code. */
562
extern struct list_head pci_root_buses; /* list of all known PCI buses */
563
extern struct list_head pci_devices;    /* list of all devices */
564
 
565
void pcibios_fixup_bus(struct pci_bus *);
566
int pcibios_enable_device(struct pci_dev *, int mask);
567
char *pcibios_setup (char *str);
568
 
569
/* Used only when drivers/pci/setup.c is used */
570
void pcibios_align_resource(void *, struct resource *,
571
                            unsigned long, unsigned long);
572
void pcibios_update_irq(struct pci_dev *, int irq);
573
 
574
/* Generic PCI functions used internally */
575
 
576
extern struct pci_bus *pci_find_bus(int domain, int busnr);
577
struct pci_bus *pci_scan_bus_parented(struct device *parent, int bus, struct pci_ops *ops, void *sysdata);
578
static inline struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata)
579
{
580
        return pci_scan_bus_parented(NULL, bus, ops, sysdata);
581
}
582
int pci_scan_slot(struct pci_bus *bus, int devfn);
583
void pci_bus_add_devices(struct pci_bus *bus);
584
void pci_name_device(struct pci_dev *dev);
585
char *pci_class_name(u32 class);
586
void pci_read_bridge_bases(struct pci_bus *child);
587
struct resource *pci_find_parent_resource(const struct pci_dev *dev, struct resource *res);
588
int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
589
extern struct pci_dev *pci_dev_get(struct pci_dev *dev);
590
extern void pci_dev_put(struct pci_dev *dev);
591
 
592
extern void pci_remove_bus_device(struct pci_dev *dev);
593
 
594
/* Generic PCI functions exported to card drivers */
595
 
596
struct pci_dev *pci_find_device (unsigned int vendor, unsigned int device, const struct pci_dev *from);
597
struct pci_dev *pci_find_device_reverse (unsigned int vendor, unsigned int device, const struct pci_dev *from);
598
struct pci_dev *pci_find_subsys (unsigned int vendor, unsigned int device,
599
                                 unsigned int ss_vendor, unsigned int ss_device,
600
                                 const struct pci_dev *from);
601
struct pci_dev *pci_find_class (unsigned int class, const struct pci_dev *from);
602
struct pci_dev *pci_find_slot (unsigned int bus, unsigned int devfn);
603
int pci_find_capability (struct pci_dev *dev, int cap);
604
struct pci_bus * pci_find_next_bus(const struct pci_bus *from);
605
 
606
struct pci_dev *pci_get_device (unsigned int vendor, unsigned int device, struct pci_dev *from);
607
struct pci_dev *pci_get_subsys (unsigned int vendor, unsigned int device,
608
                                unsigned int ss_vendor, unsigned int ss_device,
609
                                struct pci_dev *from);
610
int pci_bus_read_config_byte (struct pci_bus *bus, unsigned int devfn, int where, u8 *val);
611
int pci_bus_read_config_word (struct pci_bus *bus, unsigned int devfn, int where, u16 *val);
612
int pci_bus_read_config_dword (struct pci_bus *bus, unsigned int devfn, int where, u32 *val);
613
int pci_bus_write_config_byte (struct pci_bus *bus, unsigned int devfn, int where, u8 val);
614
int pci_bus_write_config_word (struct pci_bus *bus, unsigned int devfn, int where, u16 val);
615
int pci_bus_write_config_dword (struct pci_bus *bus, unsigned int devfn, int where, u32 val);
616
 
617
static inline int pci_read_config_byte(struct pci_dev *dev, int where, u8 *val)
618
{
619
        return pci_bus_read_config_byte (dev->bus, dev->devfn, where, val);
620
}
621
static inline int pci_read_config_word(struct pci_dev *dev, int where, u16 *val)
622
{
623
        return pci_bus_read_config_word (dev->bus, dev->devfn, where, val);
624
}
625
static inline int pci_read_config_dword(struct pci_dev *dev, int where, u32 *val)
626
{
627
        return pci_bus_read_config_dword (dev->bus, dev->devfn, where, val);
628
}
629
static inline int pci_write_config_byte(struct pci_dev *dev, int where, u8 val)
630
{
631
        return pci_bus_write_config_byte (dev->bus, dev->devfn, where, val);
632
}
633
static inline int pci_write_config_word(struct pci_dev *dev, int where, u16 val)
634
{
635
        return pci_bus_write_config_word (dev->bus, dev->devfn, where, val);
636
}
637
static inline int pci_write_config_dword(struct pci_dev *dev, int where, u32 val)
638
{
639
        return pci_bus_write_config_dword (dev->bus, dev->devfn, where, val);
640
}
641
 
642
int pci_enable_device(struct pci_dev *dev);
643
int pci_enable_device_bars(struct pci_dev *dev, int mask);
644
void pci_disable_device(struct pci_dev *dev);
645
void pci_set_master(struct pci_dev *dev);
646
#define HAVE_PCI_SET_MWI
647
int pci_set_mwi(struct pci_dev *dev);
648
void pci_clear_mwi(struct pci_dev *dev);
649
int pci_set_dma_mask(struct pci_dev *dev, u64 mask);
650
int pci_dac_set_dma_mask(struct pci_dev *dev, u64 mask);
651
int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask);
652
int pci_assign_resource(struct pci_dev *dev, int i);
653
 
654
/* Power management related routines */
655
int pci_save_state(struct pci_dev *dev, u32 *buffer);
656
int pci_restore_state(struct pci_dev *dev, u32 *buffer);
657
int pci_set_power_state(struct pci_dev *dev, int state);
658
int pci_enable_wake(struct pci_dev *dev, u32 state, int enable);
659
 
660
/* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
661
void pci_bus_assign_resources(struct pci_bus *bus);
662
void pci_bus_size_bridges(struct pci_bus *bus);
663
int pci_claim_resource(struct pci_dev *, int);
664
void pci_assign_unassigned_resources(void);
665
void pdev_enable_device(struct pci_dev *);
666
void pdev_sort_resources(struct pci_dev *, struct resource_list *);
667
void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *),
668
                    int (*)(struct pci_dev *, u8, u8));
669
#define HAVE_PCI_REQ_REGIONS    2
670
int pci_request_regions(struct pci_dev *, char *);
671
void pci_release_regions(struct pci_dev *);
672
int pci_request_region(struct pci_dev *, int, char *);
673
void pci_release_region(struct pci_dev *, int);
674
 
675
/* drivers/pci/bus.c */
676
void pci_enable_bridges(struct pci_bus *bus);
677
 
678
/* New-style probing supporting hot-pluggable devices */
679
int pci_register_driver(struct pci_driver *);
680
void pci_unregister_driver(struct pci_driver *);
681
void pci_remove_behind_bridge(struct pci_dev *);
682
struct pci_driver *pci_dev_driver(const struct pci_dev *);
683
const struct pci_device_id *pci_match_device(const struct pci_device_id *ids, const struct pci_dev *dev);
684
int pci_scan_bridge(struct pci_bus *bus, struct pci_dev * dev, int max, int pass);
685
 
686
/* kmem_cache style wrapper around pci_alloc_consistent() */
687
struct pci_pool *pci_pool_create (const char *name, struct pci_dev *dev,
688
                size_t size, size_t align, size_t allocation);
689
void pci_pool_destroy (struct pci_pool *pool);
690
 
691
void *pci_pool_alloc (struct pci_pool *pool, int flags, dma_addr_t *handle);
692
void pci_pool_free (struct pci_pool *pool, void *vaddr, dma_addr_t addr);
693
 
1047 mauro 694
void *pci_pool_alloc_usb (struct pci_pool *pool, int flags, dma_addr_t *handle);
695
 
422 giacomo 696
#if defined(CONFIG_ISA) || defined(CONFIG_EISA)
697
extern struct pci_dev *isa_bridge;
698
#endif
699
 
700
#endif /* CONFIG_PCI */
701
 
702
/* Include architecture-dependent settings and functions */
703
 
704
#include <asm/pci.h>
705
 
706
/*
707
 *  If the system does not have PCI, clearly these return errors.  Define
708
 *  these as simple inline functions to avoid hair in drivers.
709
 */
710
 
711
#ifndef CONFIG_PCI
712
#define _PCI_NOP(o,s,t) \
713
        static inline int pci_##o##_config_##s (struct pci_dev *dev, int where, t val) \
714
                { return PCIBIOS_FUNC_NOT_SUPPORTED; }
715
#define _PCI_NOP_ALL(o,x)       _PCI_NOP(o,byte,u8 x) \
716
                                _PCI_NOP(o,word,u16 x) \
717
                                _PCI_NOP(o,dword,u32 x)
718
_PCI_NOP_ALL(read, *)
719
_PCI_NOP_ALL(write,)
720
 
721
static inline struct pci_dev *pci_find_device(unsigned int vendor, unsigned int device, const struct pci_dev *from)
722
{ return NULL; }
723
 
724
static inline struct pci_dev *pci_find_class(unsigned int class, const struct pci_dev *from)
725
{ return NULL; }
726
 
727
static inline struct pci_dev *pci_find_slot(unsigned int bus, unsigned int devfn)
728
{ return NULL; }
729
 
730
static inline struct pci_dev *pci_find_subsys(unsigned int vendor, unsigned int device,
731
unsigned int ss_vendor, unsigned int ss_device, const struct pci_dev *from)
732
{ return NULL; }
733
 
734
static inline struct pci_dev *pci_get_device (unsigned int vendor, unsigned int device, struct pci_dev *from)
735
{ return NULL; }
736
 
737
static inline struct pci_dev *pci_get_subsys (unsigned int vendor, unsigned int device,
738
unsigned int ss_vendor, unsigned int ss_device, struct pci_dev *from)
739
{ return NULL; }
740
 
741
static inline void pci_set_master(struct pci_dev *dev) { }
742
static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; }
743
static inline void pci_disable_device(struct pci_dev *dev) { }
744
static inline int pci_module_init(struct pci_driver *drv) { return -ENODEV; }
745
static inline int pci_set_dma_mask(struct pci_dev *dev, u64 mask) { return -EIO; }
746
static inline int pci_dac_set_dma_mask(struct pci_dev *dev, u64 mask) { return -EIO; }
747
static inline int pci_assign_resource(struct pci_dev *dev, int i) { return -EBUSY;}
748
static inline int pci_register_driver(struct pci_driver *drv) { return 0;}
749
static inline void pci_unregister_driver(struct pci_driver *drv) { }
750
static inline int pci_find_capability (struct pci_dev *dev, int cap) {return 0; }
751
static inline const struct pci_device_id *pci_match_device(const struct pci_device_id *ids, const struct pci_dev *dev) { return NULL; }
752
 
753
/* Power management related routines */
754
static inline int pci_save_state(struct pci_dev *dev, u32 *buffer) { return 0; }
755
static inline int pci_restore_state(struct pci_dev *dev, u32 *buffer) { return 0; }
756
static inline int pci_set_power_state(struct pci_dev *dev, int state) { return 0; }
757
static inline int pci_enable_wake(struct pci_dev *dev, u32 state, int enable) { return 0; }
758
 
759
#define isa_bridge      ((struct pci_dev *)NULL)
760
 
761
#else
762
 
763
/*
764
 * a helper function which helps ensure correct pci_driver
765
 * setup and cleanup for commonly-encountered hotplug/modular cases
766
 *
767
 * This MUST stay in a header, as it checks for -DMODULE
768
 */
769
static inline int pci_module_init(struct pci_driver *drv)
770
{
771
        int rc = pci_register_driver (drv);
772
 
773
        if (rc > 0)
774
                return 0;
775
 
776
        /* iff CONFIG_HOTPLUG and built into kernel, we should
777
         * leave the driver around for future hotplug events.
778
         * For the module case, a hotplug daemon of some sort
779
         * should load a module in response to an insert event. */
780
#if defined(CONFIG_HOTPLUG) && !defined(MODULE)
781
        if (rc == 0)
782
                return 0;
783
#else
784
        if (rc == 0)
785
                rc = -ENODEV;          
786
#endif
787
 
788
        /* if we get here, we need to clean up pci driver instance
789
         * and return some sort of error */
790
        pci_unregister_driver (drv);
791
 
792
        return rc;
793
}
794
 
795
/*
796
 * PCI domain support.  Sometimes called PCI segment (eg by ACPI),
797
 * a PCI domain is defined to be a set of PCI busses which share
798
 * configuration space.
799
 */
800
#ifndef CONFIG_PCI_DOMAINS
801
static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
802
static inline int pci_name_bus(char *name, struct pci_bus *bus)
803
{
456 giacomo 804
        sprintf26(name, "%02x", bus->number);
422 giacomo 805
        return 0;
806
}
807
#endif
808
 
809
#endif /* !CONFIG_PCI */
810
 
811
/* these helpers provide future and backwards compatibility
812
 * for accessing popular PCI BAR info */
813
#define pci_resource_start(dev,bar)   ((dev)->resource[(bar)].start)
814
#define pci_resource_end(dev,bar)     ((dev)->resource[(bar)].end)
815
#define pci_resource_flags(dev,bar)   ((dev)->resource[(bar)].flags)
816
#define pci_resource_len(dev,bar) \
817
        ((pci_resource_start((dev),(bar)) == 0 &&       \
818
          pci_resource_end((dev),(bar)) ==              \
819
          pci_resource_start((dev),(bar))) ? 0 :        \
820
                                                        \
821
         (pci_resource_end((dev),(bar)) -               \
822
          pci_resource_start((dev),(bar)) + 1))
823
 
824
/* Similar to the helpers above, these manipulate per-pci_dev
825
 * driver-specific data.  They are really just a wrapper around
826
 * the generic device structure functions of these calls.
827
 */
828
static inline void *pci_get_drvdata (struct pci_dev *pdev)
829
{
830
        return dev_get_drvdata(&pdev->dev);
831
}
832
 
833
static inline void pci_set_drvdata (struct pci_dev *pdev, void *data)
834
{
835
        dev_set_drvdata(&pdev->dev, data);
836
}
837
 
838
/* If you want to know what to call your pci_dev, ask this function.
839
 * Again, it's a wrapper around the generic device.
840
 */
841
static inline char *pci_name(struct pci_dev *pdev)
842
{
843
        return pdev->dev.bus_id;
844
}
845
 
846
/* Some archs want to see the pretty pci name, so use this macro */
847
#ifdef CONFIG_PCI_NAMES
848
#define pci_pretty_name(dev) ((dev)->pretty_name)
849
#else
850
#define pci_pretty_name(dev) ""
851
#endif
852
 
853
/*
854
 *  The world is not perfect and supplies us with broken PCI devices.
855
 *  For at least a part of these bugs we need a work-around, so both
856
 *  generic (drivers/pci/quirks.c) and per-architecture code can define
857
 *  fixup hooks to be called for particular buggy devices.
858
 */
859
 
860
struct pci_fixup {
861
        int pass;
862
        u16 vendor, device;                     /* You can use PCI_ANY_ID here of course */
863
        void (*hook)(struct pci_dev *dev);
864
};
865
 
866
extern struct pci_fixup pcibios_fixups[];
867
 
868
#define PCI_FIXUP_HEADER        1               /* Called immediately after reading configuration header */
869
#define PCI_FIXUP_FINAL         2               /* Final phase of device fixups */
870
 
871
void pci_fixup_device(int pass, struct pci_dev *dev);
872
 
873
extern int pci_pci_problems;
874
#define PCIPCI_FAIL             1
875
#define PCIPCI_TRITON           2
876
#define PCIPCI_NATOMA           4
877
#define PCIPCI_VIAETBF          8
878
#define PCIPCI_VSFX             16
879
#define PCIPCI_ALIMAGIK         32
880
 
881
#endif /* __KERNEL__ */
882
#endif /* LINUX_PCI_H */