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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 422 | giacomo | 1 | /***************************************************************************** |
| 2 | * sdlapci.h WANPIPE(tm) Multiprotocol WAN Link Driver. |
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| 3 | * Definitions for the SDLA PCI adapter. |
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| 4 | * |
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| 5 | * Author: Gideon Hack <ghack@sangoma.com> |
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| 6 | * |
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| 7 | * Copyright: (c) 1999-2000 Sangoma Technologies Inc. |
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| 8 | * |
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| 9 | * This program is free software; you can redistribute it and/or |
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| 10 | * modify it under the terms of the GNU General Public License |
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| 11 | * as published by the Free Software Foundation; either version |
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| 12 | * 2 of the License, or (at your option) any later version. |
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| 13 | * ============================================================================ |
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| 14 | * Jun 02, 1999 Gideon Hack Initial version. |
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| 15 | *****************************************************************************/ |
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| 16 | #ifndef _SDLAPCI_H |
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| 17 | #define _SDLAPCI_H |
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| 18 | |||
| 19 | /****** Defines *************************************************************/ |
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| 20 | |||
| 21 | /* Definitions for identifying and finding S514 PCI adapters */ |
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| 22 | #define V3_VENDOR_ID 0x11B0 /* V3 vendor ID number */ |
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| 23 | #define V3_DEVICE_ID 0x0002 /* V3 device ID number */ |
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| 24 | #define SANGOMA_SUBSYS_VENDOR 0x4753 /* ID for Sangoma */ |
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| 25 | #define PCI_DEV_SLOT_MASK 0x1F /* mask for slot numbering */ |
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| 26 | #define PCI_IRQ_NOT_ALLOCATED 0xFF /* interrupt line for no IRQ */ |
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| 27 | |||
| 28 | /* Local PCI register offsets */ |
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| 29 | #define PCI_VENDOR_ID_WORD 0x00 /* vendor ID */ |
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| 30 | #define PCI_IO_BASE_DWORD 0x10 /* IO base */ |
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| 31 | #define PCI_MEM_BASE0_DWORD 0x14 /* memory base - apperture 0 */ |
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| 32 | #define PCI_MEM_BASE1_DWORD 0x18 /* memory base - apperture 1 */ |
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| 33 | #define PCI_SUBSYS_VENDOR_WORD 0x2C /* subsystem vendor ID */ |
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| 34 | #define PCI_INT_LINE_BYTE 0x3C /* interrupt line */ |
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| 35 | #define PCI_INT_PIN_BYTE 0x3D /* interrupt pin */ |
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| 36 | #define PCI_MAP0_DWORD 0x40 /* PCI to local bus address 0 */ |
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| 37 | #define PCI_MAP1_DWORD 0x44 /* PCI to local bus address 1 */ |
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| 38 | #define PCI_INT_STATUS 0x48 /* interrupt status */ |
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| 39 | #define PCI_INT_CONFIG 0x4C /* interrupt configuration */ |
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| 40 | |||
| 41 | /* Local PCI register usage */ |
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| 42 | #define PCI_MEMORY_ENABLE 0x00000003 /* enable PCI memory */ |
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| 43 | #define PCI_CPU_A_MEM_DISABLE 0x00000002 /* disable CPU A memory */ |
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| 44 | #define PCI_CPU_B_MEM_DISABLE 0x00100002 /* disable CPU B memory */ |
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| 45 | #define PCI_ENABLE_IRQ_CPU_A 0x005A0004 /* enable IRQ for CPU A */ |
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| 46 | #define PCI_ENABLE_IRQ_CPU_B 0x005A0008 /* enable IRQ for CPU B */ |
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| 47 | #define PCI_DISABLE_IRQ_CPU_A 0x00000004 /* disable IRQ for CPU A */ |
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| 48 | #define PCI_DISABLE_IRQ_CPU_B 0x00000008 /* disable IRQ for CPU B */ |
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| 49 | |||
| 50 | /* Setting for the Interrupt Status register */ |
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| 51 | #define IRQ_CPU_A 0x04 /* IRQ for CPU A */ |
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| 52 | #define IRQ_CPU_B 0x08 /* IRQ for CPU B */ |
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| 53 | |||
| 54 | /* The maximum size of the S514 memory */ |
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| 55 | #define MAX_SIZEOF_S514_MEMORY (256 * 1024) |
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| 56 | |||
| 57 | /* S514 control register offsets within the memory address space */ |
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| 58 | #define S514_CTRL_REG_BYTE 0x80000 |
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| 59 | |||
| 60 | /* S514 adapter control bytes */ |
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| 61 | #define S514_CPU_HALT 0x00 |
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| 62 | #define S514_CPU_START 0x01 |
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| 63 | |||
| 64 | /* The maximum number of S514 adapters supported */ |
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| 65 | #define MAX_S514_CARDS 20 |
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| 66 | |||
| 67 | #define PCI_CARD_TYPE 0x2E |
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| 68 | #define S514_DUAL_CPU 0x12 |
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| 69 | #define S514_SINGLE_CPU 0x11 |
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| 70 | |||
| 71 | #endif /* _SDLAPCI_H */ |
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| 72 |