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2 pj 1
/* Generic NS8390 register definitions. */
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/* This file is part of Donald Becker's 8390 drivers, and is distributed
3
   under the same license. Auto-loading of 8390.o added by Paul Gortmaker.
4
   Some of these names and comments originated from the Crynwr
5
   packet drivers, which are distributed under the GPL. */
6
 
7
#ifndef _8390_h
8
#define _8390_h
9
 
10
#include <linux/config.h>
11
#include <linux/if_ether.h>
12
#include <linux/ioport.h>
13
#include <linux/skbuff.h>
80 pj 14
#include "ll/sys/cdefs.h"
2 pj 15
 
80 pj 16
__BEGIN_DECLS
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/* With kmod, drivers can now load the 8390 module themselves! */
19
#if 0 /* def CONFIG_KMOD */
20
#define LOAD_8390_BY_KMOD
21
#endif
22
 
23
#define TX_2X_PAGES 12
24
#define TX_1X_PAGES 6
25
 
26
/* Should always use two Tx slots to get back-to-back transmits. */
27
#define EI_PINGPONG
28
 
29
#ifdef EI_PINGPONG
30
#define TX_PAGES TX_2X_PAGES
31
#else
32
#define TX_PAGES TX_1X_PAGES
33
#endif
34
 
35
#define ETHER_ADDR_LEN 6
36
 
37
/* The 8390 specific per-packet-header format. */
38
struct e8390_pkt_hdr {
39
  unsigned char status; /* status */
40
  unsigned char next;   /* pointer to next packet. */
41
  unsigned short count; /* header + packet length in bytes */
42
};
43
 
44
#ifdef notdef
45
extern int ei_debug;
46
#else
47
#define ei_debug 1
48
#endif
49
 
50
#ifndef HAVE_AUTOIRQ
51
/* From auto_irq.c */
52
extern void autoirq_setup(int waittime);
53
extern unsigned long autoirq_report(int waittime);
54
#endif
55
 
56
#if defined(LOAD_8390_BY_KMOD) && defined(MODULE) && !defined(NS8390_CORE)
57
 
58
/* Function pointers to be mapped onto the 8390 core support */
59
static int (*S_ethdev_init)(struct device *dev);
60
static void (*S_NS8390_init)(struct device *dev, int startp);
61
static int (*S_ei_open)(struct device *dev);
62
static int (*S_ei_close)(struct device *dev);
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static void (*S_ei_interrupt)(int irq, void *dev_id, struct pt_regs *regs);
64
 
65
 
66
#define NS8390_KSYSMS_PRESENT   (                       \
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        get_module_symbol(NULL, "ethdev_init") != 0 &&  \
68
        get_module_symbol(NULL, "NS8390_init") != 0 &&  \
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        get_module_symbol(NULL, "ei_open") != 0 &&      \
70
        get_module_symbol(NULL, "ei_close") != 0 &&     \
71
        get_module_symbol(NULL, "ei_interrupt") != 0)
72
 
73
extern __inline__ int load_8390_module(const char *driver)
74
{
75
 
76
        if (! NS8390_KSYSMS_PRESENT) {
77
                int (*request_mod)(const char *module_name);
78
 
79
                if (get_module_symbol("", "request_module") == 0) {
80
                        printk("%s: module auto-load (kmod) support not present.\n", driver);
81
                        printk("%s: unable to auto-load required 8390 module.\n", driver);
82
                        printk("%s: try \"modprobe 8390\" as root 1st.\n", driver);
83
                        return -ENOSYS;
84
                }
85
 
86
                request_mod = (void*)get_module_symbol("", "request_module");
87
                if (request_mod("8390")) {
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                        printk("%s: request to load the 8390 module failed.\n", driver);
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                        return -ENOSYS;
90
                }
91
 
92
                /* Check if module really loaded and is valid */
93
                if (! NS8390_KSYSMS_PRESENT) {
94
                        printk("%s: 8390.o not found/invalid or failed to load.\n", driver);
95
                        return -ENOSYS;
96
                }
97
 
98
                printk(KERN_INFO "%s: auto-loaded 8390 module.\n", driver);
99
        }
100
 
101
        /* Map the functions into place */
102
        S_ethdev_init = (void*)get_module_symbol(0, "ethdev_init");
103
        S_NS8390_init = (void*)get_module_symbol(0, "NS8390_init");
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        S_ei_open = (void*)get_module_symbol(0, "ei_open");
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        S_ei_close = (void*)get_module_symbol(0, "ei_close");
106
        S_ei_interrupt = (void*)get_module_symbol(0, "ei_interrupt");
107
 
108
        return 0;
109
}
110
 
111
/*
112
 * Since a kmod aware driver won't explicitly show a dependence on the
113
 * exported 8390 functions (due to the mapping above), the 8390 module
114
 * (if present, and not in-kernel) needs to be protected from garbage
115
 * collection.  NS8390_module is only defined for a modular 8390 core.
116
 */
117
 
118
extern __inline__  void lock_8390_module(void)
119
{
120
        struct module **mod = (struct module**)get_module_symbol(0, "NS8390_module");
121
 
122
        if (mod != NULL && *mod != NULL)
123
                __MOD_INC_USE_COUNT(*mod);
124
}
125
 
126
extern __inline__  void unlock_8390_module(void)
127
{
128
        struct module **mod = (struct module**)get_module_symbol(0, "NS8390_module");
129
 
130
        if (mod != NULL && *mod != NULL)
131
                __MOD_DEC_USE_COUNT(*mod);
132
}
133
 
134
/*
135
 * These are last so they only have scope over the driver
136
 * code (wd, ne, 3c503, etc.)  and not over the above code.
137
 */
138
#define ethdev_init S_ethdev_init
139
#define NS8390_init S_NS8390_init
140
#define ei_open S_ei_open
141
#define ei_close S_ei_close
142
#define ei_interrupt S_ei_interrupt
143
 
144
#else   /* not a module or kmod support not wanted */
145
 
146
#define load_8390_module(driver)        0
147
#define lock_8390_module()              do { } while (0)
148
#define unlock_8390_module()            do { } while (0)
149
extern int ethdev_init(struct device *dev);
150
extern void NS8390_init(struct device *dev, int startp);
151
extern int ei_open(struct device *dev);
152
extern int ei_close(struct device *dev);
153
extern void ei_interrupt(int irq, void *dev_id, struct pt_regs *regs);
154
 
155
#endif
156
 
157
/* Most of these entries should be in 'struct device' (or most of the
158
   things in there should be here!) */
159
/* You have one of these per-board */
160
struct ei_device {
161
        const char *name;
162
        void (*reset_8390)(struct device *);
163
        void (*get_8390_hdr)(struct device *, struct e8390_pkt_hdr *, int);
164
        void (*block_output)(struct device *, int, const unsigned char *, int);
165
        void (*block_input)(struct device *, int, struct sk_buff *, int);
166
        unsigned char mcfilter[8];
167
        unsigned open:1;
168
        unsigned word16:1;              /* We have the 16-bit (vs 8-bit) version of the card. */
169
        unsigned txing:1;               /* Transmit Active */
170
        unsigned irqlock:1;             /* 8390's intrs disabled when '1'. */
171
        unsigned dmaing:1;              /* Remote DMA Active */
172
        unsigned char tx_start_page, rx_start_page, stop_page;
173
        unsigned char current_page;     /* Read pointer in buffer  */
174
        unsigned char interface_num;    /* Net port (AUI, 10bT.) to use. */
175
        unsigned char txqueue;          /* Tx Packet buffer queue length. */
176
        short tx1, tx2;                 /* Packet lengths for ping-pong tx. */
177
        short lasttx;                   /* Alpha version consistency check. */
178
        unsigned char reg0;             /* Register '0' in a WD8013 */
179
        unsigned char reg5;             /* Register '5' in a WD8013 */
180
        unsigned char saved_irq;        /* Original dev->irq value. */
181
        struct net_device_stats stat;   /* The new statistics table. */
182
        u32 *reg_offset;                /* Register mapping table */
183
        spinlock_t page_lock;           /* Page register locks */
184
        unsigned long priv;             /* Private field to store bus IDs etc. */
185
};
186
 
187
/* The maximum number of 8390 interrupt service routines called per IRQ. */
188
#define MAX_SERVICE 12
189
 
190
/* The maximum time waited (in jiffies) before assuming a Tx failed. (20ms) */
191
#define TX_TIMEOUT (20*HZ/100)
192
 
193
#define ei_status (*(struct ei_device *)(dev->priv))
194
 
195
/* Some generic ethernet register configurations. */
196
#define E8390_TX_IRQ_MASK       0xa     /* For register EN0_ISR */
197
#define E8390_RX_IRQ_MASK       0x5
198
#define E8390_RXCONFIG          0x4     /* EN0_RXCR: broadcasts, no multicast,errors */
199
#define E8390_RXOFF             0x20    /* EN0_RXCR: Accept no packets */
200
#define E8390_TXCONFIG          0x00    /* EN0_TXCR: Normal transmit mode */
201
#define E8390_TXOFF             0x02    /* EN0_TXCR: Transmitter off */
202
 
203
/*  Register accessed at EN_CMD, the 8390 base addr.  */
204
#define E8390_STOP      0x01    /* Stop and reset the chip */
205
#define E8390_START     0x02    /* Start the chip, clear reset */
206
#define E8390_TRANS     0x04    /* Transmit a frame */
207
#define E8390_RREAD     0x08    /* Remote read */
208
#define E8390_RWRITE    0x10    /* Remote write  */
209
#define E8390_NODMA     0x20    /* Remote DMA */
210
#define E8390_PAGE0     0x00    /* Select page chip registers */
211
#define E8390_PAGE1     0x40    /* using the two high-order bits */
212
#define E8390_PAGE2     0x80    /* Page 3 is invalid. */
213
 
214
/*
215
 *      Only generate indirect loads given a machine that needs them.
216
 */
217
 
218
#if defined(CONFIG_MAC) || defined(CONFIG_AMIGA_PCMCIA) || \
219
    defined(CONFIG_ARIADNE2) || defined(CONFIG_ARIADNE2_MODULE)
220
#define EI_SHIFT(x)     (ei_local->reg_offset[x])
221
#else
222
#define EI_SHIFT(x)     (x)
223
#endif
224
 
225
#define E8390_CMD       EI_SHIFT(0x00)  /* The command register (for all pages) */
226
/* Page 0 register offsets. */
227
#define EN0_CLDALO      EI_SHIFT(0x01)  /* Low byte of current local dma addr  RD */
228
#define EN0_STARTPG     EI_SHIFT(0x01)  /* Starting page of ring bfr WR */
229
#define EN0_CLDAHI      EI_SHIFT(0x02)  /* High byte of current local dma addr  RD */
230
#define EN0_STOPPG      EI_SHIFT(0x02)  /* Ending page +1 of ring bfr WR */
231
#define EN0_BOUNDARY    EI_SHIFT(0x03)  /* Boundary page of ring bfr RD WR */
232
#define EN0_TSR         EI_SHIFT(0x04)  /* Transmit status reg RD */
233
#define EN0_TPSR        EI_SHIFT(0x04)  /* Transmit starting page WR */
234
#define EN0_NCR         EI_SHIFT(0x05)  /* Number of collision reg RD */
235
#define EN0_TCNTLO      EI_SHIFT(0x05)  /* Low  byte of tx byte count WR */
236
#define EN0_FIFO        EI_SHIFT(0x06)  /* FIFO RD */
237
#define EN0_TCNTHI      EI_SHIFT(0x06)  /* High byte of tx byte count WR */
238
#define EN0_ISR         EI_SHIFT(0x07)  /* Interrupt status reg RD WR */
239
#define EN0_CRDALO      EI_SHIFT(0x08)  /* low byte of current remote dma address RD */
240
#define EN0_RSARLO      EI_SHIFT(0x08)  /* Remote start address reg 0 */
241
#define EN0_CRDAHI      EI_SHIFT(0x09)  /* high byte, current remote dma address RD */
242
#define EN0_RSARHI      EI_SHIFT(0x09)  /* Remote start address reg 1 */
243
#define EN0_RCNTLO      EI_SHIFT(0x0a)  /* Remote byte count reg WR */
244
#define EN0_RCNTHI      EI_SHIFT(0x0b)  /* Remote byte count reg WR */
245
#define EN0_RSR         EI_SHIFT(0x0c)  /* rx status reg RD */
246
#define EN0_RXCR        EI_SHIFT(0x0c)  /* RX configuration reg WR */
247
#define EN0_TXCR        EI_SHIFT(0x0d)  /* TX configuration reg WR */
248
#define EN0_COUNTER0    EI_SHIFT(0x0d)  /* Rcv alignment error counter RD */
249
#define EN0_DCFG        EI_SHIFT(0x0e)  /* Data configuration reg WR */
250
#define EN0_COUNTER1    EI_SHIFT(0x0e)  /* Rcv CRC error counter RD */
251
#define EN0_IMR         EI_SHIFT(0x0f)  /* Interrupt mask reg WR */
252
#define EN0_COUNTER2    EI_SHIFT(0x0f)  /* Rcv missed frame error counter RD */
253
 
254
/* Bits in EN0_ISR - Interrupt status register */
255
#define ENISR_RX        0x01    /* Receiver, no error */
256
#define ENISR_TX        0x02    /* Transmitter, no error */
257
#define ENISR_RX_ERR    0x04    /* Receiver, with error */
258
#define ENISR_TX_ERR    0x08    /* Transmitter, with error */
259
#define ENISR_OVER      0x10    /* Receiver overwrote the ring */
260
#define ENISR_COUNTERS  0x20    /* Counters need emptying */
261
#define ENISR_RDC       0x40    /* remote dma complete */
262
#define ENISR_RESET     0x80    /* Reset completed */
263
#define ENISR_ALL       0x3f    /* Interrupts we will enable */
264
 
265
/* Bits in EN0_DCFG - Data config register */
266
#define ENDCFG_WTS      0x01    /* word transfer mode selection */
267
 
268
/* Page 1 register offsets. */
269
#define EN1_PHYS   EI_SHIFT(0x01)       /* This board's physical enet addr RD WR */
270
#define EN1_PHYS_SHIFT(i)  EI_SHIFT(i+1) /* Get and set mac address */
271
#define EN1_CURPAG EI_SHIFT(0x07)       /* Current memory page RD WR */
272
#define EN1_MULT   EI_SHIFT(0x08)       /* Multicast filter mask array (8 bytes) RD WR */
273
#define EN1_MULT_SHIFT(i)  EI_SHIFT(8+i) /* Get and set multicast filter */
274
 
275
/* Bits in received packet status byte and EN0_RSR*/
276
#define ENRSR_RXOK      0x01    /* Received a good packet */
277
#define ENRSR_CRC       0x02    /* CRC error */
278
#define ENRSR_FAE       0x04    /* frame alignment error */
279
#define ENRSR_FO        0x08    /* FIFO overrun */
280
#define ENRSR_MPA       0x10    /* missed pkt */
281
#define ENRSR_PHY       0x20    /* physical/multicast address */
282
#define ENRSR_DIS       0x40    /* receiver disable. set in monitor mode */
283
#define ENRSR_DEF       0x80    /* deferring */
284
 
285
/* Transmitted packet status, EN0_TSR. */
286
#define ENTSR_PTX 0x01  /* Packet transmitted without error */
287
#define ENTSR_ND  0x02  /* The transmit wasn't deferred. */
288
#define ENTSR_COL 0x04  /* The transmit collided at least once. */
289
#define ENTSR_ABT 0x08  /* The transmit collided 16 times, and was deferred. */
290
#define ENTSR_CRS 0x10  /* The carrier sense was lost. */
291
#define ENTSR_FU  0x20  /* A "FIFO underrun" occurred during transmit. */
292
#define ENTSR_CDH 0x40  /* The collision detect "heartbeat" signal was lost. */
293
#define ENTSR_OWC 0x80  /* There was an out-of-window collision. */
294
 
80 pj 295
__END_DECLS
2 pj 296
#endif /* _8390_h */