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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 436 | giacomo | 1 | /* |
| 2 | * direct.c - Low-level direct PCI config space access |
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| 3 | */ |
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| 4 | |||
| 5 | #include <linuxcomp.h> |
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| 6 | |||
| 7 | #include <linux/pci.h> |
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| 8 | #include <linux/init.h> |
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| 9 | #include "pci2.h" |
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| 10 | |||
| 11 | /* |
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| 12 | * Functions for accessing PCI configuration space with type 1 accesses |
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| 13 | */ |
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| 14 | |||
| 15 | #define PCI_CONF1_ADDRESS(bus, devfn, reg) \ |
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| 16 | (0x80000000 | (bus << 16) | (devfn << 8) | (reg & ~3)) |
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| 17 | |||
| 18 | static int pci_conf1_read (int seg, int bus, int devfn, int reg, int len, u32 *value) |
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| 19 | { |
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| 20 | unsigned long flags; |
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| 21 | |||
| 22 | if (!value || (bus > 255) || (devfn > 255) || (reg > 255)) |
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| 23 | return -EINVAL; |
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| 24 | |||
| 25 | spin_lock_irqsave(&pci_config_lock, flags); |
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| 26 | |||
| 27 | outl(PCI_CONF1_ADDRESS(bus, devfn, reg), 0xCF8); |
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| 28 | |||
| 29 | switch (len) { |
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| 30 | case 1: |
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| 31 | *value = inb(0xCFC + (reg & 3)); |
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| 32 | break; |
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| 33 | case 2: |
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| 34 | *value = inw(0xCFC + (reg & 2)); |
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| 35 | break; |
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| 36 | case 4: |
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| 37 | *value = inl(0xCFC); |
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| 38 | break; |
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| 39 | } |
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| 40 | |||
| 41 | spin_unlock_irqrestore(&pci_config_lock, flags); |
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| 42 | |||
| 43 | return 0; |
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| 44 | } |
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| 45 | |||
| 46 | static int pci_conf1_write (int seg, int bus, int devfn, int reg, int len, u32 value) |
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| 47 | { |
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| 48 | unsigned long flags; |
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| 49 | |||
| 50 | if ((bus > 255) || (devfn > 255) || (reg > 255)) |
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| 51 | return -EINVAL; |
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| 52 | |||
| 53 | spin_lock_irqsave(&pci_config_lock, flags); |
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| 54 | |||
| 55 | outl(PCI_CONF1_ADDRESS(bus, devfn, reg), 0xCF8); |
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| 56 | |||
| 57 | switch (len) { |
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| 58 | case 1: |
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| 59 | outb((u8)value, 0xCFC + (reg & 3)); |
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| 60 | break; |
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| 61 | case 2: |
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| 62 | outw((u16)value, 0xCFC + (reg & 2)); |
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| 63 | break; |
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| 64 | case 4: |
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| 65 | outl((u32)value, 0xCFC); |
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| 66 | break; |
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| 67 | } |
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| 68 | |||
| 69 | spin_unlock_irqrestore(&pci_config_lock, flags); |
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| 70 | |||
| 71 | return 0; |
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| 72 | } |
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| 73 | |||
| 74 | #undef PCI_CONF1_ADDRESS |
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| 75 | |||
| 76 | struct pci_raw_ops pci_direct_conf1 = { |
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| 77 | .read = pci_conf1_read, |
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| 78 | .write = pci_conf1_write, |
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| 79 | }; |
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| 80 | |||
| 81 | |||
| 82 | /* |
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| 83 | * Functions for accessing PCI configuration space with type 2 accesses |
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| 84 | */ |
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| 85 | |||
| 86 | #define PCI_CONF2_ADDRESS(dev, reg) (u16)(0xC000 | (dev << 8) | reg) |
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| 87 | |||
| 88 | static int pci_conf2_read(int seg, int bus, int devfn, int reg, int len, u32 *value) |
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| 89 | { |
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| 90 | unsigned long flags; |
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| 91 | int dev, fn; |
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| 92 | |||
| 93 | if (!value || (bus > 255) || (devfn > 255) || (reg > 255)) |
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| 94 | return -EINVAL; |
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| 95 | |||
| 96 | dev = PCI_SLOT(devfn); |
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| 97 | fn = PCI_FUNC(devfn); |
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| 98 | |||
| 99 | if (dev & 0x10) |
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| 100 | return PCIBIOS_DEVICE_NOT_FOUND; |
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| 101 | |||
| 102 | spin_lock_irqsave(&pci_config_lock, flags); |
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| 103 | |||
| 104 | outb((u8)(0xF0 | (fn << 1)), 0xCF8); |
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| 105 | outb((u8)bus, 0xCFA); |
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| 106 | |||
| 107 | switch (len) { |
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| 108 | case 1: |
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| 109 | *value = inb(PCI_CONF2_ADDRESS(dev, reg)); |
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| 110 | break; |
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| 111 | case 2: |
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| 112 | *value = inw(PCI_CONF2_ADDRESS(dev, reg)); |
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| 113 | break; |
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| 114 | case 4: |
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| 115 | *value = inl(PCI_CONF2_ADDRESS(dev, reg)); |
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| 116 | break; |
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| 117 | } |
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| 118 | |||
| 119 | outb(0, 0xCF8); |
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| 120 | |||
| 121 | spin_unlock_irqrestore(&pci_config_lock, flags); |
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| 122 | |||
| 123 | return 0; |
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| 124 | } |
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| 125 | |||
| 126 | static int pci_conf2_write (int seg, int bus, int devfn, int reg, int len, u32 value) |
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| 127 | { |
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| 128 | unsigned long flags; |
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| 129 | int dev, fn; |
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| 130 | |||
| 131 | if ((bus > 255) || (devfn > 255) || (reg > 255)) |
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| 132 | return -EINVAL; |
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| 133 | |||
| 134 | dev = PCI_SLOT(devfn); |
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| 135 | fn = PCI_FUNC(devfn); |
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| 136 | |||
| 137 | if (dev & 0x10) |
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| 138 | return PCIBIOS_DEVICE_NOT_FOUND; |
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| 139 | |||
| 140 | spin_lock_irqsave(&pci_config_lock, flags); |
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| 141 | |||
| 142 | outb((u8)(0xF0 | (fn << 1)), 0xCF8); |
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| 143 | outb((u8)bus, 0xCFA); |
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| 144 | |||
| 145 | switch (len) { |
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| 146 | case 1: |
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| 147 | outb((u8)value, PCI_CONF2_ADDRESS(dev, reg)); |
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| 148 | break; |
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| 149 | case 2: |
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| 150 | outw((u16)value, PCI_CONF2_ADDRESS(dev, reg)); |
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| 151 | break; |
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| 152 | case 4: |
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| 153 | outl((u32)value, PCI_CONF2_ADDRESS(dev, reg)); |
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| 154 | break; |
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| 155 | } |
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| 156 | |||
| 157 | outb(0, 0xCF8); |
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| 158 | |||
| 159 | spin_unlock_irqrestore(&pci_config_lock, flags); |
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| 160 | |||
| 161 | return 0; |
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| 162 | } |
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| 163 | |||
| 164 | #undef PCI_CONF2_ADDRESS |
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| 165 | |||
| 166 | static struct pci_raw_ops pci_direct_conf2 = { |
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| 167 | .read = pci_conf2_read, |
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| 168 | .write = pci_conf2_write, |
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| 169 | }; |
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| 170 | |||
| 171 | |||
| 172 | /* |
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| 173 | * Before we decide to use direct hardware access mechanisms, we try to do some |
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| 174 | * trivial checks to ensure it at least _seems_ to be working -- we just test |
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| 175 | * whether bus 00 contains a host bridge (this is similar to checking |
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| 176 | * techniques used in XFree86, but ours should be more reliable since we |
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| 177 | * attempt to make use of direct access hints provided by the PCI BIOS). |
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| 178 | * |
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| 179 | * This should be close to trivial, but it isn't, because there are buggy |
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| 180 | * chipsets (yes, you guessed it, by Intel and Compaq) that have no class ID. |
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| 181 | */ |
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| 182 | static int __init pci_sanity_check(struct pci_raw_ops *o) |
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| 183 | { |
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| 184 | u32 x = 0; |
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| 185 | int devfn; |
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| 186 | |||
| 187 | if (pci_probe & PCI_NO_CHECKS) |
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| 188 | return 1; |
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| 189 | |||
| 190 | for (devfn = 0; devfn < 0x100; devfn++) { |
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| 191 | if (o->read(0, 0, devfn, PCI_CLASS_DEVICE, 2, &x)) |
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| 192 | continue; |
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| 193 | if (x == PCI_CLASS_BRIDGE_HOST || x == PCI_CLASS_DISPLAY_VGA) |
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| 194 | return 1; |
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| 195 | |||
| 196 | if (o->read(0, 0, devfn, PCI_VENDOR_ID, 2, &x)) |
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| 197 | continue; |
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| 198 | if (x == PCI_VENDOR_ID_INTEL || x == PCI_VENDOR_ID_COMPAQ) |
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| 199 | return 1; |
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| 200 | } |
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| 201 | |||
| 202 | DBG("PCI: Sanity check failed\n"); |
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| 203 | return 0; |
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| 204 | } |
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| 205 | |||
| 206 | static int __init pci_check_type1(void) |
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| 207 | { |
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| 208 | unsigned long flags; |
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| 209 | unsigned int tmp; |
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| 210 | int works = 0; |
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| 211 | |||
| 212 | local_irq_save(flags); |
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| 213 | |||
| 214 | outb(0x01, 0xCFB); |
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| 215 | tmp = inl(0xCF8); |
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| 216 | outl(0x80000000, 0xCF8); |
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| 217 | if (inl(0xCF8) == 0x80000000 && pci_sanity_check(&pci_direct_conf1)) { |
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| 218 | works = 1; |
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| 219 | } |
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| 220 | outl(tmp, 0xCF8); |
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| 221 | local_irq_restore(flags); |
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| 222 | |||
| 223 | return works; |
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| 224 | } |
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| 225 | |||
| 226 | static int __init pci_check_type2(void) |
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| 227 | { |
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| 228 | unsigned long flags; |
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| 229 | int works = 0; |
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| 230 | |||
| 231 | local_irq_save(flags); |
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| 232 | |||
| 233 | outb(0x00, 0xCFB); |
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| 234 | outb(0x00, 0xCF8); |
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| 235 | outb(0x00, 0xCFA); |
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| 236 | if (inb(0xCF8) == 0x00 && inb(0xCFA) == 0x00 && |
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| 237 | pci_sanity_check(&pci_direct_conf2)) { |
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| 238 | works = 1; |
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| 239 | } |
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| 240 | |||
| 241 | local_irq_restore(flags); |
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| 242 | |||
| 243 | return works; |
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| 244 | } |
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| 245 | |||
| 440 | giacomo | 246 | int __init pci_direct_init(void) |
| 436 | giacomo | 247 | { |
| 248 | struct resource *region, *region2; |
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| 249 | |||
| 250 | if ((pci_probe & PCI_PROBE_CONF1) == 0) |
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| 251 | goto type2; |
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| 252 | region = request_region(0xCF8, 8, "PCI conf1"); |
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| 253 | if (!region) |
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| 254 | goto type2; |
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| 255 | |||
| 256 | if (pci_check_type1()) { |
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| 257 | printk(KERN_INFO "PCI: Using configuration type 1\n"); |
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| 258 | raw_pci_ops = &pci_direct_conf1; |
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| 259 | return 0; |
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| 260 | } |
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| 261 | release_resource(region); |
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| 262 | |||
| 263 | type2: |
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| 264 | if ((!pci_probe & PCI_PROBE_CONF2) == 0) |
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| 265 | goto out; |
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| 266 | region = request_region(0xCF8, 4, "PCI conf2"); |
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| 267 | if (!region) |
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| 268 | goto out; |
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| 269 | region2 = request_region(0xC000, 0x1000, "PCI conf2"); |
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| 270 | if (!region2) |
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| 271 | goto fail2; |
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| 272 | |||
| 273 | if (pci_check_type2()) { |
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| 274 | printk(KERN_INFO "PCI: Using configuration type 2\n"); |
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| 275 | raw_pci_ops = &pci_direct_conf2; |
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| 276 | return 0; |
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| 277 | } |
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| 278 | |||
| 279 | release_resource(region2); |
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| 280 | fail2: |
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| 281 | release_resource(region); |
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| 282 | |||
| 283 | out: |
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| 284 | return 0; |
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| 285 | } |
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| 286 | |||
| 287 | arch_initcall(pci_direct_init); |