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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 436 | giacomo | 1 | /* |
| 2 | * Exceptions for specific devices. Usually work-arounds for fatal design flaws. |
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| 3 | */ |
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| 4 | |||
| 5 | #include <linuxcomp.h> |
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| 6 | |||
| 7 | #include <linux/pci.h> |
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| 8 | #include <linux/init.h> |
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| 9 | #include "pci2.h" |
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| 10 | |||
| 11 | |||
| 12 | static void __devinit pci_fixup_i450nx(struct pci_dev *d) |
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| 13 | { |
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| 14 | /* |
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| 15 | * i450NX -- Find and scan all secondary buses on all PXB's. |
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| 16 | */ |
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| 17 | int pxb, reg; |
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| 18 | u8 busno, suba, subb; |
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| 19 | |||
| 20 | printk(KERN_WARNING "PCI: Searching for i450NX host bridges on %s\n", pci_name(d)); |
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| 21 | reg = 0xd0; |
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| 22 | for(pxb=0; pxb<2; pxb++) { |
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| 23 | pci_read_config_byte(d, reg++, &busno); |
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| 24 | pci_read_config_byte(d, reg++, &suba); |
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| 25 | pci_read_config_byte(d, reg++, &subb); |
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| 26 | DBG("i450NX PXB %d: %02x/%02x/%02x\n", pxb, busno, suba, subb); |
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| 27 | if (busno) |
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| 28 | pci_scan_bus(busno, &pci_root_ops, NULL); /* Bus A */ |
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| 29 | if (suba < subb) |
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| 30 | pci_scan_bus(suba+1, &pci_root_ops, NULL); /* Bus B */ |
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| 31 | } |
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| 32 | pcibios_last_bus = -1; |
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| 33 | } |
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| 34 | |||
| 35 | static void __devinit pci_fixup_i450gx(struct pci_dev *d) |
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| 36 | { |
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| 37 | /* |
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| 38 | * i450GX and i450KX -- Find and scan all secondary buses. |
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| 39 | * (called separately for each PCI bridge found) |
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| 40 | */ |
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| 41 | u8 busno; |
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| 42 | pci_read_config_byte(d, 0x4a, &busno); |
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| 43 | printk(KERN_INFO "PCI: i440KX/GX host bridge %s: secondary bus %02x\n", pci_name(d), busno); |
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| 44 | pci_scan_bus(busno, &pci_root_ops, NULL); |
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| 45 | pcibios_last_bus = -1; |
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| 46 | } |
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| 47 | |||
| 48 | static void __devinit pci_fixup_umc_ide(struct pci_dev *d) |
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| 49 | { |
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| 50 | /* |
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| 51 | * UM8886BF IDE controller sets region type bits incorrectly, |
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| 52 | * therefore they look like memory despite of them being I/O. |
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| 53 | */ |
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| 54 | int i; |
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| 55 | |||
| 56 | printk(KERN_WARNING "PCI: Fixing base address flags for device %s\n", pci_name(d)); |
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| 57 | for(i=0; i<4; i++) |
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| 58 | d->resource[i].flags |= PCI_BASE_ADDRESS_SPACE_IO; |
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| 59 | } |
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| 60 | |||
| 61 | static void __devinit pci_fixup_ncr53c810(struct pci_dev *d) |
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| 62 | { |
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| 63 | /* |
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| 64 | * NCR 53C810 returns class code 0 (at least on some systems). |
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| 65 | * Fix class to be PCI_CLASS_STORAGE_SCSI |
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| 66 | */ |
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| 67 | if (!d->class) { |
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| 68 | printk(KERN_WARNING "PCI: fixing NCR 53C810 class code for %s\n", pci_name(d)); |
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| 69 | d->class = PCI_CLASS_STORAGE_SCSI << 8; |
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| 70 | } |
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| 71 | } |
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| 72 | |||
| 73 | static void __devinit pci_fixup_ide_bases(struct pci_dev *d) |
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| 74 | { |
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| 75 | int i; |
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| 76 | |||
| 77 | /* |
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| 78 | * PCI IDE controllers use non-standard I/O port decoding, respect it. |
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| 79 | */ |
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| 80 | if ((d->class >> 8) != PCI_CLASS_STORAGE_IDE) |
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| 81 | return; |
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| 82 | DBG("PCI: IDE base address fixup for %s\n", pci_name(d)); |
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| 83 | for(i=0; i<4; i++) { |
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| 84 | struct resource *r = &d->resource[i]; |
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| 85 | if ((r->start & ~0x80) == 0x374) { |
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| 86 | r->start |= 2; |
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| 87 | r->end = r->start; |
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| 88 | } |
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| 89 | } |
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| 90 | } |
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| 91 | |||
| 92 | static void __devinit pci_fixup_ide_trash(struct pci_dev *d) |
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| 93 | { |
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| 94 | int i; |
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| 95 | |||
| 96 | /* |
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| 97 | * There exist PCI IDE controllers which have utter garbage |
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| 98 | * in first four base registers. Ignore that. |
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| 99 | */ |
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| 100 | DBG("PCI: IDE base address trash cleared for %s\n", pci_name(d)); |
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| 101 | for(i=0; i<4; i++) |
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| 102 | d->resource[i].start = d->resource[i].end = d->resource[i].flags = 0; |
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| 103 | } |
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| 104 | |||
| 105 | static void __devinit pci_fixup_latency(struct pci_dev *d) |
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| 106 | { |
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| 107 | /* |
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| 108 | * SiS 5597 and 5598 chipsets require latency timer set to |
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| 109 | * at most 32 to avoid lockups. |
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| 110 | */ |
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| 111 | DBG("PCI: Setting max latency to 32\n"); |
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| 112 | pcibios_max_latency = 32; |
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| 113 | } |
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| 114 | |||
| 115 | static void __devinit pci_fixup_piix4_acpi(struct pci_dev *d) |
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| 116 | { |
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| 117 | /* |
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| 118 | * PIIX4 ACPI device: hardwired IRQ9 |
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| 119 | */ |
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| 120 | d->irq = 9; |
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| 121 | } |
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| 122 | |||
| 123 | /* |
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| 124 | * Addresses issues with problems in the memory write queue timer in |
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| 125 | * certain VIA Northbridges. This bugfix is per VIA's specifications, |
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| 126 | * except for the KL133/KM133: clearing bit 5 on those Northbridges seems |
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| 127 | * to trigger a bug in its integrated ProSavage video card, which |
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| 128 | * causes screen corruption. We only clear bits 6 and 7 for that chipset, |
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| 129 | * until VIA can provide us with definitive information on why screen |
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| 130 | * corruption occurs, and what exactly those bits do. |
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| 131 | * |
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| 132 | * VIA 8363,8622,8361 Northbridges: |
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| 133 | * - bits 5, 6, 7 at offset 0x55 need to be turned off |
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| 134 | * VIA 8367 (KT266x) Northbridges: |
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| 135 | * - bits 5, 6, 7 at offset 0x95 need to be turned off |
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| 136 | * VIA 8363 rev 0x81/0x84 (KL133/KM133) Northbridges: |
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| 137 | * - bits 6, 7 at offset 0x55 need to be turned off |
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| 138 | */ |
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| 139 | |||
| 140 | #define VIA_8363_KL133_REVISION_ID 0x81 |
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| 141 | #define VIA_8363_KM133_REVISION_ID 0x84 |
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| 142 | |||
| 143 | static void __devinit pci_fixup_via_northbridge_bug(struct pci_dev *d) |
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| 144 | { |
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| 145 | u8 v; |
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| 146 | u8 revision; |
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| 147 | int where = 0x55; |
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| 148 | int mask = 0x1f; /* clear bits 5, 6, 7 by default */ |
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| 149 | |||
| 150 | pci_read_config_byte(d, PCI_REVISION_ID, &revision); |
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| 151 | |||
| 152 | if (d->device == PCI_DEVICE_ID_VIA_8367_0) { |
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| 153 | /* fix pci bus latency issues resulted by NB bios error |
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| 154 | it appears on bug free^Wreduced kt266x's bios forces |
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| 155 | NB latency to zero */ |
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| 156 | pci_write_config_byte(d, PCI_LATENCY_TIMER, 0); |
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| 157 | |||
| 158 | where = 0x95; /* the memory write queue timer register is |
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| 159 | different for the KT266x's: 0x95 not 0x55 */ |
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| 160 | } else if (d->device == PCI_DEVICE_ID_VIA_8363_0 && |
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| 161 | (revision == VIA_8363_KL133_REVISION_ID || |
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| 162 | revision == VIA_8363_KM133_REVISION_ID)) { |
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| 163 | mask = 0x3f; /* clear only bits 6 and 7; clearing bit 5 |
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| 164 | causes screen corruption on the KL133/KM133 */ |
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| 165 | } |
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| 166 | |||
| 167 | pci_read_config_byte(d, where, &v); |
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| 168 | if (v & ~mask) { |
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| 169 | printk(KERN_WARNING "Disabling VIA memory write queue (PCI ID %04x, rev %02x): [%02x] %02x & %02x -> %02x\n", \ |
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| 170 | d->device, revision, where, v, mask, v & mask); |
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| 171 | v &= mask; |
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| 172 | pci_write_config_byte(d, where, v); |
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| 173 | } |
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| 174 | } |
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| 175 | |||
| 176 | /* |
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| 177 | * For some reasons Intel decided that certain parts of their |
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| 178 | * 815, 845 and some other chipsets must look like PCI-to-PCI bridges |
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| 179 | * while they are obviously not. The 82801 family (AA, AB, BAM/CAM, |
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| 180 | * BA/CA/DB and E) PCI bridges are actually HUB-to-PCI ones, according |
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| 181 | * to Intel terminology. These devices do forward all addresses from |
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| 182 | * system to PCI bus no matter what are their window settings, so they are |
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| 183 | * "transparent" (or subtractive decoding) from programmers point of view. |
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| 184 | */ |
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| 185 | static void __devinit pci_fixup_transparent_bridge(struct pci_dev *dev) |
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| 186 | { |
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| 187 | if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI && |
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| 188 | (dev->device & 0xff00) == 0x2400) |
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| 189 | dev->transparent = 1; |
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| 190 | } |
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| 191 | |||
| 192 | struct pci_fixup pcibios_fixups[] = { |
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| 193 | { PCI_FIXUP_HEADER, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82451NX, pci_fixup_i450nx }, |
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| 194 | { PCI_FIXUP_HEADER, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454GX, pci_fixup_i450gx }, |
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| 195 | { PCI_FIXUP_HEADER, PCI_VENDOR_ID_UMC, PCI_DEVICE_ID_UMC_UM8886BF, pci_fixup_umc_ide }, |
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| 196 | { PCI_FIXUP_HEADER, PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5513, pci_fixup_ide_trash }, |
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| 197 | { PCI_FIXUP_HEADER, PCI_ANY_ID, PCI_ANY_ID, pci_fixup_ide_bases }, |
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| 198 | { PCI_FIXUP_HEADER, PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, pci_fixup_latency }, |
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| 199 | { PCI_FIXUP_HEADER, PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5598, pci_fixup_latency }, |
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| 200 | { PCI_FIXUP_HEADER, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, pci_fixup_piix4_acpi }, |
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| 201 | { PCI_FIXUP_HEADER, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, pci_fixup_ide_trash }, |
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| 202 | { PCI_FIXUP_HEADER, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_11, pci_fixup_ide_trash }, |
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| 203 | { PCI_FIXUP_HEADER, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_9, pci_fixup_ide_trash }, |
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| 204 | { PCI_FIXUP_HEADER, PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, pci_fixup_via_northbridge_bug }, |
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| 205 | { PCI_FIXUP_HEADER, PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8622, pci_fixup_via_northbridge_bug }, |
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| 206 | { PCI_FIXUP_HEADER, PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, pci_fixup_via_northbridge_bug }, |
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| 207 | { PCI_FIXUP_HEADER, PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8367_0, pci_fixup_via_northbridge_bug }, |
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| 208 | { PCI_FIXUP_HEADER, PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, pci_fixup_ncr53c810 }, |
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| 209 | { PCI_FIXUP_HEADER, PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_fixup_transparent_bridge }, |
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| 210 | { 0 } |
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| 211 | }; |