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428 giacomo 1
/*
440 giacomo 2
 *      $Id: pci.c,v 1.4 2004-01-30 18:30:24 giacomo Exp $
428 giacomo 3
 *
4
 *      PCI Bus Services, see include/linux/pci.h for further explanation.
5
 *
6
 *      Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
7
 *      David Mosberger-Tang
8
 *
9
 *      Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
10
 */
11
 
430 giacomo 12
#include <linuxcomp.h>
13
 
428 giacomo 14
#include <linux/delay.h>
15
#include <linux/init.h>
16
#include <linux/pci.h>
17
#include <linux/module.h>
18
#include <linux/spinlock.h>
19
#include <asm/dma.h>    /* isa_dma_bridge_buggy */
20
 
440 giacomo 21
#define DEBUG
428 giacomo 22
 
23
#ifdef DEBUG
24
#define DBG(x...) printk(x)
25
#else
26
#define DBG(x...)
27
#endif
28
 
29
/**
30
 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
31
 * @bus: pointer to PCI bus structure to search
32
 *
33
 * Given a PCI bus, returns the highest PCI bus number present in the set
34
 * including the given PCI bus and its list of child PCI buses.
35
 */
36
unsigned char __devinit
37
pci_bus_max_busnr(struct pci_bus* bus)
38
{
39
        struct list_head *tmp;
40
        unsigned char max, n;
41
 
42
        max = bus->number;
43
        list_for_each(tmp, &bus->children) {
44
                n = pci_bus_max_busnr(pci_bus_b(tmp));
45
                if(n > max)
46
                        max = n;
47
        }
48
        return max;
49
}
50
 
51
/**
52
 * pci_max_busnr - returns maximum PCI bus number
53
 *
54
 * Returns the highest PCI bus number present in the system global list of
55
 * PCI buses.
56
 */
57
unsigned char __devinit
58
pci_max_busnr(void)
59
{
60
        struct pci_bus *bus = NULL;
61
        unsigned char max, n;
62
 
63
        max = 0;
64
        while ((bus = pci_find_next_bus(bus)) != NULL) {
65
                n = pci_bus_max_busnr(bus);
66
                if(n > max)
67
                        max = n;
68
        }
69
        return max;
70
}
71
 
72
/**
73
 * pci_find_capability - query for devices' capabilities
74
 * @dev: PCI device to query
75
 * @cap: capability code
76
 *
77
 * Tell if a device supports a given PCI capability.
78
 * Returns the address of the requested capability structure within the
79
 * device's PCI configuration space or 0 in case the device does not
80
 * support it.  Possible values for @cap:
81
 *
82
 *  %PCI_CAP_ID_PM           Power Management
83
 *
84
 *  %PCI_CAP_ID_AGP          Accelerated Graphics Port
85
 *
86
 *  %PCI_CAP_ID_VPD          Vital Product Data
87
 *
88
 *  %PCI_CAP_ID_SLOTID       Slot Identification
89
 *
90
 *  %PCI_CAP_ID_MSI          Message Signalled Interrupts
91
 *
92
 *  %PCI_CAP_ID_CHSWP        CompactPCI HotSwap
93
 *
94
 *  %PCI_CAP_ID_PCIX         PCI-X
95
 */
96
int
97
pci_find_capability(struct pci_dev *dev, int cap)
98
{
99
        u16 status;
100
        u8 pos, id;
101
        int ttl = 48;
102
 
103
        pci_read_config_word(dev, PCI_STATUS, &status);
104
        if (!(status & PCI_STATUS_CAP_LIST))
105
                return 0;
106
        switch (dev->hdr_type) {
107
        case PCI_HEADER_TYPE_NORMAL:
108
        case PCI_HEADER_TYPE_BRIDGE:
109
                pci_read_config_byte(dev, PCI_CAPABILITY_LIST, &pos);
110
                break;
111
        case PCI_HEADER_TYPE_CARDBUS:
112
                pci_read_config_byte(dev, PCI_CB_CAPABILITY_LIST, &pos);
113
                break;
114
        default:
115
                return 0;
116
        }
117
        while (ttl-- && pos >= 0x40) {
118
                pos &= ~3;
119
                pci_read_config_byte(dev, pos + PCI_CAP_LIST_ID, &id);
120
                if (id == 0xff)
121
                        break;
122
                if (id == cap)
123
                        return pos;
124
                pci_read_config_byte(dev, pos + PCI_CAP_LIST_NEXT, &pos);
125
        }
126
        return 0;
127
}
128
 
129
/**
130
 * pci_bus_find_capability - query for devices' capabilities
131
 * @bus:   the PCI bus to query
132
 * @devfn: PCI device to query
133
 * @cap:   capability code
134
 *
135
 * Like pci_find_capability() but works for pci devices that do not have a
136
 * pci_dev structure set up yet.
137
 *
138
 * Returns the address of the requested capability structure within the
139
 * device's PCI configuration space or 0 in case the device does not
140
 * support it.
141
 */
142
int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
143
{
144
        u16 status;
145
        u8 pos, id;
146
        int ttl = 48;
147
        struct pci_dev *dev = bus->self;
148
 
149
        pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
150
        if (!(status & PCI_STATUS_CAP_LIST))
151
                return 0;
152
        switch (dev->hdr_type) {
153
        case PCI_HEADER_TYPE_NORMAL:
154
        case PCI_HEADER_TYPE_BRIDGE:
155
                pci_bus_read_config_byte(bus, devfn, PCI_CAPABILITY_LIST, &pos);
156
                break;
157
        case PCI_HEADER_TYPE_CARDBUS:
158
                pci_bus_read_config_byte(bus, devfn, PCI_CB_CAPABILITY_LIST, &pos);
159
                break;
160
        default:
161
                return 0;
162
        }
163
        while (ttl-- && pos >= 0x40) {
164
                pos &= ~3;
165
                pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID, &id);
166
                if (id == 0xff)
167
                        break;
168
                if (id == cap)
169
                        return pos;
170
                pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_NEXT, &pos);
171
        }
172
        return 0;
173
}
174
 
175
/**
176
 * pci_find_parent_resource - return resource region of parent bus of given region
177
 * @dev: PCI device structure contains resources to be searched
178
 * @res: child resource record for which parent is sought
179
 *
180
 *  For given resource region of given device, return the resource
181
 *  region of parent bus the given region is contained in or where
182
 *  it should be allocated from.
183
 */
184
struct resource *
185
pci_find_parent_resource(const struct pci_dev *dev, struct resource *res)
186
{
187
        const struct pci_bus *bus = dev->bus;
188
        int i;
189
        struct resource *best = NULL;
190
 
191
        for(i = 0; i < PCI_BUS_NUM_RESOURCES; i++) {
192
                struct resource *r = bus->resource[i];
193
                if (!r)
194
                        continue;
195
                if (res->start && !(res->start >= r->start && res->end <= r->end))
196
                        continue;       /* Not contained */
197
                if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM))
198
                        continue;       /* Wrong type */
199
                if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH))
200
                        return r;       /* Exact match */
201
                if ((res->flags & IORESOURCE_PREFETCH) && !(r->flags & IORESOURCE_PREFETCH))
202
                        best = r;       /* Approximating prefetchable by non-prefetchable */
203
        }
204
        return best;
205
}
206
 
207
/**
208
 * pci_set_power_state - Set the power state of a PCI device
209
 * @dev: PCI device to be suspended
210
 * @state: Power state we're entering
211
 *
212
 * Transition a device to a new power state, using the Power Management
213
 * Capabilities in the device's config space.
214
 *
215
 * RETURN VALUE:
216
 * -EINVAL if trying to enter a lower state than we're already in.
217
 * 0 if we're already in the requested state.
218
 * -EIO if device does not support PCI PM.
219
 * 0 if we can successfully change the power state.
220
 */
221
 
222
int
223
pci_set_power_state(struct pci_dev *dev, int state)
224
{
225
        int pm;
226
        u16 pmcsr;
227
 
228
        /* bound the state we're entering */
229
        if (state > 3) state = 3;
230
 
231
        /* Validate current state:
232
         * Can enter D0 from any state, but if we can only go deeper
233
         * to sleep if we're already in a low power state
234
         */
235
        if (state > 0 && dev->current_state > state)
236
                return -EINVAL;
237
        else if (dev->current_state == state)
238
                return 0;        /* we're already there */
239
 
240
        /* find PCI PM capability in list */
241
        pm = pci_find_capability(dev, PCI_CAP_ID_PM);
242
 
243
        /* abort if the device doesn't support PM capabilities */
244
        if (!pm) return -EIO;
245
 
246
        /* check if this device supports the desired state */
247
        if (state == 1 || state == 2) {
248
                u16 pmc;
249
                pci_read_config_word(dev,pm + PCI_PM_PMC,&pmc);
250
                if (state == 1 && !(pmc & PCI_PM_CAP_D1)) return -EIO;
251
                else if (state == 2 && !(pmc & PCI_PM_CAP_D2)) return -EIO;
252
        }
253
 
254
        /* If we're in D3, force entire word to 0.
255
         * This doesn't affect PME_Status, disables PME_En, and
256
         * sets PowerState to 0.
257
         */
258
        if (dev->current_state >= 3)
259
                pmcsr = 0;
260
        else {
261
                pci_read_config_word(dev, pm + PCI_PM_CTRL, &pmcsr);
262
                pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
263
                pmcsr |= state;
264
        }
265
 
266
        /* enter specified state */
267
        pci_write_config_word(dev, pm + PCI_PM_CTRL, pmcsr);
268
 
269
        /* Mandatory power management transition delays */
270
        /* see PCI PM 1.1 5.6.1 table 18 */
271
        if(state == 3 || dev->current_state == 3)
272
        {
273
                set_current_state(TASK_UNINTERRUPTIBLE);
274
                schedule_timeout(HZ/100);
275
        }
276
        else if(state == 2 || dev->current_state == 2)
277
                udelay(200);
278
        dev->current_state = state;
279
 
280
        return 0;
281
}
282
 
283
/**
284
 * pci_save_state - save the PCI configuration space of a device before suspending
285
 * @dev: - PCI device that we're dealing with
286
 * @buffer: - buffer to hold config space context
287
 *
288
 * @buffer must be large enough to hold the entire PCI 2.2 config space
289
 * (>= 64 bytes).
290
 */
291
int
292
pci_save_state(struct pci_dev *dev, u32 *buffer)
293
{
294
        int i;
295
        if (buffer) {
296
                /* XXX: 100% dword access ok here? */
297
                for (i = 0; i < 16; i++)
298
                        pci_read_config_dword(dev, i * 4,&buffer[i]);
299
        }
300
        return 0;
301
}
302
 
303
/**
304
 * pci_restore_state - Restore the saved state of a PCI device
305
 * @dev: - PCI device that we're dealing with
306
 * @buffer: - saved PCI config space
307
 *
308
 */
309
int
310
pci_restore_state(struct pci_dev *dev, u32 *buffer)
311
{
312
        int i;
313
 
314
        if (buffer) {
315
                for (i = 0; i < 16; i++)
316
                        pci_write_config_dword(dev,i * 4, buffer[i]);
317
        }
318
        /*
319
         * otherwise, write the context information we know from bootup.
320
         * This works around a problem where warm-booting from Windows
321
         * combined with a D3(hot)->D0 transition causes PCI config
322
         * header data to be forgotten.
323
         */    
324
        else {
325
                for (i = 0; i < 6; i ++)
326
                        pci_write_config_dword(dev,
327
                                               PCI_BASE_ADDRESS_0 + (i * 4),
328
                                               dev->resource[i].start);
329
                pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
330
        }
331
        return 0;
332
}
333
 
334
/**
335
 * pci_enable_device_bars - Initialize some of a device for use
336
 * @dev: PCI device to be initialized
337
 * @bars: bitmask of BAR's that must be configured
338
 *
339
 *  Initialize device before it's used by a driver. Ask low-level code
340
 *  to enable selected I/O and memory resources. Wake up the device if it
341
 *  was suspended. Beware, this function can fail.
342
 */
343
 
344
int
345
pci_enable_device_bars(struct pci_dev *dev, int bars)
346
{
347
        int err;
348
 
349
        pci_set_power_state(dev, 0);
350
        if ((err = pcibios_enable_device(dev, bars)) < 0)
351
                return err;
352
        return 0;
353
}
354
 
355
/**
356
 * pci_enable_device - Initialize device before it's used by a driver.
357
 * @dev: PCI device to be initialized
358
 *
359
 *  Initialize device before it's used by a driver. Ask low-level code
360
 *  to enable I/O and memory. Wake up the device if it was suspended.
361
 *  Beware, this function can fail.
362
 */
363
int
364
pci_enable_device(struct pci_dev *dev)
365
{
366
        return pci_enable_device_bars(dev, (1 << PCI_NUM_RESOURCES) - 1);
367
}
368
 
369
/**
370
 * pci_disable_device - Disable PCI device after use
371
 * @dev: PCI device to be disabled
372
 *
373
 * Signal to the system that the PCI device is not in use by the system
374
 * anymore.  This only involves disabling PCI bus-mastering, if active.
375
 */
376
void
377
pci_disable_device(struct pci_dev *dev)
378
{
379
        u16 pci_command;
380
 
381
        pci_read_config_word(dev, PCI_COMMAND, &pci_command);
382
        if (pci_command & PCI_COMMAND_MASTER) {
383
                pci_command &= ~PCI_COMMAND_MASTER;
384
                pci_write_config_word(dev, PCI_COMMAND, pci_command);
385
        }
386
}
387
 
388
/**
389
 * pci_enable_wake - enable device to generate PME# when suspended
390
 * @dev: - PCI device to operate on
391
 * @state: - Current state of device.
392
 * @enable: - Flag to enable or disable generation
393
 *
394
 * Set the bits in the device's PM Capabilities to generate PME# when
395
 * the system is suspended.
396
 *
397
 * -EIO is returned if device doesn't have PM Capabilities.
398
 * -EINVAL is returned if device supports it, but can't generate wake events.
399
 * 0 if operation is successful.
400
 *
401
 */
402
int pci_enable_wake(struct pci_dev *dev, u32 state, int enable)
403
{
404
        int pm;
405
        u16 value;
406
 
407
        /* find PCI PM capability in list */
408
        pm = pci_find_capability(dev, PCI_CAP_ID_PM);
409
 
410
        /* If device doesn't support PM Capabilities, but request is to disable
411
         * wake events, it's a nop; otherwise fail */
412
        if (!pm)
413
                return enable ? -EIO : 0;
414
 
415
        /* Check device's ability to generate PME# */
416
        pci_read_config_word(dev,pm+PCI_PM_PMC,&value);
417
 
418
        value &= PCI_PM_CAP_PME_MASK;
419
        value >>= ffs(value);   /* First bit of mask */
420
 
421
        /* Check if it can generate PME# from requested state. */
422
        if (!value || !(value & (1 << state)))
423
                return enable ? -EINVAL : 0;
424
 
425
        pci_read_config_word(dev, pm + PCI_PM_CTRL, &value);
426
 
427
        /* Clear PME_Status by writing 1 to it and enable PME# */
428
        value |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
429
 
430
        if (!enable)
431
                value &= ~PCI_PM_CTRL_PME_ENABLE;
432
 
433
        pci_write_config_word(dev, pm + PCI_PM_CTRL, value);
434
 
435
        return 0;
436
}
437
 
438
int
439
pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
440
{
441
        u8 pin;
442
 
443
        pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
444
        if (!pin)
445
                return -1;
446
        pin--;
447
        while (dev->bus->self) {
448
                pin = (pin + PCI_SLOT(dev->devfn)) % 4;
449
                dev = dev->bus->self;
450
        }
451
        *bridge = dev;
452
        return pin;
453
}
454
 
455
/**
456
 *      pci_release_region - Release a PCI bar
457
 *      @pdev: PCI device whose resources were previously reserved by pci_request_region
458
 *      @bar: BAR to release
459
 *
460
 *      Releases the PCI I/O and memory resources previously reserved by a
461
 *      successful call to pci_request_region.  Call this function only
462
 *      after all use of the PCI regions has ceased.
463
 */
464
void pci_release_region(struct pci_dev *pdev, int bar)
465
{
466
        if (pci_resource_len(pdev, bar) == 0)
467
                return;
468
        if (pci_resource_flags(pdev, bar) & IORESOURCE_IO)
469
                release_region(pci_resource_start(pdev, bar),
470
                                pci_resource_len(pdev, bar));
471
        else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM)
472
                release_mem_region(pci_resource_start(pdev, bar),
473
                                pci_resource_len(pdev, bar));
474
}
475
 
476
/**
477
 *      pci_request_region - Reserved PCI I/O and memory resource
478
 *      @pdev: PCI device whose resources are to be reserved
479
 *      @bar: BAR to be reserved
480
 *      @res_name: Name to be associated with resource.
481
 *
482
 *      Mark the PCI region associated with PCI device @pdev BR @bar as
483
 *      being reserved by owner @res_name.  Do not access any
484
 *      address inside the PCI regions unless this call returns
485
 *      successfully.
486
 *
487
 *      Returns 0 on success, or %EBUSY on error.  A warning
488
 *      message is also printed on failure.
489
 */
490
int pci_request_region(struct pci_dev *pdev, int bar, char *res_name)
491
{
492
        if (pci_resource_len(pdev, bar) == 0)
493
                return 0;
494
 
495
        if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) {
496
                if (!request_region(pci_resource_start(pdev, bar),
497
                            pci_resource_len(pdev, bar), res_name))
498
                        goto err_out;
499
        }
500
        else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
501
                if (!request_mem_region(pci_resource_start(pdev, bar),
502
                                        pci_resource_len(pdev, bar), res_name))
503
                        goto err_out;
504
        }
505
 
506
        return 0;
507
 
508
err_out:
509
        printk (KERN_WARNING "PCI: Unable to reserve %s region #%d:%lx@%lx for device %s\n",
510
                pci_resource_flags(pdev, bar) & IORESOURCE_IO ? "I/O" : "mem",
511
                bar + 1, /* PCI BAR # */
512
                pci_resource_len(pdev, bar), pci_resource_start(pdev, bar),
513
                pci_name(pdev));
514
        return -EBUSY;
515
}
516
 
517
 
518
/**
519
 *      pci_release_regions - Release reserved PCI I/O and memory resources
520
 *      @pdev: PCI device whose resources were previously reserved by pci_request_regions
521
 *
522
 *      Releases all PCI I/O and memory resources previously reserved by a
523
 *      successful call to pci_request_regions.  Call this function only
524
 *      after all use of the PCI regions has ceased.
525
 */
526
 
527
void pci_release_regions(struct pci_dev *pdev)
528
{
529
        int i;
530
 
531
        for (i = 0; i < 6; i++)
532
                pci_release_region(pdev, i);
533
}
534
 
535
/**
536
 *      pci_request_regions - Reserved PCI I/O and memory resources
537
 *      @pdev: PCI device whose resources are to be reserved
538
 *      @res_name: Name to be associated with resource.
539
 *
540
 *      Mark all PCI regions associated with PCI device @pdev as
541
 *      being reserved by owner @res_name.  Do not access any
542
 *      address inside the PCI regions unless this call returns
543
 *      successfully.
544
 *
545
 *      Returns 0 on success, or %EBUSY on error.  A warning
546
 *      message is also printed on failure.
547
 */
548
int pci_request_regions(struct pci_dev *pdev, char *res_name)
549
{
550
        int i;
551
 
552
        for (i = 0; i < 6; i++)
553
                if(pci_request_region(pdev, i, res_name))
554
                        goto err_out;
555
        return 0;
556
 
557
err_out:
558
        printk (KERN_WARNING "PCI: Unable to reserve %s region #%d:%lx@%lx for device %s\n",
559
                pci_resource_flags(pdev, i) & IORESOURCE_IO ? "I/O" : "mem",
560
                i + 1, /* PCI BAR # */
561
                pci_resource_len(pdev, i), pci_resource_start(pdev, i),
562
                pci_name(pdev));
563
        while(--i >= 0)
564
                pci_release_region(pdev, i);
565
 
566
        return -EBUSY;
567
}
568
 
569
/**
570
 * pci_set_master - enables bus-mastering for device dev
571
 * @dev: the PCI device to enable
572
 *
573
 * Enables bus-mastering on the device and calls pcibios_set_master()
574
 * to do the needed arch specific settings.
575
 */
576
void
577
pci_set_master(struct pci_dev *dev)
578
{
579
        u16 cmd;
580
 
581
        pci_read_config_word(dev, PCI_COMMAND, &cmd);
582
        if (! (cmd & PCI_COMMAND_MASTER)) {
583
                DBG("PCI: Enabling bus mastering for device %s\n", pci_name(dev));
584
                cmd |= PCI_COMMAND_MASTER;
585
                pci_write_config_word(dev, PCI_COMMAND, cmd);
586
        }
587
        pcibios_set_master(dev);
588
}
589
 
590
#ifndef HAVE_ARCH_PCI_MWI
591
/* This can be overridden by arch code. */
592
u8 pci_cache_line_size = L1_CACHE_BYTES >> 2;
593
 
594
/**
595
 * pci_generic_prep_mwi - helper function for pci_set_mwi
596
 * @dev: the PCI device for which MWI is enabled
597
 *
598
 * Helper function for generic implementation of pcibios_prep_mwi
599
 * function.  Originally copied from drivers/net/acenic.c.
600
 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
601
 *
602
 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
603
 */
604
static int
605
pci_generic_prep_mwi(struct pci_dev *dev)
606
{
607
        u8 cacheline_size;
608
 
609
        if (!pci_cache_line_size)
610
                return -EINVAL;         /* The system doesn't support MWI. */
611
 
612
        /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
613
           equal to or multiple of the right value. */
614
        pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
615
        if (cacheline_size >= pci_cache_line_size &&
616
            (cacheline_size % pci_cache_line_size) == 0)
617
                return 0;
618
 
619
        /* Write the correct value. */
620
        pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
621
        /* Read it back. */
622
        pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
623
        if (cacheline_size == pci_cache_line_size)
624
                return 0;
625
 
626
        printk(KERN_WARNING "PCI: cache line size of %d is not supported "
627
               "by device %s\n", pci_cache_line_size << 2, pci_name(dev));
628
 
629
        return -EINVAL;
630
}
631
#endif /* !HAVE_ARCH_PCI_MWI */
632
 
633
/**
634
 * pci_set_mwi - enables memory-write-invalidate PCI transaction
635
 * @dev: the PCI device for which MWI is enabled
636
 *
637
 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND,
638
 * and then calls @pcibios_set_mwi to do the needed arch specific
639
 * operations or a generic mwi-prep function.
640
 *
641
 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
642
 */
643
int
644
pci_set_mwi(struct pci_dev *dev)
645
{
646
        int rc;
647
        u16 cmd;
648
 
649
#ifdef HAVE_ARCH_PCI_MWI
650
        rc = pcibios_prep_mwi(dev);
651
#else
652
        rc = pci_generic_prep_mwi(dev);
653
#endif
654
 
655
        if (rc)
656
                return rc;
657
 
658
        pci_read_config_word(dev, PCI_COMMAND, &cmd);
659
        if (! (cmd & PCI_COMMAND_INVALIDATE)) {
660
                DBG("PCI: Enabling Mem-Wr-Inval for device %s\n", pci_name(dev));
661
                cmd |= PCI_COMMAND_INVALIDATE;
662
                pci_write_config_word(dev, PCI_COMMAND, cmd);
663
        }
664
 
665
        return 0;
666
}
667
 
668
/**
669
 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
670
 * @dev: the PCI device to disable
671
 *
672
 * Disables PCI Memory-Write-Invalidate transaction on the device
673
 */
674
void
675
pci_clear_mwi(struct pci_dev *dev)
676
{
677
        u16 cmd;
678
 
679
        pci_read_config_word(dev, PCI_COMMAND, &cmd);
680
        if (cmd & PCI_COMMAND_INVALIDATE) {
681
                cmd &= ~PCI_COMMAND_INVALIDATE;
682
                pci_write_config_word(dev, PCI_COMMAND, cmd);
683
        }
684
}
685
 
686
int
687
pci_set_dma_mask(struct pci_dev *dev, u64 mask)
688
{
689
        if (!pci_dma_supported(dev, mask))
690
                return -EIO;
691
 
692
        dev->dma_mask = mask;
693
 
694
        return 0;
695
}
696
 
697
int
698
pci_dac_set_dma_mask(struct pci_dev *dev, u64 mask)
699
{
700
        if (!pci_dac_dma_supported(dev, mask))
701
                return -EIO;
702
 
703
        dev->dma_mask = mask;
704
 
705
        return 0;
706
}
707
 
708
int
709
pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
710
{
711
        if (!pci_dma_supported(dev, mask))
712
                return -EIO;
713
 
714
        dev->consistent_dma_mask = mask;
715
 
716
        return 0;
717
}
718
 
436 giacomo 719
int __devinit pci_init(void)
428 giacomo 720
{
721
        struct pci_dev *dev = NULL;
722
 
723
        while ((dev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
724
                pci_fixup_device(PCI_FIXUP_FINAL, dev);
725
        }
440 giacomo 726
 
727
        dev = pci_find_class(PCI_CLASS_NETWORK_ETHERNET,NULL);
728
 
729
        printk("Find %x\n",(int)(dev));
730
 
428 giacomo 731
        return 0;
732
}
733
 
734
static int __devinit pci_setup(char *str)
735
{
736
        while (str) {
737
                char *k = strchr(str, ',');
738
                if (k)
739
                        *k++ = 0;
740
                if (*str && (str = pcibios_setup(str)) && *str) {
741
                        /* PCI layer options should be handled here */
742
                        printk(KERN_ERR "PCI: Unknown option `%s'\n", str);
743
                }
744
                str = k;
745
        }
746
        return 1;
747
}
748
 
749
device_initcall(pci_init);
750
 
751
__setup("pci=", pci_setup);
752
 
753
#if defined(CONFIG_ISA) || defined(CONFIG_EISA)
754
/* FIXME: Some boxes have multiple ISA bridges! */
755
struct pci_dev *isa_bridge;
756
EXPORT_SYMBOL(isa_bridge);
757
#endif
758
 
759
EXPORT_SYMBOL(pci_enable_device_bars);
760
EXPORT_SYMBOL(pci_enable_device);
761
EXPORT_SYMBOL(pci_disable_device);
762
EXPORT_SYMBOL(pci_max_busnr);
763
EXPORT_SYMBOL(pci_bus_max_busnr);
764
EXPORT_SYMBOL(pci_find_capability);
765
EXPORT_SYMBOL(pci_bus_find_capability);
766
EXPORT_SYMBOL(pci_release_regions);
767
EXPORT_SYMBOL(pci_request_regions);
768
EXPORT_SYMBOL(pci_release_region);
769
EXPORT_SYMBOL(pci_request_region);
770
EXPORT_SYMBOL(pci_set_master);
771
EXPORT_SYMBOL(pci_set_mwi);
772
EXPORT_SYMBOL(pci_clear_mwi);
773
EXPORT_SYMBOL(pci_set_dma_mask);
774
EXPORT_SYMBOL(pci_dac_set_dma_mask);
775
EXPORT_SYMBOL(pci_set_consistent_dma_mask);
776
EXPORT_SYMBOL(pci_assign_resource);
777
EXPORT_SYMBOL(pci_find_parent_resource);
778
 
779
EXPORT_SYMBOL(pci_set_power_state);
780
EXPORT_SYMBOL(pci_save_state);
781
EXPORT_SYMBOL(pci_restore_state);
782
EXPORT_SYMBOL(pci_enable_wake);
783
 
784
/* Quirk info */
785
 
786
EXPORT_SYMBOL(isa_dma_bridge_buggy);
787
EXPORT_SYMBOL(pci_pci_problems);