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428 giacomo 1
/*
514 giacomo 2
 * $Id: quirks.c,v 1.5 2004-03-19 16:30:12 giacomo Exp $
428 giacomo 3
 *
4
 *  This file contains work-arounds for many known PCI hardware
5
 *  bugs.  Devices present only on certain architectures (host
6
 *  bridges et cetera) should be handled in arch-specific code.
7
 *
8
 *  Copyright (c) 1999 Martin Mares <mj@ucw.cz>
9
 *
10
 *  The bridge optimization stuff has been removed. If you really
11
 *  have a silly BIOS which is unable to set your host bridge right,
12
 *  use the PowerTweak utility (see http://powertweak.sourceforge.net).
13
 */
14
 
430 giacomo 15
#include <linuxcomp.h>
16
 
428 giacomo 17
#include <linux/config.h>
18
#include <linux/types.h>
19
#include <linux/kernel.h>
20
#include <linux/pci.h>
21
#include <linux/init.h>
22
#include <linux/delay.h>
23
 
514 giacomo 24
//#define DEBUG
428 giacomo 25
 
26
/* Deal with broken BIOS'es that neglect to enable passive release,
27
   which can cause problems in combination with the 82441FX/PPro MTRRs */
28
static void __devinit quirk_passive_release(struct pci_dev *dev)
29
{
30
        struct pci_dev *d = NULL;
31
        unsigned char dlc;
32
 
33
        /* We have to make sure a particular bit is set in the PIIX3
34
           ISA bridge, so we have to go out and find it. */
35
        while ((d = pci_find_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) {
36
                pci_read_config_byte(d, 0x82, &dlc);
37
                if (!(dlc & 1<<1)) {
38
                        printk(KERN_ERR "PCI: PIIX3: Enabling Passive Release on %s\n", pci_name(d));
39
                        dlc |= 1<<1;
40
                        pci_write_config_byte(d, 0x82, dlc);
41
                }
42
        }
43
}
44
 
45
/*  The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround
46
    but VIA don't answer queries. If you happen to have good contacts at VIA
47
    ask them for me please -- Alan
48
 
49
    This appears to be BIOS not version dependent. So presumably there is a
50
    chipset level fix */
51
 
52
 
53
int isa_dma_bridge_buggy;               /* Exported */
54
 
55
static void __devinit quirk_isa_dma_hangs(struct pci_dev *dev)
56
{
57
        if (!isa_dma_bridge_buggy) {
58
                isa_dma_bridge_buggy=1;
59
                printk(KERN_INFO "Activating ISA DMA hang workarounds.\n");
60
        }
61
}
62
 
63
int pci_pci_problems;
64
 
65
/*
66
 *      Chipsets where PCI->PCI transfers vanish or hang
67
 */
68
 
69
static void __devinit quirk_nopcipci(struct pci_dev *dev)
70
{
71
        if((pci_pci_problems&PCIPCI_FAIL)==0)
72
        {
73
                printk(KERN_INFO "Disabling direct PCI/PCI transfers.\n");
74
                pci_pci_problems|=PCIPCI_FAIL;
75
        }
76
}
77
 
78
/*
79
 *      Triton requires workarounds to be used by the drivers
80
 */
81
 
82
static void __devinit quirk_triton(struct pci_dev *dev)
83
{
84
        if((pci_pci_problems&PCIPCI_TRITON)==0)
85
        {
86
                printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
87
                pci_pci_problems|=PCIPCI_TRITON;
88
        }
89
}
90
 
91
/*
92
 *      VIA Apollo KT133 needs PCI latency patch
93
 *      Made according to a windows driver based patch by George E. Breese
94
 *      see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
95
 *      Also see http://www.au-ja.org/review-kt133a-1-en.phtml for
96
 *      the info on which Mr Breese based his work.
97
 *
98
 *      Updated based on further information from the site and also on
99
 *      information provided by VIA
100
 */
101
static void __devinit quirk_vialatency(struct pci_dev *dev)
102
{
103
        struct pci_dev *p;
104
        u8 rev;
105
        u8 busarb;
106
        /* Ok we have a potential problem chipset here. Now see if we have
107
           a buggy southbridge */
108
 
109
        p=pci_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL);
110
        if(p!=NULL)
111
        {
112
                pci_read_config_byte(p, PCI_CLASS_REVISION, &rev);
113
                /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */
114
                /* Check for buggy part revisions */
115
                if (rev < 0x40 || rev > 0x42)
116
                        return;
117
        }
118
        else
119
        {
120
                p = pci_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL);
121
                if(p==NULL)     /* No problem parts */
122
                        return;
123
                pci_read_config_byte(p, PCI_CLASS_REVISION, &rev);
124
                /* Check for buggy part revisions */
125
                if (rev < 0x10 || rev > 0x12)
126
                        return;
127
        }
128
 
129
        /*
130
         *      Ok we have the problem. Now set the PCI master grant to
131
         *      occur every master grant. The apparent bug is that under high
132
         *      PCI load (quite common in Linux of course) you can get data
133
         *      loss when the CPU is held off the bus for 3 bus master requests
134
         *      This happens to include the IDE controllers....
135
         *
136
         *      VIA only apply this fix when an SB Live! is present but under
137
         *      both Linux and Windows this isnt enough, and we have seen
138
         *      corruption without SB Live! but with things like 3 UDMA IDE
139
         *      controllers. So we ignore that bit of the VIA recommendation..
140
         */
141
 
142
        pci_read_config_byte(dev, 0x76, &busarb);
143
        /* Set bit 4 and bi 5 of byte 76 to 0x01
144
           "Master priority rotation on every PCI master grant */
145
        busarb &= ~(1<<5);
146
        busarb |= (1<<4);
147
        pci_write_config_byte(dev, 0x76, busarb);
148
        printk(KERN_INFO "Applying VIA southbridge workaround.\n");
149
}
150
 
151
/*
152
 *      VIA Apollo VP3 needs ETBF on BT848/878
153
 */
154
 
155
static void __devinit quirk_viaetbf(struct pci_dev *dev)
156
{
157
        if((pci_pci_problems&PCIPCI_VIAETBF)==0)
158
        {
159
                printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
160
                pci_pci_problems|=PCIPCI_VIAETBF;
161
        }
162
}
163
static void __devinit quirk_vsfx(struct pci_dev *dev)
164
{
165
        if((pci_pci_problems&PCIPCI_VSFX)==0)
166
        {
167
                printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
168
                pci_pci_problems|=PCIPCI_VSFX;
169
        }
170
}
171
 
172
/*
173
 *      Ali Magik requires workarounds to be used by the drivers
174
 *      that DMA to AGP space. Latency must be set to 0xA and triton
175
 *      workaround applied too
176
 *      [Info kindly provided by ALi]
177
 */    
178
 
179
static void __init quirk_alimagik(struct pci_dev *dev)
180
{
181
        if((pci_pci_problems&PCIPCI_ALIMAGIK)==0)
182
        {
183
                printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
184
                pci_pci_problems|=PCIPCI_ALIMAGIK|PCIPCI_TRITON;
185
        }
186
}
187
 
188
 
189
/*
190
 *      Natoma has some interesting boundary conditions with Zoran stuff
191
 *      at least
192
 */
193
 
194
static void __devinit quirk_natoma(struct pci_dev *dev)
195
{
196
        if((pci_pci_problems&PCIPCI_NATOMA)==0)
197
        {
198
                printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
199
                pci_pci_problems|=PCIPCI_NATOMA;
200
        }
201
}
202
 
203
/*
204
 *  S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
205
 *  If it's needed, re-allocate the region.
206
 */
207
 
208
static void __devinit quirk_s3_64M(struct pci_dev *dev)
209
{
210
        struct resource *r = &dev->resource[0];
211
 
212
        if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) {
213
                r->start = 0;
214
                r->end = 0x3ffffff;
215
        }
216
}
217
 
218
static void __devinit quirk_io_region(struct pci_dev *dev, unsigned region, unsigned size, int nr)
219
{
220
        region &= ~(size-1);
221
        if (region) {
222
                struct resource *res = dev->resource + nr;
223
 
224
                res->name = pci_name(dev);
225
                res->start = region;
226
                res->end = region + size - 1;
227
                res->flags = IORESOURCE_IO;
228
                pci_claim_resource(dev, nr);
229
        }
230
}      
231
 
232
/*
233
 *      ATI Northbridge setups MCE the processor if you even
234
 *      read somewhere between 0x3b0->0x3bb or read 0x3d3
235
 */
236
 
237
static void __devinit quirk_ati_exploding_mce(struct pci_dev *dev)
238
{
239
        printk(KERN_INFO "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb.\n");
240
        /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
241
        request_region(0x3b0, 0x0C, "RadeonIGP");
242
        request_region(0x3d3, 0x01, "RadeonIGP");
243
}
244
 
245
/*
246
 * Let's make the southbridge information explicit instead
247
 * of having to worry about people probing the ACPI areas,
248
 * for example.. (Yes, it happens, and if you read the wrong
249
 * ACPI register it will put the machine to sleep with no
250
 * way of waking it up again. Bummer).
251
 *
252
 * ALI M7101: Two IO regions pointed to by words at
253
 *      0xE0 (64 bytes of ACPI registers)
254
 *      0xE2 (32 bytes of SMB registers)
255
 */
256
static void __devinit quirk_ali7101_acpi(struct pci_dev *dev)
257
{
258
        u16 region;
259
 
260
        pci_read_config_word(dev, 0xE0, &region);
261
        quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES);
262
        pci_read_config_word(dev, 0xE2, &region);
263
        quirk_io_region(dev, region, 32, PCI_BRIDGE_RESOURCES+1);
264
}
265
 
266
/*
267
 * PIIX4 ACPI: Two IO regions pointed to by longwords at
268
 *      0x40 (64 bytes of ACPI registers)
269
 *      0x90 (32 bytes of SMB registers)
270
 */
271
static void __devinit quirk_piix4_acpi(struct pci_dev *dev)
272
{
273
        u32 region;
274
 
275
        pci_read_config_dword(dev, 0x40, &region);
276
        quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES);
277
        pci_read_config_dword(dev, 0x90, &region);
278
        quirk_io_region(dev, region, 32, PCI_BRIDGE_RESOURCES+1);
279
}
280
 
281
/*
282
 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
283
 *      0x40 (128 bytes of ACPI, GPIO & TCO registers)
284
 *      0x58 (64 bytes of GPIO I/O space)
285
 */
286
static void __devinit quirk_ich4_lpc_acpi(struct pci_dev *dev)
287
{
288
        u32 region;
289
 
290
        pci_read_config_dword(dev, 0x40, &region);
291
        quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES);
292
 
293
        pci_read_config_dword(dev, 0x58, &region);
294
        quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1);
295
}
296
 
297
/*
298
 * VIA ACPI: One IO region pointed to by longword at
299
 *      0x48 or 0x20 (256 bytes of ACPI registers)
300
 */
301
static void __devinit quirk_vt82c586_acpi(struct pci_dev *dev)
302
{
303
        u8 rev;
304
        u32 region;
305
 
306
        pci_read_config_byte(dev, PCI_CLASS_REVISION, &rev);
307
        if (rev & 0x10) {
308
                pci_read_config_dword(dev, 0x48, &region);
309
                region &= PCI_BASE_ADDRESS_IO_MASK;
310
                quirk_io_region(dev, region, 256, PCI_BRIDGE_RESOURCES);
311
        }
312
}
313
 
314
/*
315
 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
316
 *      0x48 (256 bytes of ACPI registers)
317
 *      0x70 (128 bytes of hardware monitoring register)
318
 *      0x90 (16 bytes of SMB registers)
319
 */
320
static void __devinit quirk_vt82c686_acpi(struct pci_dev *dev)
321
{
322
        u16 hm;
323
        u32 smb;
324
 
325
        quirk_vt82c586_acpi(dev);
326
 
327
        pci_read_config_word(dev, 0x70, &hm);
328
        hm &= PCI_BASE_ADDRESS_IO_MASK;
329
        quirk_io_region(dev, hm, 128, PCI_BRIDGE_RESOURCES + 1);
330
 
331
        pci_read_config_dword(dev, 0x90, &smb);
332
        smb &= PCI_BASE_ADDRESS_IO_MASK;
333
        quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 2);
334
}
335
 
336
 
337
#ifdef CONFIG_X86_IO_APIC 
338
 
339
#include <asm/io_apic.h>
340
 
341
/*
342
 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
343
 * devices to the external APIC.
344
 *
345
 * TODO: When we have device-specific interrupt routers,
346
 * this code will go away from quirks.
347
 */
348
static void __devinit quirk_via_ioapic(struct pci_dev *dev)
349
{
350
        u8 tmp;
351
 
352
        if (nr_ioapics < 1)
353
                tmp = 0;    /* nothing routed to external APIC */
354
        else
355
                tmp = 0x1f; /* all known bits (4-0) routed to external APIC */
356
 
357
        printk(KERN_INFO "PCI: %sbling Via external APIC routing\n",
358
               tmp == 0 ? "Disa" : "Ena");
359
 
360
        /* Offset 0x58: External APIC IRQ output control */
361
        pci_write_config_byte (dev, 0x58, tmp);
362
}
363
 
364
/*
365
 * The AMD io apic can hang the box when an apic irq is masked.
366
 * We check all revs >= B0 (yet not in the pre production!) as the bug
367
 * is currently marked NoFix
368
 *
369
 * We have multiple reports of hangs with this chipset that went away with
370
 * noapic specified. For the moment we assume its the errata. We may be wrong
371
 * of course. However the advice is demonstrably good even if so..
372
 */
373
 
374
static void __devinit quirk_amd_ioapic(struct pci_dev *dev)
375
{
376
        u8 rev;
377
 
378
        pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
379
        if(rev >= 0x02)
380
        {
381
                printk(KERN_WARNING "I/O APIC: AMD Errata #22 may be present. In the event of instability try\n");
382
                printk(KERN_WARNING "        : booting with the \"noapic\" option.\n");
383
        }
384
}
385
 
386
static void __init quirk_ioapic_rmw(struct pci_dev *dev)
387
{
388
        if (dev->devfn == 0 && dev->bus->number == 0)
389
                sis_apic_bug = 1;
390
}
391
 
392
#define AMD8131_revA0        0x01
393
#define AMD8131_revB0        0x11
394
#define AMD8131_MISC         0x40
395
#define AMD8131_NIOAMODE_BIT 0
396
 
397
static void __init quirk_amd_8131_ioapic(struct pci_dev *dev)
398
{
399
        unsigned char revid, tmp;
400
 
401
        if (nr_ioapics == 0)
402
                return;
403
 
404
        pci_read_config_byte(dev, PCI_REVISION_ID, &revid);
405
        if (revid == AMD8131_revA0 || revid == AMD8131_revB0) {
406
                printk(KERN_INFO "Fixing up AMD8131 IOAPIC mode\n");
407
                pci_read_config_byte( dev, AMD8131_MISC, &tmp);
408
                tmp &= ~(1 << AMD8131_NIOAMODE_BIT);
409
                pci_write_config_byte( dev, AMD8131_MISC, tmp);
410
        }
411
}
412
 
413
#endif /* CONFIG_X86_IO_APIC */
414
 
415
 
416
/*
417
 * Via 686A/B:  The PCI_INTERRUPT_LINE register for the on-chip
418
 * devices, USB0/1, AC97, MC97, and ACPI, has an unusual feature:
419
 * when written, it makes an internal connection to the PIC.
420
 * For these devices, this register is defined to be 4 bits wide.
421
 * Normally this is fine.  However for IO-APIC motherboards, or
422
 * non-x86 architectures (yes Via exists on PPC among other places),
423
 * we must mask the PCI_INTERRUPT_LINE value versus 0xf to get
424
 * interrupts delivered properly.
425
 *
426
 * TODO: When we have device-specific interrupt routers,
427
 * quirk_via_irqpic will go away from quirks.
428
 */
429
 
430
/*
431
 * FIXME: it is questionable that quirk_via_acpi
432
 * is needed.  It shows up as an ISA bridge, and does not
433
 * support the PCI_INTERRUPT_LINE register at all.  Therefore
434
 * it seems like setting the pci_dev's 'irq' to the
435
 * value of the ACPI SCI interrupt is only done for convenience.
436
 *      -jgarzik
437
 */
438
static void __devinit quirk_via_acpi(struct pci_dev *d)
439
{
440
        /*
441
         * VIA ACPI device: SCI IRQ line in PCI config byte 0x42
442
         */
443
        u8 irq;
444
        pci_read_config_byte(d, 0x42, &irq);
445
        irq &= 0xf;
446
        if (irq && (irq != 2))
447
                d->irq = irq;
448
}
449
 
450
static void __devinit quirk_via_irqpic(struct pci_dev *dev)
451
{
452
        u8 irq, new_irq = dev->irq & 0xf;
453
 
454
        pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
455
 
456
        if (new_irq != irq) {
457
                printk(KERN_INFO "PCI: Via IRQ fixup for %s, from %d to %d\n",
458
                       pci_name(dev), irq, new_irq);
459
 
460
                udelay(15);
461
                pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq);
462
        }
463
}
464
 
465
 
466
/*
467
 * PIIX3 USB: We have to disable USB interrupts that are
468
 * hardwired to PIRQD# and may be shared with an
469
 * external device.
470
 *
471
 * Legacy Support Register (LEGSUP):
472
 *     bit13:  USB PIRQ Enable (USBPIRQDEN),
473
 *     bit4:   Trap/SMI On IRQ Enable (USBSMIEN).
474
 *
475
 * We mask out all r/wc bits, too.
476
 */
477
static void __devinit quirk_piix3_usb(struct pci_dev *dev)
478
{
479
        u16 legsup;
480
 
481
        pci_read_config_word(dev, 0xc0, &legsup);
482
        legsup &= 0x50ef;
483
        pci_write_config_word(dev, 0xc0, legsup);
484
}
485
 
486
/*
487
 * VIA VT82C598 has its device ID settable and many BIOSes
488
 * set it to the ID of VT82C597 for backward compatibility.
489
 * We need to switch it off to be able to recognize the real
490
 * type of the chip.
491
 */
492
static void __devinit quirk_vt82c598_id(struct pci_dev *dev)
493
{
494
        pci_write_config_byte(dev, 0xfc, 0);
495
        pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device);
496
}
497
 
498
/*
499
 * CardBus controllers have a legacy base address that enables them
500
 * to respond as i82365 pcmcia controllers.  We don't want them to
501
 * do this even if the Linux CardBus driver is not loaded, because
502
 * the Linux i82365 driver does not (and should not) handle CardBus.
503
 */
504
static void __devinit quirk_cardbus_legacy(struct pci_dev *dev)
505
{
506
        if ((PCI_CLASS_BRIDGE_CARDBUS << 8) ^ dev->class)
507
                return;
508
        pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0);
509
}
510
 
511
/*
512
 * Following the PCI ordering rules is optional on the AMD762. I'm not
513
 * sure what the designers were smoking but let's not inhale...
514
 *
515
 * To be fair to AMD, it follows the spec by default, its BIOS people
516
 * who turn it off!
517
 */
518
 
519
static void __devinit quirk_amd_ordering(struct pci_dev *dev)
520
{
521
        u32 pcic;
522
        pci_read_config_dword(dev, 0x4C, &pcic);
523
        if((pcic&6)!=6)
524
        {
525
                pcic |= 6;
526
                printk(KERN_WARNING "BIOS failed to enable PCI standards compliance, fixing this error.\n");
527
                pci_write_config_dword(dev, 0x4C, pcic);
528
                pci_read_config_dword(dev, 0x84, &pcic);
529
                pcic |= (1<<23);        /* Required in this mode */
530
                pci_write_config_dword(dev, 0x84, pcic);
531
        }
532
}
533
 
534
/*
535
 *      DreamWorks provided workaround for Dunord I-3000 problem
536
 *
537
 *      This card decodes and responds to addresses not apparently
538
 *      assigned to it. We force a larger allocation to ensure that
539
 *      nothing gets put too close to it.
540
 */
541
 
542
static void __devinit quirk_dunord ( struct pci_dev * dev )
543
{
544
        struct resource * r = & dev -> resource [ 1 ];
545
        r -> start = 0;
546
        r -> end = 0xffffff;
547
}
548
 
549
static void __devinit quirk_transparent_bridge(struct pci_dev *dev)
550
{
551
        dev->transparent = 1;
552
}
553
 
554
/*
555
 * Common misconfiguration of the MediaGX/Geode PCI master that will
556
 * reduce PCI bandwidth from 70MB/s to 25MB/s.  See the GXM/GXLV/GX1
557
 * datasheets found at http://www.national.com/ds/GX for info on what
558
 * these bits do.  <christer@weinigel.se>
559
 */
560
 
561
static void __init quirk_mediagx_master(struct pci_dev *dev)
562
{
563
        u8 reg;
564
        pci_read_config_byte(dev, 0x41, &reg);
565
        if (reg & 2) {
566
                reg &= ~2;
567
                printk(KERN_INFO "PCI: Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", reg);
568
                pci_write_config_byte(dev, 0x41, reg);
569
        }
570
}
571
 
572
/*
573
 * As per PCI spec, ignore base address registers 0-3 of the IDE controllers
574
 * running in Compatible mode (bits 0 and 2 in the ProgIf for primary and
575
 * secondary channels respectively). If the device reports Compatible mode
576
 * but does use BAR0-3 for address decoding, we assume that firmware has
577
 * programmed these BARs with standard values (0x1f0,0x3f4 and 0x170,0x374).
578
 * Exceptions (if they exist) must be handled in chip/architecture specific
579
 * fixups.
580
 *
581
 * Note: for non x86 people. You may need an arch specific quirk to handle
582
 * moving IDE devices to native mode as well. Some plug in card devices power
583
 * up in compatible mode and assume the BIOS will adjust them.
584
 *
585
 * Q: should we load the 0x1f0,0x3f4 into the registers or zap them as
586
 * we do now ? We don't want is pci_enable_device to come along
587
 * and assign new resources. Both approaches work for that.
588
 */
589
 
590
static void __devinit quirk_ide_bases(struct pci_dev *dev)
591
{
592
       struct resource *res;
593
       int first_bar = 2, last_bar = 0;
594
 
595
       if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE)
596
               return;
597
 
598
       res = &dev->resource[0];
599
 
600
       /* primary channel: ProgIf bit 0, BAR0, BAR1 */
601
       if (!(dev->class & 1) && (res[0].flags || res[1].flags)) {
602
               res[0].start = res[0].end = res[0].flags = 0;
603
               res[1].start = res[1].end = res[1].flags = 0;
604
               first_bar = 0;
605
               last_bar = 1;
606
       }
607
 
608
       /* secondary channel: ProgIf bit 2, BAR2, BAR3 */
609
       if (!(dev->class & 4) && (res[2].flags || res[3].flags)) {
610
               res[2].start = res[2].end = res[2].flags = 0;
611
               res[3].start = res[3].end = res[3].flags = 0;
612
               last_bar = 3;
613
       }
614
 
615
       if (!last_bar)
616
               return;
617
 
618
       printk(KERN_INFO "PCI: Ignoring BAR%d-%d of IDE controller %s\n",
619
              first_bar, last_bar, pci_name(dev));
620
}
621
 
622
/*
623
 *      Ensure C0 rev restreaming is off. This is normally done by
624
 *      the BIOS but in the odd case it is not the results are corruption
625
 *      hence the presence of a Linux check
626
 */
627
 
628
static void __init quirk_disable_pxb(struct pci_dev *pdev)
629
{
630
        u16 config;
631
        u8 rev;
632
 
633
        pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
634
        if(rev != 0x04)         /* Only C0 requires this */
635
                return;
636
        pci_read_config_word(pdev, 0x40, &config);
637
        if(config & (1<<6))
638
        {
639
                config &= ~(1<<6);
640
                pci_write_config_word(pdev, 0x40, config);
641
                printk(KERN_INFO "PCI: C0 revision 450NX. Disabling PCI restreaming.\n");
642
        }
643
}
644
 
645
/*
646
 *      VIA northbridges care about PCI_INTERRUPT_LINE
647
 */
648
 
649
int interrupt_line_quirk;
650
 
651
static void __devinit quirk_via_bridge(struct pci_dev *pdev)
652
{
653
        if(pdev->devfn == 0)
654
                interrupt_line_quirk = 1;
655
}
656
 
657
/*
658
 *      Serverworks CSB5 IDE does not fully support native mode
659
 */
660
static void __init quirk_svwks_csb5ide(struct pci_dev *pdev)
661
{
662
        u8 prog;
663
        pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
664
        if (prog & 5) {
665
                prog &= ~5;
666
                pdev->class &= ~5;
667
                pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
668
                /* need to re-assign BARs for compat mode */
669
                quirk_ide_bases(pdev);
670
        }
671
}
672
 
673
/* This was originally an Alpha specific thing, but it really fits here.
674
 * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
675
 */
676
 
677
static void __init quirk_eisa_bridge(struct pci_dev *dev)
678
{
679
        dev->class = PCI_CLASS_BRIDGE_EISA << 8;
680
}
681
 
682
/*
683
 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
684
 * is not activated. The myth is that Asus said that they do not want the
685
 * users to be irritated by just another PCI Device in the Win98 device
686
 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors
687
 * package 2.7.0 for details)
688
 *
689
 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
690
 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it
691
 * becomes necessary to do this tweak in two steps -- I've chosen the Host
692
 * bridge as trigger.
693
 */
694
 
695
static int __initdata asus_hides_smbus = 0;
696
 
697
static void __init asus_hides_smbus_hostbridge(struct pci_dev *dev)
698
{
699
        if (likely(dev->subsystem_vendor != PCI_VENDOR_ID_ASUSTEK))
700
                return;
701
 
702
        if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB)
703
                switch(dev->subsystem_device) {
704
                case 0x8070: /* P4B */
705
                case 0x8088: /* P4B533 */
706
                        asus_hides_smbus = 1;
707
                }
708
        if ((dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) &&
709
            (dev->subsystem_device == 0x80b2)) /* P4PE */
710
                asus_hides_smbus = 1;
711
        if ((dev->device == PCI_DEVICE_ID_INTEL_82850_HB) &&
712
            (dev->subsystem_device == 0x8030)) /* P4T533 */
713
                asus_hides_smbus = 1;
714
        if ((dev->device == PCI_DEVICE_ID_INTEL_7205_0) &&
715
            (dev->subsystem_device == 0x8070)) /* P4G8X Deluxe */
716
                asus_hides_smbus = 1;
717
        return;
718
}
719
 
720
static void __init asus_hides_smbus_lpc(struct pci_dev *dev)
721
{
722
        u16 val;
723
 
724
        if (likely(!asus_hides_smbus))
725
                return;
726
 
727
        pci_read_config_word(dev, 0xF2, &val);
728
        if (val & 0x8) {
729
                pci_write_config_word(dev, 0xF2, val & (~0x8));
730
                pci_read_config_word(dev, 0xF2, &val);
731
                if(val & 0x8)
732
                        printk(KERN_INFO "PCI: i801 SMBus device continues to play 'hide and seek'! 0x%x\n", val);
733
                else
734
                        printk(KERN_INFO "PCI: Enabled i801 SMBus device\n");
735
        }
736
}
737
 
738
/*
739
 * SiS 96x south bridge: BIOS typically hides SMBus device...
740
 */
741
static void __init quirk_sis_96x_smbus(struct pci_dev *dev)
742
{
743
        u8 val = 0;
744
        printk(KERN_INFO "Enabling SiS 96x SMBus.\n");
745
        pci_read_config_byte(dev, 0x77, &val);
746
        pci_write_config_byte(dev, 0x77, val & ~0x10);
747
        pci_read_config_byte(dev, 0x77, &val);
748
}
749
 
750
/*
751
 * ... This is further complicated by the fact that some SiS96x south
752
 * bridges pretend to be 85C503/5513 instead.  In that case see if we
753
 * spotted a compatible north bridge to make sure.
754
 * (pci_find_device doesn't work yet)
755
 *
756
 * We can also enable the sis96x bit in the discovery register..
757
 */
758
static int __devinitdata sis_96x_compatible = 0;
759
 
760
#define SIS_DETECT_REGISTER 0x40
761
 
762
static void __init quirk_sis_503_smbus(struct pci_dev *dev)
763
{
764
        u8 reg;
765
        u16 devid;
766
 
767
        pci_read_config_byte(dev, SIS_DETECT_REGISTER, &reg);
768
        pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6));
769
        pci_read_config_word(dev, PCI_DEVICE_ID, &devid);
770
        if ((devid & 0xfff0) != 0x0960) {
771
                pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg);
772
                return;
773
        }
774
 
775
        /* Make people aware that we changed the config.. */
776
        printk(KERN_WARNING "Uncovering SIS%x that hid as a SIS503 (compatible=%d)\n", devid, sis_96x_compatible);
777
 
778
        /*
779
         * Ok, it now shows up as a 96x.. The 96x quirks are after
780
         * the 503 quirk in the quirk table, so they'll automatically
781
         * run and enable things like the SMBus device
782
         */
783
        dev->device = devid;
784
}
785
 
786
static void __init quirk_sis_96x_compatible(struct pci_dev *dev)
787
{
788
        sis_96x_compatible = 1;
789
}
790
 
791
#ifdef CONFIG_SCSI_SATA
792
static void __init quirk_intel_ide_combined(struct pci_dev *pdev)
793
{
794
        u8 prog, comb, tmp;
795
 
796
        /*
797
         * Narrow down to Intel SATA PCI devices.
798
         */
799
        switch (pdev->device) {
800
        /* PCI ids taken from drivers/scsi/ata_piix.c */
801
        case 0x24d1:
802
        case 0x24df:
803
        case 0x25a3:
804
        case 0x25b0:
805
                break;
806
        default:
807
                /* we do not handle this PCI device */
808
                return;
809
        }
810
 
811
        /*
812
         * Read combined mode register.
813
         */
814
        pci_read_config_byte(pdev, 0x90, &tmp); /* combined mode reg */
815
        tmp &= 0x6;     /* interesting bits 2:1, PATA primary/secondary */
816
        if (tmp == 0x4)         /* bits 10x */
817
                comb = (1 << 0);                /* SATA port 0, PATA port 1 */
818
        else if (tmp == 0x6)    /* bits 11x */
819
                comb = (1 << 2);                /* PATA port 0, SATA port 1 */
820
        else
821
                return;                         /* not in combined mode */
822
 
823
        /*
824
         * Read programming interface register.
825
         * (Tells us if it's legacy or native mode)
826
         */
827
        pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
828
 
829
        /* if SATA port is in native mode, we're ok. */
830
        if (prog & comb)
831
                return;
832
 
833
        /* SATA port is in legacy mode.  Reserve port so that
834
         * IDE driver does not attempt to use it.  If request_region
835
         * fails, it will be obvious at boot time, so we don't bother
836
         * checking return values.
837
         */
838
        if (comb == (1 << 0))
839
                request_region(0x1f0, 8, "libata");     /* port 0 */
840
        else
841
                request_region(0x170, 8, "libata");     /* port 1 */
842
}
843
#endif /* CONFIG_SCSI_SATA */
844
 
845
/*
846
 *  The main table of quirks.
847
 *
848
 *  Note: any hooks for hotpluggable devices in this table must _NOT_
849
 *        be declared __init.
850
 */
851
 
852
static struct pci_fixup pci_fixups[] __devinitdata = {
853
        { PCI_FIXUP_HEADER,     PCI_VENDOR_ID_DUNORD,   PCI_DEVICE_ID_DUNORD_I3000,     quirk_dunord },
854
        { PCI_FIXUP_FINAL,      PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82441,      quirk_passive_release },
855
        { PCI_FIXUP_FINAL,      PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82441,      quirk_passive_release },
856
        /*
857
         * Its not totally clear which chipsets are the problematic ones
858
         * We know 82C586 and 82C596 variants are affected.
859
         */
860
        { PCI_FIXUP_FINAL,      PCI_VENDOR_ID_VIA,      PCI_DEVICE_ID_VIA_82C586_0,     quirk_isa_dma_hangs },
861
        { PCI_FIXUP_FINAL,      PCI_VENDOR_ID_VIA,      PCI_DEVICE_ID_VIA_82C596,       quirk_isa_dma_hangs },
862
        { PCI_FIXUP_FINAL,      PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82371SB_0,  quirk_isa_dma_hangs },
863
        { PCI_FIXUP_FINAL,      PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82454NX,    quirk_disable_pxb },
864
        { PCI_FIXUP_FINAL,      PCI_VENDOR_ID_NEC,      PCI_DEVICE_ID_NEC_CBUS_1,       quirk_isa_dma_hangs },
865
        { PCI_FIXUP_FINAL,      PCI_VENDOR_ID_NEC,      PCI_DEVICE_ID_NEC_CBUS_2,       quirk_isa_dma_hangs },
866
        { PCI_FIXUP_FINAL,      PCI_VENDOR_ID_NEC,      PCI_DEVICE_ID_NEC_CBUS_3,       quirk_isa_dma_hangs },
867
        { PCI_FIXUP_HEADER,     PCI_VENDOR_ID_S3,       PCI_DEVICE_ID_S3_868,           quirk_s3_64M },
868
        { PCI_FIXUP_HEADER,     PCI_VENDOR_ID_S3,       PCI_DEVICE_ID_S3_968,           quirk_s3_64M },
869
        { PCI_FIXUP_FINAL,      PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82437,      quirk_triton },
870
        { PCI_FIXUP_FINAL,      PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82437VX,    quirk_triton },
871
        { PCI_FIXUP_FINAL,      PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82439,      quirk_triton },
872
        { PCI_FIXUP_FINAL,      PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82439TX,    quirk_triton },
873
        { PCI_FIXUP_FINAL,      PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82441,      quirk_natoma },
874
        { PCI_FIXUP_FINAL,      PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82443LX_0,  quirk_natoma },
875
        { PCI_FIXUP_FINAL,      PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82443LX_1,  quirk_natoma },
876
        { PCI_FIXUP_FINAL,      PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82443BX_0,  quirk_natoma },
877
        { PCI_FIXUP_FINAL,      PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82443BX_1,  quirk_natoma },
878
        { PCI_FIXUP_FINAL,      PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82443BX_2,  quirk_natoma },
879
        { PCI_FIXUP_FINAL,      PCI_VENDOR_ID_SI,       PCI_DEVICE_ID_SI_5597,          quirk_nopcipci },
880
        { PCI_FIXUP_FINAL,      PCI_VENDOR_ID_SI,       PCI_DEVICE_ID_SI_496,           quirk_nopcipci },
881
        { PCI_FIXUP_HEADER,     PCI_VENDOR_ID_SI,       PCI_DEVICE_ID_SI_503,           quirk_sis_503_smbus },
882
        { PCI_FIXUP_HEADER,     PCI_VENDOR_ID_SI,       PCI_DEVICE_ID_SI_645,           quirk_sis_96x_compatible },
883
        { PCI_FIXUP_HEADER,     PCI_VENDOR_ID_SI,       PCI_DEVICE_ID_SI_646,           quirk_sis_96x_compatible },
884
        { PCI_FIXUP_HEADER,     PCI_VENDOR_ID_SI,       PCI_DEVICE_ID_SI_648,           quirk_sis_96x_compatible },
885
        { PCI_FIXUP_HEADER,     PCI_VENDOR_ID_SI,       PCI_DEVICE_ID_SI_650,           quirk_sis_96x_compatible },
886
        { PCI_FIXUP_HEADER,     PCI_VENDOR_ID_SI,       PCI_DEVICE_ID_SI_651,           quirk_sis_96x_compatible },
887
        { PCI_FIXUP_HEADER,     PCI_VENDOR_ID_SI,       PCI_DEVICE_ID_SI_961,           quirk_sis_96x_smbus },
888
        { PCI_FIXUP_HEADER,     PCI_VENDOR_ID_SI,       PCI_DEVICE_ID_SI_962,           quirk_sis_96x_smbus },
889
        { PCI_FIXUP_HEADER,     PCI_VENDOR_ID_SI,       PCI_DEVICE_ID_SI_963,           quirk_sis_96x_smbus },
890
        { PCI_FIXUP_FINAL,      PCI_VENDOR_ID_AL,       PCI_DEVICE_ID_AL_M1647,         quirk_alimagik },
891
        { PCI_FIXUP_FINAL,      PCI_VENDOR_ID_AL,       PCI_DEVICE_ID_AL_M1651,         quirk_alimagik },
892
        { PCI_FIXUP_FINAL,      PCI_VENDOR_ID_VIA,      PCI_DEVICE_ID_VIA_8363_0,       quirk_vialatency },
893
        { PCI_FIXUP_FINAL,      PCI_VENDOR_ID_VIA,      PCI_DEVICE_ID_VIA_8371_1,       quirk_vialatency },
894
        { PCI_FIXUP_FINAL,      PCI_VENDOR_ID_VIA,      PCI_DEVICE_ID_VIA_8361, quirk_vialatency },
895
        { PCI_FIXUP_FINAL,      PCI_VENDOR_ID_VIA,      PCI_DEVICE_ID_VIA_82C576,       quirk_vsfx },
896
        { PCI_FIXUP_FINAL,      PCI_VENDOR_ID_VIA,      PCI_DEVICE_ID_VIA_82C597_0,     quirk_viaetbf },
897
        { PCI_FIXUP_HEADER,     PCI_VENDOR_ID_VIA,      PCI_DEVICE_ID_VIA_82C597_0,     quirk_vt82c598_id },
898
        { PCI_FIXUP_HEADER,     PCI_VENDOR_ID_VIA,      PCI_DEVICE_ID_VIA_82C586_3,     quirk_vt82c586_acpi },
899
        { PCI_FIXUP_HEADER,     PCI_VENDOR_ID_VIA,      PCI_DEVICE_ID_VIA_82C686_4,     quirk_vt82c686_acpi },
900
        { PCI_FIXUP_HEADER,     PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82371AB_3,  quirk_piix4_acpi },
901
        { PCI_FIXUP_HEADER,     PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi },
902
        { PCI_FIXUP_HEADER,     PCI_VENDOR_ID_AL,       PCI_DEVICE_ID_AL_M7101,         quirk_ali7101_acpi },
903
        { PCI_FIXUP_HEADER,     PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82371SB_2,  quirk_piix3_usb },
904
        { PCI_FIXUP_HEADER,     PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82371AB_2,  quirk_piix3_usb },
905
        { PCI_FIXUP_HEADER,     PCI_ANY_ID,             PCI_ANY_ID,                     quirk_ide_bases },
906
        { PCI_FIXUP_HEADER,     PCI_VENDOR_ID_VIA,      PCI_ANY_ID,                     quirk_via_bridge },
907
        { PCI_FIXUP_FINAL,      PCI_ANY_ID,             PCI_ANY_ID,                     quirk_cardbus_legacy },
908
 
909
#ifdef CONFIG_X86_IO_APIC 
910
        { PCI_FIXUP_FINAL,      PCI_VENDOR_ID_VIA,      PCI_DEVICE_ID_VIA_82C686,       quirk_via_ioapic },
911
        { PCI_FIXUP_FINAL,      PCI_VENDOR_ID_AMD,      PCI_DEVICE_ID_AMD_VIPER_7410,   quirk_amd_ioapic },
912
        { PCI_FIXUP_FINAL,      PCI_VENDOR_ID_SI,       PCI_ANY_ID,                     quirk_ioapic_rmw },
913
        { PCI_FIXUP_FINAL,      PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_APIC,
914
          quirk_amd_8131_ioapic },
915
#endif
916
        { PCI_FIXUP_HEADER,     PCI_VENDOR_ID_VIA,      PCI_DEVICE_ID_VIA_82C586_3,     quirk_via_acpi },
917
        { PCI_FIXUP_HEADER,     PCI_VENDOR_ID_VIA,      PCI_DEVICE_ID_VIA_82C686_4,     quirk_via_acpi },
918
        { PCI_FIXUP_FINAL,      PCI_VENDOR_ID_VIA,      PCI_DEVICE_ID_VIA_82C586_2,     quirk_via_irqpic },
919
        { PCI_FIXUP_FINAL,      PCI_VENDOR_ID_VIA,      PCI_DEVICE_ID_VIA_82C686_5,     quirk_via_irqpic },
920
        { PCI_FIXUP_FINAL,      PCI_VENDOR_ID_VIA,      PCI_DEVICE_ID_VIA_82C686_6,     quirk_via_irqpic },
921
 
922
        { PCI_FIXUP_FINAL,      PCI_VENDOR_ID_AMD,      PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering },
923
        { PCI_FIXUP_FINAL,      PCI_VENDOR_ID_ATI,      PCI_DEVICE_ID_ATI_RS100,   quirk_ati_exploding_mce },
924
        /*
925
         * i82380FB mobile docking controller: its PCI-to-PCI bridge
926
         * is subtractive decoding (transparent), and does indicate this
927
         * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80
928
         * instead of 0x01.
929
         */
930
        { PCI_FIXUP_HEADER,     PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82380FB,    quirk_transparent_bridge },
931
        { PCI_FIXUP_HEADER,     PCI_VENDOR_ID_TOSHIBA,  0x605,  quirk_transparent_bridge },
932
 
933
        { PCI_FIXUP_FINAL,      PCI_VENDOR_ID_CYRIX,    PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master },
934
 
935
        { PCI_FIXUP_HEADER,     PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide },
936
 
937
        { PCI_FIXUP_HEADER,     PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82375,      quirk_eisa_bridge },
938
 
939
        /*
940
         * on Asus P4B boards, the i801SMBus device is disabled at startup.
941
         */
942
        { PCI_FIXUP_HEADER,     PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82845_HB,   asus_hides_smbus_hostbridge },
943
        { PCI_FIXUP_HEADER,     PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82845G_HB,  asus_hides_smbus_hostbridge },
944
        { PCI_FIXUP_HEADER,     PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82850_HB,   asus_hides_smbus_hostbridge },
945
        { PCI_FIXUP_HEADER,     PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_7205_0,     asus_hides_smbus_hostbridge },
946
        { PCI_FIXUP_HEADER,     PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82801DB_0,  asus_hides_smbus_lpc },
947
        { PCI_FIXUP_HEADER,     PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82801BA_0,  asus_hides_smbus_lpc },
948
 
949
#ifdef CONFIG_SCSI_SATA
950
        /* Fixup BIOSes that configure Parallel ATA (PATA / IDE) and
951
         * Serial ATA (SATA) into the same PCI ID.
952
         */
953
        { PCI_FIXUP_FINAL,      PCI_VENDOR_ID_INTEL,    PCI_ANY_ID,
954
          quirk_intel_ide_combined },
955
#endif /* CONFIG_SCSI_SATA */
956
 
957
        { 0 }
958
};
959
 
960
 
961
static void pci_do_fixups(struct pci_dev *dev, int pass, struct pci_fixup *f)
962
{
963
        while (f->pass) {
964
                if (f->pass == pass &&
965
                    (f->vendor == dev->vendor || f->vendor == (u16) PCI_ANY_ID) &&
966
                    (f->device == dev->device || f->device == (u16) PCI_ANY_ID)) {
456 giacomo 967
                        f->hook(dev);
428 giacomo 968
                }
969
                f++;
970
        }
971
}
972
 
973
void pci_fixup_device(int pass, struct pci_dev *dev)
974
{
975
        pci_do_fixups(dev, pass, pcibios_fixups);
976
        pci_do_fixups(dev, pass, pci_fixups);
977
}