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587 giacomo 1
/*
2
 * probe.c - PCI detection and setup code
3
 */
4
 
5
#include <linuxcomp.h>
6
 
7
#include <linux/init.h>
8
#include <linux/pci.h>
9
#include <linux/slab.h>
10
#include <linux/module.h>
11
 
12
//#define DEBUG
13
 
14
#ifdef DEBUG
15
#define DBG(x...) printk(x)
16
#else
17
#define DBG(x...)
18
#endif
19
 
20
#define CARDBUS_LATENCY_TIMER   176     /* secondary latency timer */
21
#define CARDBUS_RESERVE_BUSNR   3
22
 
23
/* Ugh.  Need to stop exporting this to modules. */
24
LIST_HEAD(pci_root_buses);
25
EXPORT_SYMBOL(pci_root_buses);
26
 
27
LIST_HEAD(pci_devices);
28
 
29
/*
30
 * Translate the low bits of the PCI base
31
 * to the resource type
32
 */
33
static inline unsigned int pci_calc_resource_flags(unsigned int flags)
34
{
35
        if (flags & PCI_BASE_ADDRESS_SPACE_IO)
36
                return IORESOURCE_IO;
37
 
38
        if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
39
                return IORESOURCE_MEM | IORESOURCE_PREFETCH;
40
 
41
        return IORESOURCE_MEM;
42
}
43
 
44
/*
45
 * Find the extent of a PCI decode..
46
 */
47
static u32 pci_size(u32 base, u32 maxbase, unsigned long mask)
48
{
49
        u32 size = mask & maxbase;      /* Find the significant bits */
50
        if (!size)
51
                return 0;
52
 
53
        /* Get the lowest of them to find the decode size, and
54
           from that the extent.  */
55
        size = (size & ~(size-1)) - 1;
56
 
57
        /* base == maxbase can be valid only if the BAR has
58
           already been programmed with all 1s.  */
59
        if (base == maxbase && ((base | size) & mask) != mask)
60
                return 0;
61
 
62
        return size;
63
}
64
 
65
static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
66
{
67
        unsigned int pos, reg, next;
68
        u32 l, sz;
69
        struct resource *res;
70
 
71
        for(pos=0; pos<howmany; pos = next) {
72
                next = pos+1;
73
                res = &dev->resource[pos];
74
                res->name = pci_name(dev);
75
                reg = PCI_BASE_ADDRESS_0 + (pos << 2);
76
                pci_read_config_dword(dev, reg, &l);
77
                pci_write_config_dword(dev, reg, ~0);
78
                pci_read_config_dword(dev, reg, &sz);
79
                pci_write_config_dword(dev, reg, l);
80
                if (!sz || sz == 0xffffffff)
81
                        continue;
82
                if (l == 0xffffffff)
83
                        l = 0;
84
                if ((l & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_MEMORY) {
85
                        sz = pci_size(l, sz, PCI_BASE_ADDRESS_MEM_MASK);
86
                        if (!sz)
87
                                continue;
88
                        res->start = l & PCI_BASE_ADDRESS_MEM_MASK;
89
                        res->flags |= l & ~PCI_BASE_ADDRESS_MEM_MASK;
90
                } else {
91
                        sz = pci_size(l, sz, PCI_BASE_ADDRESS_IO_MASK & 0xffff);
92
                        if (!sz)
93
                                continue;
94
                        res->start = l & PCI_BASE_ADDRESS_IO_MASK;
95
                        res->flags |= l & ~PCI_BASE_ADDRESS_IO_MASK;
96
                }
97
                res->end = res->start + (unsigned long) sz;
98
                res->flags |= pci_calc_resource_flags(l);
99
                if ((l & (PCI_BASE_ADDRESS_SPACE | PCI_BASE_ADDRESS_MEM_TYPE_MASK))
100
                    == (PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64)) {
101
                        pci_read_config_dword(dev, reg+4, &l);
102
                        next++;
103
#if BITS_PER_LONG == 64
104
                        res->start |= ((unsigned long) l) << 32;
105
                        res->end = res->start + sz;
106
                        pci_write_config_dword(dev, reg+4, ~0);
107
                        pci_read_config_dword(dev, reg+4, &sz);
108
                        pci_write_config_dword(dev, reg+4, l);
109
                        if (~sz)
110
                                res->end = res->start + 0xffffffff +
111
                                                (((unsigned long) ~sz) << 32);
112
#else
113
                        if (l) {
114
                                printk(KERN_ERR "PCI: Unable to handle 64-bit address for device %s\n", pci_name(dev));
115
                                res->start = 0;
116
                                res->flags = 0;
117
                                continue;
118
                        }
119
#endif
120
                }
121
        }
122
        if (rom) {
123
                dev->rom_base_reg = rom;
124
                res = &dev->resource[PCI_ROM_RESOURCE];
125
                res->name = pci_name(dev);
126
                pci_read_config_dword(dev, rom, &l);
127
                pci_write_config_dword(dev, rom, ~PCI_ROM_ADDRESS_ENABLE);
128
                pci_read_config_dword(dev, rom, &sz);
129
                pci_write_config_dword(dev, rom, l);
130
                if (l == 0xffffffff)
131
                        l = 0;
132
                if (sz && sz != 0xffffffff) {
133
                        sz = pci_size(l, sz, PCI_ROM_ADDRESS_MASK);
134
                        if (sz) {
135
                                res->flags = (l & PCI_ROM_ADDRESS_ENABLE) |
136
                                  IORESOURCE_MEM | IORESOURCE_PREFETCH |
137
                                  IORESOURCE_READONLY | IORESOURCE_CACHEABLE;
138
                                res->start = l & PCI_ROM_ADDRESS_MASK;
139
                                res->end = res->start + (unsigned long) sz;
140
                        }
141
                }
142
        }
143
}
144
 
145
void __devinit pci_read_bridge_bases(struct pci_bus *child)
146
{
147
        struct pci_dev *dev = child->self;
148
        u8 io_base_lo, io_limit_lo;
149
        u16 mem_base_lo, mem_limit_lo;
150
        unsigned long base, limit;
151
        struct resource *res;
152
        int i;
153
 
154
        if (!dev)               /* It's a host bus, nothing to read */
155
                return;
156
 
157
        if (dev->transparent) {
158
                printk("Transparent bridge - %s\n", pci_name(dev));
159
                for(i = 0; i < PCI_BUS_NUM_RESOURCES; i++)
160
                        child->resource[i] = child->parent->resource[i];
161
                return;
162
        }
163
 
164
        for(i=0; i<3; i++)
165
                child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
166
 
167
        res = child->resource[0];
168
        pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
169
        pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
170
        base = (io_base_lo & PCI_IO_RANGE_MASK) << 8;
171
        limit = (io_limit_lo & PCI_IO_RANGE_MASK) << 8;
172
 
173
        if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
174
                u16 io_base_hi, io_limit_hi;
175
                pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
176
                pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
177
                base |= (io_base_hi << 16);
178
                limit |= (io_limit_hi << 16);
179
        }
180
 
181
        if (base && base <= limit) {
182
                res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
183
                res->start = base;
184
                res->end = limit + 0xfff;
185
        }
186
 
187
        res = child->resource[1];
188
        pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
189
        pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
190
        base = (mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
191
        limit = (mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
192
        if (base && base <= limit) {
193
                res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
194
                res->start = base;
195
                res->end = limit + 0xfffff;
196
        }
197
 
198
        res = child->resource[2];
199
        pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
200
        pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
201
        base = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
202
        limit = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
203
 
204
        if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
205
                u32 mem_base_hi, mem_limit_hi;
206
                pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
207
                pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
208
#if BITS_PER_LONG == 64
209
                base |= ((long) mem_base_hi) << 32;
210
                limit |= ((long) mem_limit_hi) << 32;
211
#else
212
                if (mem_base_hi || mem_limit_hi) {
213
                        printk(KERN_ERR "PCI: Unable to handle 64-bit address space for %s\n", child->name);
214
                        return;
215
                }
216
#endif
217
        }
218
        if (base && base <= limit) {
219
                res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM | IORESOURCE_PREFETCH;
220
                res->start = base;
221
                res->end = limit + 0xfffff;
222
        }
223
}
224
 
225
static struct pci_bus * __devinit pci_alloc_bus(void)
226
{
227
        struct pci_bus *b;
228
 
229
        b = kmalloc(sizeof(*b), GFP_KERNEL);
230
        if (b) {
231
                memset(b, 0, sizeof(*b));
232
                INIT_LIST_HEAD(&b->node);
233
                INIT_LIST_HEAD(&b->children);
234
                INIT_LIST_HEAD(&b->devices);
235
        }
236
        return b;
237
}
238
 
239
static struct pci_bus * __devinit
240
pci_alloc_child_bus(struct pci_bus *parent, struct pci_dev *bridge, int busnr)
241
{
242
        struct pci_bus *child;
243
 
244
        /*
245
         * Allocate a new bus, and inherit stuff from the parent..
246
         */
247
        child = pci_alloc_bus();
248
 
249
        if (child) {
250
                int i;
251
 
252
                child->self = bridge;
253
                child->parent = parent;
254
                child->ops = parent->ops;
255
                child->sysdata = parent->sysdata;
256
                child->dev = &bridge->dev;
257
 
258
                /*
259
                 * Set up the primary, secondary and subordinate
260
                 * bus numbers.
261
                 */
262
                child->number = child->secondary = busnr;
263
                child->primary = parent->secondary;
264
                child->subordinate = 0xff;
265
 
266
                /* Set up default resource pointers and names.. */
267
                for (i = 0; i < 4; i++) {
268
                        child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
269
                        child->resource[i]->name = child->name;
270
                }
271
 
272
                bridge->subordinate = child;
273
        }
274
 
275
        return child;
276
}
277
 
278
struct pci_bus * __devinit pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, int busnr)
279
{
280
        struct pci_bus *child;
281
 
282
        child = pci_alloc_child_bus(parent, dev, busnr);
283
        if (child)
284
                list_add_tail(&child->node, &parent->children);
285
        return child;
286
}
287
 
288
static unsigned int __devinit pci_scan_child_bus(struct pci_bus *bus);
289
 
290
/*
291
 * If it's a bridge, configure it and scan the bus behind it.
292
 * For CardBus bridges, we don't scan behind as the devices will
293
 * be handled by the bridge driver itself.
294
 *
295
 * We need to process bridges in two passes -- first we scan those
296
 * already configured by the BIOS and after we are done with all of
297
 * them, we proceed to assigning numbers to the remaining buses in
298
 * order to avoid overlaps between old and new bus numbers.
299
 */
300
int __devinit pci_scan_bridge(struct pci_bus *bus, struct pci_dev * dev, int max, int pass)
301
{
302
        struct pci_bus *child;
303
        int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
304
        u32 buses;
305
 
306
        pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
307
 
308
        DBG("Scanning behind PCI bridge %s, config %06x, pass %d\n",
309
            pci_name(dev), buses & 0xffffff, pass);
310
 
311
        if ((buses & 0xffff00) && !pcibios_assign_all_busses() && !is_cardbus) {
312
                unsigned int cmax;
313
                /*
314
                 * Bus already configured by firmware, process it in the first
315
                 * pass and just note the configuration.
316
                 */
317
                if (pass)
318
                        return max;
319
                child = pci_alloc_child_bus(bus, dev, 0);
320
                child->primary = buses & 0xFF;
321
                child->secondary = (buses >> 8) & 0xFF;
322
                child->subordinate = (buses >> 16) & 0xFF;
323
                child->number = child->secondary;
324
                cmax = pci_scan_child_bus(child);
325
                if (cmax > max) max = cmax;
326
        } else {
327
                /*
328
                 * We need to assign a number to this bus which we always
329
                 * do in the second pass.
330
                 */
331
                if (!pass)
332
                        return max;
333
 
334
                /* Clear errors */
335
                pci_write_config_word(dev, PCI_STATUS, 0xffff);
336
 
337
                child = pci_alloc_child_bus(bus, dev, ++max);
338
                buses = (buses & 0xff000000)
339
                      | ((unsigned int)(child->primary)     <<  0)
340
                      | ((unsigned int)(child->secondary)   <<  8)
341
                      | ((unsigned int)(child->subordinate) << 16);
342
 
343
                /*
344
                 * yenta.c forces a secondary latency timer of 176.
345
                 * Copy that behaviour here.
346
                 */
347
                if (is_cardbus) {
348
                        buses &= ~0xff000000;
349
                        buses |= CARDBUS_LATENCY_TIMER << 24;
350
                }
351
 
352
                /*
353
                 * We need to blast all three values with a single write.
354
                 */
355
                pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
356
 
357
                if (!is_cardbus) {
358
                        /* Now we can scan all subordinate buses... */
359
                        max = pci_scan_child_bus(child);
360
                } else {
361
                        /*
362
                         * For CardBus bridges, we leave 4 bus numbers
363
                         * as cards with a PCI-to-PCI bridge can be
364
                         * inserted later.
365
                         */
366
                        max += CARDBUS_RESERVE_BUSNR;
367
                }
368
                /*
369
                 * Set the subordinate bus number to its real value.
370
                 */
371
                child->subordinate = max;
372
                pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
373
        }
374
 
375
        sprintf26(child->name, (is_cardbus ? "PCI CardBus #%02x" : "PCI Bus #%02x"), child->number);
376
 
377
        return max;
378
}
379
 
380
/*
381
 * Read interrupt line and base address registers.
382
 * The architecture-dependent code can tweak these, of course.
383
 */
384
static void pci_read_irq(struct pci_dev *dev)
385
{
386
        unsigned char irq;
387
 
388
        pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
389
        if (irq)
390
                pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
391
        dev->irq = irq;
392
}
393
 
394
/**
395
 * pci_setup_device - fill in class and map information of a device
396
 * @dev: the device structure to fill
397
 *
398
 * Initialize the device structure with information about the device's
399
 * vendor,class,memory and IO-space addresses,IRQ lines etc.
400
 * Called at initialisation of the PCI subsystem and by CardBus services.
401
 * Returns 0 on success and -1 if unknown type of device (not normal, bridge
402
 * or CardBus).
403
 */
404
static int pci_setup_device(struct pci_dev * dev)
405
{
406
        u32 class;
407
 
408
        dev->slot_name = dev->dev.bus_id;
409
        sprintf26(pci_name(dev), "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
410
                dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
411
 
412
        INIT_LIST_HEAD(&dev->pools);
413
 
414
        pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
415
        class >>= 8;                                /* upper 3 bytes */
416
        dev->class = class;
417
        class >>= 8;
418
 
419
        DBG("Found %02x:%02x [%04x/%04x] %06x %02x\n", dev->bus->number,
420
            dev->devfn, dev->vendor, dev->device, class, dev->hdr_type);
421
 
422
        /* "Unknown power state" */
423
        dev->current_state = 4;
424
 
425
        switch (dev->hdr_type) {                    /* header type */
426
        case PCI_HEADER_TYPE_NORMAL:                /* standard header */
427
                if (class == PCI_CLASS_BRIDGE_PCI)
428
                        goto bad;
429
                pci_read_irq(dev);
430
                pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
431
                pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
432
                pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device);
433
                break;
434
 
435
        case PCI_HEADER_TYPE_BRIDGE:                /* bridge header */
436
                if (class != PCI_CLASS_BRIDGE_PCI)
437
                        goto bad;
438
                /* The PCI-to-PCI bridge spec requires that subtractive
439
                   decoding (i.e. transparent) bridge must have programming
440
                   interface code of 0x01. */
441
                dev->transparent = ((dev->class & 0xff) == 1);
442
                pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
443
                break;
444
 
445
        case PCI_HEADER_TYPE_CARDBUS:               /* CardBus bridge header */
446
                if (class != PCI_CLASS_BRIDGE_CARDBUS)
447
                        goto bad;
448
                pci_read_irq(dev);
449
                pci_read_bases(dev, 1, 0);
450
                pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
451
                pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
452
                break;
453
 
454
        default:                                    /* unknown header */
455
                printk(KERN_ERR "PCI: device %s has unknown header type %02x, ignoring.\n",
456
                        pci_name(dev), dev->hdr_type);
457
                return -1;
458
 
459
        bad:
460
                printk(KERN_ERR "PCI: %s: class %x doesn't match header type %02x. Ignoring class.\n",
461
                       pci_name(dev), class, dev->hdr_type);
462
                dev->class = PCI_CLASS_NOT_DEFINED;
463
        }
464
 
465
        /* We found a fine healthy device, go go go... */
466
        return 0;
467
}
468
 
469
/**
470
 * pci_release_dev - free a pci device structure when all users of it are finished.
471
 * @dev: device that's been disconnected
472
 *
473
 * Will be called only by the device core when all users of this pci device are
474
 * done.
475
 */
476
static void pci_release_dev(struct device *dev)
477
{
478
        struct pci_dev *pci_dev;
479
 
480
        pci_dev = to_pci_dev(dev);
481
        kfree(pci_dev);
482
}
483
 
484
/*
485
 * Read the config data for a PCI device, sanity-check it
486
 * and fill in the dev structure...
487
 */
488
static struct pci_dev * __devinit
489
pci_scan_device(struct pci_bus *bus, int devfn)
490
{
491
        struct pci_dev *dev;
492
        u32 l;
493
        u8 hdr_type;
494
 
495
        if (pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type))
496
                return NULL;
497
 
498
        if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l))
499
                return NULL;
500
 
501
        /* some broken boards return 0 or ~0 if a slot is empty: */
502
        if (l == 0xffffffff || l == 0x00000000 ||
503
            l == 0x0000ffff || l == 0xffff0000)
504
                return NULL;
505
 
506
        dev = kmalloc(sizeof(struct pci_dev), GFP_KERNEL);
507
        if (!dev)
508
                return NULL;
509
 
510
        memset(dev, 0, sizeof(struct pci_dev));
511
        dev->bus = bus;
512
        dev->sysdata = bus->sysdata;
513
        dev->dev.parent = bus->dev;
514
        dev->dev.bus = &pci_bus_type;
515
        dev->devfn = devfn;
516
        dev->hdr_type = hdr_type & 0x7f;
517
        dev->multifunction = !!(hdr_type & 0x80);
518
        dev->vendor = l & 0xffff;
519
        dev->device = (l >> 16) & 0xffff;
520
 
521
        /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
522
           set this higher, assuming the system even supports it.  */
523
        dev->dma_mask = 0xffffffff;
524
        dev->consistent_dma_mask = 0xffffffff;
525
        if (pci_setup_device(dev) < 0) {
526
                kfree(dev);
527
                return NULL;
528
        }
529
        device_initialize(&dev->dev);
530
        dev->dev.release = pci_release_dev;
531
        pci_dev_get(dev);
532
 
533
        pci_name_device(dev);
534
 
535
        dev->dev.dma_mask = &dev->dma_mask;
536
 
537
        return dev;
538
}
539
 
540
/**
541
 * pci_scan_slot - scan a PCI slot on a bus for devices.
542
 * @bus: PCI bus to scan
543
 * @devfn: slot number to scan (must have zero function.)
544
 *
545
 * Scan a PCI slot on the specified PCI bus for devices, adding
546
 * discovered devices to the @bus->devices list.  New devices
547
 * will have an empty dev->global_list head.
548
 */
549
int __devinit pci_scan_slot(struct pci_bus *bus, int devfn)
550
{
551
        int func, nr = 0;
552
 
553
        for (func = 0; func < 8; func++, devfn++) {
554
                struct pci_dev *dev;
555
 
556
                dev = pci_scan_device(bus, devfn);
557
                if (func == 0) {
558
                        if (!dev)
559
                                break;
560
                } else {
561
                        if (!dev)
562
                                continue;
563
                        dev->multifunction = 1;
564
                }
565
 
566
                /* Fix up broken headers */
567
                pci_fixup_device(PCI_FIXUP_HEADER, dev);
568
 
569
                /*
570
                 * Add the device to our list of discovered devices
571
                 * and the bus list for fixup functions, etc.
572
                 */
573
                INIT_LIST_HEAD(&dev->global_list);
574
                list_add_tail(&dev->bus_list, &bus->devices);
575
                nr++;
576
 
577
                /*
578
                 * If this is a single function device,
579
                 * don't scan past the first function.
580
                 */
581
                if (!dev->multifunction)
582
                        break;
583
        }
584
        return nr;
585
}
586
 
587
static unsigned int __devinit pci_scan_child_bus(struct pci_bus *bus)
588
{
589
        unsigned int devfn, pass, max = bus->secondary;
590
        struct pci_dev *dev;
591
 
592
        DBG("Scanning bus %02x\n", bus->number);
593
 
594
        /* Go find them, Rover! */
595
        for (devfn = 0; devfn < 0x100; devfn += 8)
596
                pci_scan_slot(bus, devfn);
597
 
598
        /*
599
         * After performing arch-dependent fixup of the bus, look behind
600
         * all PCI-to-PCI bridges on this bus.
601
         */
602
        DBG("Fixups for bus %02x\n", bus->number);
603
        pcibios_fixup_bus(bus);
604
        for (pass=0; pass < 2; pass++)
605
                list_for_each_entry(dev, &bus->devices, bus_list) {
606
                        if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
607
                            dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
608
                                max = pci_scan_bridge(bus, dev, max, pass);
609
                }
610
 
611
        /*
612
         * We've scanned the bus and so we know all about what's on
613
         * the other side of any bridges that may be on this bus plus
614
         * any devices.
615
         *
616
         * Return how far we've got finding sub-buses.
617
         */
618
        DBG("Bus scan for %02x returning with max=%02x\n", bus->number, max);
619
        return max;
620
}
621
 
622
unsigned int __devinit pci_do_scan_bus(struct pci_bus *bus)
623
{
624
        unsigned int max;
625
 
626
        max = pci_scan_child_bus(bus);
627
 
628
        /*
629
         * Make the discovered devices available.
630
         */
631
        pci_bus_add_devices(bus);
632
 
633
        return max;
634
}
635
 
636
struct pci_bus * __devinit pci_scan_bus_parented(struct device *parent, int bus, struct pci_ops *ops, void *sysdata)
637
{
638
        struct pci_bus *b;
639
 
640
        b = pci_alloc_bus();
641
        if (!b)
642
                return NULL;
643
 
644
        b->dev = kmalloc(sizeof(*(b->dev)),GFP_KERNEL);
645
        if (!b->dev){
646
                kfree(b);
647
                return NULL;
648
        }
649
 
650
        b->sysdata = sysdata;
651
        b->ops = ops;
652
 
653
        if (pci_find_bus(pci_domain_nr(b), bus)) {
654
                /* If we already got to this bus through a different bridge, ignore it */
655
                DBG("PCI: Bus %02x already known\n", bus);
656
                kfree(b->dev);
657
                kfree(b);
658
                return NULL;
659
        }
660
 
661
        list_add_tail(&b->node, &pci_root_buses);
662
 
663
        memset(b->dev,0,sizeof(*(b->dev)));
664
        b->dev->parent = parent;
665
        sprintf26(b->dev->bus_id,"pci%04x:%02x", pci_domain_nr(b), bus);
666
        device_register(b->dev);
667
 
668
        b->number = b->secondary = bus;
669
        b->resource[0] = &ioport_resource;
670
        b->resource[1] = &iomem_resource;
671
 
672
        b->subordinate = pci_scan_child_bus(b);
673
 
674
        pci_bus_add_devices(b);
675
 
676
        return b;
677
}
678
EXPORT_SYMBOL(pci_scan_bus_parented);
679
 
680
#ifdef CONFIG_HOTPLUG
681
EXPORT_SYMBOL(pci_add_new_bus);
682
EXPORT_SYMBOL(pci_do_scan_bus);
683
EXPORT_SYMBOL(pci_scan_slot);
684
EXPORT_SYMBOL(pci_scan_bridge);
685
#endif