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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 54 | pj | 1 | #include <linux/pci.h> |
| 2 | #include <asm/io.h> |
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| 3 | #include <stdint.h> |
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| 4 | #include "svgalib_helper.h" |
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| 5 | |||
| 6 | #define ioremap(a,b) \ |
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| 7 | (((a)<0x100000) ? (void *)((u_long)(a)) : vremap(a,b)) |
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| 8 | #define iounmap(v) \ |
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| 9 | do { if ((u_long)(v) > 0x100000) vfree(v); } while (0) |
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| 10 | |||
| 11 | int vga_test_vsync(struct sh_pci_device *dev) { |
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| 12 | return inb(0x3c2)&0x80; |
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| 13 | } |
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| 14 | |||
| 15 | void vga_ack_vsync(struct sh_pci_device *dev) { |
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| 16 | int pb; |
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| 17 | |||
| 18 | /* disable interrupt, clear pending */ |
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| 19 | outb(0x11, 0x3d4); |
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| 20 | pb = inb(0x3d5); |
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| 21 | outb(0x11, 0x3d4); |
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| 22 | outb((pb&0xef) | 0x20, 0x3d5); |
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| 23 | } |
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| 24 | |||
| 25 | void vga_enable_vsync(struct sh_pci_device *dev) { |
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| 26 | int pb; |
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| 27 | |||
| 28 | /* enable interrupt, clear pending */ |
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| 29 | outb(0x11, 0x3d4); |
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| 30 | pb = inb(0x3d5); |
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| 31 | outb(0x11, 0x3d4); |
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| 32 | outb((pb&0xcf) , 0x3d5); |
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| 33 | |||
| 34 | /* Allow interrupts */ |
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| 35 | outb(0x11, 0x3d4); |
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| 36 | pb = inb(0x3d5); |
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| 37 | outb(0x11, 0x3d4); |
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| 38 | outb(pb | 0x10 , 0x3d5); |
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| 39 | } |
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| 40 | |||
| 41 | int io_test_vsync(struct sh_pci_device *dev) { |
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| 42 | return inb(dev->iobase+0x3c2)&0x80; |
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| 43 | } |
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| 44 | |||
| 45 | void io_ack_vsync(struct sh_pci_device *dev) { |
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| 46 | int pb; |
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| 47 | |||
| 48 | /* disable interrupt, clear pending */ |
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| 49 | outb(0x11, dev->iobase+0x3d4); |
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| 50 | pb = inb(dev->iobase+0x3d5); |
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| 51 | outb(0x11, dev->iobase+0x3d4); |
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| 52 | outb((pb&0xef) | 0x20, dev->iobase+0x3d5); |
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| 53 | } |
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| 54 | |||
| 55 | void io_enable_vsync(struct sh_pci_device *dev) { |
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| 56 | int pb; |
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| 57 | |||
| 58 | /* enable interrupt, clear pending */ |
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| 59 | outb(0x11, dev->iobase+0x3d4); |
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| 60 | pb = inb(dev->iobase+0x3d5); |
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| 61 | outb(0x11, dev->iobase+0x3d4); |
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| 62 | outb((pb&0xcf) , dev->iobase+0x3d5); |
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| 63 | |||
| 64 | /* Allow interrupts */ |
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| 65 | outb(0x11, dev->iobase+0x3d4); |
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| 66 | pb = inb(dev->iobase+0x3d5); |
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| 67 | outb(0x11, dev->iobase+0x3d4); |
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| 68 | outb(pb | 0x10 , dev->iobase+0x3d5); |
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| 69 | } |
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| 70 | |||
| 71 | int mm_test_vsync(struct sh_pci_device *dev) { |
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| 72 | return readb(dev->iobase+0x3c2)&0x80; |
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| 73 | } |
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| 74 | |||
| 75 | void mm_ack_vsync(struct sh_pci_device *dev) { |
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| 76 | int pb; |
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| 77 | |||
| 78 | /* disable interrupt, clear pending */ |
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| 79 | writeb(0x11, dev->iobase+0x3d4); |
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| 80 | pb = readb(dev->iobase+0x3d5); |
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| 81 | writeb(0x11, dev->iobase+0x3d4); |
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| 82 | writeb((pb&0xef) | 0x20, dev->iobase+0x3d5); |
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| 83 | } |
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| 84 | |||
| 85 | void mm_enable_vsync(struct sh_pci_device *dev) { |
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| 86 | int pb; |
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| 87 | |||
| 88 | /* enable interrupt, clear pending */ |
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| 89 | writeb(0x11, dev->iobase+0x3d4); |
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| 90 | pb = readb(dev->iobase+0x3d5); |
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| 91 | writeb(0x11, dev->iobase+0x3d4); |
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| 92 | writeb((pb&0xcf) , dev->iobase+0x3d5); |
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| 93 | |||
| 94 | /* Allow interrupts */ |
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| 95 | writeb(0x11, dev->iobase+0x3d4); |
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| 96 | pb = readb(dev->iobase+0x3d5); |
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| 97 | writeb(0x11, dev->iobase+0x3d4); |
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| 98 | writeb(pb | 0x10 , dev->iobase+0x3d5); |
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| 99 | } |
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| 100 | |||
| 101 | static uint32_t saved_pmc; |
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| 102 | |||
| 103 | int nv3_test_vsync(struct sh_pci_device *dev) { |
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| 104 | return readl(dev->iobase+0x400100)&0x100; |
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| 105 | } |
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| 106 | |||
| 107 | void nv3_ack_vsync(struct sh_pci_device *dev) { |
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| 108 | |||
| 109 | /* disable interrupt, clear pending */ |
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| 110 | writel(0xffffffff, dev->iobase + 0x000100); |
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| 111 | writel(0x100, dev->iobase + 0x400100); |
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| 112 | writel(0, dev->iobase + 0x000140); |
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| 113 | writel(0, dev->iobase + 0x400140); |
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| 114 | writel(saved_pmc, dev->iobase + 0x000200); |
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| 115 | |||
| 116 | } |
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| 117 | |||
| 118 | void nv3_enable_vsync(struct sh_pci_device *dev) { |
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| 119 | saved_pmc = inl(dev->iobase + 0x200); |
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| 120 | writel(saved_pmc|0x1000, dev->iobase+0x200); |
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| 121 | writel(0x1, dev->iobase + 0x000140); |
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| 122 | writel(0x100, dev->iobase + 0x400140); |
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| 123 | writel(0xffffffff, dev->iobase + 0x000100); |
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| 124 | writel(0xffffffff, dev->iobase + 0x400100); |
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| 125 | } |
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| 126 | |||
| 127 | int nv4_test_vsync(struct sh_pci_device *dev) { |
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| 128 | return readl(dev->iobase+0x600100)&0x1; |
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| 129 | } |
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| 130 | |||
| 131 | void nv4_ack_vsync(struct sh_pci_device *dev) { |
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| 132 | |||
| 133 | /* disable interrupt, clear pending */ |
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| 134 | writel(0xffffffff, dev->iobase + 0x000100); |
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| 135 | writel(0x1, dev->iobase + 0x600100); |
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| 136 | writel(0, dev->iobase + 0x000140); |
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| 137 | writel(0, dev->iobase + 0x600140); |
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| 138 | writel(saved_pmc, dev->iobase + 0x000200); |
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| 139 | } |
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| 140 | |||
| 141 | void nv4_enable_vsync(struct sh_pci_device *dev) { |
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| 142 | saved_pmc = inl(dev->iobase + 0x200); |
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| 143 | writel(saved_pmc|(1<<24),dev->iobase+0x200); |
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| 144 | writel(0x1, dev->iobase + 0x000140); |
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| 145 | writel(0x1, dev->iobase + 0x600140); |
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| 146 | writel(0xffffffff, dev->iobase + 0x000100); |
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| 147 | writel(0xffffffff, dev->iobase + 0x600100); |
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| 148 | } |
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| 149 | |||
| 150 | int r128_test_vsync(struct sh_pci_device *dev) { |
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| 151 | return readl(dev->iobase + 0x44) &1; |
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| 152 | } |
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| 153 | |||
| 154 | void r128_ack_vsync(struct sh_pci_device *dev) { |
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| 155 | writel(1, dev->iobase + 0x44); |
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| 156 | writel(readl(dev->iobase + 0x40) & 0xfffffffe, dev->iobase + 0x40); |
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| 157 | } |
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| 158 | |||
| 159 | void r128_enable_vsync(struct sh_pci_device *dev) { |
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| 160 | writel(1, dev->iobase + 0x44); |
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| 161 | writel(readl(dev->iobase + 0x40) | 1, dev->iobase + 0x40); |
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| 162 | } |
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| 163 | |||
| 164 | int rage_test_vsync(struct sh_pci_device *dev) { |
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| 165 | return inl(dev->iobase + 0x18) &4; |
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| 166 | } |
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| 167 | |||
| 168 | void rage_ack_vsync(struct sh_pci_device *dev) { |
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| 169 | outl((inl(dev->iobase + 0x18) & 0xfffffff8) | 4, dev->iobase + 0x18); |
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| 170 | } |
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| 171 | |||
| 172 | void rage_enable_vsync(struct sh_pci_device *dev) { |
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| 173 | outl((inl(dev->iobase + 0x18) & 0xfffffff8) | 6, dev->iobase + 0x18); |
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| 174 | } |
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| 175 | |||
| 176 | int rendition_test_vsync(struct sh_pci_device *dev) { |
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| 177 | return inw(dev->iobase + 0x44) & 1; |
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| 178 | } |
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| 179 | |||
| 180 | void rendition_ack_vsync(struct sh_pci_device *dev) { |
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| 181 | outw(1, dev->iobase + 0x44); |
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| 182 | outw(0, dev->iobase + 0x46); |
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| 183 | } |
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| 184 | |||
| 185 | void rendition_enable_vsync(struct sh_pci_device *dev) { |
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| 186 | outw(1, dev->iobase + 0x44); |
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| 187 | outw(1, dev->iobase + 0x46); |
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| 188 | } |
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| 189 | |||
| 190 | void vga_init_vsync(struct sh_pci_device *dev) { |
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| 191 | int i, id; |
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| 192 | switch(dev->vendor) { |
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| 193 | case PCI_VENDOR_ID_MATROX: |
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| 194 | i=0; |
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| 195 | if(dev->len[0]>=1048576)i=1; |
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| 196 | dev->iobase = (unsigned long)ioremap(dev->mem[i],0x2000) + 0x1c00; |
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| 197 | dev->test_vsync = mm_test_vsync; |
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| 198 | dev->ack_vsync = mm_ack_vsync; |
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| 199 | dev->enable_vsync = mm_enable_vsync; |
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| 200 | break; |
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| 201 | case PCI_VENDOR_ID_SI: /* SiS */ |
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| 202 | dev->iobase = dev->mem[2]-0x380; |
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| 203 | dev->test_vsync = io_test_vsync; |
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| 204 | dev->ack_vsync = io_ack_vsync; |
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| 205 | dev->enable_vsync = io_enable_vsync; |
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| 206 | break; |
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| 207 | case PCI_VENDOR_ID_NVIDIA_SGS: |
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| 208 | dev->iobase = (unsigned long)ioremap(dev->mem[0],0x800000); |
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| 209 | if(dev->id<0x20) { |
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| 210 | dev->test_vsync = nv3_test_vsync; |
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| 211 | dev->ack_vsync = nv3_ack_vsync; |
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| 212 | dev->enable_vsync = nv3_enable_vsync; |
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| 213 | } else { |
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| 214 | dev->test_vsync = nv4_test_vsync; |
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| 215 | dev->ack_vsync = nv4_ack_vsync; |
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| 216 | dev->enable_vsync = nv4_enable_vsync; |
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| 217 | } |
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| 218 | break; |
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| 219 | case PCI_VENDOR_ID_NVIDIA: |
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| 220 | dev->iobase = (unsigned long)ioremap(dev->mem[0],0x800000); |
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| 221 | dev->test_vsync = nv4_test_vsync; |
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| 222 | dev->ack_vsync = nv4_ack_vsync; |
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| 223 | dev->enable_vsync = nv4_enable_vsync; |
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| 224 | break; |
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| 225 | case PCI_VENDOR_ID_ATI: |
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| 226 | id=dev->id; |
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| 227 | |||
| 228 | if( (id==0x4c45) || |
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| 229 | (id==0x4c56) || |
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| 230 | (id==0x4d46) || |
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| 231 | (id==0x4d4c) || |
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| 232 | ((id>>8)==0x50) || |
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| 233 | ((id>>8)==0x52) || |
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| 234 | ((id>>8)==0x53) || |
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| 235 | ((id>>8)==0x54)) { |
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| 236 | dev->iobase = (unsigned long)ioremap(dev->mem[2], 16384); |
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| 237 | dev->test_vsync = r128_test_vsync; |
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| 238 | dev->ack_vsync = r128_ack_vsync; |
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| 239 | dev->enable_vsync = r128_enable_vsync; |
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| 240 | } else |
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| 241 | if( (id==0x4242) || |
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| 242 | (id==0x4c57) || |
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| 243 | (id==0x4c59) || |
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| 244 | (id==0x4c5a) || |
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| 245 | ((id>>8)==0x51)) { |
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| 246 | dev->iobase = (unsigned long)ioremap(dev->mem[2], 16384); |
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| 247 | dev->test_vsync = r128_test_vsync; |
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| 248 | dev->ack_vsync = r128_ack_vsync; |
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| 249 | dev->enable_vsync = r128_enable_vsync; |
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| 250 | } else { |
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| 251 | dev->iobase = dev->mem[1]; |
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| 252 | dev->test_vsync = rage_test_vsync; |
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| 253 | dev->ack_vsync = rage_ack_vsync; |
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| 254 | dev->enable_vsync = rage_enable_vsync; |
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| 255 | |||
| 256 | } |
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| 257 | break; |
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| 258 | case PCI_VENDOR_ID_RENDITION: |
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| 259 | dev->iobase = dev->mem[1]; |
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| 260 | dev->test_vsync = rendition_test_vsync; |
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| 261 | dev->ack_vsync = rendition_ack_vsync; |
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| 262 | dev->enable_vsync = rendition_enable_vsync; |
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| 263 | break; |
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| 264 | default: |
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| 265 | dev->test_vsync = vga_test_vsync; |
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| 266 | dev->ack_vsync = vga_ack_vsync; |
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| 267 | dev->enable_vsync = vga_enable_vsync; |
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| 268 | dev->iobase = 0; |
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| 269 | } |
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| 270 | |||
| 271 | } |
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| 272 |