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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 54 | pj | 1 | |
| 2 | #include "timing.h" |
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| 3 | #include "vgaregs.h" |
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| 4 | |||
| 5 | |||
| 6 | /* |
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| 7 | * Setup VGA registers for SVGA mode timing. Adapted from XFree86, |
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| 8 | * vga256/vga/vgaHW.c vgaHWInit(). |
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| 9 | * |
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| 10 | * Note that VGA registers are set up in a way that is common for |
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| 11 | * SVGA modes. This is not particularly useful for standard VGA |
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| 12 | * modes, since VGA does not have a clean packed-pixel mode. |
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| 13 | */ |
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| 14 | |||
| 15 | void __svgalib_setup_VGA_registers(unsigned char *moderegs, ModeTiming * modetiming, |
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| 16 | ModeInfo * modeinfo) |
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| 17 | { |
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| 18 | int i; |
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| 19 | /* Sync Polarities */ |
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| 20 | if ((modetiming->flags & (PHSYNC | NHSYNC)) && |
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| 21 | (modetiming->flags & (PVSYNC | NVSYNC))) { |
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| 22 | /* |
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| 23 | * If both horizontal and vertical polarity are specified, |
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| 24 | * set them as specified. |
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| 25 | */ |
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| 26 | moderegs[VGA_MISCOUTPUT] = 0x23; |
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| 27 | if (modetiming->flags & NHSYNC) |
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| 28 | moderegs[VGA_MISCOUTPUT] |= 0x40; |
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| 29 | if (modetiming->flags & NVSYNC) |
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| 30 | moderegs[VGA_MISCOUTPUT] |= 0x80; |
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| 31 | } else { |
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| 32 | /* |
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| 33 | * Otherwise, calculate the polarities according to |
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| 34 | * monitor standards. |
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| 35 | */ |
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| 36 | if (modetiming->VDisplay < 400) |
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| 37 | moderegs[VGA_MISCOUTPUT] = 0xA3; |
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| 38 | else if (modetiming->VDisplay < 480) |
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| 39 | moderegs[VGA_MISCOUTPUT] = 0x63; |
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| 40 | else if (modetiming->VDisplay < 768) |
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| 41 | moderegs[VGA_MISCOUTPUT] = 0xE3; |
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| 42 | else |
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| 43 | moderegs[VGA_MISCOUTPUT] = 0x23; |
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| 44 | } |
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| 45 | |||
| 46 | /* Sequencer */ |
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| 47 | moderegs[VGA_SR0] = 0x00; |
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| 48 | if (modeinfo->bitsPerPixel == 4) |
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| 49 | moderegs[VGA_SR0] = 0x02; |
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| 50 | moderegs[VGA_SR1] = 0x01; |
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| 51 | moderegs[VGA_SR2] = 0x0F; /* Bitplanes. */ |
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| 52 | moderegs[VGA_SR3] = 0x00; |
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| 53 | moderegs[VGA_SR4] = 0x0E; |
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| 54 | if (modeinfo->bitsPerPixel == 4) |
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| 55 | moderegs[VGA_SR4] = 0x06; |
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| 56 | |||
| 57 | /* CRTC Timing */ |
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| 58 | moderegs[VGA_CR0] = (modetiming->CrtcHTotal / 8) - 5; |
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| 59 | moderegs[VGA_CR1] = (modetiming->CrtcHDisplay / 8) - 1; |
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| 60 | moderegs[VGA_CR2] = (modetiming->CrtcHSyncStart / 8) - 1; |
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| 61 | moderegs[VGA_CR3] = ((modetiming->CrtcHSyncEnd / 8) & 0x1F) | 0x80; |
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| 62 | moderegs[VGA_CR4] = (modetiming->CrtcHSyncStart / 8); |
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| 63 | moderegs[VGA_CR5] = (((modetiming->CrtcHSyncEnd / 8) & 0x20) << 2) |
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| 64 | | ((modetiming->CrtcHSyncEnd / 8) & 0x1F); |
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| 65 | moderegs[VGA_CR6] = (modetiming->CrtcVTotal - 2) & 0xFF; |
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| 66 | moderegs[VGA_CR7] = (((modetiming->CrtcVTotal - 2) & 0x100) >> 8) |
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| 67 | | (((modetiming->CrtcVDisplay - 1) & 0x100) >> 7) |
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| 68 | | ((modetiming->CrtcVSyncStart & 0x100) >> 6) |
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| 69 | | (((modetiming->CrtcVSyncStart) & 0x100) >> 5) |
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| 70 | | 0x10 |
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| 71 | | (((modetiming->CrtcVTotal - 2) & 0x200) >> 4) |
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| 72 | | (((modetiming->CrtcVDisplay - 1) & 0x200) >> 3) |
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| 73 | | ((modetiming->CrtcVSyncStart & 0x200) >> 2); |
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| 74 | moderegs[VGA_CR8] = 0x00; |
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| 75 | moderegs[VGA_CR9] = ((modetiming->CrtcVSyncStart & 0x200) >> 4) | 0x40; |
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| 76 | if (modetiming->flags & DOUBLESCAN) |
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| 77 | moderegs[VGA_CR9] |= 0x80; |
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| 78 | moderegs[VGA_CRA] = 0x00; |
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| 79 | moderegs[VGA_CRB] = 0x00; |
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| 80 | moderegs[VGA_CRC] = 0x00; |
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| 81 | moderegs[VGA_CRD] = 0x00; |
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| 82 | moderegs[VGA_CRE] = 0x00; |
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| 83 | moderegs[VGA_CRF] = 0x00; |
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| 84 | moderegs[VGA_CR10] = modetiming->CrtcVSyncStart & 0xFF; |
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| 85 | moderegs[VGA_CR11] = (modetiming->CrtcVSyncEnd & 0x0F) | 0x20; |
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| 86 | moderegs[VGA_CR12] = (modetiming->CrtcVDisplay - 1) & 0xFF; |
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| 87 | moderegs[VGA_CR13] = modeinfo->lineWidth >> 4; /* Just a guess. */ |
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| 88 | moderegs[VGA_CR14] = 0x00; |
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| 89 | moderegs[VGA_CR15] = modetiming->CrtcVSyncStart & 0xFF; |
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| 90 | moderegs[VGA_CR16] = (modetiming->CrtcVSyncStart + 1) & 0xFF; |
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| 91 | moderegs[VGA_CR17] = 0xC3; |
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| 92 | if (modeinfo->bitsPerPixel == 4) |
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| 93 | moderegs[VGA_CR17] = 0xE3; |
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| 94 | moderegs[VGA_CR18] = 0xFF; |
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| 95 | |||
| 96 | /* Graphics Controller */ |
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| 97 | moderegs[VGA_GR0] = 0x00; |
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| 98 | moderegs[VGA_GR1] = 0x00; |
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| 99 | moderegs[VGA_GR2] = 0x00; |
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| 100 | moderegs[VGA_GR3] = 0x00; |
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| 101 | moderegs[VGA_GR4] = 0x00; |
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| 102 | moderegs[VGA_GR5] = 0x40; |
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| 103 | if (modeinfo->bitsPerPixel == 4) |
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| 104 | moderegs[VGA_GR5] = 0x02; |
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| 105 | moderegs[VGA_GR6] = 0x05; |
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| 106 | moderegs[VGA_GR7] = 0x0F; |
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| 107 | moderegs[VGA_GR8] = 0xFF; |
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| 108 | |||
| 109 | /* Attribute Controller */ |
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| 110 | for (i = 0; i < 16; i++) |
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| 111 | moderegs[VGA_AR0 + i] = i; |
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| 112 | moderegs[VGA_AR10] = 0x41; |
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| 113 | if (modeinfo->bitsPerPixel == 4) |
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| 114 | moderegs[VGA_AR10] = 0x01; /* was 0x81 */ |
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| 115 | /* Attribute register 0x11 is the overscan color. |
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| 116 | Should have no affect in svga modes. */ |
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| 117 | moderegs[VGA_AR11] = 0x00; |
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| 118 | moderegs[VGA_AR12] = 0x0F; |
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| 119 | moderegs[VGA_AR13] = 0x00; |
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| 120 | moderegs[VGA_AR14] = 0x00; |
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| 121 | } |
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| 122 |