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2 pj 1
/* Project:     OSLib
2
 * Description: The OS Construction Kit
3
 * Date:                1.6.2000
4
 * Idea by:             Luca Abeni & Gerardo Lamastra
5
 *
6
 * OSLib is an SO project aimed at developing a common, easy-to-use
7
 * low-level infrastructure for developing OS kernels and Embedded
8
 * Applications; it partially derives from the HARTIK project but it
9
 * currently is independently developed.
10
 *
11
 * OSLib is distributed under GPL License, and some of its code has
12
 * been derived from the Linux kernel source; also some important
13
 * ideas come from studying the DJGPP go32 extender.
14
 *
15
 * We acknowledge the Linux Community, Free Software Foundation,
16
 * D.J. Delorie and all the other developers who believe in the
17
 * freedom of software and ideas.
18
 *
19
 * For legalese, check out the included GPL license.
20
 */
21
 
22
/* File: Vm86.C
23
 *                             
24
 * VM86 mode switch routines!
25
 * This is basically an alternative way of invoking the
26
 * BIOS service routines; it is very useful to support
27
 * native VBE compliant Video card, without writing an explicit driver
28
 */
29
 
40 pj 30
#include <ll/i386/hw-data.h>
31
#include <ll/i386/hw-instr.h>
32
#include <ll/i386/hw-func.h>
2 pj 33
#include <ll/i386/mem.h>
34
#include <ll/i386/x-bios.h>
40 pj 35
#include <ll/i386/x-dosmem.h>
2 pj 36
#include <ll/i386/cons.h>
37
#include <ll/i386/error.h>
38
 
40 pj 39
FILE(VM-86);
2 pj 40
 
41
/*
42
#define __LL_DEBUG__
43
#define __DUMB_CODE__
44
#define __CHK_IO__
45
*/
46
 
443 giacomo 47
//#define __LL_DEBUG__
313 giacomo 48
 
444 giacomo 49
#define VM86_STACK_SIZE 8192 
2 pj 50
 
40 pj 51
extern DWORD ll_irq_table[256];
52
 
2 pj 53
/* TSS optional section */
40 pj 54
static BYTE  vm86_stack0[VM86_STACK_SIZE];
2 pj 55
 
56
static struct {
57
    TSS t;
58
    DWORD io_map[2048];
59
} vm86_TSS;
60
static LIN_ADDR vm86_stack;
61
static LIN_ADDR vm86_iretAddress;
62
 
40 pj 63
struct registers *global_regs;
443 giacomo 64
WORD   VM86_ret_ctx;
2 pj 65
 
66
#ifdef __DUMB_CODE__
67
static LIN_ADDR vm86_code;
68
static BYTE prova86[] = {
40 pj 69
                        0x1e,                   /* push ds              */
70
                        0xb8,0x00,0xb8,         /* mov ax,0xb800        */
71
                        0x8e,0xd8,              /* mov ds,ax            */
72
                        0xbf,0x9e,0x00,         /* mov di,0x009e (158)  */
73
                        0xb0,0x2a,              /* mov ax,'*'           */
74
                        0x88,0x05,              /* mov ds:[di],al       */
75
                        0x1f,                   /* pop ds               */
76
                        0xcd, 0x40,             /*???*/
77
#ifdef __CHK_IO__               
78
                        0xb0, 0x00,             /* movb   $0x0,%al*/
79
                        0x66,0xba, 0x80, 0x00,  /* movw   $0x80,%dx */
80
                        0x66,0xef,              /* outw %ax, (%dx) */
81
#endif          
82
                        0xcf,                   /* iret                 */
83
                        0xf4,                   /* hlt                  */
84
                        0};    
2 pj 85
#endif
86
 
444 giacomo 87
static BYTE vm86_retAddr[] = {0xcd, 0x48,       /* int 48h              */
88
                              0xf4,
89
                              0};
2 pj 90
 
40 pj 91
TSS *vm86_get_tss(void)
92
{
93
    return &(vm86_TSS.t);
94
}
95
 
2 pj 96
/* Just a debugging function; it dumps the status of the TSS */
97
void vm86_dump_TSS(void)
98
{
40 pj 99
    BYTE acc,gran;
100
    DWORD base,lim;
2 pj 101
    message("vm86_TSS.t dump\n");
40 pj 102
    message("Flag: %lx\n",vm86_TSS.t.eflags);
103
    message("SS: %hx SP:%lx\n", vm86_TSS.t.ss,vm86_TSS.t.esp);
104
    message("Stack0: %hx:%lx\n",vm86_TSS.t.ss0,vm86_TSS.t.esp0);
105
    message("Stack1: %hx:%lx\n",vm86_TSS.t.ss1,vm86_TSS.t.esp1);
106
    message("Stack2: %hx:%lx\n",vm86_TSS.t.ss2,vm86_TSS.t.esp2);
107
    message("CS: %hx IP: %lx",vm86_TSS.t.cs, vm86_TSS.t.eip);
108
    message("DS: %hx\n",vm86_TSS.t.ds);
109
    base = GDT_read(X_VM86_TSS,&lim,&acc,&gran);
2 pj 110
    message("Base : %lx Lim : %lx Acc : %x Gran %x\n",
40 pj 111
                    base,lim,(unsigned)(acc),(unsigned)(gran));
2 pj 112
}
113
 
114
void vm86_init(void)
115
{
116
    int register i;
40 pj 117
 
2 pj 118
    /* First of all, we need to setup a GDT entries to
119
     * allow vm86 task execution. We just need a free 386 TSS, which
120
     * will be used to store the execution context of the virtual 8086
121
     * task
122
     */
40 pj 123
    GDT_place(X_VM86_TSS,(DWORD)(&vm86_TSS),
124
              sizeof(vm86_TSS),FREE_TSS386,GRAN_16);
2 pj 125
 
443 giacomo 126
    /* Return Registers */
127
    global_regs = DOS_alloc(sizeof(struct registers));
40 pj 128
 
2 pj 129
    /* Prepare a real-mode stack, obtaining it from the
130
     * DOS memory allocator!
131
     * 8K should be OK! Stack top is vm86_stack + SIZE!
132
     */
40 pj 133
    vm86_stack = DOS_alloc(VM86_STACK_SIZE*2);
134
    vm86_stack += VM86_STACK_SIZE/2;
135
 
2 pj 136
    vm86_iretAddress = DOS_alloc(sizeof(vm86_retAddr));
40 pj 137
    memcpy(vm86_iretAddress,vm86_retAddr,sizeof(vm86_retAddr));
2 pj 138
#ifdef __LL_DEBUG__
40 pj 139
    message("PM reentry linear address=0x%lx\n", (DWORD)vm86_iretAddress);
2 pj 140
#endif
141
#ifdef __DUMB_CODE__
142
    vm86_code = DOS_alloc(2048);
40 pj 143
    lmemcpy(vm86_code,prova86,sizeof(prova86));
2 pj 144
#endif
145
    /* Zero the PM/Ring[1,2] ss:esp; they're unused! */
146
    vm86_TSS.t.esp1 = 0;
147
    vm86_TSS.t.esp2 = 0;
148
    vm86_TSS.t.ss1 = 0;
149
    vm86_TSS.t.ss2 = 0;
150
    /* Use only the GDT */
151
    vm86_TSS.t.ldt = 0;
152
    /* No paging activated */
153
    vm86_TSS.t.cr3 = 0;
154
    vm86_TSS.t.trap = 0;
155
    /* Yeah, free access to any I/O port; we trust BIOS anyway! */
156
    /* Here is the explanation: we have 65536 I/O ports... each bit
157
     * in the io_map masks/unmasks the exception for the given I/O port
158
     * If the bit is set, an exception is generated; otherwise, if the bit
159
     * is clear, everythings works fine...
160
     * Because of alignment problem, we need to add an extra byte all set
161
     * to 1, according to Intel manuals
162
     */
40 pj 163
    vm86_TSS.t.io_base = (DWORD)(&(vm86_TSS.io_map)) -
164
                        (DWORD)(&(vm86_TSS));
165
    for (i = 0; i < 2047; i++) vm86_TSS.io_map[i] = 0;
2 pj 166
    vm86_TSS.io_map[2047] = 0xFF000000;
167
}
168
 
40 pj 169
int vm86_callBIOS(int service,X_REGS16 *in,X_REGS16 *out,X_SREGS16 *s)
2 pj 170
{
171
    DWORD vm86_tmpAddr;
40 pj 172
    DWORD vm86_flags, vm86_cs,vm86_ip;
2 pj 173
    LIN_ADDR vm86_stackPtr;
174
    DWORD *IRQTable_entry;
444 giacomo 175
    BYTE p1,p2;
443 giacomo 176
 
177
    SYS_FLAGS f;
444 giacomo 178
 
443 giacomo 179
    if (service < 0x10 || in == NULL) return -1;
40 pj 180
 
443 giacomo 181
    f = ll_fsave();
182
 
2 pj 183
    /* Setup the stack frame */
40 pj 184
    vm86_tmpAddr = (DWORD)(vm86_stack);
2 pj 185
    vm86_TSS.t.ss = (vm86_tmpAddr & 0xFF000) >> 4;
186
    vm86_TSS.t.ebp = vm86_TSS.t.esp = (vm86_tmpAddr & 0x0FFF)
40 pj 187
                + VM86_STACK_SIZE - 6;
2 pj 188
    /* Build an iret stack frame which returns to vm86_iretAddress */
40 pj 189
    vm86_tmpAddr = (DWORD)(vm86_iretAddress);
2 pj 190
    vm86_cs = (vm86_tmpAddr & 0xFF000) >> 4;
191
    vm86_ip = (vm86_tmpAddr & 0xFFF);
444 giacomo 192
    vm86_flags = 0;
2 pj 193
    vm86_stackPtr = vm86_stack + VM86_STACK_SIZE;
40 pj 194
    lmempokew(vm86_stackPtr-6,vm86_ip);
195
    lmempokew(vm86_stackPtr-4,vm86_cs);
196
    lmempokew(vm86_stackPtr-2,vm86_flags);
2 pj 197
#ifdef __LL_DEBUG__
198
    message("Stack: %lx SS: %lx SP: %lx\n",
40 pj 199
        vm86_tmpAddr + VM86_STACK_SIZE,(DWORD)vm86_TSS.t.ss,vm86_TSS.t.esp);
2 pj 200
#endif
201
    /* Wanted VM86 mode + IOPL = 3! */
443 giacomo 202
    vm86_TSS.t.eflags = CPU_FLAG_VM + CPU_FLAG_IOPL;
2 pj 203
    /* Preload some standard values into the registers */
204
    vm86_TSS.t.ss0 = X_FLATDATA_SEL;
40 pj 205
    vm86_TSS.t.esp0 = (DWORD)&(vm86_stack0[VM86_STACK_SIZE-1]);
206
 
2 pj 207
#ifdef __DUMB_CODE__
40 pj 208
    vm86_TSS.t.cs = ((DWORD)(vm86_code) & 0xFFFF0) >> 4;
209
    vm86_TSS.t.eip = ((DWORD)(vm86_code) & 0x000F);
2 pj 210
#ifdef __LL_DEBUG_
211
    message("(DUMB CODE) CS:%x IP:%x/%x\n",
40 pj 212
        (DWORD)vm86_TSS.t.cs,vm86_TSS.t.eip,&prova86);
2 pj 213
    message("(DUMB CODE) Go...\n");
214
#endif
443 giacomo 215
 
216
    p1 = inp(0x21);
217
    p2 = inp(0xA1);
218
    outp(0x21,0xFF);
219
    outp(0xA1,0xFF);
444 giacomo 220
 
221
    vm86_TSS.t.back_link = ll_context_save();
222
    VM86_ret_ctx = vm86_TSS.t.back_link
2 pj 223
    ll_context_load(X_VM86_TSS);
224
 
443 giacomo 225
    outp(0x21,p1);
226
    outp(0xA1,p2);
227
 
2 pj 228
#ifdef __LL_DEBUG_
229
    message("(DUMB CODE) I am back...\n");
230
#endif
231
#else
232
    /* Copy the parms from the X_*REGS structures in the vm86 TSS */
40 pj 233
    vm86_TSS.t.eax = (DWORD)in->x.ax;
234
    vm86_TSS.t.ebx = (DWORD)in->x.bx;
235
    vm86_TSS.t.ecx = (DWORD)in->x.cx;
236
    vm86_TSS.t.edx = (DWORD)in->x.dx;
237
    vm86_TSS.t.esi = (DWORD)in->x.si;
238
    vm86_TSS.t.edi = (DWORD)in->x.di;
2 pj 239
    /* IF Segment registers are required, copy them... */
240
    if (s != NULL) {
40 pj 241
        vm86_TSS.t.es = (WORD)s->es;
242
        vm86_TSS.t.ds = (WORD)s->ds;
2 pj 243
    } else {
40 pj 244
        vm86_TSS.t.ds = vm86_TSS.t.ss;
245
        vm86_TSS.t.es = vm86_TSS.t.ss;
2 pj 246
    }
40 pj 247
    vm86_TSS.t.gs = vm86_TSS.t.ss;
248
    vm86_TSS.t.fs = vm86_TSS.t.ss;
2 pj 249
    /* Execute the BIOS call, fetching the CS:IP of the real interrupt
250
     * handler from 0:0 (DOS irq table!)
251
     */
40 pj 252
    IRQTable_entry = (void *)(0L);
253
    vm86_TSS.t.cs= ((IRQTable_entry[service]) & 0xFFFF0000) >> 16;
2 pj 254
    vm86_TSS.t.eip = ((IRQTable_entry[service]) & 0x0000FFFF);
40 pj 255
#ifdef __LL_DEBUG__    
256
    message("CS:%x IP:%lx\n", vm86_TSS.t.cs, vm86_TSS.t.eip);
2 pj 257
#endif
258
    /* Let's use the ll standard call... */
443 giacomo 259
 
260
    p1 = inp(0x21);
261
    p2 = inp(0xA1);
262
    outp(0x21,0xFF);
263
    outp(0xA1,0xFF);
444 giacomo 264
 
265
    vm86_TSS.t.back_link = ll_context_save();
266
    VM86_ret_ctx = vm86_TSS.t.back_link;    
443 giacomo 267
    sti();
2 pj 268
    ll_context_load(X_VM86_TSS);
443 giacomo 269
 
270
    outp(0x21,p1);
271
    outp(0xA1,p2);
272
 
40 pj 273
#ifdef __LL_DEBUG__    
2 pj 274
    message("I am back...\n");
275
    message("TSS CS=%hx IP=%lx\n", vm86_TSS.t.cs, vm86_TSS.t.eip);
276
#endif
277
    /* Send back in the X_*REGS structure the value obtained with
278
     * the real-mode interrupt call
279
     */
280
    if (out != NULL) {
443 giacomo 281
 
40 pj 282
      out->x.ax = global_regs->eax;
283
      out->x.bx = global_regs->ebx;
284
      out->x.cx = global_regs->ecx;
285
      out->x.dx = global_regs->edx;
286
      out->x.si = global_regs->esi;
287
      out->x.di = global_regs->edi;
288
      out->x.cflag = global_regs->flags;
443 giacomo 289
 
290
      //message("ax = %d bx = %d cx = %d dx = %d\n",out->x.ax,out->x.bx,out->x.cx,out->x.dx);
291
      //message("si = %d di = %d\n",out->x.si,out->x.di);
292
 
2 pj 293
    }
294
    if (s != NULL) {
40 pj 295
      s->es = vm86_TSS.t.es;
296
      s->ds = vm86_TSS.t.ds;
2 pj 297
    }
298
#endif
443 giacomo 299
 
444 giacomo 300
    ll_frestore(f);
443 giacomo 301
 
444 giacomo 302
    return 1;
303
 
2 pj 304
}