/shark/trunk/distrib/dos/install.bat |
---|
File deleted |
/shark/trunk/distrib/dos/myfilter.c |
---|
File deleted |
/shark/trunk/distrib/mdistrib |
---|
File deleted |
Property changes: |
Deleted: svn:executable |
## -1 +0,0 ## |
-* |
\ No newline at end of property |
Index: trunk/config/libdep.mk |
=================================================================== |
--- trunk/config/libdep.mk (revision 587) |
+++ trunk/config/libdep.mk (revision 588) |
@@ -34,15 +34,15 @@ |
endif |
-# newpci |
+# PCI |
# ---------------------------------------------------------------- |
-ifeq ($(findstring __NEWPCI__,$(USELIB)) , __NEWPCI__) |
+ifeq ($(findstring __PCI__,$(USELIB)) , __PCI__) |
-INCL += -I$(BASE)/drivers/newpci/include -I$(BASE)/drivers/linuxc26/include |
+INCL += -I$(BASE)/drivers/pci/include -I$(BASE)/drivers/linuxc26/include |
-ifeq ($(LIB_PATH)/libnewpci.a,$(wildcard $(LIB_PATH)/libnewpci.a)) |
-LINK_LIB += -lnewpci |
-LIB_DEP += $(LIB_PATH)/libnewpci.a |
+ifeq ($(LIB_PATH)/libpci.a,$(wildcard $(LIB_PATH)/libpci.a)) |
+LINK_LIB += -lpci |
+LIB_DEP += $(LIB_PATH)/libpci.a |
endif |
# newnet |
@@ -53,10 +53,10 @@ |
else |
-# HPCI |
-ifeq ($(LIB_PATH)/libhpci.a,$(wildcard $(LIB_PATH)/libhpci.a)) |
-LINK_LIB += -lhpci |
-LIB_DEP += $(LIB_PATH)/libhpci.a |
+# OLDPCI |
+ifeq ($(LIB_PATH)/liboldpci.a,$(wildcard $(LIB_PATH)/liboldpci.a)) |
+LINK_LIB += -loldpci |
+LIB_DEP += $(LIB_PATH)/liboldpci.a |
endif |
# hnet |
@@ -254,20 +254,6 @@ |
endif |
-# SVGA |
-# ---------------------------------------------------------------- |
-ifeq ($(findstring __SVGA__,$(USELIB)) , __SVGA__) |
- |
-INCL += -I$(BASE)/drivers/svga/include |
- |
-ifeq ($(LIB_PATH)/libsvga.a,$(wildcard $(LIB_PATH)/libsvga.a)) |
-LINK_LIB += -lsvga |
-LIB_DEP += $(LIB_PATH)/libsvga.a |
-endif |
- |
-endif |
- |
- |
# PCLAB |
# ---------------------------------------------------------------- |
ifeq ($(findstring __PCLAB__,$(USELIB)) , __PCLAB__) |
/shark/trunk/config/mk/gnu.mk |
---|
6,13 → 6,6 |
LD = ld |
AR = ar |
ifeq ($(TSC),TRUE) |
CFG_OPT += -D__TSC__ |
ifeq ($(APIC),TRUE) |
CFG_OPT += -D__APIC__ |
endif |
endif |
INCL = $(BASE)/include |
LIB_PATH = $(BASE)/lib |
OSLIB = $(BASE)/oslib |
23,10 → 16,24 |
LIBRARYDIR= $(LIB_PATH) |
LIBRARYOBJS= $(LIB_OBJS) |
#LIBRARYPATHNAME= $(subst /,\,$(LIB_PATH)/lib$(LIBRARY).a) |
#LIBRARYDIR= $(subst /,\,$(LIB_PATH)) |
#LIBRARYOBJS= $(subst /,\,$(LIB_OBJS)) |
ifeq ($(findstring LINUX,$(ENV)) , LINUX) |
CFG_OPT += -D__LINUX__ |
endif |
ifeq ($(findstring DJGPP,$(ENV)) , DJGPP) |
CFG_OPT += -D__GNU__ |
endif |
ifeq ($(TSC),TRUE) |
CFG_OPT += -D__TSC__ |
ifeq ($(APIC),TRUE) |
CFG_OPT += -D__APIC__ |
endif |
endif |
ifeq ($(findstring VM86,$(BIOS)) , VM86) |
CFG_OPT += -DVM86 |
endif |
ifeq ($(findstring NEW,$(TRACER)) , NEW) |
CFG_OPT += -D__NEW_TRACER__ |
endif |
35,21 → 42,29 |
endif |
INCL += -I$(BASE)/tracer/include |
ifeq ($(findstring VM86,$(BIOS)) , VM86) |
CFG_OPT += -DVM86 |
ifeq ($(findstring VESA,$(FB)) , VESA) |
CFG_VIDEO_OPT += -DCONFIG_FB_VESA -DCONFIG_LOGO |
endif |
ifeq ($(findstring FINDPCI,$(FB)) , FINDPCI) |
CFG_VIDEO_OPT += -DCONFIG_FB_RIVA -DCONFIG_FB_RADEON -DCONFIG_FB_MATROX\ |
-DCONFIG_LOGO -DCONFIG_FB_MATROX_G100 -DCONFIG_FB_MATROX_MILLENIUM\ |
-DCONFIG_FB_MATROX_MYSTIQUE |
endif |
ifeq ($(findstring VGA16,$(FB)) , VGA16) |
CFG_VIDEO_OPT += -DCONFIG_FB_VGA16 |
endif |
C_WARN = -Wimplicit-function-declaration -Wall |
C_FLAGS = -O -fno-builtin -nostdinc |
C_INC = -I$(INCL) $(OTHERINCL) -I$(OSLIB) |
C_MAC = -D__GNU__ $(CFG_OPT) |
C_MAC = $(CFG_OPT) |
ASM_WARN = |
ASM_FLAGS = -x assembler-with-cpp |
ASM_INC = -I$(INCL) -I$(OSLIB) |
ASM_MAC = -D__GNU__ $(CFG_OPT) |
ASM_INC = -I$(INCL) $(OTHERINCL) -I$(OSLIB) |
ASM_MAC = $(CFG_OPT) |
LINK_OPT = -Bstatic -Ttext $(MEM_START) -b coff-go32 --oformat coff-go32 -s -nostartfiles -nostdlib -L$(LIB_PATH) -L$(OSLIB_PATH) |
LINK_OPT = -Bstatic -Ttext $(MEM_START) -s -nostartfiles -nostdlib -L$(LIB_PATH) -L$(OSLIB_PATH) |
C_OPT = $(C_DEF) $(C_WARN) $(C_INC) $(C_MAC) $(C_FLAGS) |
C_OUTPUT = -o $*.o |
57,17 → 72,14 |
ASM_OPT = $(ASM_DEF) $(ASM_WARN) $(ASM_INC) $(ASM_MAC) $(ASM_FLAGS) |
ASM_OUTPUT = -o $*.o |
MKDIR = md |
MKDIR = mkdir |
CP = cp |
CAT = @type |
CAT = cat |
RM = rm -f |
CD = cd |
#REDIR=redir -e $(*F).err |
REDIR= |
# Common rules |
# Common rules |
%.o : %.s |
$(REDIR) $(CC) $(ASM_OPT) $(ASM_OUTPUT) -c $< |
%.o : %.c |
76,4 → 88,3 |
$(REDIR) $(CC) $(C_OPT) $(C_OUTPUT) -S $< |
%.o : %.cpp |
$(REDIR) $(CPP) $(C_OPT) $(C_OUTPUT) -c $< |
/shark/trunk/config/mk/linux.mk |
---|
16,6 → 16,13 |
LIBRARYDIR= $(LIB_PATH) |
LIBRARYOBJS= $(LIB_OBJS) |
ifeq ($(findstring LINUX,$(ENV)) , LINUX) |
CFG_OPT += -D__LINUX__ |
endif |
ifeq ($(findstring DJGPP,$(ENV)) , DJGPP) |
CFG_OPT += -D__GNU__ |
endif |
ifeq ($(TSC),TRUE) |
CFG_OPT += -D__TSC__ |
ifeq ($(APIC),TRUE) |
39,7 → 46,9 |
CFG_VIDEO_OPT += -DCONFIG_FB_VESA -DCONFIG_LOGO |
endif |
ifeq ($(findstring FINDPCI,$(FB)) , FINDPCI) |
CFG_VIDEO_OPT += -DCONFIG_FB_RIVA -DCONFIG_FB_RADEON -DCONFIG_FB_MATROX -DCONFIG_LOGO -DCONFIG_FB_MATROX_G100 -DCONFIG_FB_MATROX_MILLENIUM -DCONFIG_FB_MATROX_MYSTIQUE |
CFG_VIDEO_OPT += -DCONFIG_FB_RIVA -DCONFIG_FB_RADEON -DCONFIG_FB_MATROX\ |
-DCONFIG_LOGO -DCONFIG_FB_MATROX_G100 -DCONFIG_FB_MATROX_MILLENIUM\ |
-DCONFIG_FB_MATROX_MYSTIQUE |
endif |
ifeq ($(findstring VGA16,$(FB)) , VGA16) |
CFG_VIDEO_OPT += -DCONFIG_FB_VGA16 |
48,12 → 57,12 |
C_WARN = -Wimplicit-function-declaration -Wall |
C_FLAGS = -O -fno-builtin -nostdinc |
C_INC = -I$(INCL) $(OTHERINCL) -I$(OSLIB) |
C_MAC = -D__LINUX__ $(CFG_OPT) |
C_MAC = $(CFG_OPT) |
ASM_WARN = |
ASM_FLAGS = -x assembler-with-cpp |
ASM_INC = -I$(INCL) $(OTHERINCL) -I$(OSLIB) |
ASM_MAC = -D__LINUX__ $(CFG_OPT) |
ASM_MAC = $(CFG_OPT) |
LINK_OPT = -Bstatic -Ttext $(MEM_START) -s -nostartfiles -nostdlib -L$(LIB_PATH) -L$(OSLIB_PATH) |
/shark/trunk/oslib/mk/gnu.mk |
---|
6,10 → 6,17 |
AR = ar |
INCL = $(BASE) |
LIB_PATH = $(BASE)/lib/ |
LIB_DIR = $(BASE)\lib |
LIB_DIR = $(BASE)/lib |
ifeq ($(findstring LINUX,$(ENV)) , LINUX) |
CFG_OPT += -D__LINUX__ |
endif |
ifeq ($(findstring DJGPP,$(ENV)) , DJGPP) |
CFG_OPT += -D__GNU__ |
endif |
ifeq ($(TSC),TRUE) |
CFG_OPT = -D__TSC__ |
CFG_OPT += -D__TSC__ |
ifeq ($(APIC),TRUE) |
CFG_OPT += -D__APIC__ |
endif |
36,18 → 43,22 |
CFG_OPT += -D__OLD_TRACER__ |
endif |
C_OPT = -Wall -O -fno-builtin -nostdinc $(CFG_OPT) -D__GNU__ -I$(INCL) -DMAIN=__kernel_init__ |
ASM_OPT = -x assembler-with-cpp $(CFG_OPT) -D__GNU__ -I$(INCL) |
LINK_OPT = -T $(BASE)/mk/os.x -Bstatic -Ttext 0x320000 -oformat coff-go32 -s -nostartfiles -nostdlib -L$(LIB_PATH) |
C_OPT = -Wall -O -fno-builtin -nostdinc $(CFG_OPT) -DMAIN=__kernel_init__ -I$(INCL) |
ASM_OPT = -x assembler-with-cpp $(CFG_OPT) -I$(INCL) |
LINK_OPT = -Bstatic -Ttext $(MEM_START) -s -nostartfiles -nostdlib -L$(LIB_PATH) |
MKDIR = md |
MKDIR = mkdir |
CP = cp |
CAT = @type |
RM = -del |
RMDIR = -deltree |
CAT = cat |
RM = rm -f |
RMDIR = rm -rf |
# Common rules |
%.o : %.s |
$(REDIR) $(CC) $(ASM_OPT) -c $< |
%.o : %.c |
$(REDIR) $(CC) $(C_OPT) -c $< |
%.s : %.c |
$(REDIR) $(CC) $(C_OPT) -S $< |
/shark/trunk/oslib/mk/linux.mk |
---|
8,6 → 8,13 |
LIB_PATH = $(BASE)/lib/ |
LIB_DIR = $(BASE)/lib |
ifeq ($(findstring LINUX,$(ENV)) , LINUX) |
CFG_OPT += -D__LINUX__ |
endif |
ifeq ($(findstring DJGPP,$(ENV)) , DJGPP) |
CFG_OPT += -D__GNU__ |
endif |
ifeq ($(TSC),TRUE) |
CFG_OPT += -D__TSC__ |
ifeq ($(APIC),TRUE) |
36,9 → 43,9 |
CFG_OPT += -D__OLD_TRACER__ |
endif |
C_OPT = -Wall -O -fno-builtin -nostdinc -D__LINUX__ $(CFG_OPT) -DMAIN=__kernel_init__ -I$(INCL) |
ASM_OPT = -x assembler-with-cpp -D__LINUX__ $(CFG_OPT) -I$(INCL) |
LINK_OPT = -Bstatic -Ttext 0x220000 -s -nostartfiles -nostdlib -L$(LIB_PATH) |
C_OPT = -Wall -O -fno-builtin -nostdinc $(CFG_OPT) -DMAIN=__kernel_init__ -I$(INCL) |
ASM_OPT = -x assembler-with-cpp $(CFG_OPT) -I$(INCL) |
LINK_OPT = -Bstatic -Ttext $(MEM_START) -s -nostartfiles -nostdlib -L$(LIB_PATH) |
MKDIR = mkdir |
CP = cp |
/shark/trunk/makefile |
---|
21,6 → 21,3 |
make -C ports $@ |
make -C tracer $@ |
distrib: |
./distrib/mdistrib |
/shark/trunk/drivers/newpci/fixup.c |
---|
File deleted |
/shark/trunk/drivers/newpci/irq.c |
---|
File deleted |
/shark/trunk/drivers/newpci/pci.ids |
---|
File deleted |
/shark/trunk/drivers/newpci/syscall.c |
---|
File deleted |
/shark/trunk/drivers/newpci/pci.c |
---|
File deleted |
/shark/trunk/drivers/newpci/pcbios.c |
---|
File deleted |
/shark/trunk/drivers/newpci/quirks.c |
---|
File deleted |
/shark/trunk/drivers/newpci/names.c |
---|
File deleted |
/shark/trunk/drivers/newpci/pci.h |
---|
File deleted |
/shark/trunk/drivers/newpci/shark_pci26.c |
---|
File deleted |
/shark/trunk/drivers/newpci/pci20to26.c |
---|
File deleted |
/shark/trunk/drivers/newpci/setup-bus.c |
---|
File deleted |
/shark/trunk/drivers/newpci/setup-irq.c |
---|
File deleted |
/shark/trunk/drivers/newpci/pci-functions.h |
---|
File deleted |
/shark/trunk/drivers/newpci/numa.c |
---|
File deleted |
/shark/trunk/drivers/newpci/remove.c |
---|
File deleted |
/shark/trunk/drivers/newpci/i386.c |
---|
File deleted |
/shark/trunk/drivers/newpci/direct.c |
---|
File deleted |
/shark/trunk/drivers/newpci/pci-driver.c |
---|
File deleted |
/shark/trunk/drivers/newpci/pool.c |
---|
File deleted |
/shark/trunk/drivers/newpci/legacy.c |
---|
File deleted |
/shark/trunk/drivers/newpci/pci2.h |
---|
File deleted |
/shark/trunk/drivers/newpci/setup-res.c |
---|
File deleted |
/shark/trunk/drivers/newpci/access.c |
---|
File deleted |
/shark/trunk/drivers/newpci/probe.c |
---|
File deleted |
/shark/trunk/drivers/newpci/search.c |
---|
File deleted |
/shark/trunk/drivers/newpci/makefile |
---|
File deleted |
/shark/trunk/drivers/newpci/bus.c |
---|
File deleted |
/shark/trunk/drivers/newpci/common.c |
---|
File deleted |
/shark/trunk/drivers/oldpci/pci_scan.c |
---|
0,0 → 1,543 |
#include <ll/i386/hw-instr.h> |
#include <ll/i386/hw-data.h> |
#include <ll/i386/hw-arch.h> |
#include <ll/i386/hw-io.h> |
#include <ll/i386/cons.h> |
#include <ll/i386/mem.h> |
#include <ll/stdlib.h> |
#include <drivers/llpci.h> |
#include <drivers/pci.h> |
#include <drivers/linuxpci.h> |
#include <kernel/log.h> |
//#define DEBUG_PCISCAN |
static struct pci_dev pci_devs[N_MAX_DEVS]; |
static struct pci_bus pci_root; |
static struct pci_dev *pci_devices = NULL; |
#if 0 |
/* scan the bus to find all the connected devices */ |
DWORD pci_scan_bus(struct pci_bus *bus) |
{ |
int ndev; |
DWORD tmp; |
DWORD max, class; |
BYTE hdr; |
int ok; |
WORD dev; |
struct pci_dev **bus_last; |
struct pci_dev *device = NULL; |
int present; |
max = bus->secondary; |
bus_last = &bus->devices; |
if (pcibios_present() == 0) return -1; |
ndev = 0; |
for (dev = 0; dev <= 0xFF; dev++) { |
present = 0; |
if ((dev & 0x07) == 0) { |
present = pcibios_read_config_byte(bus->number, dev, 0x0e, &hdr); |
} |
if (hdr & 0x80) { |
present = 1; |
} |
if (present) { |
ok = pcibios_read_config_dword(bus->number, dev, 0, &tmp); |
if ( ok && (((tmp & 0xFFFF) != 0xFFFF) && ((tmp >> 16) != 0xFFFF))) { |
/* Got a PCI Device!!! */ |
device = &(pci_devs[ndev++]); |
device->bus = bus; |
device->devfn = dev; |
device->vendor = tmp & 0xffff; |
device->device = (tmp >> 16) & 0xffff; |
/* PJ: non-destructively determine if device can be a master: */ |
pcibios_read_config_byte(bus->number, devfn, PCI_COMMAND, &cmd); |
pcibios_write_config_byte(bus->number, devfn, PCI_COMMAND, cmd | PCI_COMMAND_MASTER); |
pcibios_read_config_byte(bus->number, devfn, PCI_COMMAND, &tmp); |
dev->master = ((tmp & PCI_COMMAND_MASTER) != 0); |
pcibios_write_config_byte(bus->number, devfn, PCI_COMMAND, cmd); |
/* This is by Luca... We need to set base_addr */ |
pcibios_read_config_dword(bus->number, dev, PCI_BASE_ADDRESS_0, &(device->base_address[0])); |
pcibios_read_config_byte(bus->number, dev, PCI_INTERRUPT_LINE, &irq1); |
device->irq = irq1; |
pcibios_read_config_dword(bus->number, dev, PCI_CLASS_REVISION, &class); |
class >>= 8; /* upper 3 bytes */ |
//printk(KERN_INFO "pci_scan_bus: dev=%d, class=%ld", dev, class); |
device->class = class; |
class >>= 8; |
device->hdr_type = hdr; |
#if 0 |
switch (hdr & 0x7f) { /* header type */ |
case PCI_HEADER_TYPE_NORMAL: /* standard header */ |
if (class == PCI_CLASS_BRIDGE_PCI) |
goto bad; |
/* |
* If the card generates interrupts, read IRQ number |
* (some architectures change it during pcibios_fixup()) |
*/ |
pcibios_read_config_byte(bus->number, device->devfn, PCI_INTERRUPT_PIN, &irq1); |
if (irq1) |
pcibios_read_config_byte(bus->number, device->devfn, PCI_INTERRUPT_LINE, &irq1); |
device->irq = irq1; |
/* |
* read base address registers, again pcibios_fixup() can |
* tweak these |
*/ |
pci_read_bases(device, 6); |
pcibios_read_config_dword(bus->number, dev, PCI_ROM_ADDRESS, &l); |
device->rom_address = (l == 0xffffffff) ? 0 : l; |
break; |
case PCI_HEADER_TYPE_BRIDGE: /* bridge header */ |
if (class != PCI_CLASS_BRIDGE_PCI) |
goto bad; |
pci_read_bases(device, 2); |
pcibios_read_config_dword(bus->number, dev, PCI_ROM_ADDRESS1, &l); |
device->rom_address = (l == 0xffffffff) ? 0 : l; |
break; |
case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */ |
if (class != PCI_CLASS_BRIDGE_CARDBUS) |
goto bad; |
pci_read_bases(device, 1); |
break; |
default: /* unknown header */ |
bad: |
printk(KERN_ERR "PCI: %02x:%02x [%04x/%04x/%06x] has unknown header type %02x, ignoring.\n", |
bus->number, device->devfn, device->vendor, device->device, class, hdr); |
continue; |
} |
#endif |
//printk(KERN_DEBUG "PCI: %02x:%02x [%04x/%04x]\n", bus->number, device->devfn, device->vendor, device->device); |
device->next = pci_devices; |
pci_devices = device; |
/* |
* Now insert it into the list of devices held |
* by the parent bus. |
*/ |
*bus_last = device; |
bus_last = &device->sibling; |
} |
} |
} |
// PJ: PCI bridges not supported??? |
#if 0 |
for(device = bus->devices; device; device = device->sibling) { |
/* |
* If it's a bridge, scan the bus behind it. |
*/ |
if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) { |
unsigned int buses; |
unsigned int devfn = dev->devfn; |
unsigned short cr; |
/* |
* Insert it into the tree of buses. |
*/ |
child = kmalloc(sizeof(*child), GFP_ATOMIC); |
if(child==NULL) { |
#ifdef DEBUG_PCISCAN |
printk(KERN_ERR "pci: out of memory for bridge.\n"); |
#endif |
continue; |
} |
memset(child, 0, sizeof(*child)); |
child->next = bus->children; |
bus->children = child; |
child->self = dev; |
child->parent = bus; |
/* |
* Set up the primary, secondary and subordinate |
* bus numbers. |
*/ |
child->number = child->secondary = ++max; |
child->primary = bus->secondary; |
child->subordinate = 0xff; |
/* |
* Clear all status bits and turn off memory, |
* I/O and master enables. |
*/ |
pcibios_read_config_word(bus->number, devfn, PCI_COMMAND, &cr); |
pcibios_write_config_word(bus->number, devfn, PCI_COMMAND, 0x0000); |
pcibios_write_config_word(bus->number, devfn, PCI_STATUS, 0xffff); |
/* |
* Read the existing primary/secondary/subordinate bus |
* number configuration to determine if the PCI bridge |
* has already been configured by the system. If so, |
* do not modify the configuration, merely note it. |
*/ |
pcibios_read_config_dword(bus->number, devfn, PCI_PRIMARY_BUS, &buses); |
if ((buses & 0xFFFFFF) != 0) { |
unsigned int cmax; |
child->primary = buses & 0xFF; |
child->secondary = (buses >> 8) & 0xFF; |
child->subordinate = (buses >> 16) & 0xFF; |
child->number = child->secondary; |
cmax = pci_scan_bus(child); |
if (cmax > max) max = cmax; |
} else { |
/* |
* Configure the bus numbers for this bridge: |
*/ |
buses &= 0xff000000; |
buses |= (((unsigned int)(child->primary) << 0) | |
((unsigned int)(child->secondary) << 8) | |
((unsigned int)(child->subordinate) << 16)); |
pcibios_write_config_dword(bus->number, devfn, PCI_PRIMARY_BUS, buses); |
/* |
* Now we can scan all subordinate buses: |
*/ |
max = pci_scan_bus(child); |
/* |
* Set the subordinate bus number to its real |
* value: |
*/ |
child->subordinate = max; |
buses = (buses & 0xff00ffff) |
| ((unsigned int)(child->subordinate) << 16); |
pcibios_write_config_dword(bus->number, devfn, PCI_PRIMARY_BUS, buses); |
} |
pcibios_write_config_word(bus->number, devfn, PCI_COMMAND, cr); |
} |
} |
#endif |
return max; |
} |
#endif |
/* scan the bus to find all the connected devices */ |
DWORD pci_scan_bus(struct pci_bus *bus) |
{ |
int ndev; |
DWORD tmp; |
DWORD max, class; |
BYTE hdr, irq1; |
int ok; |
WORD dev; |
struct pci_dev **bus_last; |
struct pci_dev *device = NULL; |
int present; |
max = bus->secondary; |
bus_last = &bus->devices; |
if (pcibios_present() == 0) return -1; |
ndev = 0; |
for (dev = 0; dev <= 0xFF; dev++) { |
present = 0; |
if ((dev & 0x07) == 0) { |
present = pcibios_read_config_byte(bus->number, dev, 0x0e, &hdr); |
} |
if (hdr & 0x80) { |
present = 1; |
} |
if (present) { |
ok = pcibios_read_config_dword(bus->number, dev, 0, &tmp); |
if ( ok && (((tmp & 0xFFFF) != 0xFFFF) && ((tmp >> 16) != 0xFFFF))) { |
/* Got a PCI Device!!! */ |
device = &(pci_devs[ndev++]); |
device->bus = bus; |
device->devfn = dev; |
device->vendor = tmp & 0xffff; |
device->device = (tmp >> 16) & 0xffff; |
/* This is by Luca... We need to set base_addr */ |
pcibios_read_config_dword(bus->number, dev, PCI_BASE_ADDRESS_0, &(device->base_address[0])); |
/* ...and also the interrupt number!!! */ |
pcibios_read_config_byte(bus->number, dev, PCI_INTERRUPT_LINE, &irq1); |
device->irq = irq1; |
pcibios_read_config_dword(bus->number, dev, PCI_CLASS_REVISION, &class); |
class >>= 8; /* upper 3 bytes */ |
device->class = class; |
class >>= 8; |
device->hdr_type = hdr; |
#if 0 |
switch (hdr_type & 0x7f) { /* header type */ |
case PCI_HEADER_TYPE_NORMAL: /* standard header */ |
if (class == PCI_CLASS_BRIDGE_PCI) |
goto bad; |
/* |
* If the card generates interrupts, read IRQ number |
* (some architectures change it during pcibios_fixup()) |
*/ |
pcibios_read_config_byte(bus->number, dev->devfn, PCI_INTERRUPT_PIN, &irq); |
if (irq) |
pcibios_read_config_byte(bus->number, dev->devfn, PCI_INTERRUPT_LINE, &irq); |
dev->irq = irq; |
/* |
* read base address registers, again pcibios_fixup() can |
* tweak these |
*/ |
pci_read_bases(dev, 6); |
pcibios_read_config_dword(bus->number, devfn, PCI_ROM_ADDRESS, &l); |
dev->rom_address = (l == 0xffffffff) ? 0 : l; |
break; |
case PCI_HEADER_TYPE_BRIDGE: /* bridge header */ |
if (class != PCI_CLASS_BRIDGE_PCI) |
goto bad; |
pci_read_bases(dev, 2); |
pcibios_read_config_dword(bus->number, devfn, PCI_ROM_ADDRESS1, &l); |
dev->rom_address = (l == 0xffffffff) ? 0 : l; |
break; |
case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */ |
if (class != PCI_CLASS_BRIDGE_CARDBUS) |
goto bad; |
pci_read_bases(dev, 1); |
break; |
default: /* unknown header */ |
bad: |
printk(KERN_ERR "PCI: %02x:%02x [%04x/%04x/%06x] has unknown header type %02x, ignoring.\n", |
bus->number, dev->devfn, dev->vendor, dev->device, class, hdr_type); |
continue; |
} |
DBG("PCI: %02x:%02x [%04x/%04x]\n", bus->number, dev->devfn, dev->vendor, dev->device); |
#endif |
device->next = pci_devices; |
pci_devices = device; |
/* |
* Now insert it into the list of devices held |
* by the parent bus. |
*/ |
*bus_last = device; |
bus_last = &device->sibling; |
} |
} |
} |
for(device = bus->devices; device; device = device->sibling) { |
#if 0 |
/* |
* If it's a bridge, scan the bus behind it. |
*/ |
if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) { |
unsigned int buses; |
unsigned int devfn = dev->devfn; |
unsigned short cr; |
/* |
* Insert it into the tree of buses. |
*/ |
child = kmalloc(sizeof(*child), GFP_ATOMIC); |
if(child==NULL) { |
#ifdef DEBUG_PCISCAN |
printk(KERN_ERR "pci: out of memory for bridge.\n"); |
#endif |
continue; |
} |
memset(child, 0, sizeof(*child)); |
child->next = bus->children; |
bus->children = child; |
child->self = dev; |
child->parent = bus; |
/* |
* Set up the primary, secondary and subordinate |
* bus numbers. |
*/ |
child->number = child->secondary = ++max; |
child->primary = bus->secondary; |
child->subordinate = 0xff; |
/* |
* Clear all status bits and turn off memory, |
* I/O and master enables. |
*/ |
pcibios_read_config_word(bus->number, devfn, PCI_COMMAND, &cr); |
pcibios_write_config_word(bus->number, devfn, PCI_COMMAND, 0x0000); |
pcibios_write_config_word(bus->number, devfn, PCI_STATUS, 0xffff); |
/* |
* Read the existing primary/secondary/subordinate bus |
* number configuration to determine if the PCI bridge |
* has already been configured by the system. If so, |
* do not modify the configuration, merely note it. |
*/ |
pcibios_read_config_dword(bus->number, devfn, PCI_PRIMARY_BUS, &buses); |
if ((buses & 0xFFFFFF) != 0) { |
unsigned int cmax; |
child->primary = buses & 0xFF; |
child->secondary = (buses >> 8) & 0xFF; |
child->subordinate = (buses >> 16) & 0xFF; |
child->number = child->secondary; |
cmax = pci_scan_bus(child); |
if (cmax > max) max = cmax; |
} else { |
/* |
* Configure the bus numbers for this bridge: |
*/ |
buses &= 0xff000000; |
buses |= (((unsigned int)(child->primary) << 0) | |
((unsigned int)(child->secondary) << 8) | |
((unsigned int)(child->subordinate) << 16)); |
pcibios_write_config_dword(bus->number, devfn, PCI_PRIMARY_BUS, buses); |
/* |
* Now we can scan all subordinate buses: |
*/ |
max = pci_scan_bus(child); |
/* |
* Set the subordinate bus number to its real |
* value: |
*/ |
child->subordinate = max; |
buses = (buses & 0xff00ffff) |
| ((unsigned int)(child->subordinate) << 16); |
pcibios_write_config_dword(bus->number, devfn, PCI_PRIMARY_BUS, buses); |
} |
pcibios_write_config_word(bus->number, devfn, PCI_COMMAND, cr); |
} |
#endif |
} |
return max; |
} |
void linuxpci_init(void) |
{ |
pcibios_init(); |
if (!pci_present()) { |
#ifdef DEBUG_PCISCAN |
printk("PCI: No PCI bus detected\n"); |
#endif |
return; |
} |
#ifdef DEBUG_PCISCAN |
printk("PCI: Probing PCI hardware\n"); |
#endif |
memset(&pci_root, 0, sizeof(pci_root)); |
pci_root.subordinate = pci_scan_bus(&pci_root); |
} |
struct pci_dev *pci_find_device(unsigned int vendor, unsigned int device, struct pci_dev *from) |
{ |
if (!from) |
from = pci_devices; |
else |
from = from->next; |
while (from && (from->vendor != vendor || from->device != device)) |
from = from->next; |
return from; |
} |
struct pci_dev *pci_find_class(unsigned int class, struct pci_dev *from) |
{ |
if (!from) |
from = pci_devices; |
else |
from = from->next; |
while (from && from->class != class) |
from = from->next; |
return from; |
} |
struct pci_dev * |
pci_find_slot(unsigned int bus, unsigned int devfn) |
{ |
struct pci_dev *dev; |
for(dev=pci_devices; dev; dev=dev->next) |
if (dev->bus->number == bus && dev->devfn == devfn) |
break; |
return dev; |
} |
void |
pci_set_master(struct pci_dev *dev) |
{ |
unsigned short cmd; // was: u16 |
unsigned char lat; // was: u8 |
pci_read_config_word(dev, PCI_COMMAND, &cmd); |
if (! (cmd & PCI_COMMAND_MASTER)) { |
printk("PCI: Enabling bus mastering for device %02x:%02x\n", |
dev->bus->number, dev->devfn); |
cmd |= PCI_COMMAND_MASTER; |
pci_write_config_word(dev, PCI_COMMAND, cmd); |
} |
pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat); |
if (lat < 16) { |
printk("PCI: Increasing latency timer of device %02x:%02x to 64\n", |
dev->bus->number, dev->devfn); |
pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64); |
} |
} |
/shark/trunk/drivers/oldpci/linuxpci.h |
---|
0,0 → 1,1085 |
/* |
* PCI defines and function prototypes |
* Copyright 1994, Drew Eckhardt |
* |
* For more information, please consult |
* |
* PCI BIOS Specification Revision |
* PCI Local Bus Specification |
* PCI System Design Guide |
* |
* PCI Special Interest Group |
* M/S HF3-15A |
* 5200 N.E. Elam Young Parkway |
* Hillsboro, Oregon 97124-6497 |
* +1 (503) 696-2000 |
* +1 (800) 433-5177 |
* |
* Manuals are $25 each or $50 for all three, plus $7 shipping |
* within the United States, $35 abroad. |
*/ |
/* PROCEDURE TO REPORT NEW PCI DEVICES |
* We are trying to collect information on new PCI devices, using |
* the standard PCI identification procedure. If some warning is |
* displayed at boot time, please report |
* - /proc/pci |
* - your exact hardware description. Try to find out |
* which device is unknown. It may be you mainboard chipset. |
* PCI-CPU bridge or PCI-ISA bridge. |
* - If you can't find the actual information in your hardware |
* booklet, try to read the references of the chip on the board. |
* - Send all that to linux-pcisupport@cck.uni-kl.de |
* and I'll add your device to the list as soon as possible |
* |
* BEFORE you send a mail, please check the latest linux releases |
* to be sure it has not been recently added. |
* |
* Thanks |
* Jens Maurer |
*/ |
#ifndef LINUX_PCI_H |
#define LINUX_PCI_H |
#include "ll/sys/cdefs.h" |
__BEGIN_DECLS |
/* |
* Under PCI, each device has 256 bytes of configuration address space, |
* of which the first 64 bytes are standardized as follows: |
*/ |
#define PCI_VENDOR_ID 0x00 /* 16 bits */ |
#define PCI_DEVICE_ID 0x02 /* 16 bits */ |
#define PCI_COMMAND 0x04 /* 16 bits */ |
#define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */ |
#define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */ |
#define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */ |
#define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */ |
#define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */ |
#define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */ |
#define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */ |
#define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */ |
#define PCI_COMMAND_SERR 0x100 /* Enable SERR */ |
#define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */ |
#define PCI_STATUS 0x06 /* 16 bits */ |
#define PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */ |
#define PCI_STATUS_UDF 0x40 /* Support User Definable Features */ |
#define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */ |
#define PCI_STATUS_PARITY 0x100 /* Detected parity error */ |
#define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */ |
#define PCI_STATUS_DEVSEL_FAST 0x000 |
#define PCI_STATUS_DEVSEL_MEDIUM 0x200 |
#define PCI_STATUS_DEVSEL_SLOW 0x400 |
#define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */ |
#define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */ |
#define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */ |
#define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */ |
#define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */ |
#define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8 |
revision */ |
#define PCI_REVISION_ID 0x08 /* Revision ID */ |
#define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */ |
#define PCI_CLASS_DEVICE 0x0a /* Device class */ |
#define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */ |
#define PCI_LATENCY_TIMER 0x0d /* 8 bits */ |
#define PCI_HEADER_TYPE 0x0e /* 8 bits */ |
#define PCI_BIST 0x0f /* 8 bits */ |
#define PCI_BIST_CODE_MASK 0x0f /* Return result */ |
#define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */ |
#define PCI_BIST_CAPABLE 0x80 /* 1 if BIST capable */ |
/* |
* Base addresses specify locations in memory or I/O space. |
* Decoded size can be determined by writing a value of |
* 0xffffffff to the register, and reading it back. Only |
* 1 bits are decoded. |
*/ |
#define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */ |
#define PCI_BASE_ADDRESS_1 0x14 /* 32 bits */ |
#define PCI_BASE_ADDRESS_2 0x18 /* 32 bits */ |
#define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */ |
#define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */ |
#define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */ |
#define PCI_BASE_ADDRESS_SPACE 0x01 /* 0 = memory, 1 = I/O */ |
#define PCI_BASE_ADDRESS_SPACE_IO 0x01 |
#define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00 |
#define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06 |
#define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 /* 32 bit address */ |
#define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 /* Below 1M */ |
#define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */ |
#define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */ |
#define PCI_BASE_ADDRESS_MEM_MASK (~0x0f) |
#define PCI_BASE_ADDRESS_IO_MASK (~0x03) |
/* bit 1 is reserved if address_space = 1 */ |
#define PCI_CARDBUS_CIS 0x28 |
#define PCI_SUBSYSTEM_ID 0x2c |
#define PCI_SUBSYSTEM_VENDOR_ID 0x2e |
#define PCI_ROM_ADDRESS 0x30 /* 32 bits */ |
#define PCI_ROM_ADDRESS_ENABLE 0x01 /* Write 1 to enable ROM, |
bits 31..11 are address, |
10..2 are reserved */ |
/* 0x34-0x3b are reserved */ |
#define PCI_INTERRUPT_LINE 0x3c /* 8 bits */ |
#define PCI_INTERRUPT_PIN 0x3d /* 8 bits */ |
#define PCI_MIN_GNT 0x3e /* 8 bits */ |
#define PCI_MAX_LAT 0x3f /* 8 bits */ |
#define PCI_CLASS_NOT_DEFINED 0x0000 |
#define PCI_CLASS_NOT_DEFINED_VGA 0x0001 |
#define PCI_BASE_CLASS_STORAGE 0x01 |
#define PCI_CLASS_STORAGE_SCSI 0x0100 |
#define PCI_CLASS_STORAGE_IDE 0x0101 |
#define PCI_CLASS_STORAGE_FLOPPY 0x0102 |
#define PCI_CLASS_STORAGE_IPI 0x0103 |
#define PCI_CLASS_STORAGE_RAID 0x0104 |
#define PCI_CLASS_STORAGE_OTHER 0x0180 |
#define PCI_BASE_CLASS_NETWORK 0x02 |
#define PCI_CLASS_NETWORK_ETHERNET 0x0200 |
#define PCI_CLASS_NETWORK_TOKEN_RING 0x0201 |
#define PCI_CLASS_NETWORK_FDDI 0x0202 |
#define PCI_CLASS_NETWORK_ATM 0x0203 |
#define PCI_CLASS_NETWORK_OTHER 0x0280 |
#define PCI_BASE_CLASS_DISPLAY 0x03 |
#define PCI_CLASS_DISPLAY_VGA 0x0300 |
#define PCI_CLASS_DISPLAY_XGA 0x0301 |
#define PCI_CLASS_DISPLAY_OTHER 0x0380 |
#define PCI_BASE_CLASS_MULTIMEDIA 0x04 |
#define PCI_CLASS_MULTIMEDIA_VIDEO 0x0400 |
#define PCI_CLASS_MULTIMEDIA_AUDIO 0x0401 |
#define PCI_CLASS_MULTIMEDIA_OTHER 0x0480 |
#define PCI_BASE_CLASS_MEMORY 0x05 |
#define PCI_CLASS_MEMORY_RAM 0x0500 |
#define PCI_CLASS_MEMORY_FLASH 0x0501 |
#define PCI_CLASS_MEMORY_OTHER 0x0580 |
#define PCI_BASE_CLASS_BRIDGE 0x06 |
#define PCI_CLASS_BRIDGE_HOST 0x0600 |
#define PCI_CLASS_BRIDGE_ISA 0x0601 |
#define PCI_CLASS_BRIDGE_EISA 0x0602 |
#define PCI_CLASS_BRIDGE_MC 0x0603 |
#define PCI_CLASS_BRIDGE_PCI 0x0604 |
#define PCI_CLASS_BRIDGE_PCMCIA 0x0605 |
#define PCI_CLASS_BRIDGE_NUBUS 0x0606 |
#define PCI_CLASS_BRIDGE_CARDBUS 0x0607 |
#define PCI_CLASS_BRIDGE_OTHER 0x0680 |
#define PCI_BASE_CLASS_COMMUNICATION 0x07 |
#define PCI_CLASS_COMMUNICATION_SERIAL 0x0700 |
#define PCI_CLASS_COMMUNICATION_PARALLEL 0x0701 |
#define PCI_CLASS_COMMUNICATION_OTHER 0x0780 |
#define PCI_BASE_CLASS_SYSTEM 0x08 |
#define PCI_CLASS_SYSTEM_PIC 0x0800 |
#define PCI_CLASS_SYSTEM_DMA 0x0801 |
#define PCI_CLASS_SYSTEM_TIMER 0x0802 |
#define PCI_CLASS_SYSTEM_RTC 0x0803 |
#define PCI_CLASS_SYSTEM_OTHER 0x0880 |
#define PCI_BASE_CLASS_INPUT 0x09 |
#define PCI_CLASS_INPUT_KEYBOARD 0x0900 |
#define PCI_CLASS_INPUT_PEN 0x0901 |
#define PCI_CLASS_INPUT_MOUSE 0x0902 |
#define PCI_CLASS_INPUT_OTHER 0x0980 |
#define PCI_BASE_CLASS_DOCKING 0x0a |
#define PCI_CLASS_DOCKING_GENERIC 0x0a00 |
#define PCI_CLASS_DOCKING_OTHER 0x0a01 |
#define PCI_BASE_CLASS_PROCESSOR 0x0b |
#define PCI_CLASS_PROCESSOR_386 0x0b00 |
#define PCI_CLASS_PROCESSOR_486 0x0b01 |
#define PCI_CLASS_PROCESSOR_PENTIUM 0x0b02 |
#define PCI_CLASS_PROCESSOR_ALPHA 0x0b10 |
#define PCI_CLASS_PROCESSOR_POWERPC 0x0b20 |
#define PCI_CLASS_PROCESSOR_CO 0x0b40 |
#define PCI_BASE_CLASS_SERIAL 0x0c |
#define PCI_CLASS_SERIAL_FIREWIRE 0x0c00 |
#define PCI_CLASS_SERIAL_ACCESS 0x0c01 |
#define PCI_CLASS_SERIAL_SSA 0x0c02 |
#define PCI_CLASS_SERIAL_USB 0x0c03 |
#define PCI_CLASS_SERIAL_FIBER 0x0c04 |
#define PCI_CLASS_OTHERS 0xff |
/* |
* Vendor and card ID's: sort these numerically according to vendor |
* (and according to card ID within vendor). Send all updates to |
* <linux-pcisupport@cck.uni-kl.de>. |
*/ |
#define PCI_VENDOR_ID_COMPAQ 0x0e11 |
#define PCI_DEVICE_ID_COMPAQ_1280 0x3033 |
#define PCI_DEVICE_ID_COMPAQ_TRIFLEX 0x4000 |
#define PCI_DEVICE_ID_COMPAQ_SMART2P 0xae10 |
#define PCI_DEVICE_ID_COMPAQ_NETEL100 0xae32 |
#define PCI_DEVICE_ID_COMPAQ_NETEL10 0xae34 |
#define PCI_DEVICE_ID_COMPAQ_NETFLEX3I 0xae35 |
#define PCI_DEVICE_ID_COMPAQ_NETEL100D 0xae40 |
#define PCI_DEVICE_ID_COMPAQ_NETEL100PI 0xae43 |
#define PCI_DEVICE_ID_COMPAQ_NETEL100I 0xb011 |
#define PCI_DEVICE_ID_COMPAQ_THUNDER 0xf130 |
#define PCI_DEVICE_ID_COMPAQ_NETFLEX3B 0xf150 |
#define PCI_VENDOR_ID_NCR 0x1000 |
#define PCI_DEVICE_ID_NCR_53C810 0x0001 |
#define PCI_DEVICE_ID_NCR_53C820 0x0002 |
#define PCI_DEVICE_ID_NCR_53C825 0x0003 |
#define PCI_DEVICE_ID_NCR_53C815 0x0004 |
#define PCI_DEVICE_ID_NCR_53C860 0x0006 |
#define PCI_DEVICE_ID_NCR_53C896 0x000b |
#define PCI_DEVICE_ID_NCR_53C895 0x000c |
#define PCI_DEVICE_ID_NCR_53C885 0x000d |
#define PCI_DEVICE_ID_NCR_53C875 0x000f |
#define PCI_DEVICE_ID_NCR_53C875J 0x008f |
#define PCI_VENDOR_ID_ATI 0x1002 |
#define PCI_DEVICE_ID_ATI_68800 0x4158 |
#define PCI_DEVICE_ID_ATI_215CT222 0x4354 |
#define PCI_DEVICE_ID_ATI_210888CX 0x4358 |
#define PCI_DEVICE_ID_ATI_215GB 0x4742 |
#define PCI_DEVICE_ID_ATI_215GD 0x4744 |
#define PCI_DEVICE_ID_ATI_215GI 0x4749 |
#define PCI_DEVICE_ID_ATI_215GP 0x4750 |
#define PCI_DEVICE_ID_ATI_215GQ 0x4751 |
#define PCI_DEVICE_ID_ATI_215GT 0x4754 |
#define PCI_DEVICE_ID_ATI_215GTB 0x4755 |
#define PCI_DEVICE_ID_ATI_210888GX 0x4758 |
#define PCI_DEVICE_ID_ATI_215LG 0x4c47 |
#define PCI_DEVICE_ID_ATI_264LT 0x4c54 |
#define PCI_DEVICE_ID_ATI_264VT 0x5654 |
#define PCI_VENDOR_ID_VLSI 0x1004 |
#define PCI_DEVICE_ID_VLSI_82C592 0x0005 |
#define PCI_DEVICE_ID_VLSI_82C593 0x0006 |
#define PCI_DEVICE_ID_VLSI_82C594 0x0007 |
#define PCI_DEVICE_ID_VLSI_82C597 0x0009 |
#define PCI_DEVICE_ID_VLSI_82C541 0x000c |
#define PCI_DEVICE_ID_VLSI_82C543 0x000d |
#define PCI_DEVICE_ID_VLSI_82C532 0x0101 |
#define PCI_DEVICE_ID_VLSI_82C534 0x0102 |
#define PCI_DEVICE_ID_VLSI_82C535 0x0104 |
#define PCI_DEVICE_ID_VLSI_82C147 0x0105 |
#define PCI_DEVICE_ID_VLSI_VAS96011 0x0702 |
#define PCI_VENDOR_ID_ADL 0x1005 |
#define PCI_DEVICE_ID_ADL_2301 0x2301 |
#define PCI_VENDOR_ID_NS 0x100b |
#define PCI_DEVICE_ID_NS_87415 0x0002 |
#define PCI_DEVICE_ID_NS_87410 0xd001 |
#define PCI_VENDOR_ID_TSENG 0x100c |
#define PCI_DEVICE_ID_TSENG_W32P_2 0x3202 |
#define PCI_DEVICE_ID_TSENG_W32P_b 0x3205 |
#define PCI_DEVICE_ID_TSENG_W32P_c 0x3206 |
#define PCI_DEVICE_ID_TSENG_W32P_d 0x3207 |
#define PCI_DEVICE_ID_TSENG_ET6000 0x3208 |
#define PCI_VENDOR_ID_WEITEK 0x100e |
#define PCI_DEVICE_ID_WEITEK_P9000 0x9001 |
#define PCI_DEVICE_ID_WEITEK_P9100 0x9100 |
#define PCI_VENDOR_ID_DEC 0x1011 |
#define PCI_DEVICE_ID_DEC_BRD 0x0001 |
#define PCI_DEVICE_ID_DEC_TULIP 0x0002 |
#define PCI_DEVICE_ID_DEC_TGA 0x0004 |
#define PCI_DEVICE_ID_DEC_TULIP_FAST 0x0009 |
#define PCI_DEVICE_ID_DEC_TGA2 0x000D |
#define PCI_DEVICE_ID_DEC_FDDI 0x000F |
#define PCI_DEVICE_ID_DEC_TULIP_PLUS 0x0014 |
#define PCI_DEVICE_ID_DEC_21142 0x0019 |
#define PCI_DEVICE_ID_DEC_21052 0x0021 |
#define PCI_DEVICE_ID_DEC_21150 0x0022 |
#define PCI_DEVICE_ID_DEC_21152 0x0024 |
#define PCI_VENDOR_ID_CIRRUS 0x1013 |
#define PCI_DEVICE_ID_CIRRUS_7548 0x0038 |
#define PCI_DEVICE_ID_CIRRUS_5430 0x00a0 |
#define PCI_DEVICE_ID_CIRRUS_5434_4 0x00a4 |
#define PCI_DEVICE_ID_CIRRUS_5434_8 0x00a8 |
#define PCI_DEVICE_ID_CIRRUS_5436 0x00ac |
#define PCI_DEVICE_ID_CIRRUS_5446 0x00b8 |
#define PCI_DEVICE_ID_CIRRUS_5480 0x00bc |
#define PCI_DEVICE_ID_CIRRUS_5464 0x00d4 |
#define PCI_DEVICE_ID_CIRRUS_5465 0x00d6 |
#define PCI_DEVICE_ID_CIRRUS_6729 0x1100 |
#define PCI_DEVICE_ID_CIRRUS_6832 0x1110 |
#define PCI_DEVICE_ID_CIRRUS_7542 0x1200 |
#define PCI_DEVICE_ID_CIRRUS_7543 0x1202 |
#define PCI_DEVICE_ID_CIRRUS_7541 0x1204 |
#define PCI_VENDOR_ID_IBM 0x1014 |
#define PCI_DEVICE_ID_IBM_FIRE_CORAL 0x000a |
#define PCI_DEVICE_ID_IBM_TR 0x0018 |
#define PCI_DEVICE_ID_IBM_82G2675 0x001d |
#define PCI_DEVICE_ID_IBM_MCA 0x0020 |
#define PCI_DEVICE_ID_IBM_82351 0x0022 |
#define PCI_DEVICE_ID_IBM_SERVERAID 0x002e |
#define PCI_DEVICE_ID_IBM_TR_WAKE 0x003e |
#define PCI_DEVICE_ID_IBM_3780IDSP 0x007d |
#define PCI_VENDOR_ID_WD 0x101c |
#define PCI_DEVICE_ID_WD_7197 0x3296 |
#define PCI_VENDOR_ID_AMD 0x1022 |
#define PCI_DEVICE_ID_AMD_LANCE 0x2000 |
#define PCI_DEVICE_ID_AMD_SCSI 0x2020 |
#define PCI_VENDOR_ID_TRIDENT 0x1023 |
#define PCI_DEVICE_ID_TRIDENT_9397 0x9397 |
#define PCI_DEVICE_ID_TRIDENT_9420 0x9420 |
#define PCI_DEVICE_ID_TRIDENT_9440 0x9440 |
#define PCI_DEVICE_ID_TRIDENT_9660 0x9660 |
#define PCI_DEVICE_ID_TRIDENT_9750 0x9750 |
#define PCI_VENDOR_ID_AI 0x1025 |
#define PCI_DEVICE_ID_AI_M1435 0x1435 |
#define PCI_VENDOR_ID_MATROX 0x102B |
#define PCI_DEVICE_ID_MATROX_MGA_2 0x0518 |
#define PCI_DEVICE_ID_MATROX_MIL 0x0519 |
#define PCI_DEVICE_ID_MATROX_MYS 0x051A |
#define PCI_DEVICE_ID_MATROX_MIL_2 0x051b |
#define PCI_DEVICE_ID_MATROX_MIL_2_AGP 0x051f |
#define PCI_DEVICE_ID_MATROX_MGA_IMP 0x0d10 |
#define PCI_VENDOR_ID_CT 0x102c |
#define PCI_DEVICE_ID_CT_65545 0x00d8 |
#define PCI_DEVICE_ID_CT_65548 0x00dc |
#define PCI_DEVICE_ID_CT_65550 0x00e0 |
#define PCI_DEVICE_ID_CT_65554 0x00e4 |
#define PCI_DEVICE_ID_CT_65555 0x00e5 |
#define PCI_VENDOR_ID_MIRO 0x1031 |
#define PCI_DEVICE_ID_MIRO_36050 0x5601 |
#define PCI_VENDOR_ID_NEC 0x1033 |
#define PCI_DEVICE_ID_NEC_PCX2 0x0046 |
#define PCI_VENDOR_ID_FD 0x1036 |
#define PCI_DEVICE_ID_FD_36C70 0x0000 |
#define PCI_VENDOR_ID_SI 0x1039 |
#define PCI_DEVICE_ID_SI_5591_AGP 0x0001 |
#define PCI_DEVICE_ID_SI_6202 0x0002 |
#define PCI_DEVICE_ID_SI_503 0x0008 |
#define PCI_DEVICE_ID_SI_ACPI 0x0009 |
#define PCI_DEVICE_ID_SI_5597_VGA 0x0200 |
#define PCI_DEVICE_ID_SI_6205 0x0205 |
#define PCI_DEVICE_ID_SI_501 0x0406 |
#define PCI_DEVICE_ID_SI_496 0x0496 |
#define PCI_DEVICE_ID_SI_601 0x0601 |
#define PCI_DEVICE_ID_SI_5107 0x5107 |
#define PCI_DEVICE_ID_SI_5511 0x5511 |
#define PCI_DEVICE_ID_SI_5513 0x5513 |
#define PCI_DEVICE_ID_SI_5571 0x5571 |
#define PCI_DEVICE_ID_SI_5591 0x5591 |
#define PCI_DEVICE_ID_SI_5597 0x5597 |
#define PCI_DEVICE_ID_SI_7001 0x7001 |
#define PCI_VENDOR_ID_HP 0x103c |
#define PCI_DEVICE_ID_HP_J2585A 0x1030 |
#define PCI_DEVICE_ID_HP_J2585B 0x1031 |
#define PCI_VENDOR_ID_PCTECH 0x1042 |
#define PCI_DEVICE_ID_PCTECH_RZ1000 0x1000 |
#define PCI_DEVICE_ID_PCTECH_RZ1001 0x1001 |
#define PCI_DEVICE_ID_PCTECH_SAMURAI_0 0x3000 |
#define PCI_DEVICE_ID_PCTECH_SAMURAI_1 0x3010 |
#define PCI_DEVICE_ID_PCTECH_SAMURAI_IDE 0x3020 |
#define PCI_VENDOR_ID_DPT 0x1044 |
#define PCI_DEVICE_ID_DPT 0xa400 |
#define PCI_VENDOR_ID_OPTI 0x1045 |
#define PCI_DEVICE_ID_OPTI_92C178 0xc178 |
#define PCI_DEVICE_ID_OPTI_82C557 0xc557 |
#define PCI_DEVICE_ID_OPTI_82C558 0xc558 |
#define PCI_DEVICE_ID_OPTI_82C621 0xc621 |
#define PCI_DEVICE_ID_OPTI_82C700 0xc700 |
#define PCI_DEVICE_ID_OPTI_82C701 0xc701 |
#define PCI_DEVICE_ID_OPTI_82C814 0xc814 |
#define PCI_DEVICE_ID_OPTI_82C822 0xc822 |
#define PCI_DEVICE_ID_OPTI_82C825 0xd568 |
#define PCI_VENDOR_ID_SGS 0x104a |
#define PCI_DEVICE_ID_SGS_2000 0x0008 |
#define PCI_DEVICE_ID_SGS_1764 0x0009 |
#define PCI_VENDOR_ID_BUSLOGIC 0x104B |
#define PCI_DEVICE_ID_BUSLOGIC_MULTIMASTER_NC 0x0140 |
#define PCI_DEVICE_ID_BUSLOGIC_MULTIMASTER 0x1040 |
#define PCI_DEVICE_ID_BUSLOGIC_FLASHPOINT 0x8130 |
#define PCI_VENDOR_ID_TI 0x104c |
#define PCI_DEVICE_ID_TI_TVP4010 0x3d04 |
#define PCI_DEVICE_ID_TI_TVP4020 0x3d07 |
#define PCI_DEVICE_ID_TI_PCI1130 0xac12 |
#define PCI_DEVICE_ID_TI_PCI1131 0xac15 |
#define PCI_DEVICE_ID_TI_PCI1250 0xac16 |
#define PCI_VENDOR_ID_OAK 0x104e |
#define PCI_DEVICE_ID_OAK_OTI107 0x0107 |
/* Winbond have two vendor IDs! See 0x10ad as well */ |
#define PCI_VENDOR_ID_WINBOND2 0x1050 |
#define PCI_DEVICE_ID_WINBOND2_89C940 0x0940 |
#define PCI_VENDOR_ID_MOTOROLA 0x1057 |
#define PCI_DEVICE_ID_MOTOROLA_MPC105 0x0001 |
#define PCI_DEVICE_ID_MOTOROLA_MPC106 0x0002 |
#define PCI_DEVICE_ID_MOTOROLA_RAVEN 0x4801 |
#define PCI_VENDOR_ID_PROMISE 0x105a |
#define PCI_DEVICE_ID_PROMISE_20246 0x4d33 |
#define PCI_DEVICE_ID_PROMISE_5300 0x5300 |
#define PCI_VENDOR_ID_N9 0x105d |
#define PCI_DEVICE_ID_N9_I128 0x2309 |
#define PCI_DEVICE_ID_N9_I128_2 0x2339 |
#define PCI_DEVICE_ID_N9_I128_T2R 0x493d |
#define PCI_VENDOR_ID_UMC 0x1060 |
#define PCI_DEVICE_ID_UMC_UM8673F 0x0101 |
#define PCI_DEVICE_ID_UMC_UM8891A 0x0891 |
#define PCI_DEVICE_ID_UMC_UM8886BF 0x673a |
#define PCI_DEVICE_ID_UMC_UM8886A 0x886a |
#define PCI_DEVICE_ID_UMC_UM8881F 0x8881 |
#define PCI_DEVICE_ID_UMC_UM8886F 0x8886 |
#define PCI_DEVICE_ID_UMC_UM9017F 0x9017 |
#define PCI_DEVICE_ID_UMC_UM8886N 0xe886 |
#define PCI_DEVICE_ID_UMC_UM8891N 0xe891 |
#define PCI_VENDOR_ID_X 0x1061 |
#define PCI_DEVICE_ID_X_AGX016 0x0001 |
#define PCI_VENDOR_ID_PICOP 0x1066 |
#define PCI_DEVICE_ID_PICOP_PT86C52X 0x0001 |
#define PCI_DEVICE_ID_PICOP_PT80C524 0x8002 |
#define PCI_VENDOR_ID_APPLE 0x106b |
#define PCI_DEVICE_ID_APPLE_BANDIT 0x0001 |
#define PCI_DEVICE_ID_APPLE_GC 0x0002 |
#define PCI_DEVICE_ID_APPLE_HYDRA 0x000e |
#define PCI_VENDOR_ID_NEXGEN 0x1074 |
#define PCI_DEVICE_ID_NEXGEN_82C501 0x4e78 |
#define PCI_VENDOR_ID_QLOGIC 0x1077 |
#define PCI_DEVICE_ID_QLOGIC_ISP1020 0x1020 |
#define PCI_DEVICE_ID_QLOGIC_ISP1022 0x1022 |
#define PCI_VENDOR_ID_CYRIX 0x1078 |
#define PCI_DEVICE_ID_CYRIX_5510 0x0000 |
#define PCI_DEVICE_ID_CYRIX_PCI_MASTER 0x0001 |
#define PCI_DEVICE_ID_CYRIX_5520 0x0002 |
#define PCI_DEVICE_ID_CYRIX_5530_LEGACY 0x0100 |
#define PCI_DEVICE_ID_CYRIX_5530_SMI 0x0101 |
#define PCI_DEVICE_ID_CYRIX_5530_IDE 0x0102 |
#define PCI_DEVICE_ID_CYRIX_5530_AUDIO 0x0103 |
#define PCI_DEVICE_ID_CYRIX_5530_VIDEO 0x0104 |
#define PCI_VENDOR_ID_LEADTEK 0x107d |
#define PCI_DEVICE_ID_LEADTEK_805 0x0000 |
#define PCI_VENDOR_ID_CONTAQ 0x1080 |
#define PCI_DEVICE_ID_CONTAQ_82C599 0x0600 |
#define PCI_DEVICE_ID_CONTAQ_82C693 0xc693 |
#define PCI_VENDOR_ID_FOREX 0x1083 |
#define PCI_VENDOR_ID_OLICOM 0x108d |
#define PCI_DEVICE_ID_OLICOM_OC3136 0x0001 |
#define PCI_DEVICE_ID_OLICOM_OC2315 0x0011 |
#define PCI_DEVICE_ID_OLICOM_OC2325 0x0012 |
#define PCI_DEVICE_ID_OLICOM_OC2183 0x0013 |
#define PCI_DEVICE_ID_OLICOM_OC2326 0x0014 |
#define PCI_DEVICE_ID_OLICOM_OC6151 0x0021 |
#define PCI_VENDOR_ID_SUN 0x108e |
#define PCI_DEVICE_ID_SUN_EBUS 0x1000 |
#define PCI_DEVICE_ID_SUN_HAPPYMEAL 0x1001 |
#define PCI_DEVICE_ID_SUN_SIMBA 0x5000 |
#define PCI_DEVICE_ID_SUN_PBM 0x8000 |
#define PCI_DEVICE_ID_SUN_SABRE 0xa000 |
#define PCI_VENDOR_ID_CMD 0x1095 |
#define PCI_DEVICE_ID_CMD_640 0x0640 |
#define PCI_DEVICE_ID_CMD_643 0x0643 |
#define PCI_DEVICE_ID_CMD_646 0x0646 |
#define PCI_DEVICE_ID_CMD_670 0x0670 |
#define PCI_VENDOR_ID_VISION 0x1098 |
#define PCI_DEVICE_ID_VISION_QD8500 0x0001 |
#define PCI_DEVICE_ID_VISION_QD8580 0x0002 |
#define PCI_VENDOR_ID_BROOKTREE 0x109e |
#define PCI_DEVICE_ID_BROOKTREE_848 0x0350 |
#define PCI_DEVICE_ID_BROOKTREE_849A 0x0351 |
#define PCI_DEVICE_ID_BROOKTREE_8474 0x8474 |
#define PCI_VENDOR_ID_SIERRA 0x10a8 |
#define PCI_DEVICE_ID_SIERRA_STB 0x0000 |
#define PCI_VENDOR_ID_ACC 0x10aa |
#define PCI_DEVICE_ID_ACC_2056 0x0000 |
#define PCI_VENDOR_ID_WINBOND 0x10ad |
#define PCI_DEVICE_ID_WINBOND_83769 0x0001 |
#define PCI_DEVICE_ID_WINBOND_82C105 0x0105 |
#define PCI_DEVICE_ID_WINBOND_83C553 0x0565 |
#define PCI_VENDOR_ID_DATABOOK 0x10b3 |
#define PCI_DEVICE_ID_DATABOOK_87144 0xb106 |
#define PCI_VENDOR_ID_PLX 0x10b5 |
#define PCI_DEVICE_ID_PLX_9080 0x9080 |
#define PCI_VENDOR_ID_MADGE 0x10b6 |
#define PCI_DEVICE_ID_MADGE_MK2 0x0002 |
#define PCI_VENDOR_ID_3COM 0x10b7 |
#define PCI_DEVICE_ID_3COM_3C339 0x3390 |
#define PCI_DEVICE_ID_3COM_3C590 0x5900 |
#define PCI_DEVICE_ID_3COM_3C595TX 0x5950 |
#define PCI_DEVICE_ID_3COM_3C595T4 0x5951 |
#define PCI_DEVICE_ID_3COM_3C595MII 0x5952 |
#define PCI_DEVICE_ID_3COM_3C900TPO 0x9000 |
#define PCI_DEVICE_ID_3COM_3C900COMBO 0x9001 |
#define PCI_DEVICE_ID_3COM_3C905TX 0x9050 |
#define PCI_DEVICE_ID_3COM_3C905T4 0x9051 |
#define PCI_DEVICE_ID_3COM_3C905B_TX 0x9055 |
#define PCI_VENDOR_ID_SMC 0x10b8 |
#define PCI_DEVICE_ID_SMC_EPIC100 0x0005 |
#define PCI_VENDOR_ID_AL 0x10b9 |
#define PCI_DEVICE_ID_AL_M1445 0x1445 |
#define PCI_DEVICE_ID_AL_M1449 0x1449 |
#define PCI_DEVICE_ID_AL_M1451 0x1451 |
#define PCI_DEVICE_ID_AL_M1461 0x1461 |
#define PCI_DEVICE_ID_AL_M1489 0x1489 |
#define PCI_DEVICE_ID_AL_M1511 0x1511 |
#define PCI_DEVICE_ID_AL_M1513 0x1513 |
#define PCI_DEVICE_ID_AL_M1521 0x1521 |
#define PCI_DEVICE_ID_AL_M1523 0x1523 |
#define PCI_DEVICE_ID_AL_M1531 0x1531 |
#define PCI_DEVICE_ID_AL_M1533 0x1533 |
#define PCI_DEVICE_ID_AL_M3307 0x3307 |
#define PCI_DEVICE_ID_AL_M4803 0x5215 |
#define PCI_DEVICE_ID_AL_M5219 0x5219 |
#define PCI_DEVICE_ID_AL_M5229 0x5229 |
#define PCI_DEVICE_ID_AL_M5237 0x5237 |
#define PCI_DEVICE_ID_AL_M7101 0x7101 |
#define PCI_VENDOR_ID_MITSUBISHI 0x10ba |
#define PCI_VENDOR_ID_SURECOM 0x10bd |
#define PCI_DEVICE_ID_SURECOM_NE34 0x0e34 |
#define PCI_VENDOR_ID_NEOMAGIC 0x10c8 |
#define PCI_DEVICE_ID_NEOMAGIC_MAGICGRAPH_NM2070 0x0001 |
#define PCI_DEVICE_ID_NEOMAGIC_MAGICGRAPH_128V 0x0002 |
#define PCI_DEVICE_ID_NEOMAGIC_MAGICGRAPH_128ZV 0x0003 |
#define PCI_DEVICE_ID_NEOMAGIC_MAGICGRAPH_NM2160 0x0004 |
#define PCI_VENDOR_ID_ASP 0x10cd |
#define PCI_DEVICE_ID_ASP_ABP940 0x1200 |
#define PCI_DEVICE_ID_ASP_ABP940U 0x1300 |
#define PCI_DEVICE_ID_ASP_ABP940UW 0x2300 |
#define PCI_VENDOR_ID_MACRONIX 0x10d9 |
#define PCI_DEVICE_ID_MACRONIX_MX98713 0x0512 |
#define PCI_DEVICE_ID_MACRONIX_MX987x5 0x0531 |
#define PCI_VENDOR_ID_CERN 0x10dc |
#define PCI_DEVICE_ID_CERN_SPSB_PMC 0x0001 |
#define PCI_DEVICE_ID_CERN_SPSB_PCI 0x0002 |
#define PCI_DEVICE_ID_CERN_HIPPI_DST 0x0021 |
#define PCI_DEVICE_ID_CERN_HIPPI_SRC 0x0022 |
#define PCI_VENDOR_ID_NVIDIA 0x10de |
#define PCI_VENDOR_ID_IMS 0x10e0 |
#define PCI_DEVICE_ID_IMS_8849 0x8849 |
#define PCI_VENDOR_ID_TEKRAM2 0x10e1 |
#define PCI_DEVICE_ID_TEKRAM2_690c 0x690c |
#define PCI_VENDOR_ID_TUNDRA 0x10e3 |
#define PCI_DEVICE_ID_TUNDRA_CA91C042 0x0000 |
#define PCI_VENDOR_ID_AMCC 0x10e8 |
#define PCI_DEVICE_ID_AMCC_MYRINET 0x8043 |
#define PCI_DEVICE_ID_AMCC_S5933 0x807d |
#define PCI_DEVICE_ID_AMCC_S5933_HEPC3 0x809c |
#define PCI_VENDOR_ID_INTERG 0x10ea |
#define PCI_DEVICE_ID_INTERG_1680 0x1680 |
#define PCI_DEVICE_ID_INTERG_1682 0x1682 |
#define PCI_VENDOR_ID_REALTEK 0x10ec |
#define PCI_DEVICE_ID_REALTEK_8029 0x8029 |
#define PCI_DEVICE_ID_REALTEK_8129 0x8129 |
#define PCI_DEVICE_ID_REALTEK_8139 0x8139 |
#define PCI_VENDOR_ID_TRUEVISION 0x10fa |
#define PCI_DEVICE_ID_TRUEVISION_T1000 0x000c |
#define PCI_VENDOR_ID_INIT 0x1101 |
#define PCI_DEVICE_ID_INIT_320P 0x9100 |
#define PCI_DEVICE_ID_INIT_360P 0x9500 |
#define PCI_VENDOR_ID_VIA 0x1106 |
#define PCI_DEVICE_ID_VIA_82C505 0x0505 |
#define PCI_DEVICE_ID_VIA_82C561 0x0561 |
#define PCI_DEVICE_ID_VIA_82C586_1 0x0571 |
#define PCI_DEVICE_ID_VIA_82C576 0x0576 |
#define PCI_DEVICE_ID_VIA_82C585 0x0585 |
#define PCI_DEVICE_ID_VIA_82C586_0 0x0586 |
#define PCI_DEVICE_ID_VIA_82C595 0x0595 |
#define PCI_DEVICE_ID_VIA_82C597_0 0x0597 |
#define PCI_DEVICE_ID_VIA_82C926 0x0926 |
#define PCI_DEVICE_ID_VIA_82C416 0x1571 |
#define PCI_DEVICE_ID_VIA_82C595_97 0x1595 |
#define PCI_DEVICE_ID_VIA_82C586_2 0x3038 |
#define PCI_DEVICE_ID_VIA_82C586_3 0x3040 |
#define PCI_DEVICE_ID_VIA_86C100A 0x6100 |
#define PCI_DEVICE_ID_VIA_82C597_1 0x8597 |
#define PCI_VENDOR_ID_VORTEX 0x1119 |
#define PCI_DEVICE_ID_VORTEX_GDT60x0 0x0000 |
#define PCI_DEVICE_ID_VORTEX_GDT6000B 0x0001 |
#define PCI_DEVICE_ID_VORTEX_GDT6x10 0x0002 |
#define PCI_DEVICE_ID_VORTEX_GDT6x20 0x0003 |
#define PCI_DEVICE_ID_VORTEX_GDT6530 0x0004 |
#define PCI_DEVICE_ID_VORTEX_GDT6550 0x0005 |
#define PCI_DEVICE_ID_VORTEX_GDT6x17 0x0006 |
#define PCI_DEVICE_ID_VORTEX_GDT6x27 0x0007 |
#define PCI_DEVICE_ID_VORTEX_GDT6537 0x0008 |
#define PCI_DEVICE_ID_VORTEX_GDT6557 0x0009 |
#define PCI_DEVICE_ID_VORTEX_GDT6x15 0x000a |
#define PCI_DEVICE_ID_VORTEX_GDT6x25 0x000b |
#define PCI_DEVICE_ID_VORTEX_GDT6535 0x000c |
#define PCI_DEVICE_ID_VORTEX_GDT6555 0x000d |
#define PCI_DEVICE_ID_VORTEX_GDT6x17RP 0x0100 |
#define PCI_DEVICE_ID_VORTEX_GDT6x27RP 0x0101 |
#define PCI_DEVICE_ID_VORTEX_GDT6537RP 0x0102 |
#define PCI_DEVICE_ID_VORTEX_GDT6557RP 0x0103 |
#define PCI_DEVICE_ID_VORTEX_GDT6x11RP 0x0104 |
#define PCI_DEVICE_ID_VORTEX_GDT6x21RP 0x0105 |
#define PCI_DEVICE_ID_VORTEX_GDT6x17RP1 0x0110 |
#define PCI_DEVICE_ID_VORTEX_GDT6x27RP1 0x0111 |
#define PCI_DEVICE_ID_VORTEX_GDT6537RP1 0x0112 |
#define PCI_DEVICE_ID_VORTEX_GDT6557RP1 0x0113 |
#define PCI_DEVICE_ID_VORTEX_GDT6x11RP1 0x0114 |
#define PCI_DEVICE_ID_VORTEX_GDT6x21RP1 0x0115 |
#define PCI_DEVICE_ID_VORTEX_GDT6x17RP2 0x0120 |
#define PCI_DEVICE_ID_VORTEX_GDT6x27RP2 0x0121 |
#define PCI_DEVICE_ID_VORTEX_GDT6537RP2 0x0122 |
#define PCI_DEVICE_ID_VORTEX_GDT6557RP2 0x0123 |
#define PCI_DEVICE_ID_VORTEX_GDT6x11RP2 0x0124 |
#define PCI_DEVICE_ID_VORTEX_GDT6x21RP2 0x0125 |
#define PCI_VENDOR_ID_EF 0x111a |
#define PCI_DEVICE_ID_EF_ATM_FPGA 0x0000 |
#define PCI_DEVICE_ID_EF_ATM_ASIC 0x0002 |
#define PCI_VENDOR_ID_FORE 0x1127 |
#define PCI_DEVICE_ID_FORE_PCA200PC 0x0210 |
#define PCI_DEVICE_ID_FORE_PCA200E 0x0300 |
#define PCI_VENDOR_ID_IMAGINGTECH 0x112f |
#define PCI_DEVICE_ID_IMAGINGTECH_ICPCI 0x0000 |
#define PCI_VENDOR_ID_PHILIPS 0x1131 |
#define PCI_DEVICE_ID_PHILIPS_SAA7146 0x7146 |
#define PCI_VENDOR_ID_CYCLONE 0x113c |
#define PCI_DEVICE_ID_CYCLONE_SDK 0x0001 |
#define PCI_VENDOR_ID_ALLIANCE 0x1142 |
#define PCI_DEVICE_ID_ALLIANCE_PROMOTIO 0x3210 |
#define PCI_DEVICE_ID_ALLIANCE_PROVIDEO 0x6422 |
#define PCI_DEVICE_ID_ALLIANCE_AT24 0x6424 |
#define PCI_DEVICE_ID_ALLIANCE_AT3D 0x643d |
#define PCI_VENDOR_ID_VMIC 0x114a |
#define PCI_DEVICE_ID_VMIC_VME 0x7587 |
#define PCI_VENDOR_ID_DIGI 0x114f |
#define PCI_DEVICE_ID_DIGI_EPC 0x0002 |
#define PCI_DEVICE_ID_DIGI_RIGHTSWITCH 0x0003 |
#define PCI_DEVICE_ID_DIGI_XEM 0x0004 |
#define PCI_DEVICE_ID_DIGI_XR 0x0005 |
#define PCI_DEVICE_ID_DIGI_CX 0x0006 |
#define PCI_DEVICE_ID_DIGI_XRJ 0x0009 |
#define PCI_DEVICE_ID_DIGI_EPCJ 0x000a |
#define PCI_DEVICE_ID_DIGI_XR_920 0x0027 |
#define PCI_VENDOR_ID_MUTECH 0x1159 |
#define PCI_DEVICE_ID_MUTECH_MV1000 0x0001 |
#define PCI_VENDOR_ID_RENDITION 0x1163 |
#define PCI_DEVICE_ID_RENDITION_VERITE 0x0001 |
#define PCI_DEVICE_ID_RENDITION_VERITE2100 0x2000 |
#define PCI_VENDOR_ID_TOSHIBA 0x1179 |
#define PCI_DEVICE_ID_TOSHIBA_601 0x0601 |
#define PCI_DEVICE_ID_TOSHIBA_TOPIC95 0x060a |
#define PCI_DEVICE_ID_TOSHIBA_TOPIC97 0x060f |
#define PCI_VENDOR_ID_RICOH 0x1180 |
#define PCI_DEVICE_ID_RICOH_RL5C466 0x0466 |
#define PCI_VENDOR_ID_ARTOP 0x1191 |
#define PCI_DEVICE_ID_ARTOP_ATP850UF 0x0005 |
#define PCI_VENDOR_ID_ZEITNET 0x1193 |
#define PCI_DEVICE_ID_ZEITNET_1221 0x0001 |
#define PCI_DEVICE_ID_ZEITNET_1225 0x0002 |
#define PCI_VENDOR_ID_OMEGA 0x119b |
#define PCI_DEVICE_ID_OMEGA_82C092G 0x1221 |
#define PCI_VENDOR_ID_LITEON 0x11ad |
#define PCI_DEVICE_ID_LITEON_LNE100TX 0x0002 |
#define PCI_VENDOR_ID_NP 0x11bc |
#define PCI_DEVICE_ID_NP_PCI_FDDI 0x0001 |
#define PCI_VENDOR_ID_ATT 0x11c1 |
#define PCI_DEVICE_ID_ATT_L56XMF 0x0440 |
#define PCI_VENDOR_ID_SPECIALIX 0x11cb |
#define PCI_DEVICE_ID_SPECIALIX_XIO 0x4000 |
#define PCI_DEVICE_ID_SPECIALIX_RIO 0x8000 |
#define PCI_VENDOR_ID_AURAVISION 0x11d1 |
#define PCI_DEVICE_ID_AURAVISION_VXP524 0x01f7 |
#define PCI_VENDOR_ID_IKON 0x11d5 |
#define PCI_DEVICE_ID_IKON_10115 0x0115 |
#define PCI_DEVICE_ID_IKON_10117 0x0117 |
#define PCI_VENDOR_ID_ZORAN 0x11de |
#define PCI_DEVICE_ID_ZORAN_36057 0x6057 |
#define PCI_DEVICE_ID_ZORAN_36120 0x6120 |
#define PCI_VENDOR_ID_KINETIC 0x11f4 |
#define PCI_DEVICE_ID_KINETIC_2915 0x2915 |
#define PCI_VENDOR_ID_COMPEX 0x11f6 |
#define PCI_DEVICE_ID_COMPEX_ENET100VG4 0x0112 |
#define PCI_DEVICE_ID_COMPEX_RL2000 0x1401 |
#define PCI_VENDOR_ID_RP 0x11fe |
#define PCI_DEVICE_ID_RP8OCTA 0x0001 |
#define PCI_DEVICE_ID_RP8INTF 0x0002 |
#define PCI_DEVICE_ID_RP16INTF 0x0003 |
#define PCI_DEVICE_ID_RP32INTF 0x0004 |
#define PCI_VENDOR_ID_CYCLADES 0x120e |
#define PCI_DEVICE_ID_CYCLOM_Y_Lo 0x0100 |
#define PCI_DEVICE_ID_CYCLOM_Y_Hi 0x0101 |
#define PCI_DEVICE_ID_CYCLOM_Z_Lo 0x0200 |
#define PCI_DEVICE_ID_CYCLOM_Z_Hi 0x0201 |
#define PCI_VENDOR_ID_ESSENTIAL 0x120f |
#define PCI_DEVICE_ID_ESSENTIAL_ROADRUNNER 0x0001 |
#define PCI_VENDOR_ID_O2 0x1217 |
#define PCI_DEVICE_ID_O2_6832 0x6832 |
#define PCI_VENDOR_ID_3DFX 0x121a |
#define PCI_DEVICE_ID_3DFX_VOODOO 0x0001 |
#define PCI_DEVICE_ID_3DFX_VOODOO2 0x0002 |
#define PCI_VENDOR_ID_SIGMADES 0x1236 |
#define PCI_DEVICE_ID_SIGMADES_6425 0x6401 |
#define PCI_VENDOR_ID_CCUBE 0x123f |
#define PCI_VENDOR_ID_DIPIX 0x1246 |
#define PCI_VENDOR_ID_STALLION 0x124d |
#define PCI_DEVICE_ID_STALLION_ECHPCI832 0x0000 |
#define PCI_DEVICE_ID_STALLION_ECHPCI864 0x0002 |
#define PCI_DEVICE_ID_STALLION_EIOPCI 0x0003 |
#define PCI_VENDOR_ID_OPTIBASE 0x1255 |
#define PCI_DEVICE_ID_OPTIBASE_FORGE 0x1110 |
#define PCI_DEVICE_ID_OPTIBASE_FUSION 0x1210 |
#define PCI_DEVICE_ID_OPTIBASE_VPLEX 0x2110 |
#define PCI_DEVICE_ID_OPTIBASE_VPLEXCC 0x2120 |
#define PCI_DEVICE_ID_OPTIBASE_VQUEST 0x2130 |
#define PCI_VENDOR_ID_SATSAGEM 0x1267 |
#define PCI_DEVICE_ID_SATSAGEM_PCR2101 0x5352 |
#define PCI_DEVICE_ID_SATSAGEM_TELSATTURBO 0x5a4b |
#define PCI_VENDOR_ID_ENSONIQ 0x1274 |
#define PCI_DEVICE_ID_ENSONIQ_AUDIOPCI 0x5000 |
#define PCI_VENDOR_ID_PICTUREL 0x12c5 |
#define PCI_DEVICE_ID_PICTUREL_PCIVST 0x0081 |
#define PCI_VENDOR_ID_NVIDIA_SGS 0x12d2 |
#define PCI_DEVICE_ID_NVIDIA_SGS_RIVA128 0x0018 |
#define PCI_VENDOR_ID_CBOARDS 0x1307 |
#define PCI_DEVICE_ID_CBOARDS_DAS1602_16 0x0001 |
#define PCI_VENDOR_ID_SYMPHONY 0x1c1c |
#define PCI_DEVICE_ID_SYMPHONY_101 0x0001 |
#define PCI_VENDOR_ID_TEKRAM 0x1de1 |
#define PCI_DEVICE_ID_TEKRAM_DC290 0xdc29 |
#define PCI_VENDOR_ID_3DLABS 0x3d3d |
#define PCI_DEVICE_ID_3DLABS_300SX 0x0001 |
#define PCI_DEVICE_ID_3DLABS_500TX 0x0002 |
#define PCI_DEVICE_ID_3DLABS_DELTA 0x0003 |
#define PCI_DEVICE_ID_3DLABS_PERMEDIA 0x0004 |
#define PCI_DEVICE_ID_3DLABS_MX 0x0006 |
#define PCI_VENDOR_ID_AVANCE 0x4005 |
#define PCI_DEVICE_ID_AVANCE_ALG2064 0x2064 |
#define PCI_DEVICE_ID_AVANCE_2302 0x2302 |
#define PCI_VENDOR_ID_NETVIN 0x4a14 |
#define PCI_DEVICE_ID_NETVIN_NV5000SC 0x5000 |
#define PCI_VENDOR_ID_S3 0x5333 |
#define PCI_DEVICE_ID_S3_PLATO_PXS 0x0551 |
#define PCI_DEVICE_ID_S3_ViRGE 0x5631 |
#define PCI_DEVICE_ID_S3_TRIO 0x8811 |
#define PCI_DEVICE_ID_S3_AURORA64VP 0x8812 |
#define PCI_DEVICE_ID_S3_TRIO64UVP 0x8814 |
#define PCI_DEVICE_ID_S3_ViRGE_VX 0x883d |
#define PCI_DEVICE_ID_S3_868 0x8880 |
#define PCI_DEVICE_ID_S3_928 0x88b0 |
#define PCI_DEVICE_ID_S3_864_1 0x88c0 |
#define PCI_DEVICE_ID_S3_864_2 0x88c1 |
#define PCI_DEVICE_ID_S3_964_1 0x88d0 |
#define PCI_DEVICE_ID_S3_964_2 0x88d1 |
#define PCI_DEVICE_ID_S3_968 0x88f0 |
#define PCI_DEVICE_ID_S3_TRIO64V2 0x8901 |
#define PCI_DEVICE_ID_S3_PLATO_PXG 0x8902 |
#define PCI_DEVICE_ID_S3_ViRGE_DXGX 0x8a01 |
#define PCI_DEVICE_ID_S3_ViRGE_GX2 0x8a10 |
#define PCI_DEVICE_ID_S3_ViRGE_MX 0x8c01 |
#define PCI_DEVICE_ID_S3_ViRGE_MXP 0x8c02 |
#define PCI_DEVICE_ID_S3_ViRGE_MXPMV 0x8c03 |
#define PCI_DEVICE_ID_S3_SONICVIBES 0xca00 |
#define PCI_VENDOR_ID_INTEL 0x8086 |
#define PCI_DEVICE_ID_INTEL_82375 0x0482 |
#define PCI_DEVICE_ID_INTEL_82424 0x0483 |
#define PCI_DEVICE_ID_INTEL_82378 0x0484 |
#define PCI_DEVICE_ID_INTEL_82430 0x0486 |
#define PCI_DEVICE_ID_INTEL_82434 0x04a3 |
#define PCI_DEVICE_ID_INTEL_82092AA_0 0x1221 |
#define PCI_DEVICE_ID_INTEL_82092AA_1 0x1222 |
#define PCI_DEVICE_ID_INTEL_7116 0x1223 |
#define PCI_DEVICE_ID_INTEL_82596 0x1226 |
#define PCI_DEVICE_ID_INTEL_82865 0x1227 |
#define PCI_DEVICE_ID_INTEL_82557 0x1229 |
#define PCI_DEVICE_ID_INTEL_82437 0x122d |
#define PCI_DEVICE_ID_INTEL_82371_0 0x122e |
#define PCI_DEVICE_ID_INTEL_82371_1 0x1230 |
#define PCI_DEVICE_ID_INTEL_82371MX 0x1234 |
#define PCI_DEVICE_ID_INTEL_82437MX 0x1235 |
#define PCI_DEVICE_ID_INTEL_82441 0x1237 |
#define PCI_DEVICE_ID_INTEL_82380FB 0x124b |
#define PCI_DEVICE_ID_INTEL_82439 0x1250 |
#define PCI_DEVICE_ID_INTEL_82371SB_0 0x7000 |
#define PCI_DEVICE_ID_INTEL_82371SB_1 0x7010 |
#define PCI_DEVICE_ID_INTEL_82371SB_2 0x7020 |
#define PCI_DEVICE_ID_INTEL_82437VX 0x7030 |
#define PCI_DEVICE_ID_INTEL_82439TX 0x7100 |
#define PCI_DEVICE_ID_INTEL_82371AB_0 0x7110 |
#define PCI_DEVICE_ID_INTEL_82371AB 0x7111 |
#define PCI_DEVICE_ID_INTEL_82371AB_2 0x7112 |
#define PCI_DEVICE_ID_INTEL_82371AB_3 0x7113 |
#define PCI_DEVICE_ID_INTEL_82443LX_0 0x7180 |
#define PCI_DEVICE_ID_INTEL_82443LX_1 0x7181 |
#define PCI_DEVICE_ID_INTEL_82443BX_0 0x7190 |
#define PCI_DEVICE_ID_INTEL_82443BX_1 0x7191 |
#define PCI_DEVICE_ID_INTEL_82443BX_2 0x7192 |
#define PCI_DEVICE_ID_INTEL_P6 0x84c4 |
#define PCI_DEVICE_ID_INTEL_82450GX 0x84c5 |
#define PCI_VENDOR_ID_KTI 0x8e2e |
#define PCI_DEVICE_ID_KTI_ET32P2 0x3000 |
#define PCI_VENDOR_ID_ADAPTEC 0x9004 |
#define PCI_DEVICE_ID_ADAPTEC_7810 0x1078 |
#define PCI_DEVICE_ID_ADAPTEC_7850 0x5078 |
#define PCI_DEVICE_ID_ADAPTEC_7855 0x5578 |
#define PCI_DEVICE_ID_ADAPTEC_5800 0x5800 |
#define PCI_DEVICE_ID_ADAPTEC_7860 0x6078 |
#define PCI_DEVICE_ID_ADAPTEC_7861 0x6178 |
#define PCI_DEVICE_ID_ADAPTEC_7870 0x7078 |
#define PCI_DEVICE_ID_ADAPTEC_7871 0x7178 |
#define PCI_DEVICE_ID_ADAPTEC_7872 0x7278 |
#define PCI_DEVICE_ID_ADAPTEC_7873 0x7378 |
#define PCI_DEVICE_ID_ADAPTEC_7874 0x7478 |
#define PCI_DEVICE_ID_ADAPTEC_7895 0x7895 |
#define PCI_DEVICE_ID_ADAPTEC_7880 0x8078 |
#define PCI_DEVICE_ID_ADAPTEC_7881 0x8178 |
#define PCI_DEVICE_ID_ADAPTEC_7882 0x8278 |
#define PCI_DEVICE_ID_ADAPTEC_7883 0x8378 |
#define PCI_DEVICE_ID_ADAPTEC_7884 0x8478 |
#define PCI_DEVICE_ID_ADAPTEC_1030 0x8b78 |
#define PCI_VENDOR_ID_ATRONICS 0x907f |
#define PCI_DEVICE_ID_ATRONICS_2015 0x2015 |
#define PCI_VENDOR_ID_HER 0xedd8 |
#define PCI_DEVICE_ID_HER_STING 0xa091 |
#define PCI_DEVICE_ID_HER_STINGARK 0xa099 |
#define PCI_VENDOR_ID_HOLTEK 0x9412 |
#define PCI_DEVICE_ID_HOLTEK_6565 0x6565 |
#define PCI_VENDOR_ID_TIGERJET 0xe159 |
#define PCI_DEVICE_ID_TIGERJET_300 0x0001 |
#define PCI_VENDOR_ID_ARK 0xedd8 |
#define PCI_DEVICE_ID_ARK_STING 0xa091 |
#define PCI_DEVICE_ID_ARK_STINGARK 0xa099 |
#define PCI_DEVICE_ID_ARK_2000MT 0xa0a1 |
/* |
* The PCI interface treats multi-function devices as independent |
* devices. The slot/function address of each device is encoded |
* in a single byte as follows: |
* |
* 7:3 = slot |
* 2:0 = function |
*/ |
#define PCI_DEVFN(slot,func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) |
#define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) |
#define PCI_FUNC(devfn) ((devfn) & 0x07) |
/* |
* There is one pci_dev structure for each slot-number/function-number |
* combination: |
*/ |
struct pci_dev { |
struct pci_bus *bus; /* bus this device is on */ |
struct pci_dev *sibling; /* next device on this bus */ |
struct pci_dev *next; /* chain of all devices */ |
void *sysdata; /* hook for sys-specific extension */ |
struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */ |
unsigned int devfn; /* encoded device & function index */ |
unsigned short vendor; |
unsigned short device; |
unsigned int class; /* 3 bytes: (base,sub,prog-if) */ |
unsigned int hdr_type; /* PCI header type */ |
unsigned int master : 1; /* set if device is master capable */ |
/* |
* In theory, the irq level can be read from configuration |
* space and all would be fine. However, old PCI chips don't |
* support these registers and return 0 instead. For example, |
* the Vision864-P rev 0 chip can uses INTA, but returns 0 in |
* the interrupt line and pin registers. pci_init() |
* initializes this field with the value at PCI_INTERRUPT_LINE |
* and it is the job of pcibios_fixup() to change it if |
* necessary. The field must not be 0 unless the device |
* cannot generate interrupts at all. |
*/ |
unsigned int irq; /* irq generated by this device */ |
/* Base registers for this device, can be adjusted by |
* pcibios_fixup() as necessary. |
*/ |
unsigned long base_address[6]; |
unsigned long rom_address; |
}; |
struct pci_bus { |
struct pci_bus *parent; /* parent bus this bridge is on */ |
struct pci_bus *children; /* chain of P2P bridges on this bus */ |
struct pci_bus *next; /* chain of all PCI buses */ |
struct pci_dev *self; /* bridge device as seen by parent */ |
struct pci_dev *devices; /* devices behind this bridge */ |
void *sysdata; /* hook for sys-specific extension */ |
struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */ |
unsigned char number; /* bus number */ |
unsigned char primary; /* number of primary bridge */ |
unsigned char secondary; /* number of secondary bridge */ |
unsigned char subordinate; /* max number of subordinate buses */ |
}; |
/* |
* This is used to map a vendor-id/device-id pair into device-specific |
* information. |
*/ |
struct pci_dev_info { |
unsigned short vendor; /* vendor id */ |
unsigned short device; /* device id */ |
const char *name; /* device name */ |
unsigned char bridge_type; /* bridge type or 0xff */ |
}; |
extern struct pci_bus pci_root; /* root bus */ |
extern struct pci_dev *pci_devices; /* list of all devices */ |
/* Generic PCI interface functions */ |
void pci_setup(char *str, int *ints); /* ??? */ |
void pci_quirks_init(void); /* ??? */ |
DWORD pci_scan_bus(struct pci_bus *bus); |
struct pci_bus *pci_scan_peer_bridge(int bus); |
int get_pci_list(char *buf); /* ??? */ |
struct pci_dev *pci_find_device (unsigned int vendor, unsigned int device, struct pci_dev *from); |
struct pci_dev *pci_find_class (unsigned int class, struct pci_dev *from); |
struct pci_dev *pci_find_slot (unsigned int bus, unsigned int devfn); |
#define pci_present pcibios_present |
int pci_read_config_byte(struct pci_dev *dev, BYTE where, BYTE *val); |
int pci_read_config_word(struct pci_dev *dev, BYTE where, WORD *val); |
int pci_read_config_dword(struct pci_dev *dev, BYTE where, DWORD *val); |
int pci_write_config_byte(struct pci_dev *dev, BYTE where, BYTE val); |
int pci_write_config_word(struct pci_dev *dev, BYTE where, WORD val); |
int pci_write_config_dword(struct pci_dev *dev, BYTE where, DWORD val); |
void pci_set_master(struct pci_dev *dev); |
extern const char *pci_strclass (unsigned int class); |
extern const char *pci_strvendor (unsigned int vendor); |
__END_DECLS |
#endif /* LINUX_PCI_H */ |
/shark/trunk/drivers/oldpci/pci.h |
---|
0,0 → 1,78 |
/* Project: HARTIK 3.0 Network Library */ |
/* Description: Hard Real TIme Kernel for 8086 compatible */ |
/* Author: Luca Abeni */ |
/* Date: 14/4/1997 */ |
/* File: PCI.H */ |
/* Revision: 1.02 */ |
#ifndef __PCI_H__ |
#define __PCI_H__ |
#include "ll/sys/cdefs.h" |
__BEGIN_DECLS |
#define N_MAX_DEVS 10 |
typedef struct pci_regs { |
WORD VendorId; |
WORD DeviceId; |
WORD PciCommand; |
WORD PciStatus; |
BYTE reserved1; |
BYTE dummy; |
WORD ClassCode; |
BYTE reserved2; |
BYTE LatencyTimer; |
BYTE HeaderType; |
BYTE reserved3; |
DWORD IoBaseAddress; |
DWORD reserved4; |
DWORD reserved5; |
DWORD reserved6; |
DWORD reserved7; |
DWORD reserved8; |
DWORD reserved9; |
DWORD reserved10; |
DWORD BiosRomControl; |
DWORD reserved11; |
DWORD reserver12; |
BYTE InterruptLine; |
BYTE InterruptPin; |
BYTE MinGnt; |
BYTE MaxLat; |
DWORD InternalConfig; |
} PCI_REGS; |
typedef struct pci_des { |
BYTE bus; |
BYTE dev; |
BYTE mem[256]; |
} PCI_DES; |
/* |
* Error values that may be returned by the PCI bios. Use |
* pcibios_strerror() to convert to a printable string. |
*/ |
#define PCIBIOS_SUCCESSFUL 0x00 |
#define PCIBIOS_FUNC_NOT_SUPPORTED 0x81 |
#define PCIBIOS_BAD_VENDOR_ID 0x83 |
#define PCIBIOS_DEVICE_NOT_FOUND 0x86 |
#define PCIBIOS_BAD_REGISTER_NUMBER 0x87 |
#define PCIBIOS_SET_FAILED 0x88 |
#define PCIBIOS_BUFFER_TOO_SMALL 0x89 |
/*int pci_detect(struct pci_des *p_des); |
void pci_show(struct pci_des *PCIdes, int n);*/ |
int pci_init(void); |
void pci_show(void); |
int scan_bus(struct pci_des *p_des); |
struct pci_regs *pci_class(DWORD class_code, WORD index, BYTE *bus, BYTE *dev); |
struct pci_regs *pci_device(WORD vendor, WORD device, WORD index, BYTE *bus, BYTE *dev); |
__END_DECLS |
#endif |
/shark/trunk/drivers/oldpci/llpci.c |
---|
0,0 → 1,191 |
#include <ll/i386/hw-instr.h> |
#include <ll/i386/hw-data.h> |
#include <ll/i386/hw-arch.h> |
#include <ll/i386/hw-io.h> |
#include <drivers/llpci.h> |
int (*pcibios_read_config_byte)(BYTE bus, BYTE dev, BYTE where, BYTE *val); |
int (*pcibios_read_config_word)(BYTE bus, BYTE dev, BYTE where, WORD *val); |
int (*pcibios_read_config_dword)(BYTE bus, BYTE dev, BYTE where, DWORD *val); |
int (*pcibios_write_config_byte)(BYTE bus, BYTE dev, BYTE where, BYTE val); |
int (*pcibios_write_config_word)(BYTE bus, BYTE dev, BYTE where, WORD val); |
int (*pcibios_write_config_dword)(BYTE bus, BYTE dev, BYTE where, DWORD val); |
static int PCItype = 0; |
/* LowLevel Functions */ |
int pci_conf1_read_config_dword(BYTE bus, BYTE dev, BYTE where, DWORD *val) |
{ |
if (where & 3) |
return -1; |
outpd(0x0CF8, 0x80000000 | (bus <<16) | (dev << 8) | (where & ~3)); |
*val = inpd(0x0CFC); |
return 1; |
} |
int pci_conf2_read_config_dword(BYTE bus, BYTE dev, BYTE where, DWORD *val) |
{ |
if (dev & 0x80) |
return -1; |
outpw(0xCF8, (((dev & 7) << 1) | 0xf0)); |
outpw(0xCFA, bus); |
*val = inpd((0xC000 | ((dev & 0x78) << 5)) + where); |
outpw(0xCF8,0); |
return 1; |
} |
int pci_conf1_read_config_byte(BYTE bus, BYTE dev, BYTE where, BYTE *val) |
{ |
outpd(0x0CF8, 0x80000000 | (bus <<16) | (dev << 8) | (where & ~3)); |
*val = inp(0x0CFC + (where & 3)); |
return 1; |
} |
int pci_conf2_read_config_byte(BYTE bus, BYTE dev, BYTE where, BYTE *val) |
{ |
if (dev & 0x80) |
return -1; |
outpw(0xCF8, (((dev & 7) << 1) | 0xf0)); |
outpw(0xCFA, bus); |
*val = inp((0xC000 | ((dev & 0x78) << 5)) + where); |
outpw(0xCF8,0); |
return 1; |
} |
int pci_conf1_read_config_word(BYTE bus, BYTE dev, BYTE where, WORD *val) |
{ |
if (where & 1) |
return -1; |
outpd(0x0CF8, 0x80000000 | (bus <<16) | (dev << 8) | (where & ~3)); |
*val = inpw(0x0CFC + (where & 2)); |
return 1; |
} |
int pci_conf2_read_config_word(BYTE bus, BYTE dev, BYTE where, WORD *val) |
{ |
if (dev & 0x80) |
return -1; |
outpw(0xCF8, (((dev & 7) << 1) | 0xf0)); |
outpw(0xCFA, bus); |
*val = inpw((0xC000 | ((dev & 0x78) << 5)) + where); |
/* *val = inpw(0xC000 | ((dev & 0x78) << 5) + where); */ |
outpw(0xCF8,0); |
return 1; |
} |
int pci_conf1_write_config_dword(BYTE bus, BYTE dev, BYTE where, DWORD val) |
{ |
if (where & 3) |
return -1; |
outpd(0x0CF8, 0x80000000 | (bus <<16) | (dev << 8) | (where & ~3)); |
outpd(0x0CFC, val); |
return 1; |
} |
int pci_conf2_write_config_dword(BYTE bus, BYTE dev, BYTE where, DWORD val) |
{ |
if (dev & 0x80) |
return -1; |
outpw(0xCF8, (((dev & 7) << 1) | 0xf0)); |
outpw(0xCFA, bus); |
outpd((0xC000 | ((dev & 0x78) << 5)) + where, val); |
outpw(0xCF8,0); |
return 1; |
} |
int pci_conf1_write_config_byte(BYTE bus, BYTE dev, BYTE where, BYTE val) |
{ |
outpd(0x0CF8, 0x80000000 | (bus <<16) | (dev << 8) | (where & ~3)); |
outp(0x0CFC + (where & 3), val); |
return 1; |
} |
int pci_conf2_write_config_byte(BYTE bus, BYTE dev, BYTE where, BYTE val) |
{ |
if (dev & 0x80) |
return -1; |
outpw(0xCF8, (((dev & 7) << 1) | 0xf0)); |
outpw(0xCFA, bus); |
outp((0xC000 | ((dev & 0x78) << 5)) + where, val); |
outpw(0xCF8,0); |
return 1; |
} |
int pci_conf1_write_config_word(BYTE bus, BYTE dev, BYTE where, WORD val) |
{ |
if (where & 1) |
return -1; |
outpd(0x0CF8, 0x80000000 | (bus <<16) | (dev << 8) | (where & ~3)); |
outpw(0x0CFC + (where & 2), val); |
return 1; |
} |
int pci_conf2_write_config_word(BYTE bus, BYTE dev, BYTE where, WORD val) |
{ |
if (dev & 0x80) |
return -1; |
outpw(0xCF8, (((dev & 7) << 1) | 0xf0)); |
outpw(0xCFA, bus); |
outpw((0xC000 | ((dev & 0x78) << 5)) + where, val); |
outpw(0xCF8,0); |
return 1; |
} |
int pci_check_direct() |
{ |
int PCItype; |
DWORD tmp; |
PCItype = 0; |
outp(0xCFB, 0x01); |
tmp = inpd(0xCF8); |
outpd(0xCF8, 0x80000000); |
if (inpd(0xCF8) == 0x80000000) { |
outpd(0xCF8, tmp); |
pcibios_read_config_dword = pci_conf1_read_config_dword; |
pcibios_read_config_word = pci_conf1_read_config_word; |
pcibios_read_config_byte = pci_conf1_read_config_byte; |
pcibios_write_config_dword = pci_conf1_write_config_dword; |
pcibios_write_config_word = pci_conf1_write_config_word; |
pcibios_write_config_byte = pci_conf1_write_config_byte; |
PCItype = 1; |
} |
outpw(0x0CF8,tmp); |
outp(0xCFB, 0); |
outp(0xCF8, 0); |
outp(0x0CFA,0); |
if ((inp(0x0CF8) == 0) && (inp(0x0CFA) == 0)) { |
pcibios_read_config_dword = pci_conf2_read_config_dword; |
pcibios_read_config_word = pci_conf2_read_config_word; |
pcibios_read_config_byte = pci_conf2_read_config_byte; |
pcibios_write_config_dword = pci_conf2_write_config_dword; |
pcibios_write_config_word = pci_conf2_write_config_word; |
pcibios_write_config_byte = pci_conf2_write_config_byte; |
PCItype = 2; |
} |
return PCItype; |
} |
/*__________________________________________________________________________*/ |
/*__________________________________________________________________________*/ |
int pcibios_present(void) |
{ |
return (PCItype != 0); |
} |
int pcibios_init(void) |
{ |
if (ll_arch.x86.cpu < 3) { |
return -1; /* CPU < 386 --> No PCI */ |
} |
PCItype = pci_check_direct(); |
if (PCItype == 0) { |
return -1; |
} |
return 1; |
} |
/shark/trunk/drivers/oldpci/TODO |
---|
0,0 → 1,4 |
Some tests... |
1) for the PCI raw interface |
2) for the devlib interface (inherited from HARTIK) |
3) for the Linux Interface... :) |
/shark/trunk/drivers/oldpci/pci.c |
---|
0,0 → 1,158 |
#include <ll/i386/hw-instr.h> |
#include <ll/i386/hw-data.h> |
#include <ll/i386/hw-arch.h> |
#include <ll/i386/hw-io.h> |
#include <ll/i386/cons.h> |
#include <ll/stdlib.h> |
#include <drivers/llpci.h> |
#include <drivers/pci.h> |
#include <drivers/linuxpci.h> |
#include <kernel/log.h> |
static int ndev = 0; |
static struct pci_des pci_devs[N_MAX_DEVS]; |
static int initialized = 0; |
/* scan the bus to find all the connected devices */ |
int scan_bus(struct pci_des *p_des) |
{ |
int ndev; |
DWORD tmp; |
BYTE hdr; |
int j, ok; |
BYTE bus, b; |
WORD dev; |
int present; |
if (pcibios_present() == 0) return -1; |
ndev = 0; |
for (bus = 0; bus <= 1; bus++) { |
for (dev = 0; dev <= 0xFF; dev++) { |
present = 0; |
if ((dev & 0x07) == 0) { |
present = pcibios_read_config_byte(bus, dev, 0x0e, &hdr); |
} |
if (hdr & 0x80) { |
present = 1; |
} |
if (present) { |
ok = pcibios_read_config_dword(bus, dev, 0, &tmp); |
if ( ok && (((tmp & 0xFFFF) != 0xFFFF) && ((tmp >> 16) != 0xFFFF))) { |
p_des[ndev].bus = bus; |
p_des[ndev].dev = dev; |
for (j = 0; j <= 255; j++) { |
pcibios_read_config_byte(bus, dev, j, &b); |
p_des[ndev].mem[j] = b; |
} |
ndev++; |
} |
} |
} |
} |
return ndev; |
} |
struct pci_regs *pci_device(WORD vendor, WORD device, WORD index, BYTE *bus, BYTE *dev) |
{ |
int i, curr; |
struct pci_regs *regs; |
curr = 0; |
for (i = 0; i < ndev; i++) { |
regs = (struct pci_regs *)pci_devs[i].mem; |
if ((regs->VendorId == vendor) && (regs->DeviceId == device)) { |
if (curr == index) { |
*dev = pci_devs[i].dev; |
*bus = pci_devs[i].bus; |
return regs; |
} |
++curr; |
} |
} |
return NULL; |
} |
struct pci_regs *pci_class(DWORD class_code, WORD index, BYTE *bus, BYTE *dev) |
{ |
int i, curr; |
struct pci_regs *regs; |
curr = 0; |
for (i = 0; i < ndev; i++) { |
regs = (struct pci_regs *)pci_devs[i].mem; |
if ((regs->ClassCode << 8) == class_code) { |
if (curr == index) { |
*dev = pci_devs[i].dev; |
*bus = pci_devs[i].bus; |
return regs; |
} |
++curr; |
} |
} |
return NULL; |
} |
int pcibios_find_device(WORD vendor, WORD device, WORD index, BYTE *bus, BYTE *dev) |
{ |
if (pci_device(vendor, device, index, bus, dev) != NULL) { |
return PCIBIOS_SUCCESSFUL; |
} else { |
return PCIBIOS_DEVICE_NOT_FOUND; |
} |
} |
int pcibios_find_class(DWORD class_code, WORD index, BYTE *bus, BYTE *dev) |
{ |
if (pci_class(class_code, index, bus, dev) != NULL) { |
#ifdef DEBUG_PCI |
printk(KERN_DEBUG "PCIBIOS_FIND_CLASS:" |
"found at bus %d, dev %d\n", *bus, *dev); |
#endif |
return PCIBIOS_SUCCESSFUL; |
} else { |
return PCIBIOS_DEVICE_NOT_FOUND; |
} |
} |
/* shows the detected devices */ |
void pci_show(void) |
{ |
int i; |
struct pci_regs *r; |
printk(KERN_INFO "DevLib PCI support\n\n"); |
printk(KERN_INFO "PCI config type %d\n", pcibios_present()); |
printk(KERN_INFO "%d PCI devices found:\n\n", ndev); |
for(i = 0; i < ndev; i++) { |
r = (struct pci_regs *) pci_devs[i].mem; |
printk(KERN_INFO "%d: bus %d dev %d\n", |
i, pci_devs[i].bus, pci_devs[i].dev); |
printk(KERN_INFO "Vendor: %s Class: %s\n", pci_strvendor(r->VendorId), |
pci_strclass(r->ClassCode << 8)); |
} |
} |
/*Linux-->unsigned long pci_init(unsigned long mem_start, unsigned long mem_end) */ |
/* H-PCI --> void pci_init(void) */ |
/* (mem_start/mem_end have no sense) */ |
int pci_init(void) |
{ |
if (initialized == 1) return 1; |
if (pcibios_init() == -1) { |
return -1; |
} |
ndev = scan_bus(pci_devs); |
initialized = 1; |
return 1; |
} |
/shark/trunk/drivers/oldpci/linuxpci.c |
---|
0,0 → 1,169 |
#include <ll/i386/hw-data.h> |
#include "linuxpci.h" |
/***************************************************************************/ |
/* This is from Linux!!! */ |
/***************************************************************************/ |
const char *pci_strclass (unsigned int class) |
{ |
switch (class >> 8) { |
case PCI_CLASS_NOT_DEFINED: return "Non-VGA device"; |
case PCI_CLASS_NOT_DEFINED_VGA: return "VGA compatible device"; |
case PCI_CLASS_STORAGE_SCSI: return "SCSI storage controller"; |
case PCI_CLASS_STORAGE_IDE: return "IDE interface"; |
case PCI_CLASS_STORAGE_FLOPPY: return "Floppy disk controller"; |
case PCI_CLASS_STORAGE_IPI: return "IPI bus controller"; |
case PCI_CLASS_STORAGE_RAID: return "RAID bus controller"; |
case PCI_CLASS_STORAGE_OTHER: return "Unknown mass storage controller"; |
case PCI_CLASS_NETWORK_ETHERNET: return "Ethernet controller"; |
case PCI_CLASS_NETWORK_TOKEN_RING: return "Token ring network controller"; |
case PCI_CLASS_NETWORK_FDDI: return "FDDI network controller"; |
case PCI_CLASS_NETWORK_ATM: return "ATM network controller"; |
case PCI_CLASS_NETWORK_OTHER: return "Network controller"; |
case PCI_CLASS_DISPLAY_VGA: return "VGA compatible controller"; |
case PCI_CLASS_DISPLAY_XGA: return "XGA compatible controller"; |
case PCI_CLASS_DISPLAY_OTHER: return "Display controller"; |
case PCI_CLASS_MULTIMEDIA_VIDEO: return "Multimedia video controller"; |
case PCI_CLASS_MULTIMEDIA_AUDIO: return "Multimedia audio controller"; |
case PCI_CLASS_MULTIMEDIA_OTHER: return "Multimedia controller"; |
case PCI_CLASS_MEMORY_RAM: return "RAM memory"; |
case PCI_CLASS_MEMORY_FLASH: return "FLASH memory"; |
case PCI_CLASS_MEMORY_OTHER: return "Memory"; |
case PCI_CLASS_BRIDGE_HOST: return "Host bridge"; |
case PCI_CLASS_BRIDGE_ISA: return "ISA bridge"; |
case PCI_CLASS_BRIDGE_EISA: return "EISA bridge"; |
case PCI_CLASS_BRIDGE_MC: return "MicroChannel bridge"; |
case PCI_CLASS_BRIDGE_PCI: return "PCI bridge"; |
case PCI_CLASS_BRIDGE_PCMCIA: return "PCMCIA bridge"; |
case PCI_CLASS_BRIDGE_NUBUS: return "NuBus bridge"; |
case PCI_CLASS_BRIDGE_CARDBUS: return "CardBus bridge"; |
case PCI_CLASS_BRIDGE_OTHER: return "Bridge"; |
case PCI_CLASS_COMMUNICATION_SERIAL: return "Serial controller"; |
case PCI_CLASS_COMMUNICATION_PARALLEL: return "Parallel controller"; |
case PCI_CLASS_COMMUNICATION_OTHER: return "Communication controller"; |
case PCI_CLASS_SYSTEM_PIC: return "PIC"; |
case PCI_CLASS_SYSTEM_DMA: return "DMA controller"; |
case PCI_CLASS_SYSTEM_TIMER: return "Timer"; |
case PCI_CLASS_SYSTEM_RTC: return "RTC"; |
case PCI_CLASS_SYSTEM_OTHER: return "System peripheral"; |
case PCI_CLASS_INPUT_KEYBOARD: return "Keyboard controller"; |
case PCI_CLASS_INPUT_PEN: return "Digitizer Pen"; |
case PCI_CLASS_INPUT_MOUSE: return "Mouse controller"; |
case PCI_CLASS_INPUT_OTHER: return "Input device controller"; |
case PCI_CLASS_DOCKING_GENERIC: return "Generic Docking Station"; |
case PCI_CLASS_DOCKING_OTHER: return "Docking Station"; |
case PCI_CLASS_PROCESSOR_386: return "386"; |
case PCI_CLASS_PROCESSOR_486: return "486"; |
case PCI_CLASS_PROCESSOR_PENTIUM: return "Pentium"; |
case PCI_CLASS_PROCESSOR_ALPHA: return "Alpha"; |
case PCI_CLASS_PROCESSOR_POWERPC: return "Power PC"; |
case PCI_CLASS_PROCESSOR_CO: return "Co-processor"; |
case PCI_CLASS_SERIAL_FIREWIRE: return "FireWire (IEEE 1394)"; |
case PCI_CLASS_SERIAL_ACCESS: return "ACCESS Bus"; |
case PCI_CLASS_SERIAL_SSA: return "SSA"; |
case PCI_CLASS_SERIAL_USB: return "USB Controller"; |
case PCI_CLASS_SERIAL_FIBER: return "Fiber Channel"; |
default: return "Unknown class"; |
} |
} |
const char *pci_strvendor(unsigned int vendor) |
{ |
switch (vendor) { |
case PCI_VENDOR_ID_COMPAQ: return "Compaq"; |
case PCI_VENDOR_ID_NCR: return "NCR"; |
case PCI_VENDOR_ID_ATI: return "ATI"; |
case PCI_VENDOR_ID_VLSI: return "VLSI"; |
case PCI_VENDOR_ID_ADL: return "Advance Logic"; |
case PCI_VENDOR_ID_NS: return "NS"; |
case PCI_VENDOR_ID_TSENG: return "Tseng'Lab"; |
case PCI_VENDOR_ID_WEITEK: return "Weitek"; |
case PCI_VENDOR_ID_DEC: return "DEC"; |
case PCI_VENDOR_ID_CIRRUS: return "Cirrus Logic"; |
case PCI_VENDOR_ID_IBM: return "IBM"; |
case PCI_VENDOR_ID_WD: return "Western Digital"; |
case PCI_VENDOR_ID_AMD: return "AMD"; |
case PCI_VENDOR_ID_TRIDENT: return "Trident"; |
case PCI_VENDOR_ID_AI: return "Acer Incorporated"; |
case PCI_VENDOR_ID_MATROX: return "Matrox"; |
case PCI_VENDOR_ID_CT: return "Chips & Technologies"; |
case PCI_VENDOR_ID_MIRO: return "Miro"; |
case PCI_VENDOR_ID_FD: return "Future Domain"; |
case PCI_VENDOR_ID_SI: return "Silicon Integrated Systems"; |
case PCI_VENDOR_ID_HP: return "Hewlett Packard"; |
case PCI_VENDOR_ID_PCTECH: return "PCTECH"; |
case PCI_VENDOR_ID_DPT: return "DPT"; |
case PCI_VENDOR_ID_OPTI: return "OPTI"; |
case PCI_VENDOR_ID_SGS: return "SGS Thomson"; |
case PCI_VENDOR_ID_BUSLOGIC: return "BusLogic"; |
case PCI_VENDOR_ID_OAK: return "OAK"; |
case PCI_VENDOR_ID_PROMISE: return "Promise Technology"; |
case PCI_VENDOR_ID_N9: return "Number Nine"; |
case PCI_VENDOR_ID_UMC: return "UMC"; |
case PCI_VENDOR_ID_X: return "X TECHNOLOGY"; |
case PCI_VENDOR_ID_NEXGEN: return "Nexgen"; |
case PCI_VENDOR_ID_QLOGIC: return "Q Logic"; |
case PCI_VENDOR_ID_LEADTEK: return "Leadtek Research"; |
case PCI_VENDOR_ID_CONTAQ: return "Contaq"; |
case PCI_VENDOR_ID_FOREX: return "Forex"; |
case PCI_VENDOR_ID_OLICOM: return "Olicom"; |
case PCI_VENDOR_ID_CMD: return "CMD"; |
case PCI_VENDOR_ID_VISION: return "Vision"; |
case PCI_VENDOR_ID_SIERRA: return "Sierra"; |
case PCI_VENDOR_ID_ACC: return "ACC MICROELECTRONICS"; |
case PCI_VENDOR_ID_WINBOND: return "Winbond"; |
case PCI_VENDOR_ID_3COM: return "3Com"; |
case PCI_VENDOR_ID_AL: return "Acer Labs"; |
case PCI_VENDOR_ID_ASP: return "Advanced System Products"; |
case PCI_VENDOR_ID_CERN: return "CERN"; |
case PCI_VENDOR_ID_IMS: return "IMS"; |
case PCI_VENDOR_ID_TEKRAM2: return "Tekram"; |
case PCI_VENDOR_ID_AMCC: return "AMCC"; |
case PCI_VENDOR_ID_INTERG: return "Intergraphics"; |
case PCI_VENDOR_ID_REALTEK: return "Realtek"; |
case PCI_VENDOR_ID_INIT: return "Initio Corp"; |
case PCI_VENDOR_ID_VIA: return "VIA Technologies"; |
case PCI_VENDOR_ID_VORTEX: return "VORTEX"; |
case PCI_VENDOR_ID_EF: return "Efficient Networks"; |
case PCI_VENDOR_ID_FORE: return "Fore Systems"; |
case PCI_VENDOR_ID_IMAGINGTECH: return "Imaging Technology"; |
case PCI_VENDOR_ID_PLX: return "PLX"; |
case PCI_VENDOR_ID_ALLIANCE: return "Alliance"; |
case PCI_VENDOR_ID_VMIC: return "VMIC"; |
case PCI_VENDOR_ID_DIGI: return "Digi Intl."; |
case PCI_VENDOR_ID_MUTECH: return "Mutech"; |
case PCI_VENDOR_ID_TOSHIBA: return "Toshiba"; |
case PCI_VENDOR_ID_ZEITNET: return "ZeitNet"; |
case PCI_VENDOR_ID_SPECIALIX: return "Specialix"; |
case PCI_VENDOR_ID_RP: return "Comtrol"; |
case PCI_VENDOR_ID_CYCLADES: return "Cyclades"; |
case PCI_VENDOR_ID_SYMPHONY: return "Symphony"; |
case PCI_VENDOR_ID_TEKRAM: return "Tekram"; |
case PCI_VENDOR_ID_3DLABS: return "3Dlabs"; |
case PCI_VENDOR_ID_AVANCE: return "Avance"; |
case PCI_VENDOR_ID_S3: return "S3 Inc."; |
case PCI_VENDOR_ID_INTEL: return "Intel"; |
case PCI_VENDOR_ID_ADAPTEC: return "Adaptec"; |
case PCI_VENDOR_ID_ATRONICS: return "Atronics"; |
case PCI_VENDOR_ID_HER: return "Hercules"; |
default: return "Unknown vendor"; |
} |
} |
/***************************************************************************/ |
/shark/trunk/drivers/oldpci/makefile |
---|
0,0 → 1,16 |
# The OLD PCI library |
ifndef BASE |
BASE=../.. |
endif |
include $(BASE)/config/config.mk |
LIBRARY = oldpci |
OBJS_PATH = $(BASE)/drivers/oldpci |
OBJS = llpci.o pci.o linuxpci.o pci_access.o pci_scan.o |
include $(BASE)/config/lib.mk |
/shark/trunk/drivers/oldpci/pci_access.c |
---|
0,0 → 1,33 |
#include <ll/i386/hw-data.h> |
#include <drivers/llpci.h> |
#include <drivers/linuxpci.h> |
int pci_read_config_byte(struct pci_dev *dev, BYTE where, BYTE *val) |
{ |
return pcibios_read_config_byte(dev->bus->number, dev->devfn, where, val); |
} |
int pci_read_config_word(struct pci_dev *dev, BYTE where, WORD *val) |
{ |
return pcibios_read_config_word(dev->bus->number, dev->devfn, where, val); |
} |
int pci_read_config_dword(struct pci_dev *dev, BYTE where, DWORD *val) |
{ |
return pcibios_read_config_dword(dev->bus->number, dev->devfn, where, val); |
} |
int pci_write_config_byte(struct pci_dev *dev, BYTE where, BYTE val) |
{ |
return pcibios_write_config_byte(dev->bus->number, dev->devfn, where, val); |
} |
int pci_write_config_word(struct pci_dev *dev, BYTE where, WORD val) |
{ |
return pcibios_write_config_word(dev->bus->number, dev->devfn, where, val); |
} |
int pci_write_config_dword(struct pci_dev *dev, BYTE where, DWORD val) |
{ |
return pcibios_write_config_dword(dev->bus->number, dev->devfn, where, val); |
} |
/shark/trunk/drivers/oldpci/pci_lin.c |
---|
0,0 → 1,41 |
local struct pci_bus pci_root; |
struct pci_dev *pci_devices = NULL; |
void pci_init(void)) |
{ |
pcibios_init(); |
if (!pci_present()) { |
printk("PCI: No PCI bus detected\n"); |
return; |
} |
printk("PCI: Probing PCI hardware\n"); |
memset(&pci_root, 0, sizeof(pci_root)); |
pci_root.subordinate = pci_scan_bus(&pci_root); |
} |
struct pci_dev *pci_find_device(unsigned int vendor, unsigned int device, struct pci_dev *from) |
{ |
if (!from) |
from = pci_devices; |
else |
from = from->next; |
while (from && (from->vendor != vendor || from->device != device)) |
from = from->next; |
return from; |
} |
struct pci_dev *pci_find_class(unsigned int class, struct pci_dev *from) |
{ |
if (!from) |
from = pci_devices; |
else |
from = from->next; |
while (from && from->class != class) |
from = from->next; |
return from; |
} |