1,5 → 1,5 |
/* |
* (c) 2003 Advanced Micro Devices, Inc. |
* (c) 2003, 2004 Advanced Micro Devices, Inc. |
* Your use of this code is subject to the terms and conditions of the |
* GNU general public license version 2. See "../../../COPYING" or |
* http://www.gnu.org/licenses/gpl.html |
20,7 → 20,6 |
/* writes (wrmsr - opcode 0f 30), the register number is placed in ecx, and */ |
/* the value to write is placed in edx:eax. For reads (rdmsr - opcode 0f 32), */ |
/* the register number is placed in ecx, and the data is returned in edx:eax. */ |
|
#define MSR_FIDVID_CTL 0xc0010041 |
#define MSR_FIDVID_STATUS 0xc0010042 |
|
46,9 → 45,8 |
#define MSR_S_HI_CURRENT_VID 0x0000001f |
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/* fids (frequency identifiers) are arranged in 2 tables - lo and hi */ |
#define LO_FID_TABLE_TOP 6 |
#define HI_FID_TABLE_BOTTOM 8 |
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#define LO_FID_TABLE_TOP 6 /* fid values marking the boundary */ |
#define HI_FID_TABLE_BOTTOM 8 /* between the low and high tables */ |
#define LO_VCOFREQ_TABLE_TOP 1400 /* corresponding vco frequency values */ |
#define HI_VCOFREQ_TABLE_BOTTOM 1600 |
|
55,33 → 53,25 |
#define MIN_FREQ_RESOLUTION 200 /* fids jump by 2 matching freq jumps by 200 */ |
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#define MAX_FID 0x2a /* Spec only gives FID values as far as 5 GHz */ |
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#define LEAST_VID 0x1e /* Lowest (numerically highest) useful vid value */ |
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#define MIN_FREQ 800 /* Min and max freqs, per spec */ |
#define MAX_FREQ 5000 |
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#define INVALID_FID_MASK 0xffffffc1 /* not a valid fid if these bits are set */ |
#define INVALID_FID_MASK 0xffffffc1 /* not a valid fid if these bits are set */ |
#define INVALID_VID_MASK 0xffffffe0 /* not a valid vid if these bits are set */ |
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#define INVALID_VID_MASK 0xffffffe0 /* not a valid vid if these bits are set */ |
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#define STOP_GRANT_5NS 1 /* min poss memory access latency for voltage change */ |
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#define PLL_LOCK_CONVERSION (1000/5) /* ms to ns, then divide by clock period */ |
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#define MAXIMUM_VID_STEPS 1 /* Current cpus only allow a single step of 25mV */ |
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#define VST_UNITS_20US 20 /* Voltage Stabalization Time is in units of 20us */ |
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/* |
Version 1.4 of the PSB table. This table is constructed by BIOS and is |
to tell the OS's power management driver which VIDs and FIDs are |
supported by this particular processor. This information is obtained from |
the data sheets for each processor model by the system vendor and |
incorporated into the BIOS. |
If the data in the PSB / PST is wrong, then this driver will program the |
wrong values into hardware, which is very likely to lead to a crash. |
*/ |
* Version 1.4 of the PSB table. This table is constructed by BIOS and is |
* to tell the OS's power management driver which VIDs and FIDs are |
* supported by this particular processor. |
* If the data in the PSB / PST is wrong, then this driver will program the |
* wrong values into hardware, which is very likely to lead to a crash. |
*/ |
|
#define PSB_ID_STRING "AMDK7PNOW!" |
#define PSB_ID_STRING_LEN 10 |
111,7 → 101,3 |
static inline int core_voltage_pre_transition(u32 reqvid); |
static inline int core_voltage_post_transition(u32 reqvid); |
static inline int core_frequency_transition(u32 reqfid); |
static int powernowk8_verify(struct cpufreq_policy *pol); |
static int powernowk8_target(struct cpufreq_policy *pol, unsigned targfreq, |
unsigned relation); |
static int __init powernowk8_cpu_init(struct cpufreq_policy *pol); |