0,0 → 1,172 |
/* |
* Project: S.Ha.R.K. |
* |
* Coordinators: |
* Giorgio Buttazzo <giorgio@sssup.it> |
* Paolo Gai <pj@gandalf.sssup.it> |
* |
* Authors : |
* Paolo Gai <pj@gandalf.sssup.it> |
* Massimiliano Giorgi <massy@gandalf.sssup.it> |
* Luca Abeni <luca@gandalf.sssup.it> |
* (see the web pages for full authors list) |
* |
* ReTiS Lab (Scuola Superiore S.Anna - Pisa - Italy) |
* |
* http://www.sssup.it |
* http://retis.sssup.it |
* http://shark.sssup.it |
*/ |
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/** |
------------ |
CVS : $Id: _rtc.h,v 1.1 2003-03-24 10:54:16 pj Exp $ |
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File: $File$ |
Revision: $Revision: 1.1 $ |
Last update: $Date: 2003-03-24 10:54:16 $ |
------------ |
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Author: Massimiliano Giorgi |
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A source from Linux 2.2.9 modified to work with S.Ha.R.K. |
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mc146818rtc.h - register definitions for the Real-Time-Clock / CMOS RAM |
Copyright Torsten Duwe <duwe@informatik.uni-erlangen.de> 1993 |
derived from Data Sheet, Copyright Motorola 1984 (!). |
It was written to be part of the Linux operating system. |
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**/ |
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/* |
* Copyright (C) 2000 Paolo Gai |
* |
* This program is free software; you can redistribute it and/or modify |
* it under the terms of the GNU General Public License as published by |
* the Free Software Foundation; either version 2 of the License, or |
* (at your option) any later version. |
* |
* This program is distributed in the hope that it will be useful, |
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
* GNU General Public License for more details. |
* |
* You should have received a copy of the GNU General Public License |
* along with this program; if not, write to the Free Software |
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
* |
*/ |
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#ifndef _MC146818RTC_H |
#define _MC146818RTC_H |
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#include <drivers/rtc.h> |
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#ifndef RTC_PORT |
#define RTC_PORT(x) (0x70 + (x)) |
#define RTC_ALWAYS_BCD 1 |
#endif |
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/********************************************************************** |
* register summary |
**********************************************************************/ |
#define RTC_SECONDS 0 |
#define RTC_SECONDS_ALARM 1 |
#define RTC_MINUTES 2 |
#define RTC_MINUTES_ALARM 3 |
#define RTC_HOURS 4 |
#define RTC_HOURS_ALARM 5 |
/* RTC_*_alarm is always true if 2 MSBs are set */ |
# define RTC_ALARM_DONT_CARE 0xC0 |
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#define RTC_DAY_OF_WEEK 6 |
#define RTC_DAY_OF_MONTH 7 |
#define RTC_MONTH 8 |
#define RTC_YEAR 9 |
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/* control registers - Moto names |
*/ |
#define RTC_REG_A 10 |
#define RTC_REG_B 11 |
#define RTC_REG_C 12 |
#define RTC_REG_D 13 |
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/********************************************************************** |
* register details |
**********************************************************************/ |
#define RTC_FREQ_SELECT RTC_REG_A |
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/* update-in-progress - set to "1" 244 microsecs before RTC goes off the bus, |
* reset after update (may take 1.984ms @ 32768Hz RefClock) is complete, |
* totalling to a max high interval of 2.228 ms. |
*/ |
# define RTC_UIP 0x80 |
# define RTC_DIV_CTL 0x70 |
/* divider control: refclock values 4.194 / 1.049 MHz / 32.768 kHz */ |
# define RTC_REF_CLCK_4MHZ 0x00 |
# define RTC_REF_CLCK_1MHZ 0x10 |
# define RTC_REF_CLCK_32KHZ 0x20 |
/* 2 values for divider stage reset, others for "testing purposes only" */ |
# define RTC_DIV_RESET1 0x60 |
# define RTC_DIV_RESET2 0x70 |
/* Periodic intr. / Square wave rate select. 0=none, 1=32.8kHz,... 15=2Hz */ |
# define RTC_RATE_SELECT 0x0F |
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/**********************************************************************/ |
#define RTC_CONTROL RTC_REG_B |
# define RTC_SET 0x80 /* disable updates for clock setting */ |
# define RTC_PIE 0x40 /* periodic interrupt enable */ |
# define RTC_AIE 0x20 /* alarm interrupt enable */ |
# define RTC_UIE 0x10 /* update-finished interrupt enable */ |
# define RTC_SQWE 0x08 /* enable square-wave output */ |
# define RTC_DM_BINARY 0x04 /* all time/date values are BCD if clear */ |
# define RTC_24H 0x02 /* 24 hour mode - else hours bit 7 means pm */ |
# define RTC_DST_EN 0x01 /* auto switch DST - works f. USA only */ |
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/**********************************************************************/ |
#define RTC_INTR_FLAGS RTC_REG_C |
/* caution - cleared by read */ |
# define RTC_IRQF 0x80 /* any of the following 3 is active */ |
# define RTC_PF 0x40 |
# define RTC_AF 0x20 |
# define RTC_UF 0x10 |
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/**********************************************************************/ |
#define RTC_VALID RTC_REG_D |
# define RTC_VRT 0x80 /* valid RAM and time */ |
/**********************************************************************/ |
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/* example: !(CMOS_READ(RTC_CONTROL) & RTC_DM_BINARY) |
* determines if the following two #defines are needed |
*/ |
#ifndef BCD_TO_BIN |
#define BCD_TO_BIN(val) ((val)=((val)&15) + ((val)>>4)*10) |
#endif |
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#ifndef BIN_TO_BCD |
#define BIN_TO_BCD(val) ((val)=(((val)/10)<<4) + (val)%10) |
#endif |
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/* |
* ioctl calls that are permitted to the /dev/rtc interface, if |
* CONFIG_RTC was enabled. |
*/ |
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#define RTC_AIE_ON _IO('p', 0x01) /* Alarm int. enable on */ |
#define RTC_AIE_OFF _IO('p', 0x02) /* ... off */ |
#define RTC_UIE_ON _IO('p', 0x03) /* Update int. enable on */ |
#define RTC_UIE_OFF _IO('p', 0x04) /* ... off */ |
#define RTC_PIE_ON _IO('p', 0x05) /* Periodic int. enable on */ |
#define RTC_PIE_OFF _IO('p', 0x06) /* ... off */ |
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#define RTC_ALM_SET _IOW('p', 0x07, struct rtc_time) /* Set alarm time */ |
#define RTC_ALM_READ _IOR('p', 0x08, struct rtc_time) /* Read alarm time */ |
#define RTC_RD_TIME _IOR('p', 0x09, struct rtc_time) /* Read RTC time */ |
#define RTC_SET_TIME _IOW('p', 0x0a, struct rtc_time) /* Set RTC time */ |
#define RTC_IRQP_READ _IOR('p', 0x0b, unsigned long) /* Read IRQ rate */ |
#define RTC_IRQP_SET _IOW('p', 0x0c, unsigned long) /* Set IRQ rate */ |
#define RTC_EPOCH_READ _IOR('p', 0x0d, unsigned long) /* Read epoch */ |
#define RTC_EPOCH_SET _IOW('p', 0x0e, unsigned long) /* Set epoch */ |
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#endif /* _MC146818RTC_H */ |