36,31 → 36,31 |
/* TSC */ |
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#define rdtsc(low,high) \ |
__asm__ __volatile__("xorl %%eax,%%eax\n\t" \ |
"cpuid\n\t" \ |
"rdtsc\n\t" \ |
: "=a" (low), "=d" (high) \ |
:: "ebx", "ecx") |
__asm__ __volatile__("xorl %%eax,%%eax\n\t" \ |
"cpuid\n\t" \ |
"rdtsc\n\t" \ |
: "=a" (low), "=d" (high) \ |
:: "ebx", "ecx") |
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#define rdtscll(val) \ |
__asm__ __volatile__("xorl %%eax,%%eax\n\t" \ |
"cpuid\n\t" \ |
"rdtsc\n\t" \ |
: "=A" (val) \ |
:: "ebx","ecx") |
__asm__ __volatile__("xorl %%eax,%%eax\n\t" \ |
"cpuid\n\t" \ |
"rdtsc\n\t" \ |
: "=A" (val) \ |
:: "ebx","ecx") |
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#ifdef __O1000__ |
#define ll_read_timespec ll_read_timespec_1000 |
#define ll_read_timespec ll_read_timespec_1000 |
#else |
#ifdef __02000__ |
#define ll_read_timespec ll_read_timespec_2000 |
#else |
#ifdef __O4000__ |
#define ll_read_timespec ll_read_timespec_4000 |
#else |
#define ll_read_timespec ll_read_timespec_8000 |
#endif |
#endif |
#ifdef __02000__ |
#define ll_read_timespec ll_read_timespec_2000 |
#else |
#ifdef __O4000__ |
#define ll_read_timespec ll_read_timespec_4000 |
#else |
#define ll_read_timespec ll_read_timespec_8000 |
#endif |
#endif |
#endif |
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//Low level time read function: Optimized for CPU < 1 GHz |
142,40 → 142,48 |
//Low level time read function |
extern __inline__ void ll_read_timespec_8000(struct timespec *tspec) |
{ |
extern unsigned int clk_opt_0,clk_opt_5; |
extern unsigned long long *ptr_init_tsc; |
extern unsigned int clk_opt_0,clk_opt_5; |
extern unsigned long long *ptr_init_tsc; |
extern struct timespec init_time; |
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if (clk_opt_0 == 0) { |
NULL_TIMESPEC(tspec); |
return; |
} |
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if (clk_opt_0 == 0) { |
NULL_TIMESPEC(tspec); |
return; |
} |
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__asm__("rdtsc\n\t" |
"subl (%%edi),%%eax\n\t" |
"sbbl 4(%%edi),%%edx\n\t" |
"shrdl $1,%%edx,%%eax\n\t" |
"shrl %%edx\n\t" |
"divl %%ebx\n\t" |
"movl %%eax,%%ebx\n\t" |
"xorl %%eax,%%eax\n\t" |
"shrdl $2,%%edx,%%eax\n\t" |
"shrl $2,%%edx\n\t" |
"divl %%ecx\n\t" |
: "=b" (tspec->tv_sec), "=a" (tspec->tv_nsec) |
: "D" (ptr_init_tsc), "b" (clk_opt_0), "c" (clk_opt_5) |
: "edx"); |
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__asm__("rdtsc\n\t" |
"subl (%%edi),%%eax\n\t" |
"sbbl 4(%%edi),%%edx\n\t" |
"shrdl $1,%%edx,%%eax\n\t" |
"shrl %%edx\n\t" |
"divl %%ebx\n\t" |
"movl %%eax,%%ebx\n\t" |
"xorl %%eax,%%eax\n\t" |
"shrdl $2,%%edx,%%eax\n\t" |
"shrl $2,%%edx\n\t" |
"divl %%ecx\n\t" |
: "=b" (tspec->tv_sec), "=a" (tspec->tv_nsec) |
: "D" (ptr_init_tsc), "b" (clk_opt_0), "c" (clk_opt_5) |
: "edx"); |
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if (init_time.tv_sec != 0 || init_time.tv_nsec != 0) { |
__asm__("divl %%ecx\n\t" |
"addl %%ebx,%%eax\n\t" |
:"=a" (tspec->tv_sec), "=d" (tspec->tv_nsec) |
:"a" (init_time.tv_nsec+tspec->tv_nsec), "b" (tspec->tv_sec+init_time.tv_sec), "c" (0x3B9ACA00), "d" (0)); |
}; |
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} |
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#define rdmsr(msr,val1,val2) \ |
__asm__ __volatile__("rdmsr" \ |
: "=a" (val1), "=d" (val2) \ |
: "c" (msr)) |
__asm__ __volatile__("rdmsr" \ |
: "=a" (val1), "=d" (val2) \ |
: "c" (msr)) |
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#define wrmsr(msr,val1,val2) \ |
__asm__ __volatile__("wrmsr" \ |
: /* no outputs */ \ |
: "c" (msr), "a" (val1), "d" (val2)) |
__asm__ __volatile__("wrmsr" \ |
: /* no outputs */ \ |
: "c" (msr), "a" (val1), "d" (val2)) |
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/* RTC */ |
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