/shark/trunk/oslib/kl/time.c |
---|
48,6 → 48,7 |
extern struct pitspec globalCounter; /* From event.c */ |
extern BYTE frc; |
extern int activeEvent; |
extern BYTE use_tsc; |
FILE(Time); |
54,7 → 55,7 |
TIME ll_gettime(int mode, struct timespec *tsres) |
{ |
#ifndef __TSC__ |
if (!use_tsc) { |
DWORD res, tc; |
BYTE isr; |
136,23 → 137,15 |
} |
} |
return 0; |
#else |
} else { |
if (tsres != NULL) { |
ll_read_timespec(tsres); |
return TIMESPEC2USEC(tsres); |
} else { |
struct timespec tmp; |
ll_read_timespec(&tmp); |
return TIMESPEC2USEC(&tmp); |
} |
#endif |
} |
} |
/shark/trunk/oslib/kl/event.c |
---|
77,6 → 77,7 |
extern void (*evt_epil) (void); |
extern unsigned int apic_clk_per_msec; |
extern unsigned char use_apic, use_tsc; |
void event_setlasthandler(void *p) |
{ |
94,8 → 95,7 |
} |
/* Switched to timespec */ |
int periodic_event_post(struct timespec time, void (*handler) (void *p), |
void *par) |
int periodic_event_post(struct timespec time, void (*handler) (void *p), void *par) |
{ |
struct event *p; |
struct event *p1, *t; |
174,19 → 174,18 |
} |
void periodic_wake_up(void) |
{ /* CHANGE the NAME, please... */ |
{ |
/* CHANGE the NAME, please... */ |
struct event *p, *pp; |
#ifndef __TSC__ |
WORD tmp; |
#endif |
TRACER_LOGEVENT(FTrace_EVT_timer_wakeup_start, 0, 0); |
#ifndef __TSC__ |
if (use_tsc) { |
tmp = pit_read(frc); |
ADDPITSPEC((WORD) (lastTime - tmp), &globalCounter); |
lastTime = tmp; |
#endif |
} |
activeInt++; |
if (activeInt == 1 && evt_prol != NULL) { |
193,11 → 192,10 |
evt_prol(); |
} |
#ifndef __TSC__ |
if (use_tsc) |
ll_read_timespec(&actTime); |
else |
ADDNANO2TIMESPEC(nts, &actTime); |
#else |
ll_read_timespec(&actTime); |
#endif |
for (p = firstevent; p != NULL; p = pp) { |
/* |
223,7 → 221,6 |
activeInt--; |
TRACER_LOGEVENT(FTrace_EVT_timer_wakeup_end, (unsigned short int)currCtx, 0); |
} |
void event_init(struct ll_initparms *l) |
233,31 → 230,27 |
int i; |
BYTE mask; |
TIME t; |
#ifdef __APIC__ |
DWORD apic_clk; |
#endif |
#ifdef __TSC__ |
if (use_tsc) |
ll_init_advtimer(); |
#endif |
#ifndef __APIC__ |
if (use_apic) |
IDT_place(0x39,ll_apic_timer); |
else |
IDT_place(0x40,ll_timer); |
#else |
IDT_place(0x39,ll_apic_timer); |
#endif |
if (l->mode != LL_PERIODIC) { |
message("One-shot mode\n"); |
t = 0; |
#ifndef __APIC__ |
/* Mode: Binary/Mode 4/16 bit Time_const/Counter 0 */ |
pit_init(0, TMR_MD4, 0xFFFF); /* Timer 0, Mode 4, constant 0xFFFF */ |
#else |
if (use_apic) { |
set_APIC_timer(0xFFFFFFFF); |
enable_APIC_timer(); |
#endif |
} else { |
/* Mode: Binary/Mode 4/16 bit Time_const/Counter 0 */ |
pit_init(0, TMR_MD4, 0xFFFF); /* Timer 0, Mode 4, constant 0xFFFF */ |
} |
} else { |
t = l->tick; |
/* Translate the tick value in usec into a suitable time constant */ |
269,8 → 262,11 |
/* If T-C == 0 -> T-C = 65536 (Max available) */ |
ticksize = t; |
#ifndef __APIC__ |
if (use_apic) { |
mul32div32to32(t,apic_clk_per_msec,1000,apic_clk); |
set_APIC_timer(apic_clk); |
enable_APIC_timer(); |
} else { |
mul32div32to32(t,1193182,1000000,t); |
/* Only for security! This should cause timer overrun */ |
280,18 → 276,11 |
pit_time_const = (WORD) (t & 0xFFFF); |
/* Mode: Binary/Mode 2/16 bit Time_const/Counter 0 */ |
pit_init(0, TMR_MD2, t); /* Timer 0, Mode 2, Time constant t */ |
#else |
mul32div32to32(t,apic_clk_per_msec,1000,apic_clk); |
set_APIC_timer(apic_clk); |
enable_APIC_timer(); |
#endif |
} |
} |
timermode = l->mode; |
#ifndef __APIC__ |
if (!use_apic) { |
if (ll_arch.x86.cpu > 4) { |
/* Timer1: mode 0, time const 0... */ |
pit_init(1, TMR_MD0, 0); |
301,7 → 290,7 |
pit_init(2, TMR_MD0, 0); |
outp(0x61, 3); |
} |
#endif |
} |
mask = ll_in(0x21); |
mask &= 0xFE; /* 0xFE = ~0x01 */ |
337,8 → 326,6 |
} |
/* Last but not least... */ |
#ifndef __APIC__ |
if (!use_apic) |
irq_unmask(0); |
#endif |
} |
/shark/trunk/oslib/kl/event1.c |
---|
62,10 → 62,10 |
extern void (*evt_epil) (void); |
extern unsigned int apic_clk_per_msec; |
extern unsigned char use_tsc, use_apic; |
/* Switched to timespec */ |
int oneshot_event_post(struct timespec time, void (*handler) (void *p), |
void *par) |
int oneshot_event_post(struct timespec time, void (*handler) (void *p), void *par) |
{ |
struct event *p; |
struct event *p1, *t; |
107,11 → 107,11 |
} else { |
firstevent = p; |
if (!activeEvent) { |
#ifndef __TSC__ |
if (!use_tsc) { |
ll_gettime(TIME_NEW, &now); |
#else |
} else { |
ll_read_timespec(&now); |
#endif |
} |
if (TIMESPEC_A_GT_B(&now, &(firstevent->time))) { |
NULL_TIMESPEC(&tmp); |
} else { |
118,47 → 118,40 |
SUBTIMESPEC(&(firstevent->time), &now, &tmp); |
} |
tnext = TIMESPEC2USEC(&tmp); |
#ifndef __APIC__ |
if (!use_apic) { |
mul32div32to32(tnext,1193182,1000000,tnext); |
pit_setconstant(0, tnext); |
#else |
} else { |
mul32div32to32(tnext,apic_clk_per_msec,1000,tnext); |
set_APIC_timer(tnext); |
#endif |
} |
} |
} |
p->next = p1; |
return p->index; |
} |
void oneshot_wake_up(void) |
{ /* CHANGE the NAME, please... */ |
{ |
/* CHANGE the NAME, please... */ |
struct event *p = NULL, *pp; |
struct timespec now, ttmp; |
#ifndef __TSC__ |
WORD tmp; |
#endif |
DWORD tnext; |
TRACER_LOGEVENT(FTrace_EVT_timer_wakeup_start, 0, 0); |
#ifndef __TSC__ |
if (!use_tsc) { |
tmp = pit_read(frc); |
ADDPITSPEC((WORD) (lastTime - tmp), &globalCounter); |
lastTime = tmp; |
PITSPEC2TIMESPEC(&globalCounter, &now); |
#else |
} else { |
ll_read_timespec(&now); |
} |
#endif |
if (firstevent != NULL) { |
activeEvent = 1; |
if (TIMESPEC_A_GT_B(&now, &(firstevent->time))) { |
186,21 → 179,16 |
activeInt--; |
} |
#ifndef __TSC__ |
if (!use_tsc) { |
tmp = pit_read(frc); |
ADDPITSPEC((WORD) (lastTime - tmp), &globalCounter); |
lastTime = tmp; |
PITSPEC2TIMESPEC(&globalCounter, &now); |
#else |
} else { |
ll_read_timespec(&now); |
} |
#endif |
if (TIMESPEC_A_GT_B(&now, &(firstevent->time))) { |
NULL_TIMESPEC(&ttmp); |
} else { |
208,24 → 196,22 |
} |
/* SUBTIMESPEC(&(firstevent->time), &now, &ttmp); */ |
tnext = TIMESPEC2USEC(&ttmp); |
#ifndef __APIC__ |
if (!use_apic) { |
mul32div32to32(tnext,1193182,1000000,tnext); |
pit_setconstant(0, tnext); |
#else |
} else { |
mul32div32to32(tnext,apic_clk_per_msec,1000,tnext); |
set_APIC_timer(tnext); |
#endif |
} |
activeEvent = 0; |
} else { |
#ifndef __APIC__ |
if (!use_apic) |
pit_setconstant(0, 0xFFFF); |
#else |
else |
set_APIC_timer(0xFFFFFFFF); |
#endif |
} |
TRACER_LOGEVENT(FTrace_EVT_timer_wakeup_end, (unsigned short int)currCtx, 0); |
} |
int oneshot_event_delete(int index) |
261,18 → 247,16 |
if (!activeEvent) { |
if (firstevent == NULL) { |
#ifndef __APIC__ |
if (!use_apic) |
pit_setconstant(0, 0xFFFF); |
#else |
else |
set_APIC_timer(0xFFFFFFFF); |
#endif |
} else { |
if (firstdeleted) { |
#ifndef __TSC__ |
if (!use_tsc) |
ll_gettime(TIME_NEW, &now); |
#else |
else |
ll_read_timespec(&now); |
#endif |
if (TIMESPEC_A_GT_B(&now, &(firstevent->time))) { |
NULL_TIMESPEC(&tmp); |
} else { |
280,15 → 264,15 |
} |
/*SUBTIMESPEC(&now, &(firstevent->time), &tmp); */ |
tnext = TIMESPEC2USEC(&tmp); |
#ifndef __APIC__ |
if (!use_apic) { |
mul32div32to32(tnext,1193182,1000000,tnext); |
pit_setconstant(0, tnext); |
#else |
} else { |
mul32div32to32(tnext,apic_clk_per_msec,1000,tnext); |
set_APIC_timer(tnext); |
#endif |
} |
} |
} |
} |
return 1; |
} |
/shark/trunk/oslib/kl/advtimer.c |
---|
58,6 → 58,11 |
unsigned char save_CMOS_regA; |
unsigned char save_CMOS_regB; |
unsigned char X86_tsc = 0; |
unsigned char X86_apic = 0; |
unsigned char use_tsc = 0; |
unsigned char use_apic = 0; |
#ifdef CONFIG_MELAN |
# define CLOCK_TICK_RATE 1189200 /* AMD Elan has different frequency! */ |
#else |
95,11 → 100,9 |
barrier(); |
do { |
outp(0x43,0x00); |
end_8253 = inp(0x42); |
end_8253 |= inp(0x42) << 8; |
} while (end_8253 > COUNTER_END); |
barrier(); |
130,7 → 133,6 |
clk_per_msec = dtsc * CLOCK_TICK_RATE / delta_8253 / 1000; |
message("Calibrated Clk_per_msec = %10d\n",clk_per_msec); |
} |
#define CMOS_INIT 0 |
144,7 → 146,6 |
void calibrate_tsc_IRQ8(void *p) |
{ |
unsigned char set; |
CMOS_READ(0x0C,set); |
165,13 → 166,11 |
if (cmos_calibrate_status == CMOS_INIT) { |
cmos_calibrate_status = CMOS_BEGIN; |
} |
} |
//TSC Calibration using RTC |
void ll_calibrate_tsc_cmos(void) |
{ |
unsigned long long dtsc; |
irq_bind(8, calibrate_tsc_IRQ8, INT_FORCE); |
235,7 → 234,6 |
CMOS_WRITE(0x0A,save_CMOS_regA); |
CMOS_WRITE(0x0B,save_CMOS_regB); |
} |
int apic_get_maxlvt(void) |
339,7 → 337,6 |
apic_write_around(APIC_LVT1, value); |
apic_write(APIC_ESR, 0); |
} |
void disable_APIC_timer(void) |
348,7 → 345,6 |
v = apic_read(APIC_LVTT); |
apic_write_around(APIC_LVTT, v | APIC_LVT_MASKED); |
} |
void enable_APIC_timer(void) |
357,7 → 353,6 |
v = apic_read(APIC_LVTT); |
apic_write_around(APIC_LVTT, v & ~APIC_LVT_MASKED); |
} |
#define LOCAL_TIMER_VECTOR 0x39 |
386,7 → 381,6 |
void ll_calibrate_apic(void) |
{ |
unsigned int apic_start = 0, apic_end = 0, dapic; |
unsigned long long tsc_start = 0, tsc_end = 0, dtsc; |
unsigned int tmp_value; |
426,17 → 420,22 |
apic_set_limit = ((apic_clk_per_msec / 100) != 0) ? (apic_clk_per_msec/100) : APIC_SET_LIMIT; |
message("Calibrated APIC Clk/msec = %10d\n",apic_clk_per_msec); |
} |
void ll_init_advtimer() |
{ |
unsigned long msr_low_orig, tmp; |
#ifdef __APIC__ |
unsigned long msr_low_orig, tmp; |
use_apic = X86_apic; |
#endif |
#ifdef __TSC__ |
use_tsc = X86_tsc; |
#endif |
if (use_tsc) { |
#ifdef CALIBRATE_USING_CMOS |
ll_calibrate_tsc_cmos(); |
#else |
446,8 → 445,7 |
rdtscll(init_tsc); // Read start TSC |
init_nsec = 0; |
#ifdef __APIC__ |
if (use_apic) { |
rdmsr(APIC_BASE_MSR, msr_low_orig, tmp); |
wrmsr(APIC_BASE_MSR, msr_low_orig|(1<<11), 0); |
458,17 → 456,14 |
setup_local_APIC(); |
setup_APIC_timer(); |
#endif |
#endif |
} |
} |
} |
void ll_restore_adv() |
{ |
/* Disable APIC */ |
#ifdef __APIC__ |
if (use_apic) { |
unsigned int msr_low_orig, tmp; |
cli(); |
479,7 → 474,5 |
wrmsr(APIC_BASE_MSR, msr_low_orig&~(1<<11), 0); |
sti(); |
#endif |
} |
} |
/shark/trunk/oslib/xlib/vm86.c |
---|
51,6 → 51,7 |
#define VM86_STACK_SIZE 8192 |
extern DWORD ll_irq_table[256]; |
extern BYTE use_apic, use_tsc; |
/* TSS optional section */ |
static BYTE vm86_stack0[VM86_STACK_SIZE]; |
180,10 → 181,7 |
LIN_ADDR vm86_stackPtr; |
DWORD *IRQTable_entry; |
BYTE p1,p2; |
#ifdef __APIC__ |
DWORD msr1 = 0,msr2 = 0; |
#endif |
SYS_FLAGS f; |
229,10 → 227,10 |
outp(0x21,0xFF); |
outp(0xA1,0xFF); |
#ifdef __APIC__ |
if (use_apic) { |
rdmsr(APIC_BASE_MSR,msr1,msr2); |
disable_APIC_timer(); |
#endif |
} |
vm86_TSS.t.back_link = ll_context_save(); |
VM86_ret_ctx = vm86_TSS.t.back_link |
240,10 → 238,10 |
ll_context_load(X_VM86_TSS); |
cli(); |
#ifdef __APIC__ |
if (use_apic) { |
wrmsr(APIC_BASE_MSR,msr1,msr2); |
enable_APIC_timer(); |
#endif |
} |
outp(0x21,p1); |
outp(0xA1,p2); |
285,10 → 283,10 |
outp(0x21,0xFF); |
outp(0xA1,0xFF); |
#ifdef __APIC__ |
if (use_apic) { |
rdmsr(APIC_BASE_MSR,msr1,msr2); |
disable_APIC_timer(); |
#endif |
} |
vm86_TSS.t.back_link = ll_context_save(); |
VM86_ret_ctx = vm86_TSS.t.back_link; |
296,10 → 294,10 |
ll_context_load(X_VM86_TSS); |
cli(); |
#ifdef __APIC__ |
if (use_apic) { |
wrmsr(APIC_BASE_MSR,msr1,msr2); |
enable_APIC_timer(); |
#endif |
} |
outp(0x21,p1); |
outp(0xA1,p2); |
/shark/trunk/oslib/xlib/xbios.c |
---|
37,28 → 37,27 |
void X_callBIOS(int service,X_REGS16 *in,X_REGS16 *out,X_SREGS16 *s) |
{ |
/* Assembler gate JMP instruction */ |
extern BYTE use_tsc, use_apic; |
extern void _x_callBIOS(void); |
X_CALLBIOS *xbc = x_bios_address(); |
#ifdef __APIC__ |
DWORD msr1 = 0,msr2 = 0; |
#endif |
/* Send interrupt request & register through the X_Info structure */ |
xbc->_irqno = service; |
memcpy(&(xbc->_ir),in,sizeof(X_REGS16)); |
memcpy(&(xbc->_sr),s,sizeof(X_SREGS16)); |
#ifdef __APIC__ |
if (use_apic) { |
rdmsr(APIC_BASE_MSR,msr1,msr2); |
disable_APIC_timer(); |
#endif |
} |
/* Back to RM to execute the BIOS routine */ |
_x_callBIOS(); |
/* Get the return register values */ |
#ifdef __APIC__ |
if (use_apic) { |
wrmsr(APIC_BASE_MSR,msr1,msr2); |
enable_APIC_timer(); |
#endif |
} |
memcpy(out,&(xbc->_or),sizeof(X_REGS16)); |
memcpy(s,&(xbc->_sr),sizeof(X_SREGS16)); |
} |
/shark/trunk/oslib/xlib/xinit.c |
---|
73,10 → 73,11 |
{ |
register int i; |
struct ll_cpuInfo cpuInfo; |
extern BYTE X86_apic; |
extern BYTE X86_tsc; |
extern BYTE X86_fpu; |
LIN_ADDR b; |
for(i = 0; i < 256; i++) { |
ll_irq_table[i] = (DWORD)dummyfun; |
} |
88,6 → 89,9 |
ll_arch.x86.fpu = X86_fpu; |
memcpy(&(ll_arch.x86.vendor), &(cpuInfo.X86_vendor_1), 12); |
X86_apic = cpuInfo.X86_StandardFeature & (1<<4); |
X86_tsc = cpuInfo.X86_StandardFeature & (1<<9); |
/* TODO! Need to map featuresXXX & Signature onto ll_arch! */ |
/* TODO! Need to check for CPU bugs!! */ |
99,6 → 103,8 |
message("Features #1: 0x%lx\n", cpuInfo.X86_IntelFeature_1); |
message("Features #2: 0x%lx\n", cpuInfo.X86_IntelFeature_2); |
message("Features #3: 0x%lx\n", cpuInfo.X86_StandardFeature); |
message("Has APIC: %s\n", X86_apic); |
message("Has TSC: %s\n", X86_tsc); |
#endif /* __LL_DEBUG__ */ |
IDT_init(); |