Subversion Repositories shark

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Ignore whitespace Rev 434 → Rev 433

/shark/trunk/drivers/linuxc26/include/media/id.h
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/shark/trunk/drivers/linuxc26/include/media/tuner.h
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/shark/trunk/drivers/linuxc26/include/media/video-buf.h
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/shark/trunk/drivers/linuxc26/include/media/saa7146_vv.h
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/shark/trunk/drivers/linuxc26/include/media/saa6752hs.h
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/shark/trunk/drivers/linuxc26/include/media/audiochip.h
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/shark/trunk/drivers/linuxc26/include/media/saa7146.h
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/shark/trunk/drivers/linuxc26/include/acpi/processor.h
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/shark/trunk/drivers/linuxc26/include/acpi/acdisasm.h
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/shark/trunk/drivers/linuxc26/include/acpi/acpi_bus.h
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/shark/trunk/drivers/linuxc26/include/acpi/acnamesp.h
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/shark/trunk/drivers/linuxc26/include/acpi/acdispat.h
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/shark/trunk/drivers/linuxc26/include/acpi/platform/acenv.h
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/shark/trunk/drivers/linuxc26/include/acpi/platform/acgcc.h
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/shark/trunk/drivers/linuxc26/include/acpi/platform/aclinux.h
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/shark/trunk/drivers/linuxc26/include/acpi/amlcode.h
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/shark/trunk/drivers/linuxc26/include/acpi/acutils.h
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/shark/trunk/drivers/linuxc26/include/acpi/acglobal.h
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/shark/trunk/drivers/linuxc26/include/acpi/actypes.h
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/shark/trunk/drivers/linuxc26/include/acpi/acexcep.h
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/shark/trunk/drivers/linuxc26/include/acpi/acevents.h
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/shark/trunk/drivers/linuxc26/include/acpi/acpi_drivers.h
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/shark/trunk/drivers/linuxc26/include/acpi/achware.h
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/shark/trunk/drivers/linuxc26/include/acpi/acpi.h
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/shark/trunk/drivers/linuxc26/include/acpi/actables.h
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/shark/trunk/drivers/linuxc26/include/acpi/acresrc.h
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/shark/trunk/drivers/linuxc26/include/acpi/actbl.h
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/shark/trunk/drivers/linuxc26/include/acpi/acmacros.h
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/shark/trunk/drivers/linuxc26/include/acpi/acstruct.h
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/shark/trunk/drivers/linuxc26/include/acpi/acdebug.h
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/shark/trunk/drivers/linuxc26/include/acpi/actbl71.h
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/shark/trunk/drivers/linuxc26/include/acpi/aclocal.h
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/shark/trunk/drivers/linuxc26/include/acpi/acparser.h
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/shark/trunk/drivers/linuxc26/include/acpi/acoutput.h
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/shark/trunk/drivers/linuxc26/include/acpi/acinterp.h
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/shark/trunk/drivers/linuxc26/include/acpi/actbl1.h
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/shark/trunk/drivers/linuxc26/include/acpi/actbl2.h
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/shark/trunk/drivers/linuxc26/include/acpi/amlresrc.h
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/shark/trunk/drivers/linuxc26/include/acpi/acconfig.h
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/shark/trunk/drivers/linuxc26/include/acpi/acpixf.h
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/shark/trunk/drivers/linuxc26/include/acpi/acobject.h
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/shark/trunk/drivers/linuxc26/include/acpi/acpiosxf.h
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/shark/trunk/drivers/linuxc26/include/linuxcomp.h
13,7 → 13,6
#define NR_IRQS 15
#define NR_IRQ_VECTORS 15
 
#define APIC_DEFINITION
#define __BIT_TYPES_DEFINED__
 
#include <ll/i386/mem.h>
/shark/trunk/drivers/linuxc26/include/asm/ipi.h
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/shark/trunk/drivers/linuxc26/include/asm/mpparse.h
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/shark/trunk/drivers/linuxc26/include/asm/apicdef.h
1,11 → 1,377
#ifndef _GENAPIC_MACH_APICDEF_H
#define _GENAPIC_MACH_APICDEF_H 1
#ifndef __ASM_APICDEF_H
#define __ASM_APICDEF_H
 
#ifndef APIC_DEFINITION
#include <asm/genapic.h>
/*
* Constants for various Intel APICs. (local APIC, IOAPIC, etc.)
*
* Alan Cox <Alan.Cox@linux.org>, 1995.
* Ingo Molnar <mingo@redhat.com>, 1999, 2000
*/
 
#define GET_APIC_ID (genapic->get_apic_id)
#define APIC_ID_MASK (genapic->apic_id_mask)
#define APIC_DEFAULT_PHYS_BASE 0xfee00000
#define APIC_ID 0x20
#define APIC_LVR 0x30
#define APIC_LVR_MASK 0xFF00FF
#define GET_APIC_VERSION(x) ((x)&0xFF)
#define GET_APIC_MAXLVT(x) (((x)>>16)&0xFF)
#define APIC_INTEGRATED(x) ((x)&0xF0)
#define APIC_TASKPRI 0x80
#define APIC_TPRI_MASK 0xFF
#define APIC_ARBPRI 0x90
#define APIC_ARBPRI_MASK 0xFF
#define APIC_PROCPRI 0xA0
#define APIC_EOI 0xB0
#define APIC_EIO_ACK 0x0 /* Write this to the EOI register */
#define APIC_RRR 0xC0
#define APIC_LDR 0xD0
#define APIC_LDR_MASK (0xFF<<24)
#define GET_APIC_LOGICAL_ID(x) (((x)>>24)&0xFF)
#define SET_APIC_LOGICAL_ID(x) (((x)<<24))
#define APIC_ALL_CPUS 0xFF
#define APIC_DFR 0xE0
#define APIC_DFR_CLUSTER 0x0FFFFFFFul
#define APIC_DFR_FLAT 0xFFFFFFFFul
#define APIC_SPIV 0xF0
#define APIC_SPIV_FOCUS_DISABLED (1<<9)
#define APIC_SPIV_APIC_ENABLED (1<<8)
#define APIC_ISR 0x100
#define APIC_TMR 0x180
#define APIC_IRR 0x200
#define APIC_ESR 0x280
#define APIC_ESR_SEND_CS 0x00001
#define APIC_ESR_RECV_CS 0x00002
#define APIC_ESR_SEND_ACC 0x00004
#define APIC_ESR_RECV_ACC 0x00008
#define APIC_ESR_SENDILL 0x00020
#define APIC_ESR_RECVILL 0x00040
#define APIC_ESR_ILLREGA 0x00080
#define APIC_ICR 0x300
#define APIC_DEST_SELF 0x40000
#define APIC_DEST_ALLINC 0x80000
#define APIC_DEST_ALLBUT 0xC0000
#define APIC_ICR_RR_MASK 0x30000
#define APIC_ICR_RR_INVALID 0x00000
#define APIC_ICR_RR_INPROG 0x10000
#define APIC_ICR_RR_VALID 0x20000
#define APIC_INT_LEVELTRIG 0x08000
#define APIC_INT_ASSERT 0x04000
#define APIC_ICR_BUSY 0x01000
#define APIC_DEST_LOGICAL 0x00800
#define APIC_DM_FIXED 0x00000
#define APIC_DM_LOWEST 0x00100
#define APIC_DM_SMI 0x00200
#define APIC_DM_REMRD 0x00300
#define APIC_DM_NMI 0x00400
#define APIC_DM_INIT 0x00500
#define APIC_DM_STARTUP 0x00600
#define APIC_DM_EXTINT 0x00700
#define APIC_VECTOR_MASK 0x000FF
#define APIC_ICR2 0x310
#define GET_APIC_DEST_FIELD(x) (((x)>>24)&0xFF)
#define SET_APIC_DEST_FIELD(x) ((x)<<24)
#define APIC_LVTT 0x320
#define APIC_LVTTHMR 0x330
#define APIC_LVTPC 0x340
#define APIC_LVT0 0x350
#define APIC_LVT_TIMER_BASE_MASK (0x3<<18)
#define GET_APIC_TIMER_BASE(x) (((x)>>18)&0x3)
#define SET_APIC_TIMER_BASE(x) (((x)<<18))
#define APIC_TIMER_BASE_CLKIN 0x0
#define APIC_TIMER_BASE_TMBASE 0x1
#define APIC_TIMER_BASE_DIV 0x2
#define APIC_LVT_TIMER_PERIODIC (1<<17)
#define APIC_LVT_MASKED (1<<16)
#define APIC_LVT_LEVEL_TRIGGER (1<<15)
#define APIC_LVT_REMOTE_IRR (1<<14)
#define APIC_INPUT_POLARITY (1<<13)
#define APIC_SEND_PENDING (1<<12)
#define GET_APIC_DELIVERY_MODE(x) (((x)>>8)&0x7)
#define SET_APIC_DELIVERY_MODE(x,y) (((x)&~0x700)|((y)<<8))
#define APIC_MODE_FIXED 0x0
#define APIC_MODE_NMI 0x4
#define APIC_MODE_EXINT 0x7
#define APIC_LVT1 0x360
#define APIC_LVTERR 0x370
#define APIC_TMICT 0x380
#define APIC_TMCCT 0x390
#define APIC_TDCR 0x3E0
#define APIC_TDR_DIV_TMBASE (1<<2)
#define APIC_TDR_DIV_1 0xB
#define APIC_TDR_DIV_2 0x0
#define APIC_TDR_DIV_4 0x1
#define APIC_TDR_DIV_8 0x2
#define APIC_TDR_DIV_16 0x3
#define APIC_TDR_DIV_32 0x8
#define APIC_TDR_DIV_64 0x9
#define APIC_TDR_DIV_128 0xA
 
#define APIC_BASE (fix_to_virt(FIX_APIC_BASE))
 
#ifdef CONFIG_NUMA
#define MAX_IO_APICS 32
#else
#define MAX_IO_APICS 8
#endif
 
/*
* the local APIC register structure, memory mapped. Not terribly well
* tested, but we might eventually use this one in the future - the
* problem why we cannot use it right now is the P5 APIC, it has an
* errata which cannot take 8-bit reads and writes, only 32-bit ones ...
*/
#define u32 unsigned int
 
#define lapic ((volatile struct local_apic *)APIC_BASE)
 
struct local_apic {
 
/*000*/ struct { u32 __reserved[4]; } __reserved_01;
 
/*010*/ struct { u32 __reserved[4]; } __reserved_02;
 
/*020*/ struct { /* APIC ID Register */
u32 __reserved_1 : 24,
phys_apic_id : 4,
__reserved_2 : 4;
u32 __reserved[3];
} id;
 
/*030*/ const
struct { /* APIC Version Register */
u32 version : 8,
__reserved_1 : 8,
max_lvt : 8,
__reserved_2 : 8;
u32 __reserved[3];
} version;
 
/*040*/ struct { u32 __reserved[4]; } __reserved_03;
 
/*050*/ struct { u32 __reserved[4]; } __reserved_04;
 
/*060*/ struct { u32 __reserved[4]; } __reserved_05;
 
/*070*/ struct { u32 __reserved[4]; } __reserved_06;
 
/*080*/ struct { /* Task Priority Register */
u32 priority : 8,
__reserved_1 : 24;
u32 __reserved_2[3];
} tpr;
 
/*090*/ const
struct { /* Arbitration Priority Register */
u32 priority : 8,
__reserved_1 : 24;
u32 __reserved_2[3];
} apr;
 
/*0A0*/ const
struct { /* Processor Priority Register */
u32 priority : 8,
__reserved_1 : 24;
u32 __reserved_2[3];
} ppr;
 
/*0B0*/ struct { /* End Of Interrupt Register */
u32 eoi;
u32 __reserved[3];
} eoi;
 
/*0C0*/ struct { u32 __reserved[4]; } __reserved_07;
 
/*0D0*/ struct { /* Logical Destination Register */
u32 __reserved_1 : 24,
logical_dest : 8;
u32 __reserved_2[3];
} ldr;
 
/*0E0*/ struct { /* Destination Format Register */
u32 __reserved_1 : 28,
model : 4;
u32 __reserved_2[3];
} dfr;
 
/*0F0*/ struct { /* Spurious Interrupt Vector Register */
u32 spurious_vector : 8,
apic_enabled : 1,
focus_cpu : 1,
__reserved_2 : 22;
u32 __reserved_3[3];
} svr;
 
/*100*/ struct { /* In Service Register */
/*170*/ u32 bitfield;
u32 __reserved[3];
} isr [8];
 
/*180*/ struct { /* Trigger Mode Register */
/*1F0*/ u32 bitfield;
u32 __reserved[3];
} tmr [8];
 
/*200*/ struct { /* Interrupt Request Register */
/*270*/ u32 bitfield;
u32 __reserved[3];
} irr [8];
 
/*280*/ union { /* Error Status Register */
struct {
u32 send_cs_error : 1,
receive_cs_error : 1,
send_accept_error : 1,
receive_accept_error : 1,
__reserved_1 : 1,
send_illegal_vector : 1,
receive_illegal_vector : 1,
illegal_register_address : 1,
__reserved_2 : 24;
u32 __reserved_3[3];
} error_bits;
struct {
u32 errors;
u32 __reserved_3[3];
} all_errors;
} esr;
 
/*290*/ struct { u32 __reserved[4]; } __reserved_08;
 
/*2A0*/ struct { u32 __reserved[4]; } __reserved_09;
 
/*2B0*/ struct { u32 __reserved[4]; } __reserved_10;
 
/*2C0*/ struct { u32 __reserved[4]; } __reserved_11;
 
/*2D0*/ struct { u32 __reserved[4]; } __reserved_12;
 
/*2E0*/ struct { u32 __reserved[4]; } __reserved_13;
 
/*2F0*/ struct { u32 __reserved[4]; } __reserved_14;
 
/*300*/ struct { /* Interrupt Command Register 1 */
u32 vector : 8,
delivery_mode : 3,
destination_mode : 1,
delivery_status : 1,
__reserved_1 : 1,
level : 1,
trigger : 1,
__reserved_2 : 2,
shorthand : 2,
__reserved_3 : 12;
u32 __reserved_4[3];
} icr1;
 
/*310*/ struct { /* Interrupt Command Register 2 */
union {
u32 __reserved_1 : 24,
phys_dest : 4,
__reserved_2 : 4;
u32 __reserved_3 : 24,
logical_dest : 8;
} dest;
u32 __reserved_4[3];
} icr2;
 
/*320*/ struct { /* LVT - Timer */
u32 vector : 8,
__reserved_1 : 4,
delivery_status : 1,
__reserved_2 : 3,
mask : 1,
timer_mode : 1,
__reserved_3 : 14;
u32 __reserved_4[3];
} lvt_timer;
 
/*330*/ struct { /* LVT - Thermal Sensor */
u32 vector : 8,
delivery_mode : 3,
__reserved_1 : 1,
delivery_status : 1,
__reserved_2 : 3,
mask : 1,
__reserved_3 : 15;
u32 __reserved_4[3];
} lvt_thermal;
 
/*340*/ struct { /* LVT - Performance Counter */
u32 vector : 8,
delivery_mode : 3,
__reserved_1 : 1,
delivery_status : 1,
__reserved_2 : 3,
mask : 1,
__reserved_3 : 15;
u32 __reserved_4[3];
} lvt_pc;
 
/*350*/ struct { /* LVT - LINT0 */
u32 vector : 8,
delivery_mode : 3,
__reserved_1 : 1,
delivery_status : 1,
polarity : 1,
remote_irr : 1,
trigger : 1,
mask : 1,
__reserved_2 : 15;
u32 __reserved_3[3];
} lvt_lint0;
 
/*360*/ struct { /* LVT - LINT1 */
u32 vector : 8,
delivery_mode : 3,
__reserved_1 : 1,
delivery_status : 1,
polarity : 1,
remote_irr : 1,
trigger : 1,
mask : 1,
__reserved_2 : 15;
u32 __reserved_3[3];
} lvt_lint1;
 
/*370*/ struct { /* LVT - Error */
u32 vector : 8,
__reserved_1 : 4,
delivery_status : 1,
__reserved_2 : 3,
mask : 1,
__reserved_3 : 15;
u32 __reserved_4[3];
} lvt_error;
 
/*380*/ struct { /* Timer Initial Count Register */
u32 initial_count;
u32 __reserved_2[3];
} timer_icr;
 
/*390*/ const
struct { /* Timer Current Count Register */
u32 curr_count;
u32 __reserved_2[3];
} timer_ccr;
 
/*3A0*/ struct { u32 __reserved[4]; } __reserved_16;
 
/*3B0*/ struct { u32 __reserved[4]; } __reserved_17;
 
/*3C0*/ struct { u32 __reserved[4]; } __reserved_18;
 
/*3D0*/ struct { u32 __reserved[4]; } __reserved_19;
 
/*3E0*/ struct { /* Timer Divide Configuration Register */
u32 divisor : 4,
__reserved_1 : 28;
u32 __reserved_2[3];
} timer_dcr;
 
/*3F0*/ struct { u32 __reserved[4]; } __reserved_20;
 
} __attribute__ ((packed));
 
#undef u32
 
#endif
/shark/trunk/drivers/linuxc26/include/asm/apic.h
1,31 → 1,104
#ifndef __ASM_MACH_APIC_H
#define __ASM_MACH_APIC_H
#ifndef __ASM_APIC_H
#define __ASM_APIC_H
 
#include <asm/genapic.h>
#include <linux/config.h>
#include <linux/pm.h>
#include <asm/fixmap.h>
#include <asm/apicdef.h>
#include <asm/system.h>
 
#define esr_disable (genapic->esr_disable)
#define NO_BALANCE_IRQ (genapic->no_balance_irq)
#define NO_IOAPIC_CHECK (genapic->no_ioapic_check)
#define APIC_BROADCAST_ID (genapic->apic_broadcast_id)
#define INT_DELIVERY_MODE (genapic->int_delivery_mode)
#define INT_DEST_MODE (genapic->int_dest_mode)
#define TARGET_CPUS (genapic->target_cpus())
#define apic_id_registered (genapic->apic_id_registered)
#define apic_id_registered (genapic->apic_id_registered)
#define init_apic_ldr (genapic->init_apic_ldr)
#define ioapic_phys_id_map (genapic->ioapic_phys_id_map)
#define clustered_apic_check (genapic->clustered_apic_check)
#define multi_timer_check (genapic->multi_timer_check)
#define apicid_to_node (genapic->apicid_to_node)
#define cpu_to_logical_apicid (genapic->cpu_to_logical_apicid)
#define cpu_present_to_apicid (genapic->cpu_present_to_apicid)
#define apicid_to_cpu_present (genapic->apicid_to_cpu_present)
#define mpc_apic_id (genapic->mpc_apic_id)
#define setup_portio_remap (genapic->setup_portio_remap)
#define check_apicid_present (genapic->check_apicid_present)
#define check_phys_apicid_present (genapic->check_phys_apicid_present)
#define check_apicid_used (genapic->check_apicid_used)
#define cpu_mask_to_apicid (genapic->cpu_mask_to_apicid)
#define enable_apic_mode (genapic->enable_apic_mode)
#define APIC_DEBUG 0
 
#endif /* __ASM_MACH_APIC_H */
#if APIC_DEBUG
#define Dprintk(x...) printk(x)
#else
#define Dprintk(x...)
#endif
 
#ifdef CONFIG_X86_LOCAL_APIC
 
/*
* Basic functions accessing APICs.
*/
 
static __inline void apic_write(unsigned long reg, unsigned long v)
{
*((volatile unsigned long *)(APIC_BASE+reg)) = v;
}
 
static __inline void apic_write_atomic(unsigned long reg, unsigned long v)
{
xchg((volatile unsigned long *)(APIC_BASE+reg), v);
}
 
static __inline unsigned long apic_read(unsigned long reg)
{
return *((volatile unsigned long *)(APIC_BASE+reg));
}
 
static __inline__ void apic_wait_icr_idle(void)
{
do { } while ( apic_read( APIC_ICR ) & APIC_ICR_BUSY );
}
 
#ifdef CONFIG_X86_GOOD_APIC
# define FORCE_READ_AROUND_WRITE 0
# define apic_read_around(x)
# define apic_write_around(x,y) apic_write((x),(y))
#else
# define FORCE_READ_AROUND_WRITE 1
# define apic_read_around(x) apic_read(x)
# define apic_write_around(x,y) apic_write_atomic((x),(y))
#endif
 
static inline void ack_APIC_irq(void)
{
/*
* ack_APIC_irq() actually gets compiled as a single instruction:
* - a single rmw on Pentium/82489DX
* - a single write on P6+ cores (CONFIG_X86_GOOD_APIC)
* ... yummie.
*/
 
/* Docs say use 0 for future compatibility */
apic_write_around(APIC_EOI, 0);
}
 
extern void (*wait_timer_tick)(void);
 
extern int get_maxlvt(void);
extern void clear_local_APIC(void);
extern void connect_bsp_APIC (void);
extern void disconnect_bsp_APIC (void);
extern void disable_local_APIC (void);
extern int verify_local_APIC (void);
extern void cache_APIC_registers (void);
extern void sync_Arb_IDs (void);
extern void init_bsp_APIC (void);
extern void setup_local_APIC (void);
extern void init_apic_mappings (void);
extern void smp_local_timer_interrupt (struct pt_regs * regs);
extern void setup_boot_APIC_clock (void);
extern void setup_secondary_APIC_clock (void);
extern void setup_apic_nmi_watchdog (void);
extern void disable_lapic_nmi_watchdog(void);
extern void enable_lapic_nmi_watchdog(void);
extern void disable_timer_nmi_watchdog(void);
extern void enable_timer_nmi_watchdog(void);
extern inline void nmi_watchdog_tick (struct pt_regs * regs);
extern int APIC_init_uniprocessor (void);
extern void disable_APIC_timer(void);
extern void enable_APIC_timer(void);
 
extern int check_nmi_watchdog (void);
extern void enable_NMI_through_LVT0 (void * dummy);
 
extern unsigned int nmi_watchdog;
#define NMI_NONE 0
#define NMI_IO_APIC 1
#define NMI_LOCAL_APIC 2
#define NMI_INVALID 3
 
#endif /* CONFIG_X86_LOCAL_APIC */
 
#endif /* __ASM_APIC_H */
/shark/trunk/drivers/linuxc26/include/asm/mpspec.h
1,13 → 1,95
#ifndef __ASM_MACH_MPSPEC_H
#define __ASM_MACH_MPSPEC_H
#ifndef __ASM_MPSPEC_H
#define __ASM_MPSPEC_H
 
/*
* a maximum of 256 APICs with the current APIC ID architecture.
*/
#define MAX_APICS 256
#include <linux/cpumask.h>
#include <asm/mpspec_def.h>
#include <mach_mpspec.h>
 
#define MAX_IRQ_SOURCES 256
extern int mp_bus_id_to_type [MAX_MP_BUSSES];
extern int mp_bus_id_to_node [MAX_MP_BUSSES];
extern int mp_bus_id_to_local [MAX_MP_BUSSES];
extern int quad_local_to_mp_bus_id [NR_CPUS/4][4];
extern int mp_bus_id_to_pci_bus [MAX_MP_BUSSES];
 
#define MAX_MP_BUSSES 32
extern unsigned int boot_cpu_physical_apicid;
extern int smp_found_config;
extern void find_smp_config (void);
extern void get_smp_config (void);
extern int nr_ioapics;
extern int apic_version [MAX_APICS];
extern int mp_bus_id_to_type [MAX_MP_BUSSES];
extern int mp_irq_entries;
extern struct mpc_config_intsrc mp_irqs [MAX_IRQ_SOURCES];
extern int mpc_default_type;
extern int mp_bus_id_to_pci_bus [MAX_MP_BUSSES];
extern int mp_current_pci_id;
extern unsigned long mp_lapic_addr;
extern int pic_mode;
extern int using_apic_timer;
 
#endif /* __ASM_MACH_MPSPEC_H */
#ifdef CONFIG_X86_SUMMIT
extern void setup_summit (void);
#endif
 
#ifdef CONFIG_ACPI_BOOT
extern void mp_register_lapic (u8 id, u8 enabled);
extern void mp_register_lapic_address (u64 address);
extern void mp_register_ioapic (u8 id, u32 address, u32 irq_base);
extern void mp_override_legacy_irq (u8 bus_irq, u8 polarity, u8 trigger, u32 global_irq);
extern void mp_config_acpi_legacy_irqs (void);
extern void mp_parse_prt (void);
 
#ifdef CONFIG_X86_IO_APIC
extern void mp_config_ioapic_for_sci(int irq);
#else
static inline void mp_config_ioapic_for_sci(int irq)
{ }
#endif
#endif /*CONFIG_ACPI_BOOT*/
 
#define PHYSID_ARRAY_SIZE BITS_TO_LONGS(MAX_APICS)
 
struct physid_mask
{
unsigned long mask[PHYSID_ARRAY_SIZE];
};
 
typedef struct physid_mask physid_mask_t;
 
#define physid_set(physid, map) set_bit(physid, (map).mask)
#define physid_clear(physid, map) clear_bit(physid, (map).mask)
#define physid_isset(physid, map) test_bit(physid, (map).mask)
#define physid_test_and_set(physid, map) test_and_set_bit(physid, (map).mask)
 
#define physids_and(dst, src1, src2) bitmap_and((dst).mask, (src1).mask, (src2).mask, MAX_APICS)
#define physids_or(dst, src1, src2) bitmap_or((dst).mask, (src1).mask, (src2).mask, MAX_APICS)
#define physids_clear(map) bitmap_clear((map).mask, MAX_APICS)
#define physids_complement(map) bitmap_complement((map).mask, MAX_APICS)
#define physids_empty(map) bitmap_empty((map).mask, MAX_APICS)
#define physids_equal(map1, map2) bitmap_equal((map1).mask, (map2).mask, MAX_APICS)
#define physids_weight(map) bitmap_weight((map).mask, MAX_APICS)
#define physids_shift_right(d, s, n) bitmap_shift_right((d).mask, (s).mask, n, MAX_APICS)
#define physids_shift_left(d, s, n) bitmap_shift_left((d).mask, (s).mask, n, MAX_APICS)
#define physids_coerce(map) ((map).mask[0])
 
#define physids_promote(physids) \
({ \
physid_mask_t __physid_mask = PHYSID_MASK_NONE; \
__physid_mask.mask[0] = physids; \
__physid_mask; \
})
 
#define physid_mask_of_physid(physid) \
({ \
physid_mask_t __physid_mask = PHYSID_MASK_NONE; \
physid_set(physid, __physid_mask); \
__physid_mask; \
})
 
#define PHYSID_MASK_ALL { {[0 ... PHYSID_ARRAY_SIZE-1] = ~0UL} }
#define PHYSID_MASK_NONE { {[0 ... PHYSID_ARRAY_SIZE-1] = 0UL} }
 
extern physid_mask_t phys_cpu_present_map;
 
#endif