| /shark/trunk/oslib/xlib/vm86.c |
|---|
| 51,7 → 51,6 |
| #define VM86_STACK_SIZE 8192 |
| extern DWORD ll_irq_table[256]; |
| extern BYTE use_apic, use_tsc; |
| /* TSS optional section */ |
| static BYTE vm86_stack0[VM86_STACK_SIZE]; |
| 181,8 → 180,11 |
| LIN_ADDR vm86_stackPtr; |
| DWORD *IRQTable_entry; |
| BYTE p1,p2; |
| DWORD msr1 = 0,msr2 = 0; |
| #ifdef __APIC__ |
| DWORD msr1 = 0,msr2 = 0; |
| #endif |
| SYS_FLAGS f; |
| if (service < 0x10 || in == NULL) return -1; |
| 227,10 → 229,10 |
| outp(0x21,0xFF); |
| outp(0xA1,0xFF); |
| if (use_apic) { |
| #ifdef __APIC__ |
| rdmsr(APIC_BASE_MSR,msr1,msr2); |
| disable_APIC_timer(); |
| } |
| #endif |
| vm86_TSS.t.back_link = ll_context_save(); |
| VM86_ret_ctx = vm86_TSS.t.back_link |
| 238,10 → 240,10 |
| ll_context_load(X_VM86_TSS); |
| cli(); |
| if (use_apic) { |
| #ifdef __APIC__ |
| wrmsr(APIC_BASE_MSR,msr1,msr2); |
| enable_APIC_timer(); |
| } |
| #endif |
| outp(0x21,p1); |
| outp(0xA1,p2); |
| 283,10 → 285,10 |
| outp(0x21,0xFF); |
| outp(0xA1,0xFF); |
| if (use_apic) { |
| #ifdef __APIC__ |
| rdmsr(APIC_BASE_MSR,msr1,msr2); |
| disable_APIC_timer(); |
| } |
| #endif |
| vm86_TSS.t.back_link = ll_context_save(); |
| VM86_ret_ctx = vm86_TSS.t.back_link; |
| 294,10 → 296,10 |
| ll_context_load(X_VM86_TSS); |
| cli(); |
| if (use_apic) { |
| #ifdef __APIC__ |
| wrmsr(APIC_BASE_MSR,msr1,msr2); |
| enable_APIC_timer(); |
| } |
| #endif |
| outp(0x21,p1); |
| outp(0xA1,p2); |
| /shark/trunk/oslib/xlib/xbios.c |
|---|
| 37,27 → 37,28 |
| void X_callBIOS(int service,X_REGS16 *in,X_REGS16 *out,X_SREGS16 *s) |
| { |
| /* Assembler gate JMP instruction */ |
| extern BYTE use_tsc, use_apic; |
| extern void _x_callBIOS(void); |
| X_CALLBIOS *xbc = x_bios_address(); |
| DWORD msr1 = 0,msr2 = 0; |
| #ifdef __APIC__ |
| DWORD msr1 = 0,msr2 = 0; |
| #endif |
| /* Send interrupt request & register through the X_Info structure */ |
| xbc->_irqno = service; |
| memcpy(&(xbc->_ir),in,sizeof(X_REGS16)); |
| memcpy(&(xbc->_sr),s,sizeof(X_SREGS16)); |
| if (use_apic) { |
| #ifdef __APIC__ |
| rdmsr(APIC_BASE_MSR,msr1,msr2); |
| disable_APIC_timer(); |
| } |
| #endif |
| /* Back to RM to execute the BIOS routine */ |
| _x_callBIOS(); |
| /* Get the return register values */ |
| if (use_apic) { |
| #ifdef __APIC__ |
| wrmsr(APIC_BASE_MSR,msr1,msr2); |
| enable_APIC_timer(); |
| } |
| #endif |
| memcpy(out,&(xbc->_or),sizeof(X_REGS16)); |
| memcpy(s,&(xbc->_sr),sizeof(X_SREGS16)); |
| } |
| /shark/trunk/oslib/xlib/xinit.c |
|---|
| 73,10 → 73,9 |
| { |
| register int i; |
| struct ll_cpuInfo cpuInfo; |
| extern BYTE X86_apic; |
| extern BYTE X86_tsc; |
| extern BYTE X86_fpu; |
| LIN_ADDR b; |
| LIN_ADDR b; |
| for(i = 0; i < 256; i++) { |
| ll_irq_table[i] = (DWORD)dummyfun; |
| 89,9 → 88,6 |
| ll_arch.x86.fpu = X86_fpu; |
| memcpy(&(ll_arch.x86.vendor), &(cpuInfo.X86_vendor_1), 12); |
| X86_apic = cpuInfo.X86_StandardFeature & (1<<4); |
| X86_tsc = cpuInfo.X86_StandardFeature & (1<<9); |
| /* TODO! Need to map featuresXXX & Signature onto ll_arch! */ |
| /* TODO! Need to check for CPU bugs!! */ |
| 103,10 → 99,8 |
| message("Features #1: 0x%lx\n", cpuInfo.X86_IntelFeature_1); |
| message("Features #2: 0x%lx\n", cpuInfo.X86_IntelFeature_2); |
| message("Features #3: 0x%lx\n", cpuInfo.X86_StandardFeature); |
| message("Has APIC: %s\n", X86_apic); |
| message("Has TSC: %s\n", X86_tsc); |
| #endif /* __LL_DEBUG__ */ |
| IDT_init(); |
| /* Init coprocessor & assign it to main() */ |