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Ignore whitespace Rev 85 → Rev 102

/shark/tags/rel_0_5/drivers/grx/drawfun/fun16.h
1,3 → 1,6
#include "ll/sys/cdefs.h"
 
__BEGIN_DECLS
#define memsetw(addr, val, n) {LIN_ADDR i; for(i = addr; i < addr + n; i += 2) lmempokew(i, val);}
 
 
17,3 → 20,4
void linWr16(WORD x, WORD y, DWORD color);
DWORD RdPixel_Hi(WORD x, WORD y);
DWORD linRd16(WORD x, WORD y);
__END_DECLS
/shark/tags/rel_0_5/drivers/grx/drawfun/fun8.h
1,3 → 1,6
#include "ll/sys/cdefs.h"
 
__BEGIN_DECLS
void RdWin_256(WORD x1, WORD y1, WORD x2, WORD y2, BYTE *buf);
void linGet8(WORD x1, WORD y1, WORD x2, WORD y2, BYTE *buf);
void WrWin_256(WORD x1, WORD y1, WORD x2, WORD y2, BYTE *buf);
14,3 → 17,4
void linWr8(WORD x, WORD y, DWORD color);
DWORD RdPixel_256(WORD x, WORD y);
DWORD linRd8(WORD x, WORD y);
__END_DECLS
/shark/tags/rel_0_5/drivers/grx/gd.c
290,7 → 290,7
return -2;
}
 
int gd_getmodeinfo(vga_modeinfo *m)
int gd_getmodeinfo(grx_vga_modeinfo *m)
{
if (actualmode.modenum == 0) {
return -1;
/shark/tags/rel_0_5/drivers/grx/makefile
3,6 → 3,8
ifndef BASE
BASE=../..
endif
 
 
include $(BASE)/config/config.mk
 
#C_OPT += -DVM86
/shark/tags/rel_0_5/drivers/grx/drivers/trident.h
1,4 → 1,8
#include "ll/sys/cdefs.h"
 
__BEGIN_DECLS
int trident_test(void);
void trident_setpage(int page);
void trident_showinfo(void);
DWORD trident_getmem(void);
__END_DECLS
/shark/tags/rel_0_5/drivers/grx/drivers/vesa.h
1,4 → 1,8
#include <ll/i386/x-dos.h>
#include "ll/sys/cdefs.h"
 
__BEGIN_DECLS
 
/****************************************************************************/
/* DEFINIZIONE DEI TIPI */
/****************************************************************************/
94,3 → 98,4
int vbe_checkmode(WORD mode);
 
DWORD vbe_getmem(void);
__END_DECLS
/shark/tags/rel_0_5/drivers/grx/drivers/s3.h
1,3 → 1,6
#include "ll/sys/cdefs.h"
 
__BEGIN_DECLS
int s3_test(void);
void s3_setpage(int page);
void s3_setpage864(int page);
4,3 → 7,4
void s3_linear(DWORD param);
void s3_showinfo(void);
DWORD s3_getmem(void);
__END_DECLS
/shark/tags/rel_0_5/drivers/grx/glib.c
125,7 → 125,7
int grx_setmode(WORD mode)
{
int lin;
vga_modeinfo m;
grx_vga_modeinfo m;
 
if ((lin = gd_setmode(mode)) < 0){
return -1;
245,7 → 245,7
 
void grx_clear(DWORD color)
{
vga_modeinfo m;
grx_vga_modeinfo m;
 
gd_getmodeinfo(&m);
grx_box(0, 0, m.width, m.height, color);
/shark/tags/rel_0_5/drivers/oldsnd/blaster.h
1,6 → 1,9
#include "semaphore.h"
#include "ll/sys/cdefs.h"
 
__BEGIN_DECLS
 
 
typedef struct sb_device {
DWORD BaseAddress;
BYTE IntLine;
43,3 → 46,5
void sb_dma16buffop(BYTE i_o);
void sb_stopdsp(BYTE b);
void sb_show(void);
 
__END_DECLS
/shark/tags/rel_0_5/drivers/oldsnd/sbio.h
1,3 → 1,7
#include "ll/sys/cdefs.h"
 
__BEGIN_DECLS
 
/* DSP Registers */
#define RESET 0x06
#define READDATA 0x0A
56,3 → 60,5
BYTE inpb(WORD addr);
void outpb(WORD addr, BYTE val);
 
__END_DECLS
 
/shark/tags/rel_0_5/drivers/oldsnd/makefile
3,6 → 3,7
ifndef BASE
BASE=../..
endif
 
include $(BASE)/config/config.mk
 
LIBRARY = hsnd
/shark/tags/rel_0_5/drivers/net/netbuff.h
20,11 → 20,11
 
/**
------------
CVS : $Id: netbuff.h,v 1.1.1.1 2002-03-29 14:12:50 pj Exp $
CVS : $Id: netbuff.h,v 1.2 2003-03-13 13:54:07 pj Exp $
 
File: $File$
Revision: $Revision: 1.1.1.1 $
Last update: $Date: 2002-03-29 14:12:50 $
Revision: $Revision: 1.2 $
Last update: $Date: 2003-03-13 13:54:07 $
------------
**/
 
56,10 → 56,10
#ifndef __NETBUFF_H__
#define __NETBUFF_H__
 
#ifdef __cplusplus
extern "C" {
#endif
#include "ll/sys/cdefs.h"
 
__BEGIN_DECLS
 
typedef struct netbuff{
BYTE *b;
BYTE **pb;
73,8 → 73,6
void *netbuff_sequentialget(struct netbuff *netb, BYTE to);
void netbuff_release(struct netbuff *netb, void *m);
 
#ifdef __cplusplus
};
#endif
__END_DECLS
 
#endif
/shark/tags/rel_0_5/drivers/net/ne.c
227,12 → 227,12
}
if (!pdev)
continue;
printk(KERN_INFO "ne.c: PCI BIOS reports %s at i/o %#x, irq %d.\n",
printk(KERN_INFO "ne.c: PCI BIOS reports %s at i/o %x, irq %d.\n",
pci_clone_list[i].name,
pci_ioaddr, pci_irq_line);
printk("*\n* Use of the PCI-NE2000 driver with this card is recommended!\n*\n");
if (ne_probe1(dev, pci_ioaddr) != 0) { /* Shouldn't happen. */
printk(KERN_ERR "ne.c: Probe of PCI card at %#x failed.\n", pci_ioaddr);
printk(KERN_ERR "ne.c: Probe of PCI card at %x failed.\n", pci_ioaddr);
pci_irq_line = 0;
return -ENXIO;
}
285,7 → 285,7
if (ei_debug && version_printed++ == 0)
printk(version);
 
printk(KERN_INFO "NE*000 ethercard probe at %#3x:", ioaddr);
printk(KERN_INFO "NE*000 ethercard probe at %3x:", ioaddr);
 
/* A user with a poor card that fails to ack the reset, or that
does not have a valid 0x57,0x57 signature can still use this
473,7 → 473,7
dev->dev_addr[i] = SA_prom[i];
}
 
printk("\n%s: %s found at %#x, using IRQ %d.\n",
printk("\n%s: %s found at %x, using IRQ %d.\n",
dev->name, name, ioaddr, dev->irq);
 
ei_status.name = name;
638,7 → 638,7
} while (--tries > 0);
if (tries <= 0)
printk(KERN_WARNING "%s: RX transfer address mismatch,"
"%#4.4x (expected) vs. %#4.4x (actual).\n",
"%4.4x (expected) vs. %4.4x (actual).\n",
dev->name, ring_offset + xfer_count, addr);
}
#endif
/shark/tags/rel_0_5/drivers/net/8390.h
11,7 → 11,10
#include <linux/if_ether.h>
#include <linux/ioport.h>
#include <linux/skbuff.h>
#include "ll/sys/cdefs.h"
 
__BEGIN_DECLS
 
/* With kmod, drivers can now load the 8390 module themselves! */
#if 0 /* def CONFIG_KMOD */
#define LOAD_8390_BY_KMOD
289,4 → 292,5
#define ENTSR_CDH 0x40 /* The collision detect "heartbeat" signal was lost. */
#define ENTSR_OWC 0x80 /* There was an out-of-window collision. */
 
__END_DECLS
#endif /* _8390_h */
/shark/tags/rel_0_5/drivers/net/eth.c
20,11 → 20,11
 
/**
------------
CVS : $Id: eth.c,v 1.1.1.1 2002-03-29 14:12:50 pj Exp $
CVS : $Id: eth.c,v 1.3 2002-11-11 08:41:31 pj Exp $
 
File: $File$
Revision: $Revision: 1.1.1.1 $
Last update: $Date: 2002-03-29 14:12:50 $
Revision: $Revision: 1.3 $
Last update: $Date: 2002-11-11 08:41:31 $
------------
**/
 
74,6 → 74,8
/*#include "lowlev.h"
//#include "3com.h" */
 
//#define DEBUG_ETH
 
#define ETH_PAGE 5
 
struct eth_service{
131,7 → 133,7
 
void dev_tint(struct device *dev)
{
cprintf("Warning!!!! dev_tint called!!! (Why???)\n");
printk(KERN_WARNING "Warning!!!! dev_tint called!!! (Why?)\n");
sys_abort(201);
}
145,7 → 147,7
{
//cprintf("DENTRO netif_rx, skbuf=%p\n",skb->data);
if (nettask_pid == NIL) {
cprintf("Net receives packets, but the driver doesn't exist!!!\n");
printk(KERN_CRIT "Net receives packets, but the driver doesn't exist!!!\n");
sys_abort(300);
}
200,7 → 202,7
/* formatted print of an ethernet header */
void eth_printHeader(struct eth_header *p)
{
cprintf("Dest : %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x \n",p->dest.ad[0],
cprintf("Dest : %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x \n",p->dest.ad[0],
p->dest.ad[1],
p->dest.ad[2],
p->dest.ad[3],
338,27 → 340,27
{
int p;
 
if (err != ETH_BUFFERS_FULL) cprintf("Ethernet : ");
if (err != ETH_BUFFERS_FULL) printk(KERN_ERR "Ethernet : ");
switch (err) {
case ETH_DRIVER_NOT_FOUND :
cprintf("NET PANIC --> Etherlink not found.\n");
printk(KERN_ERR "NET PANIC --> Etherlink not found.\n");
return 0;
case ETH_RXERROR :
cprintf("Receive error (vero dramma!!!).\n");
printk(KERN_ERR "Receive error (vero dramma!!!).\n");
return 0;
case ETH_TXERROR :
cprintf("Transimit error: N. Max Retry.\n");
printk(KERN_ERR "Transimit error: N. Max Retry.\n");
return 0;
case ETH_PROTOCOL_ERROR :
cprintf("Too much protocols.\n");
printk(KERN_ERR "Too much protocols.\n");
return 0;
case ETH_BUFFERS_FULL:
cprintf("Buffers full: frame lost!\n");
printk(KERN_ERR "Buffers full: frame lost!\n");
return 1;
case ETH_NULLPROTOCOL_EXC:
cprintf("Null protocol called!!!\n");
printk(KERN_ERR "Null protocol called!!!\n");
for (p = 0; p < ETH_MAX_PROTOCOLS; p++) {
cprintf("%d: %d\n", p, eth_table[p].type);
printk(KERN_ERR "%d: %d\n", p, eth_table[p].type);
}
return 0;
default :
377,7 → 379,7
int linux_found = 0;
 
if (!ethIsInstalled) {
cprintf(" Hartik Net lib\n\n");
printk(KERN_INFO "Hartik/Shark Net lib");
/* Scan the devices connected to the PCI bus */
cardtype = NONE;
 
391,24 → 393,30
soft_task_def_aperiodic(m_soft);
soft_task_def_system(m_soft);
soft_task_def_nokill(m_soft);
m = &m_soft;
m = (TASK_MODEL *)&m_soft;
}
 
nettask_pid = task_create("rxProc", net_extern_driver, m, NULL);
if (nettask_pid == NIL) {
cprintf("Can't create extern driver!!!\n");
return 0;
printk(KERN_ERR "Can't create extern driver!!!\n");
return 0;
}
task_activate(nettask_pid);
if (pci_init() == 1) {
linuxpci_init();
// pci_show();
cprintf("LF %d\n", linux_found);
#ifdef DEBUG_ETH
printk(KERN_DEBUG "LF %d\n", linux_found);
#endif
linux_found += (rtl8139_probe(&device0) == 0);
cprintf("LF %d\n", linux_found);
#ifdef DEBUG_ETH
printk(KERN_DEBUG "LF %d\n", linux_found);
#endif
linux_found += (tc59x_probe(&device0) == 0);
cprintf("LF %d\n", linux_found);
#ifdef DEBUG_ETH
printk(KERN_DEBUG "LF %d\n", linux_found);
#endif
#if 0
ndev = pci_scan_bus(pci_devs);
#ifdef __ETH_DBG__
434,7 → 442,7
} else {
lowlev_send = vortex_send_mem;
}
cprintf("PCI Ethlink card found:\n");
printk(KERN_INFO "PCI Ethlink card found:\n");
lowlev_info(r);
cardtype = VORTEX;
}
460,10 → 468,14
#else
}
if (linux_found == 0) {
linux_found += (el3_probe(&device0) == 0);
cprintf("LF %d\n", linux_found);
linux_found += (ne_probe(&device0) == 0);
cprintf("LF %d\n", linux_found);
linux_found += (el3_probe(&device0) == 0);
#ifdef DEBUG_ETH
printk(KERN_DEBUG "LF %d\n", linux_found);
#endif
linux_found += (ne_probe(&device0) == 0);
#ifdef DEBUG_ETH
printk(KERN_DEBUG "LF %d\n", linux_found);
#endif
}
 
/*
474,9 → 486,9
*/
if (linux_found) {
device0.open(&device0);
cprintf("Net card found!!!\n");
printk(KERN_INFO "Net card found!!!\n");
} else {
cprintf("No card found... \n");
printk(KERN_INFO "No card found... \n");
/* cprintf("No card found... Installing loopback device\n");
loopback_init(&device0);
device0.open(&device0);*/
497,7 → 509,7
sys_atrunlevel(eth_close,NULL,RUNLEVEL_BEFORE_EXIT);
 
} else {
cprintf("Ethernet already installed!!!\n");
printk(KERN_INFO "Ethernet already installed!!!\n");
return 0;
}
return 1;
505,10 → 517,12
 
void eth_close(void *a)
{
kern_printf("CLOSE!!!!\n");
if (ethIsInstalled == TRUE) {
device0.stop(&device0); /*This seems to break everithing...
// lowlev_close(eth_dev.BaseAddress);*/
ethIsInstalled = FALSE;
}
#ifdef DEBUG_ETH
printk(KERN_DEBUG "CLOSE!!!!\n");
#endif
if (ethIsInstalled == TRUE) {
device0.stop(&device0); /*This seems to break everithing...
// lowlev_close(eth_dev.BaseAddress);*/
ethIsInstalled = FALSE;
}
}
/shark/tags/rel_0_5/drivers/net/eth_priv.h
20,11 → 20,11
 
/**
------------
CVS : $Id: eth_priv.h,v 1.1.1.1 2002-03-29 14:12:50 pj Exp $
CVS : $Id: eth_priv.h,v 1.2 2003-03-13 13:54:07 pj Exp $
 
File: $File$
Revision: $Revision: 1.1.1.1 $
Last update: $Date: 2002-03-29 14:12:50 $
Revision: $Revision: 1.2 $
Last update: $Date: 2003-03-13 13:54:07 $
------------
**/
 
57,10 → 57,10
#ifndef __ETH_H__
#define __ETH_H__
 
#ifdef __cplusplus
extern "C" {
#endif
#include "ll/sys/cdefs.h"
 
__BEGIN_DECLS
 
#define LOOPBACK 2
#define ETH_MAX_LEN 1528
111,8 → 111,5
void eth_getAddress(struct eth_addr *eth);
 
 
#ifdef __cplusplus
};
__END_DECLS
#endif
 
#endif
/shark/tags/rel_0_5/drivers/net/net.c
20,11 → 20,11
 
/**
------------
CVS : $Id: net.c,v 1.1.1.1 2002-03-29 14:12:50 pj Exp $
CVS : $Id: net.c,v 1.2 2002-10-28 08:01:36 pj Exp $
 
File: $File$
Revision: $Revision: 1.1.1.1 $
Last update: $Date: 2002-03-29 14:12:50 $
Revision: $Revision: 1.2 $
Last update: $Date: 2002-10-28 08:01:36 $
------------
**/
 
63,6 → 63,8
#include <drivers/net.h>
#include "eth_priv.h"
 
//#define DEBUG_NET
 
/* OKKIO!!!!! net_base must change if you change NET_MAX_PROTOCOLS!!!! */
struct net_model net_base = {0, 0, {NULL, NULL, NULL, NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL, NULL, NULL, NULL,
88,8 → 90,10
}
/* Then, the high level layers */
for(i = 0; i < m->numprotocol; i++) {
cprintf("Protocol %d init \n", i);
m->protocol[i].initfun(m->protocol[i].initparms);
#ifdef DEBUG_NET
printk(KERN_DEBUG "Protocol %d init \n", i);
#endif
m->protocol[i].initfun(m->protocol[i].initparms);
}
 
return 1;
/shark/tags/rel_0_5/drivers/net/arp.h
20,11 → 20,11
 
/**
------------
CVS : $Id: arp.h,v 1.1.1.1 2002-03-29 14:12:50 pj Exp $
CVS : $Id: arp.h,v 1.2 2003-03-13 13:54:07 pj Exp $
 
File: $File$
Revision: $Revision: 1.1.1.1 $
Last update: $Date: 2002-03-29 14:12:50 $
Revision: $Revision: 1.2 $
Last update: $Date: 2003-03-13 13:54:07 $
------------
**/
 
58,10 → 58,10
#ifndef __ARP_H__
#define __ARP_H__
 
#ifdef __cplusplus
extern "C" {
#endif
#include "ll/sys/cdefs.h"
 
__BEGIN_DECLS
 
#define ARP_IP_TYPE 0x0800
#define ARP_ETH_TYPE 1
90,8 → 90,6
int arp_req(IP_ADDR dest);
void arp_sendRequest(int i);
 
#ifdef __cplusplus
};
#endif
__BEGIN_DECLS
 
#endif
/shark/tags/rel_0_5/drivers/net/makefile
3,6 → 3,7
ifndef BASE
BASE=../..
endif
 
include $(BASE)/config/config.mk
 
LIBRARY = hnet
/shark/tags/rel_0_5/drivers/block/sstf/sstf.h
42,7 → 42,10
 
#include "phdsk.h"
#include "glue.h"
#include "ll/sys/cdefs.h"
 
__BEGIN_DECLS
 
typedef struct TAGsstf_queue_t {
struct phdskinfo *disk;
/**/
65,4 → 68,5
#define bqueue_getrequest sstf_getrequest
#define bqueue_removerequest sstf_removerequest
 
__END_DECLS
#endif
/shark/tags/rel_0_5/drivers/block/fcfs/fcfs.h
42,7 → 42,10
 
#include "phdsk.h"
#include "glue.h"
#include "ll/sys/cdefs.h"
 
__BEGIN_DECLS
 
typedef struct TAGfcfs_queue_t {
struct phdskinfo *disk;
/**/
64,4 → 67,5
#define bqueue_getrequest fcfs_getrequest
#define bqueue_removerequest fcfs_removerequest
 
__END_DECLS
#endif
/shark/tags/rel_0_5/drivers/block/glue.h
20,7 → 20,10
*/
#include <kernel/int_sem.h>
#include "ll/sys/cdefs.h"
 
__BEGIN_DECLS
 
/*+ a semaphore object +*/
typedef internal_sem_t __b_mutex_t;
 
128,5 → 131,5
while (__gettimer()<t); \
}
 
__END_DECLS
#endif
 
/shark/tags/rel_0_5/drivers/block/ide.h
21,11 → 21,11
 
/***************************************
 
CVS : $Id: ide.h,v 1.1.1.1 2002-03-29 14:12:49 pj Exp $
CVS : $Id: ide.h,v 1.2 2003-03-13 13:43:13 pj Exp $
Revision: $Revision: 1.1.1.1 $
Revision: $Revision: 1.2 $
 
Last update: $Date: 2002-03-29 14:12:49 $
Last update: $Date: 2003-03-13 13:43:13 $
 
Header file for all the modules of the IDE block device interface
sub-system.
57,7 → 57,10
#include "glue.h"
#include "bdev.h"
#include "bqueue.h"
#include "ll/sys/cdefs.h"
 
__BEGIN_DECLS
 
/*+ max number of ide interface (must be <= 8) +*/
#define MAXIDEINTERFACES 4
 
444,6 → 447,7
#define is_communicatordev(p) ((((p)->config&0x1f00)>>8)==0x09)
#define is_arraydev(p) ((((p)->config&0x1f00)>>8)==0x0c)
 
__END_DECLS
#endif
 
 
/shark/tags/rel_0_5/drivers/block/edf/edf.h
42,7 → 42,10
 
#include "phdsk.h"
#include "glue.h"
#include "ll/sys/cdefs.h"
 
__BEGIN_DECLS
 
typedef struct TAGbd_edf_queue_t {
struct phdskinfo *disk;
/**/
65,4 → 68,5
#define bqueue_getrequest bd_edf_getrequest
#define bqueue_removerequest bd_edf_removerequest
 
__END_DECLS
#endif
/shark/tags/rel_0_5/drivers/block/idereq.h
9,7 → 9,10
 
#include "bqueue.h"
#include "glue.h"
#include "ll/sys/cdefs.h"
 
__BEGIN_DECLS
 
#define MAXIDEREQUEST 64
 
/* -------- */
60,4 → 63,5
/* remove the request that we have served blocking the queue*/
int remove_idereq_blocking(int ideif);
 
__END_DECLS
#endif
/shark/tags/rel_0_5/drivers/block/phdsk.h
38,11 → 38,11
*/
 
/*
* CVS : $Id: phdsk.h,v 1.1.1.1 2002-03-29 14:12:49 pj Exp $
* CVS : $Id: phdsk.h,v 1.2 2003-03-13 13:43:13 pj Exp $
*
* File: $File$
* Revision: $Revision: 1.1.1.1 $
* Last update: $Date: 2002-03-29 14:12:49 $
* Revision: $Revision: 1.2 $
* Last update: $Date: 2003-03-13 13:43:13 $
*/
 
#ifndef __PHDSK_H__
49,7 → 49,10
#define __PHDSK_H__
 
#include "glue.h"
#include "ll/sys/cdefs.h"
 
__BEGIN_DECLS
 
#define MAXPHDSK 4
 
#define MAXPHDSKNAME 16
85,4 → 88,5
void phdsk_init(void);
struct phdskinfo *phdsk_register(struct phdskinfo *disk);
 
__END_DECLS
#endif
/shark/tags/rel_0_5/drivers/block/lodsk.h
39,11 → 39,11
*/
 
/*
* CVS : $Id: lodsk.h,v 1.1.1.1 2002-03-29 14:12:49 pj Exp $
* CVS : $Id: lodsk.h,v 1.2 2003-03-13 13:43:13 pj Exp $
*
* File: $File$
* Revision: $Revision: 1.1.1.1 $
* Last update: $Date: 2002-03-29 14:12:49 $
* Revision: $Revision: 1.2 $
* Last update: $Date: 2003-03-13 13:43:13 $
*/
 
#ifndef __LODSK_H__
50,7 → 50,10
#define __LODSK_H__
 
#include "glue.h"
#include "ll/sys/cdefs.h"
 
__BEGIN_DECLS
 
#define MSDOS_LABEL_MAGIC 0xAA55
 
struct phpartition {
91,5 → 94,6
 
int lodsk_scan(__dev_t device, lodsk_callback_func func,
void *data, int showinfo, char *lname);
 
__END_DECLS
#endif
/shark/tags/rel_0_5/drivers/block/look/look.h
42,7 → 42,10
 
#include "phdsk.h"
#include "glue.h"
#include "ll/sys/cdefs.h"
 
__BEGIN_DECLS
 
typedef struct TAGlook_queue_t {
struct phdskinfo *disk;
/**/
64,4 → 67,5
#define bqueue_getrequest look_getrequest
#define bqueue_removerequest look_removerequest
 
__END_DECLS
#endif
/shark/tags/rel_0_5/drivers/block/pscan/pscan.h
42,7 → 42,10
 
#include "phdsk.h"
#include "glue.h"
#include "ll/sys/cdefs.h"
 
__BEGIN_DECLS
 
/* must be in sync with <modules/bd_pscan.h> */
#define NUMPRIORITY 4
 
70,4 → 73,5
#define bqueue_getrequest pscan_getrequest
#define bqueue_removerequest pscan_removerequest
 
__END_DECLS
#endif
/shark/tags/rel_0_5/drivers/block/ideglue.h
1,9 → 1,13
 
#ifndef __IDEGLUE_H
#define __IDEGLUE_H
#include "ll/sys/cdefs.h"
 
__BEGIN_DECLS
 
void ide_glue_send_request(int ideif);
int ide_glue_activate_interface(int ideif);
void ide_glue_unactivate_interface(int ideif);
 
__END_DECLS
#endif
/shark/tags/rel_0_5/drivers/block/bdev.h
39,11 → 39,11
*/
 
/*
* CVS : $Id: bdev.h,v 1.1.1.1 2002-03-29 14:12:49 pj Exp $
* CVS : $Id: bdev.h,v 1.2 2003-03-13 13:43:13 pj Exp $
*
* File: $File$
* Revision: $Revision: 1.1.1.1 $
* Last update: $Date: 2002-03-29 14:12:49 $
* Revision: $Revision: 1.2 $
* Last update: $Date: 2003-03-13 13:43:13 $
*/
 
#ifndef __BDEV_H__
52,7 → 52,10
#include "glue.h"
#include <fs/bdevinit.h>
#include <fs/bdev.h>
#include "ll/sys/cdefs.h"
 
__BEGIN_DECLS
 
#define MAXBLOCKDEVICE 8
 
struct block_device {
105,4 → 108,5
int bdev_seek(__dev_t dev, __blkcnt_t blocknum);
int bdev_write(__dev_t dev, __blkcnt_t blocknum, __uint8_t *buffer);
 
__END_DECLS
#endif
/shark/tags/rel_0_5/drivers/block/clook/clook.h
43,7 → 43,10
 
#include "phdsk.h"
#include "glue.h"
#include "ll/sys/cdefs.h"
 
__BEGIN_DECLS
 
typedef struct TAGclook_queue_t {
struct phdskinfo *disk;
/**/
65,4 → 68,5
#define bqueue_getrequest clook_getrequest
#define bqueue_removerequest clook_removerequest
 
__END_DECLS
#endif
/shark/tags/rel_0_5/drivers/block/bqueue.h
20,11 → 20,11
 
/***************************************
 
CVS : $Id: bqueue.h,v 1.1.1.1 2002-03-29 14:12:49 pj Exp $
CVS : $Id: bqueue.h,v 1.2 2003-03-13 13:43:13 pj Exp $
Revision: $Revision: 1.1.1.1 $
Revision: $Revision: 1.2 $
 
Last update: $Date: 2002-03-29 14:12:49 $
Last update: $Date: 2003-03-13 13:43:13 $
 
This module is responsable of the protocol between the IDE device driver
interface and the host (the computer).
74,6 → 74,10
#include "pscan/pscan.h"
#endif
 
#include "ll/sys/cdefs.h"
 
__BEGIN_DECLS
 
#define REQ_DUMMY 0
#define REQ_SEEK 1
#define REQ_READ 2
95,5 → 99,5
int bqueue_insertrequest(bqueue_t *, struct request_prologue *);
struct request_prologue *bqueue_getrequest(bqueue_t *);
int bqueue_removerequest(bqueue_t *);
 
__END_DECLS
#endif
/shark/tags/rel_0_5/drivers/block/debug.h
1,3 → 1,8
#include "ll/sys/cdefs.h"
 
__BEGIN_DECLS
 
/* si trova in fs/util/ */
void dump_buffer(char *buf, int size);
 
__END_DECLS
/shark/tags/rel_0_5/drivers/block/makefile
5,6 → 5,7
ifndef BASE
BASE=../..
endif
 
include $(BASE)/config/config.mk
 
LIBRARY = blk
/shark/tags/rel_0_5/drivers/pci/linuxpci.h
46,6 → 46,10
#ifndef LINUX_PCI_H
#define LINUX_PCI_H
 
#include "ll/sys/cdefs.h"
 
__BEGIN_DECLS
 
/*
* Under PCI, each device has 256 bytes of configuration address space,
* of which the first 64 bytes are standardized as follows:
1076,4 → 1080,6
extern const char *pci_strclass (unsigned int class);
extern const char *pci_strvendor (unsigned int vendor);
 
__END_DECLS
 
#endif /* LINUX_PCI_H */
/shark/tags/rel_0_5/drivers/pci/pci.h
9,10 → 9,10
#ifndef __PCI_H__
#define __PCI_H__
 
#ifdef __cplusplus
extern "C" {
#endif
#include "ll/sys/cdefs.h"
 
__BEGIN_DECLS
 
#define N_MAX_DEVS 10
 
typedef struct pci_regs {
72,9 → 72,7
struct pci_regs *pci_class(DWORD class_code, WORD index, BYTE *bus, BYTE *dev);
struct pci_regs *pci_device(WORD vendor, WORD device, WORD index, BYTE *bus, BYTE *dev);
 
#ifdef __cplusplus
};
#endif
__END_DECLS
 
#endif
 
/shark/tags/rel_0_5/drivers/pci/makefile
3,6 → 3,7
ifndef BASE
BASE=../..
endif
 
include $(BASE)/config/config.mk
 
LIBRARY = hpci
/shark/tags/rel_0_5/drivers/pci/pci.c
3,15 → 3,13
#include <ll/i386/hw-arch.h>
#include <ll/i386/hw-io.h>
#include <ll/i386/cons.h>
 
#include <ll/stdlib.h>
 
 
 
#include <drivers/llpci.h>
#include <drivers/pci.h>
#include <drivers/linuxpci.h>
 
#include <kernel/log.h>
 
static int ndev = 0;
static struct pci_des pci_devs[N_MAX_DEVS];
 
29,7 → 27,7
if (pcibios_present() == 0) return -1;
ndev = 0;
 
for (bus = 0; bus <= 0; bus++) {
for (bus = 0; bus <= 1; bus++) {
for (dev = 0; dev <= 0xFF; dev++) {
present = 0;
if ((dev & 0x07) == 0) {
108,7 → 106,10
{
 
if (pci_class(class_code, index, bus, dev) != NULL) {
cprintf("PCIBIOS_FIND_CLASS: found at bus %d, dev %d\n", *bus, *dev);
#ifdef DEBUG_PCI
printk(KERN_DEBUG "PCIBIOS_FIND_CLASS:"
"found at bus %d, dev %d\n", *bus, *dev);
#endif
return PCIBIOS_SUCCESSFUL;
} else {
return PCIBIOS_DEVICE_NOT_FOUND;
122,14 → 123,15
int i;
struct pci_regs *r;
 
cprintf(" DevLib PCI support\n\n");
cprintf(" PCI config type %d\n", pcibios_present());
cprintf(" %d PCI devices found:\n\n", ndev);
printk(KERN_INFO "DevLib PCI support\n\n");
printk(KERN_INFO "PCI config type %d\n", pcibios_present());
printk(KERN_INFO "%d PCI devices found:\n\n", ndev);
for(i = 0; i < ndev; i++) {
cprintf(" %d: bus %d dev %d\n",i , pci_devs[i].bus, pci_devs[i].dev);
r = (struct pci_regs *) pci_devs[i].mem;
cprintf(" Vendor: %s", pci_strvendor(r->VendorId));
cprintf(" Class: %s\n", pci_strclass(r->ClassCode << 8));
printk(KERN_INFO "%d: bus %d dev %d\n",
i, pci_devs[i].bus, pci_devs[i].dev);
printk(KERN_INFO "Vendor: %s", pci_strvendor(r->VendorId));
printk(KERN_INFO "Class: %s\n", pci_strclass(r->ClassCode << 8));
}
}
 
/shark/tags/rel_0_5/drivers/pci/pci_scan.c
3,17 → 3,15
#include <ll/i386/hw-arch.h>
#include <ll/i386/hw-io.h>
#include <ll/i386/cons.h>
#include <ll/i386/error.h>
#include <ll/i386/mem.h>
 
#include <ll/stdlib.h>
 
 
 
#include <drivers/llpci.h>
#include <drivers/pci.h>
#include <drivers/linuxpci.h>
#include <kernel/log.h>
 
//#define DEBUG_PCISCAN
 
static struct pci_dev pci_devs[N_MAX_DEVS];
 
static struct pci_bus pci_root;
146,7 → 144,9
*/
child = kmalloc(sizeof(*child), GFP_ATOMIC);
if(child==NULL) {
error(KERN_ERR "pci: out of memory for bridge.\n");
#ifdef DEBUG_PCISCAN
printk(KERN_ERR "pci: out of memory for bridge.\n");
#endif
continue;
}
memset(child, 0, sizeof(*child));
221,11 → 221,15
pcibios_init();
 
if (!pci_present()) {
error("PCI: No PCI bus detected\n");
#ifdef DEBUG_PCISCAN
printk("PCI: No PCI bus detected\n");
#endif
return;
}
 
error("PCI: Probing PCI hardware\n");
#ifdef DEBUG_PCISCAN
printk("PCI: Probing PCI hardware\n");
#endif
memset(&pci_root, 0, sizeof(pci_root));
pci_root.subordinate = pci_scan_bus(&pci_root);
}
/shark/tags/rel_0_5/drivers/char/8042.h
20,11 → 20,11
 
/**
------------
CVS : $Id: 8042.h,v 1.1.1.1 2002-03-29 14:12:49 pj Exp $
CVS : $Id: 8042.h,v 1.2 2003-03-13 13:49:53 pj Exp $
 
File: $File$
Revision: $Revision: 1.1.1.1 $
Last update: $Date: 2002-03-29 14:12:49 $
Revision: $Revision: 1.2 $
Last update: $Date: 2003-03-13 13:49:53 $
------------
 
8042.h
63,6 → 63,10
#ifndef __8042_H__
#define __8042_H__
 
#include "ll/sys/cdefs.h"
 
__BEGIN_DECLS
 
#define C8042_KEYBOARDIRQ 1
#define C8042_PS2IRQ 12
 
213,6 → 217,7
need
*/
 
__END_DECLS
#endif
 
 
/shark/tags/rel_0_5/drivers/char/sermouse.h
20,11 → 20,11
 
/**
------------
CVS : $Id: sermouse.h,v 1.1.1.1 2002-03-29 14:12:49 pj Exp $
CVS : $Id: sermouse.h,v 1.2 2003-03-13 13:49:53 pj Exp $
 
File: $File$
Revision: $Revision: 1.1.1.1 $
Last update: $Date: 2002-03-29 14:12:49 $
Revision: $Revision: 1.2 $
Last update: $Date: 2003-03-13 13:49:53 $
------------
 
Author: Massimiliano Giorgi
59,7 → 59,10
#define __SERMOUSE_H__
 
#include <drivers/mouse.h>
#include "ll/sys/cdefs.h"
 
__BEGIN_DECLS
 
typedef struct sermouse_info {
int type; /* MSMOUSE, MMMOUSE,... */
int port; /* COM1,COM2,... */
88,4 → 91,5
int M_mm(MOUSE_EVT *evt,unsigned char *data);
int M_logi(MOUSE_EVT *evt,unsigned char *data);
 
__END_DECLS
#endif
/shark/tags/rel_0_5/drivers/char/ps2mouse.h
20,11 → 20,11
 
/**
------------
CVS : $Id: ps2mouse.h,v 1.1.1.1 2002-03-29 14:12:49 pj Exp $
CVS : $Id: ps2mouse.h,v 1.2 2003-03-13 13:49:53 pj Exp $
 
File: $File$
Revision: $Revision: 1.1.1.1 $
Last update: $Date: 2002-03-29 14:12:49 $
Revision: $Revision: 1.2 $
Last update: $Date: 2003-03-13 13:49:53 $
------------
 
Author: Massimiliano Giorgi
59,7 → 59,10
#define __PS2MOUSE_H__
 
#include <drivers/mouse.h>
#include "ll/sys/cdefs.h"
 
__BEGIN_DECLS
 
extern int C8042_ps2mousepresent(void);
#define ps2mouse_present() C8042_ps2mousepresent()
 
75,4 → 78,5
 
extern int M_ps2(MOUSE_EVT *evt, unsigned char *data);
 
__END_DECLS
#endif
/shark/tags/rel_0_5/drivers/char/_mouse.h
20,11 → 20,11
 
/**
------------
CVS : $Id: _mouse.h,v 1.1.1.1 2002-03-29 14:12:49 pj Exp $
CVS : $Id: _mouse.h,v 1.2 2003-03-13 13:49:53 pj Exp $
 
File: $File$
Revision: $Revision: 1.1.1.1 $
Last update: $Date: 2002-03-29 14:12:49 $
Revision: $Revision: 1.2 $
Last update: $Date: 2003-03-13 13:49:53 $
------------
 
_mouse.h
52,7 → 52,10
 
#ifndef ___MOUSE_H__
#define ___MOUSE_H__
#include "ll/sys/cdefs.h"
 
__BEGIN_DECLS
 
/* "virtual operations" on a mouse */
struct mouse_operations {
char *name; /* name! */
134,6 → 137,7
/* (to not declare saved_x & saved_y public) */
void _mouse_getsavedposition(int *xptr, int *yptr);
 
__END_DECLS
#endif
 
 
/shark/tags/rel_0_5/drivers/char/makefile
3,6 → 3,7
ifndef BASE
BASE=../..
endif
 
include $(BASE)/config/config.mk
 
LIBRARY = hdev
/shark/tags/rel_0_5/drivers/char/mcurgrx.c
20,11 → 20,11
 
/**
------------
CVS : $Id: mcurgrx.c,v 1.1.1.1 2002-03-29 14:12:49 pj Exp $
CVS : $Id: mcurgrx.c,v 1.2 2003-02-28 11:11:04 pj Exp $
 
File: $File$
Revision: $Revision: 1.1.1.1 $
Last update: $Date: 2002-03-29 14:12:49 $
Revision: $Revision: 1.2 $
Last update: $Date: 2003-02-28 11:11:04 $
------------
 
Author: Massimiliano Giorgi
153,7 → 153,7
int mouse_grxshape(BYTE *shapeptr, BYTE *maskptr)
{
int result;
vga_modeinfo info;
grx_vga_modeinfo info;
int nb;
BYTE b;
int pc;
/shark/tags/rel_0_5/drivers/char/scom.c
20,11 → 20,11
 
/**
------------
CVS : $Id: scom.c,v 1.1.1.1 2002-03-29 14:12:49 pj Exp $
CVS : $Id: scom.c,v 1.2 2003-01-07 17:14:05 pj Exp $
 
File: $File$
Revision: $Revision: 1.1.1.1 $
Last update: $Date: 2002-03-29 14:12:49 $
Revision: $Revision: 1.2 $
Last update: $Date: 2003-01-07 17:14:05 $
------------
 
Author: Massimiliano Giorgi
482,7 → 482,6
task_activate(p3);
task_endcycle();
sys_end();
sys_status(NORM_STATUS);
#ifdef __DEBUG_SERIAL__
cprintf("RxServer was activated %d times\n",rx_time);
cprintf("TxServer was activated %d times\n",tx_time);
/shark/tags/rel_0_5/drivers/char/sermouse.c
20,11 → 20,11
 
/**
------------
CVS : $Id: sermouse.c,v 1.1.1.1 2002-03-29 14:12:49 pj Exp $
CVS : $Id: sermouse.c,v 1.2 2002-11-11 08:41:31 pj Exp $
 
File: $File$
Revision: $Revision: 1.1.1.1 $
Last update: $Date: 2002-03-29 14:12:49 $
Revision: $Revision: 1.2 $
Last update: $Date: 2002-11-11 08:41:31 $
------------
 
Author: Gerardo Lamastra
84,6 → 84,7
//#include <cons.h>
 
#include <kernel/kern.h>
#include <time.h>
//#include "sys/sys.h"
//#include "vm.h"
//#include "kern.h"
405,15 → 406,19
int port;
int ret;
int found;
struct timespec delay;
 
delay.tv_sec = 0;
delay.tv_nsec = 500000000;
 
found=0;
for (port=COM1;port<=COM4;port++) {
ret=com_open(port,1200,NONE,7,1);
if (ret==1) {
com_write(port,MCR,0x0e);
task_delay(500000l); /* necessary? */
nanosleep(&delay,NULL); /* necessary? */
com_write(port,MCR,0x0f);
task_delay(500000l); /* necessary? */
nanosleep(&delay,NULL); /* necessary? */
ret=sem_wait(&com_link[mouse_port].rx_sem);
if (ret==TRUE) {
if (*(com_link[mouse_port].rx_buf)=='M') found=1;
/shark/tags/rel_0_5/drivers/char/rtc.c
20,11 → 20,11
 
/**
------------
CVS : $Id: rtc.c,v 1.1.1.1 2002-03-29 14:12:49 pj Exp $
CVS : $Id: rtc.c,v 1.2 2002-11-11 08:41:31 pj Exp $
 
File: $File$
Revision: $Revision: 1.1.1.1 $
Last update: $Date: 2002-03-29 14:12:49 $
Revision: $Revision: 1.2 $
Last update: $Date: 2002-11-11 08:41:31 $
------------
 
Author: Massimiliano Giorgi
183,7 → 183,7
SYS_FLAGS flags;
unsigned char ctrl;
unsigned retries=0;
unsigned delay;
struct timespec delay;
 
/*
* read RTC once any update in progress is done. The update
201,8 → 201,9
barrier();
*/
 
delay=1000;
while (rtc_is_updating()&&++retries<=5) task_delay(delay);
delay.tv_nsec = 1000000;
delay.tv_sec = 0;
while (rtc_is_updating()&&++retries<=5) nanosleep(&delay, NULL);
if (retries>5) return -1;
 
/*
/shark/tags/rel_0_5/drivers/char/8042.c
20,11 → 20,11
 
/**
------------
CVS : $Id: 8042.c,v 1.1.1.1 2002-03-29 14:12:49 pj Exp $
CVS : $Id: 8042.c,v 1.2 2002-11-11 08:41:31 pj Exp $
 
File: $File$
Revision: $Revision: 1.1.1.1 $
Last update: $Date: 2002-03-29 14:12:49 $
Revision: $Revision: 1.2 $
Last update: $Date: 2002-11-11 08:41:31 $
------------
 
8042.h
348,7 → 348,7
static int C8042_reset(void)
{
int c;
int c=0;
int retries=16;
 
trace("8042 reset START");
/shark/tags/rel_0_5/drivers/pci6025e/makefile
3,6 → 3,7
ifndef BASE
BASE=../..
endif
 
include $(BASE)/config/config.mk
 
LIBRARY = 6025e
/shark/tags/rel_0_5/drivers/linuxcom/include/linux/netdevice.h
8,13 → 8,25
 
#include <linux/skbuff.h>
#include <linux/notifier.h>
#include <time.h>
#include "ll/sys/cdefs.h"
 
__BEGIN_DECLS
 
// for 3c59x.c (!!!)
#define le32_to_cpu(val) (val)
#define cpu_to_le32(val) (val)
#define test_and_set_bit(val, addr) set_bit(val, addr)
#define mdelay(x) task_delay((x)*1000)
#define kfree(x) { }
 
static __inline__ void mdelay(int x)
{
struct timespec delay;
delay.tv_sec=x/1000;
delay.tv_nsec=(x%1000)*1000000;
nanosleep(&delay, NULL);
}
 
#define kfree(x) free(x)
#define ioremap(a,b) \
(((a)<0x100000) ? (void *)((u_long)(a)) : vremap(a,b))
#define iounmap(v) \
249,6 → 261,7
 
void netif_rx(struct sk_buff *skb);
 
__END_DECLS
#endif
 
 
/shark/tags/rel_0_5/drivers/linuxcom/include/linux/stddef.h
1,6 → 1,10
#ifndef _LINUX_STDDEF_H
#define _LINUX_STDDEF_H
 
#include "ll/sys/cdefs.h"
 
__BEGIN_DECLS
 
#ifndef _SIZE_T
#define _SIZE_T
typedef unsigned int size_t;
12,4 → 16,6
#undef offsetof
#define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER)
 
__END_DECLS
 
#endif
/shark/tags/rel_0_5/drivers/linuxcom/include/linux/notifier.h
2,7 → 2,10
#define __NOTIFIER__
 
#include <linux/compatib.h>
#include "ll/sys/cdefs.h"
 
__BEGIN_DECLS
 
struct notifier_block
{
int (*notifier_call)(struct notifier_block *this, unsigned long, void *);
10,4 → 13,6
int priority;
};
 
__END_DECLS
 
#endif
/shark/tags/rel_0_5/drivers/linuxcom/include/linux/kernel.h
2,7 → 2,10
#define __KERNEL__
 
#include <linux/compatib.h>
#include "ll/sys/cdefs.h"
 
__BEGIN_DECLS
 
/* Optimization barrier */
#define barrier() __asm__("": : :"memory")
 
14,4 → 17,6
#define KERN_NOTICE "<5>" /* normal but significant condition */
#define KERN_INFO "<6>" /* informational */
#define KERN_DEBUG "<7>" /* debug-level messages */
 
__END_DECLS
#endif
/shark/tags/rel_0_5/drivers/linuxcom/include/linux/etherdevice.h
5,7 → 5,10
 
#include <linux/if_ether.h>
#include <linux/socket.h>
#include "ll/sys/cdefs.h"
 
__BEGIN_DECLS
 
#define eth_header panic_stub
#if 0
extern int eth_header(struct sk_buff *skb, struct device *dev,
27,4 → 30,5
unsigned char *src, int length, int base);
extern struct device * init_etherdev(struct device *, int);
 
__END_DECLS
#endif
/shark/tags/rel_0_5/drivers/linuxcom/include/linux/interrupt.h
2,7 → 2,10
#define __INTERRUPT__
 
#include <linux/compatib.h>
#include "ll/sys/cdefs.h"
 
__BEGIN_DECLS
 
#define NR_IRQS 128
 
int request_irq(unsigned int irq, void (*handler)(int, void *dev_id, struct pt_regs *), unsigned long flags, const char *device, void *dev_id);
13,4 → 16,5
 
void free_irq(unsigned int irq, void *d);
 
__END_DECLS
#endif
/shark/tags/rel_0_5/drivers/linuxcom/include/linux/compatib.h
1,5 → 1,8
#include <kernel/kern.h>
#include "ll/sys/cdefs.h"
 
__BEGIN_DECLS
 
#ifndef __UNIXCOMP__
#define __UNIXCOMP__
 
56,7 → 59,7
 
/* Linux kernel call emulation */
#define kmalloc(a,b) malloc(a)
#define printk cprintf
//#define printk cprintf I would like to use the kernel printk if possible...
#define check_region(a,b) 0
#define request_region(a,b,c)
 
134,4 → 137,5
/* *** from linux-2.2.17/include/linux/byteorder/generic.h */
#define le16_to_cpu __le16_to_cpu
 
__END_DECLS
#endif
/shark/tags/rel_0_5/drivers/linuxcom/include/linux/skbuff.h
2,7 → 2,10
#define __SKBUFF__
 
#include <linux/compatib.h>
#include "ll/sys/cdefs.h"
 
__BEGIN_DECLS
 
#define HAVE_ALLOC_SKB /* For the drivers to know */
#define HAVE_ALIGNABLE_SKB /* Ditto 8) */
 
128,5 → 131,5
extern void skb_queue_head_init(struct sk_buff_head *list);
extern struct sk_buff * skb_clone(struct sk_buff *skb, int priority);
extern void skb_reserve(struct sk_buff *skb, int len);
 
__END_DECLS
#endif
/shark/tags/rel_0_5/drivers/linuxcom/include/linux/timer.h
20,11 → 20,11
 
/**
------------
CVS : $Id: timer.h,v 1.1.1.1 2002-03-29 14:12:49 pj Exp $
CVS : $Id: timer.h,v 1.2 2003-03-13 13:48:05 pj Exp $
 
File: $File$
Revision: $Revision: 1.1.1.1 $
Last update: $Date: 2002-03-29 14:12:49 $
Revision: $Revision: 1.2 $
Last update: $Date: 2003-03-13 13:48:05 $
------------
**/
 
51,7 → 51,10
 
#include <kernel/kern.h>
#include <linux/compatib.h>
#include "ll/sys/cdefs.h"
 
__BEGIN_DECLS
 
/*
* This is completely separate from the above, and is the
* "new and improved" way of handling timers more dynamically.
83,5 → 86,5
 
int add_timer(struct timer_list *timer);
void del_timer(struct timer_list *timer);
 
__END_DECLS
#endif
/shark/tags/rel_0_5/drivers/linuxcom/include/linux/socket.h
1,6 → 1,10
#ifndef _LINUX_SOCKET_H
#define _LINUX_SOCKET_H
 
#include "ll/sys/cdefs.h"
 
__BEGIN_DECLS
 
struct sockaddr
{
unsigned short sa_family; /* address family, AF_xxx */
135,4 → 139,6
extern int move_addr_to_user(void *kaddr, int klen, void *uaddr, int *ulen);
extern int move_addr_to_kernel(void *uaddr, int ulen, void *kaddr);
#endif
 
__END_DECLS
#endif /* _LINUX_SOCKET_H */
/shark/tags/rel_0_5/drivers/linuxcom/include/asm/bitops.h
2,7 → 2,10
#define __BITOPS__
 
#include <linux/compatib.h>
#include "ll/sys/cdefs.h"
 
__BEGIN_DECLS
 
#define LOCK_PREFIX ""
#define SMPVOL
 
40,4 → 43,5
return ((1UL << (nr & 31)) & (((const unsigned int *) addr)[nr >> 5])) != 0;
}
 
__END_DECLS
#endif
/shark/tags/rel_0_5/drivers/linuxcom/include/asm/io.h
2,7 → 2,10
#define __IO__
 
#include <linux/compatib.h>
#include "ll/sys/cdefs.h"
 
__BEGIN_DECLS
 
/*
* Thanks to James van Artsdalen for a better timing-fix than
* the two short jumps: using outb's to a nonexistent port seems
71,5 → 74,5
#define writew(b,addr) (*(volatile unsigned short *) __io_virt(addr) = (b))
#define writel(b,addr) (*(volatile unsigned int *) __io_virt(addr) = (b))
 
 
__END_DECLS
#endif
/shark/tags/rel_0_5/drivers/linuxcom/include/net/sock.h
20,11 → 20,11
 
/**
------------
CVS : $Id: sock.h,v 1.1.1.1 2002-03-29 14:12:49 pj Exp $
CVS : $Id: sock.h,v 1.2 2003-03-13 13:48:05 pj Exp $
 
File: $File$
Revision: $Revision: 1.1.1.1 $
Last update: $Date: 2002-03-29 14:12:49 $
Revision: $Revision: 1.2 $
Last update: $Date: 2003-03-13 13:48:05 $
------------
**/
 
56,8 → 56,11
#include <linux/netdevice.h>
#include <linux/skbuff.h> /* struct sk_buff */
 
#include "ll/sys/cdefs.h"
 
__BEGIN_DECLS
 
 
/*
* This structure really needs to be cleaned up.
* Most of it is for TCP, and not used by any of
239,4 → 242,6
};
 
__END_DECLS
 
#endif
/shark/tags/rel_0_5/drivers/linuxcom/auto_irq.c
1,5 → 1,6
#include<asm/bitops.h>
#include<kernel/kern.h>
#include <time.h>
 
struct device *irq2dev_map[16] = {0, 0, /* ... zeroed */};
 
17,6 → 18,7
int autoirq_setup(int waittime)
{
int i;
struct timespec delay;
 
handled = 0;
 
27,7 → 29,9
}
 
/* Hang out at least <waittime> jiffies waiting for bogus IRQ hits. */
task_delay(waittime);
delay.tv_sec = waittime/1000000;
delay.tv_nsec = (waittime%1000000)*1000;
nanosleep(&delay, NULL);
 
return handled;
}
34,10 → 38,13
 
int autoirq_report(int waittime)
{
struct timespec delay;
int i;
 
/* Hang out at least <waittime> jiffies waiting for the IRQ. */
task_delay(waittime);
delay.tv_sec=waittime/1000000;
delay.tv_nsec=(waittime%1000000)*1000;
nanosleep(&delay, NULL);
 
/* Retract the irq handlers that we installed. */
for (i = 0; i < 16; i++) {
/shark/tags/rel_0_5/drivers/linuxcom/makefile
3,6 → 3,7
ifndef BASE
BASE=../..
endif
 
include $(BASE)/config/config.mk
 
LIBRARY = comp
/shark/tags/rel_0_5/drivers/svga/vgaregs.h
0,0 → 1,124
#include "ll/sys/cdefs.h"
 
__BEGIN_DECLS
 
 
/* Register indices into mode state array. */
 
#define VGA_CRTC_COUNT 24
#define VGA_ATC_COUNT 21
#define VGA_GRAPHICS_COUNT 9
#define VGA_SEQUENCER_COUNT 5
 
#define VGA_CRTC_OFFSET 0 /* 24 registers */
#define VGA_ATC_OFFSET 24 /* 21 registers */
#define VGA_GRAPHICS_OFFSET 45 /* 9 registers. */
#define VGA_SEQUENCER_OFFSET 54 /* 5 registers. */
#define VGA_MISCOUTPUT 59 /* (single register) */
#define VGA_TOTAL_REGS 60
 
/* Total of 60 registers. */
 
#define VGAREG_CR(i) (i)
#define VGAREG_AR(i) (i + VGA_ATC_OFFSET)
#define VGAREG_GR(i) (i + VGA_GRAPHICS_OFFSET)
#define VGAREG_SR(i) (i + VGA_SEQUENCER_OFFSET)
 
#define VGA_CR0 VGAREG_CR(0x00)
#define VGA_CR1 VGAREG_CR(0x01)
#define VGA_CR2 VGAREG_CR(0x02)
#define VGA_CR3 VGAREG_CR(0x03)
#define VGA_CR4 VGAREG_CR(0x04)
#define VGA_CR5 VGAREG_CR(0x05)
#define VGA_CR6 VGAREG_CR(0x06)
#define VGA_CR7 VGAREG_CR(0x07)
#define VGA_CR8 VGAREG_CR(0x08)
#define VGA_CR9 VGAREG_CR(0x09)
#define VGA_CRA VGAREG_CR(0x0A)
#define VGA_CRB VGAREG_CR(0x0B)
#define VGA_CRC VGAREG_CR(0x0C)
#define VGA_CRD VGAREG_CR(0x0D)
#define VGA_CRE VGAREG_CR(0x0E)
#define VGA_CRF VGAREG_CR(0x0F)
#define VGA_CR10 VGAREG_CR(0x10)
#define VGA_CR11 VGAREG_CR(0x11)
#define VGA_CR12 VGAREG_CR(0x12)
#define VGA_CR13 VGAREG_CR(0x13)
#define VGA_SCANLINEOFFSET VGAREG_CR(0x13)
#define VGA_CR14 VGAREG_CR(0x14)
#define VGA_CR15 VGAREG_CR(0x15)
#define VGA_CR16 VGAREG_CR(0x16)
#define VGA_CR17 VGAREG_CR(0x17)
#define VGA_CR18 VGAREG_CR(0x18)
 
#define VGA_AR0 VGAREG_AR(0x00)
#define VGA_AR10 VGAREG_AR(0x10)
#define VGA_AR11 VGAREG_AR(0x11)
#define VGA_AR12 VGAREG_AR(0x12)
#define VGA_AR13 VGAREG_AR(0x13)
#define VGA_AR14 VGAREG_AR(0x14)
 
#define VGA_GR0 VGAREG_GR(0x00)
#define VGA_GR1 VGAREG_GR(0x01)
#define VGA_GR2 VGAREG_GR(0x02)
#define VGA_GR3 VGAREG_GR(0x03)
#define VGA_GR4 VGAREG_GR(0x04)
#define VGA_GR5 VGAREG_GR(0x05)
#define VGA_GR6 VGAREG_GR(0x06)
#define VGA_GR7 VGAREG_GR(0x07)
#define VGA_GR8 VGAREG_GR(0x08)
 
#define VGA_SR0 VGAREG_SR(0x00)
#define VGA_SR1 VGAREG_SR(0x01)
#define VGA_SR2 VGAREG_SR(0x02)
#define VGA_SR3 VGAREG_SR(0x03)
#define VGA_SR4 VGAREG_SR(0x04)
 
 
/*
* Set the bits bytemask in variable bytevar with the value of bits
* valuemask in value (masks must match, but may be shifted relative
* to eachother). With proper masks, should optimize into shifts.
*/
 
#define SETBITSFROMVALUE(bytevar, bytemask, value, valuemask) \
if (valuemask > bytemask) \
bytevar = (bytevar & (~(unsigned char)bytemask)) \
| (((value) & valuemask) / (valuemask / bytemask)); \
else \
bytevar = (bytevar & (~(unsigned char)bytemask)) \
| (((value) & valuemask) * (bytemask / valuemask));
 
/*
* Set bits bytemask in bytevar, with value bits (no shifting).
*/
 
#define SETBITS(bytevar, bytemask, bits) \
bytevar = (bytevar & (~(unsigned char)bytemask)) + bits;
 
#ifdef min
#undef min
#endif
#define min(x, y) ((x) < (y) ? (x) : (y))
#define LIMIT(var, lim) if (var > lim) var = lim;
 
 
/* Prototypes of functions defined in vgaregs.c. */
 
void __svgalib_setup_VGA_registers(
unsigned char *moderegs,
ModeTiming * modetiming,
ModeInfo * modeinfo
);
 
#define __svgalib_inGR __svgalib_ingra
#define __svgalib_outGR __svgalib_outgra
#define __svgalib_outbGR __svgalib_outgra
#define __svgalib_inSR __svgalib_inseq
#define __svgalib_outSR __svgalib_outseq
#define __svgalib_outbSR __svgalib_outseq
#define __svgalib_inCR __svgalib_incrtc
#define __svgalib_outCR __svgalib_outcrtc
#define __svgalib_outbCR __svgalib_outcrtc
 
__END_DECLS
/shark/tags/rel_0_5/drivers/svga/savage.c
0,0 → 1,1304
/*
Savage chipset driver
 
Written by Matan Ziv-Av (matan@svgalib.org)
 
Based on XFree 3.3.6 driver by S. Marineau and Tim Roberts.
And XFree 4.1.0 driver by Kevin Brosius.
 
*/
 
#include <stdlib.h>
//#include <stdio.h>
#include <string.h>
#include <unistd.h>
//#include <sys/mman.h>
#include "vga.h"
#include "libvga.h"
#include "driver.h"
#include "timing.h"
#include "vgaregs.h"
#include "interface.h"
#include "vgapci.h"
#include "endianess.h"
#include "vgammvgaio.h"
 
#define SAVAGEREG_SAVE(i) (VGA_TOTAL_REGS+i)
#define TOTAL_REGS (VGA_TOTAL_REGS + 64)
 
typedef struct {
 
unsigned char SR08, SR0A, SR0E, SR0F, SR10, SR11, SR12, SR13;
unsigned char SR15, SR18, SR1B, SR29, SR30;
unsigned char SR54, SR55, SR56, SR57;
unsigned char Clock;
// unsigned char s3DacRegs[0x101];
unsigned char CR31, CR33, CR34, CR36, CR3A, CR3B, CR3C;
unsigned char CR40, CR41, CR42, CR43, CR45;
unsigned char CR50, CR51, CR53, CR54, CR55, CR58, CR5B, CR5D, CR5E;
unsigned char CR63, CR65, CR66, CR67, CR68, CR69, CR6D, CR6F; /* Video attrib. */
unsigned char CR7B, CR7D;
unsigned char CR85, CR86, CR87, CR88;
unsigned char CR90, CR91, CR92, CR93, CRB0;
} vgaS3VRec, *vgaS3VPtr;
 
static int savage_init(int, int, int);
static void unlock(void);
static void lock(void);
static int savage_linear(int op, int param);
 
enum { UNKNOWN, TRIO64, TRIO3D, TRIO3D2X,
VIRGE, VIRGEVX, VIRGEDX, VIRGEGX2, VIRGEMX,
SAVAGE3D, SAVAGEMX, SAVAGE4, SAVAGEPRO, SAVAGE2000 };
 
static int memory, chipset;
static int is_linear, linear_base;
 
static CardSpecs *cardspecs;
 
static void savage_setpage(int page)
{
__svgalib_outcrtc(0x6a, page);
}
 
static int inlinearmode(void)
{
return is_linear;
}
 
/* Fill in chipset specific mode information */
 
static void savage_getmodeinfo(int mode, vga_modeinfo *modeinfo)
{
 
if(modeinfo->colors==16)return;
 
modeinfo->maxpixels = memory*1024/modeinfo->bytesperpixel;
modeinfo->maxlogicalwidth = 4088;
modeinfo->startaddressrange = memory * 1024 - 1;
modeinfo->haveblit = 0;
modeinfo->flags &= ~HAVE_RWPAGE;
 
if (modeinfo->bytesperpixel >= 1) {
if(linear_base)modeinfo->flags |= CAPABLE_LINEAR;
if (inlinearmode())
modeinfo->flags |= IS_LINEAR | LINEAR_MODE;
}
}
 
/* Read and save chipset-specific registers */
 
static int savage_saveregs(unsigned char regs[])
{
unsigned char cr3a, cr66;
vgaS3VPtr save = (vgaS3VPtr)(regs+VGA_TOTAL_REGS);
 
unlock();
 
cr66 = __svgalib_incrtc(0x66);
__svgalib_outcrtc(0x66, cr66 | 0x80);
cr3a = __svgalib_incrtc(0x3a);
__svgalib_outcrtc(0x3a, cr3a | 0x80);
 
cr66 = __svgalib_incrtc(0x66);
__svgalib_outcrtc(0x66, cr66 | 0x80);
cr3a = __svgalib_incrtc(0x3a);
__svgalib_outcrtc(0x3a, cr3a | 0x80);
 
#if 0
save = (vgaS3VPtr)vgaHWSave((vgaHWPtr)save, sizeof(vgaS3VRec));
#endif
 
__svgalib_outcrtc(0x66, cr66);
__svgalib_outcrtc(0x3a, cr3a);
__svgalib_outcrtc(0x66, cr66);
__svgalib_outcrtc(0x3a, cr3a);
 
/* First unlock extended sequencer regs */
save->SR08 = __svgalib_inseq(0x08);
__svgalib_outseq(0x08, 0x06);
 
/* Now we save all the s3 extended regs we need */
save->CR31 = __svgalib_incrtc(0x31);
save->CR34 = __svgalib_incrtc(0x34);
save->CR36 = __svgalib_incrtc(0x36);
save->CR3A = __svgalib_incrtc(0x3a);
 
if(chipset>TRIO3D)
save->CR40 = __svgalib_incrtc(0x40);
 
if(chipset==VIRGEMX)
save->CR41 = __svgalib_incrtc(0x41);
 
save->CR42 = __svgalib_incrtc(0x42);
save->CR45 = __svgalib_incrtc(0x45);
 
if(chipset>=SAVAGE3D)
save->CR50 = __svgalib_incrtc(0x50);
 
save->CR51 = __svgalib_incrtc(0x51);
save->CR53 = __svgalib_incrtc(0x53);
 
if(chipset<SAVAGE3D){
save->CR54 = __svgalib_incrtc(0x54);
save->CR55 = __svgalib_incrtc(0x55);
}
 
save->CR58 = __svgalib_incrtc(0x58);
 
if(chipset<SAVAGE3D)
save->CR63 = __svgalib_incrtc(0x63);
 
save->CR66 = __svgalib_incrtc(0x66);
save->CR67 = __svgalib_incrtc(0x67);
save->CR68 = __svgalib_incrtc(0x68);
save->CR69 = __svgalib_incrtc(0x69);
 
if(chipset>=SAVAGE3D)
save->CR6F = __svgalib_incrtc(0x6f);
 
save->CR33 = __svgalib_incrtc(0x33);
 
if((chipset==TRIO3D2X)||(chipset==VIRGEGX2)||(chipset==VIRGEMX))
save->CR85 = __svgalib_incrtc(0x85);
 
if((chipset==VIRGEDX)||(chipset>=SAVAGE3D))
save->CR86 = __svgalib_incrtc(0x86);
if((chipset==TRIO3D2X)||(chipset==VIRGEGX2)||(chipset==VIRGEMX)) {
save->CR7B = __svgalib_incrtc(0x7b);
save->CR7D = __svgalib_incrtc(0x7d);
save->CR87 = __svgalib_incrtc(0x87);
save->CR92 = __svgalib_incrtc(0x92);
save->CR93 = __svgalib_incrtc(0x93);
}
 
if((chipset==TRIO3D2X)||(chipset==VIRGEDX)||(chipset==VIRGEGX2)||
(chipset==VIRGEMX)) {
save->CR90 = __svgalib_incrtc(0x90);
save->CR91 = __svgalib_incrtc(0x91);
}
if(chipset>=SAVAGE3D) {
save->CR88 = __svgalib_incrtc(0x88);
save->CR90 = __svgalib_incrtc(0x90);
save->CR91 = __svgalib_incrtc(0x91);
save->CRB0 = __svgalib_incrtc(0xb0) | 0x80;
}
save->CR3B = __svgalib_incrtc(0x3b);
save->CR3C = __svgalib_incrtc(0x3c);
save->CR43 = __svgalib_incrtc(0x43);
save->CR5D = __svgalib_incrtc(0x5d);
save->CR5E = __svgalib_incrtc(0x5e);
save->CR65 = __svgalib_incrtc(0x65);
 
if(chipset<SAVAGE3D)
save->CR6D = __svgalib_incrtc(0x6d);
 
/* Save sequencer extended regs for DCLK PLL programming */
save->SR0E = __svgalib_inseq(0x0E);
save->SR10 = __svgalib_inseq(0x10);
save->SR11 = __svgalib_inseq(0x11);
save->SR12 = __svgalib_inseq(0x12);
save->SR13 = __svgalib_inseq(0x13);
 
if(chipset>=SAVAGE3D)
save->SR29 = __svgalib_inseq(0x29);
 
if((chipset==TRIO3D2X)||(chipset==VIRGEGX2)||(chipset==VIRGEMX)) {
save->SR29 = __svgalib_inseq(0x29);
save->SR54 = __svgalib_inseq(0x54);
save->SR55 = __svgalib_inseq(0x55);
save->SR56 = __svgalib_inseq(0x56);
save->SR57 = __svgalib_inseq(0x57);
}
save->SR15 = __svgalib_inseq(0x15);
 
if(chipset>=SAVAGE3D)
save->SR30 = __svgalib_inseq(0x30);
 
save->SR18 = __svgalib_inseq(0x18);
 
if(chipset>=SAVAGE3D)
save->SR1B = __svgalib_inseq(0x1B);
 
if(chipset<=TRIO3D) {
save->SR0A = __svgalib_inseq(0x0a);
save->SR0F = __svgalib_inseq(0x0f);
}
 
__svgalib_outcrtc(0x3a, cr3a);
__svgalib_outcrtc(0x66, cr66);
 
return TOTAL_REGS - VGA_TOTAL_REGS;
}
 
/* Set chipset-specific registers */
 
static void savage_setregs(const unsigned char regs[], int mode)
{
int tmp;
vgaS3VPtr restore = (vgaS3VPtr)(regs+VGA_TOTAL_REGS);
unlock();
 
#if 0
/* Are we going to reenable STREAMS in this new mode? */
s3vPriv.STREAMSRunning = restore->CR67 & 0x0c;
 
/* First reset GE to make sure nothing is going on */
outb(vgaCRIndex, 0x66);
if(port_in(vgaCRReg) & 0x01) S3SAVGEReset(0,__LINE__,__FILE__);
#endif
/* As per databook, always disable STREAMS before changing modes */
__svgalib_outcrtc(0x67, __svgalib_incrtc(0x67)&0xf3);
 
if(chipset<SAVAGE3D)
__svgalib_outcrtc(0x63, restore->CR63);
 
__svgalib_outcrtc(0x66, restore->CR66);
__svgalib_outcrtc(0x3a, restore->CR3A);
__svgalib_outcrtc(0x31, restore->CR31);
__svgalib_outcrtc(0x58, restore->CR58);
if(chipset<SAVAGE3D)
__svgalib_outcrtc(0x55, restore->CR55);
#if 0 /* why is it done twice? */
__svgalib_outseq(0x08, 0x06);
__svgalib_outseq(0x12, restore->SR12);
__svgalib_outseq(0x13, restore->SR13);
__svgalib_outseq(0x29, restore->SR29);
__svgalib_outseq(0x15, restore->SR15);
#endif
 
__svgalib_outcrtc(0x53, restore->CR53);
__svgalib_outcrtc(0x5d, restore->CR5D);
__svgalib_outcrtc(0x5e, restore->CR5E);
__svgalib_outcrtc(0x3b, restore->CR3B);
__svgalib_outcrtc(0x3c, restore->CR3C);
__svgalib_outcrtc(0x43, restore->CR43);
__svgalib_outcrtc(0x65, restore->CR65);
 
if(chipset<SAVAGE3D)
__svgalib_outcrtc(0x6d, restore->CR6D);
 
/* Restore the desired video mode with CR67 */
 
if(chipset<SAVAGE3D)
__svgalib_outcrtc(0x67, 0x50 | (__svgalib_incrtc(0x67)&0x0f));
else
__svgalib_outcrtc(0x67, 0x50 | (__svgalib_incrtc(0x67)&0xf3));
sleep(1);
__svgalib_outcrtc(0x67, restore->CR67&0xf3);
__svgalib_outcrtc(0x34, restore->CR34);
 
if(chipset>TRIO3D)
__svgalib_outcrtc(0x40, restore->CR40);
 
if(chipset==VIRGEMX)
__svgalib_outcrtc(0x41, restore->CR41);
 
__svgalib_outcrtc(0x42, restore->CR42);
__svgalib_outcrtc(0x45, restore->CR45);
 
if(chipset>=SAVAGE3D)
__svgalib_outcrtc(0x50, restore->CR50);
 
__svgalib_outcrtc(0x51, restore->CR51);
 
if(chipset<SAVAGE3D)
__svgalib_outcrtc(0x54, restore->CR54);
 
__svgalib_outcrtc(0x36, restore->CR36);
__svgalib_outcrtc(0x68, restore->CR68);
__svgalib_outcrtc(0x69, restore->CR69);
 
if(chipset>=SAVAGE3D)
__svgalib_outcrtc(0x6f, restore->CR6F);
 
__svgalib_outcrtc(0x33, restore->CR33);
 
if(chipset>=SAVAGE3D) {
__svgalib_outcrtc(0x86, restore->CR86);
__svgalib_outcrtc(0x88, restore->CR88);
__svgalib_outcrtc(0x90, restore->CR90);
__svgalib_outcrtc(0x91, restore->CR91);
__svgalib_outcrtc(0xb0, restore->CRB0);
}
 
if((chipset==TRIO3D2X)||(chipset==VIRGEGX2)||(chipset==VIRGEMX))
__svgalib_outcrtc(0x85, restore->CR85);
 
if(chipset==VIRGEDX)
__svgalib_outcrtc(0x86, restore->CR86);
 
if(chipset==VIRGEGX2) {
__svgalib_outcrtc(0x7b, restore->CR7B);
__svgalib_outcrtc(0x7d, restore->CR7D);
__svgalib_outcrtc(0x87, restore->CR87);
__svgalib_outcrtc(0x92, restore->CR92);
__svgalib_outcrtc(0x93, restore->CR93);
}
 
if((chipset==TRIO3D2X)||(chipset==VIRGEDX)||(chipset==VIRGEGX2)||(chipset==VIRGEMX)) {
__svgalib_outcrtc(0x90, restore->CR90);
__svgalib_outcrtc(0x91, restore->CR91);
}
 
__svgalib_outseq(0x08, 0x06);
/* Restore extended sequencer regs for MCLK. SR10 == 255 indicates that
* we should leave the default SR10 and SR11 values there.
*/
 
if (restore->SR10 != 255) {
__svgalib_outseq(0x10, restore->SR10);
__svgalib_outseq(0x11, restore->SR11);
}
 
/* Restore extended sequencer regs for DCLK */
 
__svgalib_outseq(0x12, restore->SR12);
__svgalib_outseq(0x13, restore->SR13);
 
if(chipset>=SAVAGE3D)
__svgalib_outseq(0x29, restore->SR29);
 
if((chipset==TRIO3D2X)||(chipset==VIRGEGX2)||(chipset==VIRGEMX)) {
__svgalib_outseq(0x29, restore->SR29);
__svgalib_outseq(0x54, restore->SR54);
__svgalib_outseq(0x55, restore->SR55);
__svgalib_outseq(0x56, restore->SR56);
__svgalib_outseq(0x57, restore->SR57);
}
 
__svgalib_outseq(0x18, restore->SR18);
 
if(chipset>=SAVAGE3D)
__svgalib_outseq(0x1B, restore->SR1B);
 
tmp = __svgalib_inseq(0x15) & ~0x21;
__svgalib_outseq(0x15, tmp | 0x03);
__svgalib_outseq(0x15, tmp | 0x23);
__svgalib_outseq(0x15, tmp | 0x03);
__svgalib_outseq(0x15, restore->SR15);
sleep(1);
if(chipset<=TRIO3D) {
__svgalib_outseq(0x0a, restore->SR0A);
__svgalib_outseq(0x0f, restore->SR0F);
} else if (chipset >= SAVAGE3D) {
__svgalib_outseq(0x30, restore->SR30);
}
 
__svgalib_outseq(0x08, restore->SR08);
 
 
/* Now write out CR67 in full, possibly starting STREAMS */
__svgalib_outcrtc(0x67, 0x50);
sleep(1);
__svgalib_outcrtc(0x67, restore->CR67&0xf3);
 
__svgalib_outcrtc(0x53, restore->CR53);
__svgalib_outcrtc(0x66, restore->CR66);
__svgalib_outcrtc(0x3a, restore->CR3A);
}
 
 
/* Return nonzero if mode is available */
 
static int savage_modeavailable(int mode)
{
struct info *info;
ModeTiming *modetiming;
ModeInfo *modeinfo;
 
if (IS_IN_STANDARD_VGA_DRIVER(mode))
return __svgalib_vga_driverspecs.modeavailable(mode);
 
info = &__svgalib_infotable[mode];
if (memory * 1024 < info->ydim * info->xbytes)
return 0;
 
modeinfo = __svgalib_createModeInfoStructureForSvgalibMode(mode);
 
if(modeinfo->bytesPerPixel==3) return 0;
 
modetiming = malloc(sizeof(ModeTiming));
 
if (__svgalib_getmodetiming(modetiming, modeinfo, cardspecs)) {
free(modetiming);
free(modeinfo);
return 0;
}
 
free(modetiming);
free(modeinfo);
return SVGADRV;
}
 
/* Local, called by setmode(). */
#define BASE_FREQ 14.31818
 
static void savageCalcClock(long freq, int min_m, int min_n1, int max_n1, int min_n2, int max_n2,
long freq_min, long freq_max, unsigned int *mdiv, unsigned int *ndiv, unsigned int *r)
{
double ffreq, ffreq_min, ffreq_max;
double div, diff, best_diff;
unsigned int m;
unsigned char n1, n2;
unsigned char best_n1=16+2, best_n2=2, best_m=125+2;
 
ffreq = freq / 1000.0 / BASE_FREQ;
ffreq_min = freq_min / 1000.0 / BASE_FREQ;
ffreq_max = freq_max / 1000.0 / BASE_FREQ;
 
if (ffreq < ffreq_min / (1<<max_n2)) {
ffreq = ffreq_min / (1<<max_n2);
}
if (ffreq > ffreq_max / (1<<min_n2)) {
ffreq = ffreq_max / (1<<min_n2);
}
 
/* work out suitable timings */
 
best_diff = ffreq;
for (n2=min_n2; n2<=max_n2; n2++) {
for (n1 = min_n1+2; n1 <= max_n1+2; n1++) {
m = (int)(ffreq * n1 * (1<<n2) + 0.5) ;
if (m < min_m+2 || m > 127+2)
continue;
div = (double)(m) / (double)(n1);
if ((div >= ffreq_min) &&
(div <= ffreq_max)) {
diff = ffreq - div / (1<<n2);
if (diff < 0.0)
diff = -diff;
if (diff < best_diff) {
best_diff = diff;
best_m = m;
best_n1 = n1;
best_n2 = n2;
}
}
}
}
*ndiv = best_n1 - 2;
*r = best_n2;
*mdiv = best_m - 2;
}
 
 
static void savage_initializemode(unsigned char *moderegs,
ModeTiming * modetiming, ModeInfo * modeinfo, int mode)
{
#ifdef NL
#undef NL
#endif
#define NL (1<<30)
int i, j, dclk, width, tmp;
int clocklimits[14][2]={
{},
{86000,0}, /* Trio 64 - Guess */
{115000,115000}, /* Trio 3D */
{NL,0}, /* Trio 3D2X */
{80000,0}, /* Virge */
{110000,110000}, /* Virge VX */
{80000,0}, /* Virge DX */
{NL,0}, /* Virge GX2 */
{NL,0}, /* Virge MX */
{NL,NL}, /* Savage 3D */
{0,0}, /* Savage MX */
{NL,NL}, /* Savage 4 */
{NL,NL}, /* Savage Pro */
{230000,230000}, /* Savage 2000 */
};
int cargs[14][4]= {
{},
{31, 0, 3, 86000}, /* Trio 64 - Guess */
{31, 0, 4, 230000},
{31, 0, 4, 170000},
{31, 0, 3, 135000},
{31, 0, 4, 220000},
{31, 0, 3, 135000},
{31, 0, 4, 170000},
{31, 0, 4, 170000},
{127, 0, 4, 180000},
{127, 0, 4, 180000},
{127, 0, 4, 180000},
{127, 0, 4, 180000},
{127, 0, 4, 180000},
};
#undef NL
vgaS3VPtr new = (vgaS3VPtr)(moderegs+VGA_TOTAL_REGS);
if(modeinfo->bitsPerPixel==16) {
if((chipset==VIRGE)|| (chipset==TRIO64)) {
modetiming->HDisplay *=2;
modetiming->HSyncStart *=2;
modetiming->HSyncEnd *=2;
modetiming->HTotal *=2;
modetiming->CrtcHDisplay =modetiming->HDisplay;
modetiming->CrtcHSyncStart =modetiming->HSyncStart;
modetiming->CrtcHSyncEnd =modetiming->HSyncEnd;
modetiming->CrtcHTotal =modetiming->HTotal;
}
}
 
__svgalib_setup_VGA_registers(moderegs, modetiming, modeinfo);
 
tmp = __svgalib_incrtc(0x3a);
if((chipset==TRIO3D2X)||(chipset==VIRGEGX2)||(chipset==VIRGEMX)) {
if(0) new->CR3A = tmp | 0x90; /* ENH 256, no PCI burst! */
else new->CR3A = (tmp & 0x38) | 0x10; /* ENH 256, PCI burst */
} else {
if(0) new->CR3A = tmp | 0x95; /* ENH 256, no PCI burst! */
else new->CR3A = (tmp & 0x7f) | 0x15; /* ENH 256, PCI burst */
}
 
new->CR53 |= 0x08; /* Disables MMIO */
new->CR31 = 0x09; /* Enable 64k window */
 
if(chipset==VIRGEVX) {
new->CR66 = 0x90;
new->CR63 = 0x09;
new->CR58 = 0x40;
} else {
if((chipset==TRIO3D2X)||(chipset==VIRGEGX2)||(chipset==VIRGEMX)) {
new->CR63 = 0x08;
} else {
new->CR63 = 0x00;
}
new->CR66 = 0x89;
new->CR58 = 0;
}
/* Now do clock PLL programming. Use the s3gendac function to get m,n */
/* Also determine if we need doubling etc. */
 
dclk = modetiming->pixelClock;
new->CR67 = 0x00; /* Defaults */
if(chipset > TRIO3D) {
new->SR15 = 0x03 | 0x80;
if(chipset==VIRGE)
new->SR15 = (__svgalib_inseq(0x15) & 0x80) | 3;
} else {
new->SR15 = (__svgalib_inseq(0x15) & 0x80) | 3;
new->SR0A = __svgalib_inseq(0x0a);
}
new->SR18 = 0x00;
new->CR43 = 0x00;
new->CR45 = 0x00;
new->CR65 = 0x00;
new->CR54 = 0x00;
if(chipset > TRIO3D)
new->CR40 = __svgalib_incrtc(0x40) & 0xfe ;
new->SR10 = 255; /* This is a reserved value, so we use as flag */
new->SR11 = 255;
 
new->SR1B = 0;
new->SR30 = __svgalib_inseq(0x30);
 
switch( modeinfo->colorBits ) {
case 8:
new->CR67 = 0x00; /* 8bpp, 1 pixel/clock */
if(dclk >= clocklimits[chipset][0]) new->CR67 |= 0x10;
break;
case 15:
new->CR67 = 0x20;
if(dclk >= clocklimits[chipset][1]) new->CR67 |= 0x10;
break;
case 16:
new->CR67 = 0x40;
if(dclk >= clocklimits[chipset][1]) new->CR67 |= 0x10;
break;
case 24:
new->CR67 = 0xd0;
break;
}
/* Now the special cases */
if(chipset==VIRGE) {
if(new->CR67 == 0x10) {
new->SR15 |= 0x10;
new->SR18 = 0x80;
}
}
{
unsigned int m, n, r;
 
savageCalcClock(dclk, 1, 1, cargs[chipset][0], cargs[chipset][1],
cargs[chipset][2], cargs[chipset][3], cargs[chipset][3]*2,
&m, &n, &r);
if(chipset < SAVAGE3D)
new->SR12 = (r << 5) | (n & 0x1F);
else new->SR12 = (r << 6) | (n & 0x3F);
new->SR13 = m & 0xFF;
new->SR29 = (r & 4) | (m & 0x100) >> 5 | (n & 0x40) >> 2;
}
 
 
/* If we have an interlace mode, set the interlace bit. Note that mode
* vertical timings are already adjusted by the standard VGA code
*/
if (modetiming->flags & INTERLACED) {
new->CR42 = 0x20; /* Set interlace mode */
} else {
new->CR42 = 0x00;
}
 
/* Set display fifo */
if((chipset==TRIO3D2X)||(chipset==VIRGEGX2)||(chipset==VIRGEMX)) {
new->CR34 = 0;
} else {
new->CR34 = 0x10;
}
 
/* Now we adjust registers for extended mode timings */
/* This is taken without change from the accel/s3_virge code */
 
i = ((((modetiming->CrtcHTotal >> 3) - 5) & 0x100) >> 8) |
((((modetiming->CrtcHDisplay >> 3) - 1) & 0x100) >> 7) |
((((modetiming->CrtcHSyncStart >> 3) - 1) & 0x100) >> 6) |
((modetiming->CrtcHSyncStart & 0x800) >> 7);
 
if ((modetiming->CrtcHSyncEnd >> 3) - (modetiming->CrtcHSyncStart >> 3) > 64)
i |= 0x08; /* add another 64 DCLKs to blank pulse width */
 
if ((modetiming->CrtcHSyncEnd >> 3) - (modetiming->CrtcHSyncStart >> 3) > 32)
i |= 0x20; /* add another 32 DCLKs to hsync pulse width */
 
j = ( moderegs[0] + ((i&0x01)<<8)
+ moderegs[4] + ((i&0x10)<<4) + 1) / 2;
 
if (j-(moderegs[4] + ((i&0x10)<<4)) < 4) {
if (moderegs[4] + ((i&0x10)<<4) + 4 <= moderegs[0]+ ((i&0x01)<<8))
j = moderegs[4] + ((i&0x10)<<4) + 4;
else
j = moderegs[0]+ ((i&0x01)<<8) + 1;
}
new->CR3B = j & 0xFF;
i |= (j & 0x100) >> 2;
new->CR3C = (moderegs[0] + ((i&0x01)<<8))/2;
 
new->CR5D = i;
 
new->CR5E = (((modetiming->CrtcVTotal - 2) & 0x400) >> 10) |
(((modetiming->CrtcVDisplay - 1) & 0x400) >> 9) |
(((modetiming->CrtcVSyncStart) & 0x400) >> 8) |
(((modetiming->CrtcVSyncStart) & 0x400) >> 6) | 0x40;
width = modeinfo->lineWidth >> 3;
moderegs[19] = 0xFF & width;
new->CR51 = (0x300 & width) >> 4; /* Extension bits */
/* And finally, select clock source 2 for programmable PLL */
moderegs[VGA_MISCOUTPUT] |= 0x0c;
 
if(chipset>=SAVAGE3D) {
/* Set frame buffer description */
if (modeinfo->colorBits <= 8) {
new->CR50 = 0;
} else {
if (modeinfo->colorBits <= 16) {
new->CR50 = 0x10;
} else {
new->CR50 = 0x30;
}
}
if (modeinfo->width == 640)
new->CR50 |= 0x40;
else if (modeinfo->width == 800)
new->CR50 |= 0x80;
else if (modeinfo->width == 1024);
else if (modeinfo->width == 1152)
new->CR50 |= 0x01;
else if (modeinfo->width == 1280)
new->CR50 |= 0x41;
else if (modeinfo->width == 2048 && new->CR31 & 2);
else if (modeinfo->width == 1600)
new->CR50 |= 0x81; /* TODO: need to consider bpp=4 */
else
new->CR50 |= 0xC1; /* default to use GlobalBD */
 
new->CR33 = 0x08;
new->CR6F = __svgalib_incrtc(0x6f);
new->CR86 = __svgalib_incrtc(0x86);
new->CR88 = __svgalib_incrtc(0x88);
new->CRB0 = __svgalib_incrtc(0xb0) | 0x80;
} else /* trio, virge */ {
new->CR33 = 0x20;
if((chipset==VIRGEDX)||(chipset<=TRIO3D)) {
new->CR86 = 0x80;
}
 
if((chipset!=VIRGEVX)&&(chipset!=VIRGE)) {
new->CR91 = (modeinfo->lineWidth+7) >> 3;
new->CR90 = 0x80 | ((modeinfo->lineWidth+7) >> 11);
}
 
if(chipset == VIRGEVX) {
if(modeinfo->colorBits>16) new->CR6D = 0x51 ; else new->CR6D=0;
} else {
new->CR6D = __svgalib_incrtc(0x6d);
new->CR65 &= ~0x38;
switch(modeinfo->colorBits) {
case 8:
break;
case 15:
case 16:
new->CR65 |= 2<<3;
break;
default:
new->CR65 |= 4<<3;
break;
}
}
 
if(chipset == VIRGEMX) {
new->SR54=0x10;
new->SR55=0x80;
new->SR56=0x10;
new->SR57=0x80;
} else {
new->SR54=0x1f;
new->SR55=0x9f;
new->SR56=0x1f;
new->SR57=0x9f;
}
}
 
/* Now we handle various XConfig memory options and others */
 
new->CR36 = __svgalib_incrtc(0x36);
#if 0
if (mode->Private) {
new->CR67 &= ~1;
if(
(s3vPriv.chip != S3_SAVAGE2000) &&
(mode->Private[0] & (1 << S3_INVERT_VCLK)) &&
(mode->Private[S3_INVERT_VCLK])
)
new->CR67 |= 1;
 
if (mode->Private[0] & (1 << S3_BLANK_DELAY)) {
new->CR65 = (new->CR65 & ~0x38)
| (mode->Private[S3_BLANK_DELAY] & 0x07) << 3;
}
}
#endif
 
if(__svgalib_emulatepage || is_linear) new->CR58 |= 0x13;
new->CR68 = __svgalib_incrtc(0x68);
new->CR69 = 0;
 
return ;
}
 
 
static int savage_setmode(int mode, int prv_mode)
{
unsigned char *moderegs;
ModeTiming *modetiming;
ModeInfo *modeinfo;
 
if (IS_IN_STANDARD_VGA_DRIVER(mode)) {
__svgalib_outcrtc(0x34, 0);
return __svgalib_vga_driverspecs.setmode(mode, prv_mode);
}
if (!savage_modeavailable(mode))
return 1;
 
modeinfo = __svgalib_createModeInfoStructureForSvgalibMode(mode);
 
modetiming = malloc(sizeof(ModeTiming));
if (__svgalib_getmodetiming(modetiming, modeinfo, cardspecs)) {
free(modetiming);
free(modeinfo);
return 1;
}
 
moderegs = malloc(TOTAL_REGS);
savage_initializemode(moderegs, modetiming, modeinfo, mode);
free(modetiming);
 
__svgalib_setregs(moderegs); /* Set standard regs. */
savage_setregs(moderegs, mode); /* Set extended regs. */
free(moderegs);
 
free(modeinfo);
 
return 0;
}
 
 
/* Unlock chipset-specific registers */
 
static void unlock(void)
{
__svgalib_outcrtc(0x11,__svgalib_incrtc(0x11)&0x7f);
__svgalib_outcrtc(0x38, 0x48);
__svgalib_outcrtc(0x39, 0xa5);
__svgalib_outcrtc(0x40,__svgalib_incrtc(0x40)&0xfe);
}
 
static void lock(void)
{
}
 
 
#define VENDOR_ID 0x5333
 
/* Indentify chipset, initialize and return non-zero if detected */
 
int savage_test(void)
{
int found;
int id;
unsigned long buf[64];
found=__svgalib_pci_find_vendor_vga(VENDOR_ID,buf,0);
id=(buf[0]>>16)&0xffff;
if(found)return 0;
switch(id) {
case 0x8811:
case 0x8903:
case 0x8904:
case 0x8a13:
case 0x5631:
case 0x883d:
case 0x8a01:
case 0x8a10:
case 0x8c00:
case 0x8c01:
case 0x8c02:
case 0x8c03:
case 0x8a20:
case 0x8a21:
case 0x8a22:
case 0x8a23:
case 0x8c10:
case 0x8c12:
case 0x9102:
case 0x8d03:
case 0x8d04:
savage_init(0,0,0);
return 1;
break;
default:
return 0;
}
}
 
 
/* Set display start address (not for 16 color modes) */
 
static void savage_setdisplaystart(int address)
{
address=address >> 2;
__svgalib_outcrtc(0x0d,address&0xff);
__svgalib_outcrtc(0x0c,(address>>8)&0xff);
__svgalib_outcrtc(0x69,(address>>16)&0xff);
}
 
/* Set logical scanline length (usually multiple of 8) */
/* Cirrus supports multiples of 8, up to 4088 */
 
static void savage_setlogicalwidth(int width)
{
int offset = width >> 3;
__svgalib_outcrtc(0x13,offset&0xff);
}
 
static int savage_linear(int op, int param)
{
if (op==LINEAR_ENABLE){
__svgalib_outcrtc(0x58,__svgalib_incrtc(0x58)|0x13);
is_linear=1;
return 0;
};
if (op==LINEAR_DISABLE) {
__svgalib_outcrtc(0x58,__svgalib_incrtc(0x58)&~0x13);
is_linear=0;
return 0;
};
if (op==LINEAR_QUERY_BASE) return linear_base;
if (op == LINEAR_QUERY_RANGE || op == LINEAR_QUERY_GRANULARITY) return 0; /* No granularity or range. */
else return -1; /* Unknown function. */
}
 
static int match_programmable_clock(int clock)
{
return clock ;
}
 
static int map_clock(int bpp, int clock)
{
return clock ;
}
 
static int map_horizontal_crtc(int bpp, int pixelclock, int htiming)
{
return htiming;
}
 
static struct {
unsigned char c8;
unsigned short c15;
unsigned short c16;
unsigned int c32;
} cursor_colors[16*2];
 
static int pal=1, palette[768];
 
static int findcolor(int rgb) {
int i,j,k,l=0;
 
if(pal)vga_getpalvec(0,256,palette);
pal=0;
k=0xffffff;
for(i=0;i<256;i++) {
j=((rgb&0xff)-(palette[i*3+2]<<2))*((rgb&0xff)-(palette[i*3+2]<<2))+
(((rgb>>8)&0xff)-(palette[i*3+1]<<2))*(((rgb>>8)&0xff)-(palette[i*3+1]<<2))+
(((rgb>>16)&0xff)-(palette[i*3]<<2))*(((rgb>>16)&0xff)-(palette[i*3]<<2));
if(j==0) {
return i;
}
if(j<k) {
k=j;
l=i;
}
}
return l;
}
 
static int savage_cursor( int cmd, int p1, int p2, int p3, int p4, void *p5) {
unsigned long *b3;
unsigned char *buf;
int i, j;
unsigned int l1, l2;
switch(cmd){
case CURSOR_INIT:
return 1;
case CURSOR_HIDE:
__svgalib_outcrtc(0x45,__svgalib_incrtc(0x45)&0xfe);
break;
case CURSOR_SHOW:
__svgalib_outcrtc(0x45,__svgalib_incrtc(0x45)|0x01); /* Windows */
break;
case CURSOR_POSITION:
__svgalib_outcrtc(0x46,p1>>8);
__svgalib_outcrtc(0x47,p1&0xff);
__svgalib_outcrtc(0x49,p2&0xff);
__svgalib_outcrtc(0x4e,0);
__svgalib_outcrtc(0x4f,0);
__svgalib_outcrtc(0x48,p2>>8);
break;
case CURSOR_SELECT:
i=memory-(16-p1);
switch(CI.colors) {
case 256:
__svgalib_incrtc(0x45);
__svgalib_outcrtc(0x4b,cursor_colors[p1*2].c8);
__svgalib_outcrtc(0x4b,cursor_colors[p1*2].c8);
__svgalib_incrtc(0x45);
__svgalib_outcrtc(0x4a,cursor_colors[p1*2+1].c8);
__svgalib_outcrtc(0x4a,cursor_colors[p1*2+1].c8);
break;
case 32768:
__svgalib_incrtc(0x45);
__svgalib_outcrtc(0x4b,cursor_colors[p1*2].c15&0xff);
__svgalib_outcrtc(0x4b,cursor_colors[p1*2].c15>>8);
__svgalib_outcrtc(0x4b,cursor_colors[p1*2].c15&0xff);
__svgalib_outcrtc(0x4b,cursor_colors[p1*2].c15>>8);
__svgalib_incrtc(0x45);
__svgalib_outcrtc(0x4a,cursor_colors[p1*2+1].c15&0xff);
__svgalib_outcrtc(0x4a,cursor_colors[p1*2+1].c15>>8);
__svgalib_outcrtc(0x4a,cursor_colors[p1*2+1].c15&0xff);
__svgalib_outcrtc(0x4a,cursor_colors[p1*2+1].c15>>8);
break;
case 65536:
__svgalib_incrtc(0x45);
__svgalib_outcrtc(0x4b,cursor_colors[p1*2].c16&0xff);
__svgalib_outcrtc(0x4b,cursor_colors[p1*2].c16>>8);
__svgalib_outcrtc(0x4b,cursor_colors[p1*2].c16&0xff);
__svgalib_outcrtc(0x4b,cursor_colors[p1*2].c16>>8);
__svgalib_incrtc(0x45);
__svgalib_outcrtc(0x4a,cursor_colors[p1*2+1].c16&0xff);
__svgalib_outcrtc(0x4a,cursor_colors[p1*2+1].c16>>8);
__svgalib_outcrtc(0x4a,cursor_colors[p1*2+1].c16&0xff);
__svgalib_outcrtc(0x4a,cursor_colors[p1*2+1].c16>>8);
break;
case (1<<24):
__svgalib_incrtc(0x45);
__svgalib_outcrtc(0x4b,cursor_colors[p1*2].c32&0xff);
__svgalib_outcrtc(0x4b,(cursor_colors[p1*2].c32>>8)&0xff);
__svgalib_outcrtc(0x4b,(cursor_colors[p1*2].c32>>16)&0xff);
__svgalib_incrtc(0x45);
__svgalib_outcrtc(0x4a,cursor_colors[p1*2+1].c32&0xff);
__svgalib_outcrtc(0x4a,(cursor_colors[p1*2+1].c32>>8)&0xff);
__svgalib_outcrtc(0x4a,(cursor_colors[p1*2+1].c32>>16)&0xff);
break;
}
__svgalib_outcrtc(0x4d, i&0xff);
__svgalib_outcrtc(0x4c, i>>8);
break;
case CURSOR_IMAGE:
buf=malloc(1024);
cursor_colors[p1*2].c8=findcolor(p3);
cursor_colors[p1*2].c32=p3;
cursor_colors[p1*2].c16=((p3&0xf80000)>>8)|((p3&0xfc00)>>5)|((p3&0xf8)>>3);
cursor_colors[p1*2].c15=((p3&0xf80000)>>9)|((p3&0xf800)>>5)|((p3&0xf8)>>3);
cursor_colors[p1*2+1].c8=findcolor(p4);
cursor_colors[p1*2+1].c32=p4;
cursor_colors[p1*2+1].c16=((p4&0xf80000)>>8)|((p4&0xfc00)>>5)|((p4&0xf8)>>3);
cursor_colors[p1*2+1].c15=((p4&0xf80000)>>9)|((p4&0xf800)>>5)|((p4&0xf8)>>3);
i=memory*1024-(16-p1)*1024;
b3=(unsigned long *)p5;
switch(p2) {
case 0:
for(j=0;j<32;j++) {
l2=*(b3+j);
l1=*(b3+32+j);
l1=BE32(l1);
l2=BE32(l2);
l2=l2&l1;
l1=~l1;
*(unsigned short *)(buf+16*j)=l1&0xffff;
*(unsigned short *)(buf+16*j+2)=l2&0xffff;
*(unsigned short *)(buf+16*j+4)=(l1>>16)&0xffff;
*(unsigned short *)(buf+16*j+6)=(l2>>16)&0xffff;
*(unsigned short *)(buf+16*j+8)=0xffff;
*(unsigned short *)(buf+16*j+10)=0;
*(unsigned short *)(buf+16*j+12)=0xffff;
*(unsigned short *)(buf+16*j+14)=0;
}
for(j=32;j<64;j++) {
*(unsigned short *)(buf+16*j)=0xffff;
*(unsigned short *)(buf+16*j+2)=0;
*(unsigned short *)(buf+16*j+4)=0xffff;
*(unsigned short *)(buf+16*j+6)=0;
*(unsigned short *)(buf+16*j+8)=0xffff;
*(unsigned short *)(buf+16*j+10)=0;
*(unsigned short *)(buf+16*j+12)=0xffff;
*(unsigned short *)(buf+16*j+14)=0;
}
break;
}
vga_drawscansegment(buf, i/CI.bytesperpixel,0,1024);
break;
}
return 0;
}
 
/* Function table (exported) */
DriverSpecs __svgalib_savage_driverspecs =
{
savage_saveregs,
savage_setregs,
unlock,
lock,
savage_test,
savage_init,
savage_setpage,
NULL,
NULL,
savage_setmode,
savage_modeavailable,
savage_setdisplaystart,
savage_setlogicalwidth,
savage_getmodeinfo,
0, /* old blit funcs */
0,
0,
0,
0,
0, /* ext_set */
0, /* accel */
savage_linear,
0, /* accelspecs, filled in during init. */
NULL, /* Emulation */
savage_cursor,
};
 
/* Initialize chipset (called after detection) */
static int savage_init(int force, int par1, int par2)
{
unsigned long buf[64];
unsigned long mmio_base;
int found=0, config1;
int mems[8]={2,4,8,12,16,32,64,2};
char *chipnames[] = {"Unknown", "Trio64", "Trio 3D", "Trio 3d/2X", "Virge", "Virge VX",
"Virge DX", "Virge GX2", "Virge MX",
"Savage3D", "SavageMX", "Savage4", "SavagePro", "Savage2000"};
int vmems[9][8]= { {0},
{0,0,0,1,0,0,1,0},
{4,0,4,0,2,0,0,0},
{4,0,4,0,0,0,2,0},
{4,0,0,0,2,0,1,0},
{2,4,6,8,2,4,6,8},
{4,0,0,0,2,0,1,0},
{0,0,4,4,0,0,2,2},
{0,0,4,4,0,0,2,2}
};
int id;
 
// unlock();
if (force) {
memory = par1;
chipset = par2;
} else {
 
};
 
found=__svgalib_pci_find_vendor_vga(VENDOR_ID,buf,0);
if (found) {
printk("Savage Card Not Found !\n");
return 0;
}
id=(buf[0]>>16)&0xffff;
switch(id) {
case 0x8811:
chipset = TRIO64;
break;
case 0x8903:
case 0x8904:
chipset = TRIO3D;
break;
case 0x8a13:
chipset = TRIO3D2X;
break;
case 0x5631:
chipset = VIRGE;
break;
case 0x883d:
chipset = VIRGEVX;
break;
case 0x8a01:
chipset = VIRGEDX;
break;
case 0x8a10:
chipset = VIRGEGX2;
break;
case 0x8c00:
case 0x8c01:
case 0x8c02:
case 0x8c03:
chipset = VIRGEMX;
break;
case 0x8a20:
case 0x8a21:
chipset = SAVAGE3D;
break;
case 0x8c10:
case 0x8c12:
chipset = SAVAGEMX;
break;
case 0x8a22:
case 0x8a23:
case 0x8d03:
case 0x8d04:
chipset = SAVAGE4;
break;
case 0x9102:
chipset = SAVAGE2000;
break;
default:
chipset = UNKNOWN;
}
 
if(chipset<SAVAGE3D) {
linear_base=buf[4]&0xffffff00;
mmio_base = linear_base + 0x1000000;
#if 1 /* You need to write linear address to CR59 5A, and enable MMIO in CR53 -
But how to do it if it's a secondary card??? */
if(__svgalib_secondary) {
__svgalib_mmio_base = mmio_base;
__svgalib_mmio_size = 0x10000;
map_mmio();
__svgalib_vgammbase=0x8000;
__svgalib_mm_io_mapio();
}
#endif
unlock();
config1=__svgalib_incrtc(0x36);
memory = 1024 * vmems[chipset][(config1&0xe0)>>5];
} else {
linear_base=buf[5]&0xffffff00;
mmio_base =buf[4]&0xffffff00;
__svgalib_mmio_base = mmio_base;
__svgalib_mmio_size = 0x10000;
map_mmio();
__svgalib_vgammbase=0x8000;
__svgalib_mm_io_mapio();
unlock();
config1=__svgalib_incrtc(0x36);
if(chipset >= SAVAGE4) {
memory=mems[config1>>5]*1024;
} else {
switch(config1>>6) {
case 0:
memory=8192;
break;
case 0x40:
case 0x80:
memory=4096;
break;
case 0xC0:
memory=2048;
break;
}
}
}
 
if (__svgalib_driver_report) {
printk(KERN_INFO "Using SAVAGE driver, %iKB. Chipset: %s\n",memory, chipnames[chipset]);
};
cardspecs = malloc(sizeof(CardSpecs));
cardspecs->videoMemory = memory;
cardspecs->maxPixelClock4bpp = 0;
cardspecs->maxPixelClock8bpp = 250000;
cardspecs->maxPixelClock16bpp = 250000;
cardspecs->maxPixelClock24bpp = 220000;
cardspecs->maxPixelClock32bpp = 220000;
cardspecs->flags = INTERLACE_DIVIDE_VERT | CLOCK_PROGRAMMABLE;
cardspecs->maxHorizontalCrtc = 4088;
cardspecs->nClocks = 0;
cardspecs->mapClock = map_clock;
cardspecs->mapHorizontalCrtc = map_horizontal_crtc;
cardspecs->matchProgrammableClock=match_programmable_clock;
__svgalib_driverspecs = &__svgalib_savage_driverspecs;
__svgalib_banked_mem_base=0xa0000;
__svgalib_banked_mem_size=0x10000;
__svgalib_linear_mem_base=linear_base;
__svgalib_linear_mem_size=memory*0x400;
 
sleep(4);
return 0;
 
}
/shark/tags/rel_0_5/drivers/svga/vgapal.c
0,0 → 1,149
/* VGAlib version 1.2 - (c) 1993 Tommy Frandsen */
/* */
/* This library is free software; you can redistribute it and/or */
/* modify it without any restrictions. This library is distributed */
/* in the hope that it will be useful, but without any warranty. */
 
/* Multi-chipset support Copyright 1993 Harm Hanemaayer */
/* partially copyrighted (C) 1993 by Hartmut Schirmer */
 
/* Converted to especially ugly code and seriously hacked for Mach32: */
/* M. Weller in 1994 */
#include <stdlib.h>
 
#include "vga.h"
#include "vgaio.h"
#include "libvga.h"
#include "driver.h"
 
/*
* In grayscale mode, we convert RGB colors to a Y component on the
* green-channel (the Y component is used in grayscale TV sets for the
* same purpose and corresponds to the "brightness" of the color as
* perceived by the human eye. In order to be able to return to the
* user the original green-component, we save a backup copy of the
* green channel in __svgalib_green_backup:
*/
int __svgalib_green_backup[256];
 
 
static int set_lut(int index, int red, int green, int blue)
{
if (__svgalib_novga) return 1;
/* prevents lockups */
if ((__svgalib_chipset == MACH64)) {
outb(0x02ec+0x5c00,index);
outb(0x02ec+0x5c01,red);
outb(0x02ec+0x5c01,green);
outb(0x02ec+0x5c01,blue);
return 0;
}
 
__svgalib_outpal(index,red,green,blue);
return 0;
}
 
 
static int get_lut(int index, int *red, int *green, int *blue)
{
if (__svgalib_novga) return 0;
 
/* prevents lockups on mach64 */
if ((__svgalib_chipset == MACH64)) {
outb(0x02ec+0x5c00,index);
*red=port_in(0x02ec+0x5c01);
*green=port_in(0x02ec+0x5c01);
*blue=port_in(0x02ec+0x5c01);
return 0;
}
 
__svgalib_inpal(index,red,green,blue);
 
return 0;
}
 
int vga_setpalette(int index, int red, int green, int blue)
{
 
DTP(("setpalette %i %i %i %i\n",index,red,green,blue));
 
if (__svgalib_grayscale) {
if ((unsigned) index >= sizeof(__svgalib_green_backup) / sizeof(__svgalib_green_backup[0])) {
cprintf("vga_setpalette: color index %d out of range\n", index);
}
__svgalib_green_backup[index] = green;
 
green = 0.299 * red + 0.587 * green + 0.114 * blue;
if (green < 0)
green = 0;
if (green > 255)
green = 255;
}
 
if (__svgalib_driverspecs->emul && __svgalib_driverspecs->emul->setpalette) {
return __svgalib_driverspecs->emul->setpalette(index, red, green, blue);
} else {
return set_lut(index, red, green, blue);
}
}
 
int vga_getpalette(int index, int *red, int *green, int *blue)
{
if (__svgalib_driverspecs->emul && __svgalib_driverspecs->emul->getpalette)
__svgalib_driverspecs->emul->getpalette(index, red, green, blue);
else get_lut(index, red, green, blue);
if (__svgalib_grayscale) {
if ((unsigned) index >= sizeof(__svgalib_green_backup) / sizeof(__svgalib_green_backup[0])) {
cprintf("vga_getpalette: color index %d out of range\n", index);
}
*green = __svgalib_green_backup[index];
}
return 0;
}
 
 
int vga_setpalvec(int start, int num, int *pal)
{
int i;
 
DTP(("setpalvec %i %i %x\n",start,num,pal));
 
if ((__svgalib_driverspecs->emul && __svgalib_driverspecs->emul->setpalette) ||
(__svgalib_outpal!=__svgalib_vga_outpal)) {
for (i = start; i < start + num; ++i) {
vga_setpalette(i, pal[0], pal[1], pal[2]);
pal += 3;
}
} else {
unsigned char string[768];
 
if ( num > 256 )
return 0;
 
for (i = 0; i < num * 3; i++)
string[i] = pal[i];
 
port_out ( start, 0x3c8 );
#if 0
port_rep_outb( string, num * 3, 0x3c9 );
#else
for(i=0;i<num*3;i++)port_out(string[i],0x3c9);
#endif
}
 
return num;
}
 
 
int vga_getpalvec(int start, int num, int *pal)
{
int i;
 
for (i = start; i < start + num; ++i) {
vga_getpalette(i, pal + 0, pal + 1, pal + 2);
pal += 3;
}
return num;
}
/shark/tags/rel_0_5/drivers/svga/ics_gendac.c
0,0 → 1,261
/*
* ics_gendac.c:
*
* This works only with ARK, since it has ARK specific code.
*/
 
#include <stdio.h>
#include "libvga.h"
#include "timing.h"
#include "vgaregs.h"
#include "driver.h" /* for __svgalib_driver_report */
#include "ramdac.h"
 
/* SDAC/GENDAC registers */
#define SDAC_COMMAND 0
#define GENDAC_COMMAND 0
#define SDAC_PLL_WRITEINDEX 1
#define SDAC_PLL_READINDEX 2
#define SDAC_PLL_M 3 /* f2 programmed clock */
#define SDAC_PLL_N1_N2 4
#define SDAC_PLL_CONTROL 5
 
#define GENDAC_STATESIZE 6
 
static void GENDAC_init(void)
{
}
 
 
/*
* From XFree86 common_hw/S3gendac.c and S3gendac.h.
*
* Progaming of the S3 gendac programable clocks, from the S3 Gendac
* programing documentation by S3 Inc.
* Jon Tombs <jon@esix2.us.es>
*
* Returns nonzero if success, 0 if failure.
*/
#define BASE_FREQ 14.31818 /* MHz */
 
#define DEBUG_FINDCLOCK 0
 
static int S3dacsFindClock(int freq_in, int min_n2, int freq_min, int freq_max,
int *best_m_out, int *best_n1_out, int *best_n2_out)
{
double ffreq_in, ffreq_min, ffreq_max;
double ffreq_out, diff, best_diff;
unsigned int m;
unsigned char n1, n2;
unsigned char best_n1 = 16 + 2, best_n2 = 2, best_m = 125 + 2;
 
#if DEBUG_FINDCLOCK
cprintf("S3dacsFindClock: Trying to match clock of %0.3f MHz\n", freq_in / 1000.0);
#endif
ffreq_in = freq_in / 1000.0 / BASE_FREQ;
ffreq_min = freq_min / 1000.0 / BASE_FREQ;
ffreq_max = freq_max / 1000.0 / BASE_FREQ;
 
/* Check if getting freq_in is possible at all */
if (freq_in < freq_min / 8) {
#if DEBUG_FINDCLOCK
cprintf("S3dacsFindClock: %0.3f MHz is too low (lowest is %0.3f MHz)\n",
freq_in / 1000.0, freq_min / 1000.0 / 8);
#endif
return 0;
}
if (freq_in > freq_max / (1 << min_n2)) {
#if DEBUG_FINDCLOCK
cprintf("S3dacsFindClock: %0.3f MHz is too high (highest is %0.3f MHz)\n",
freq_in / 1000.0, freq_max / 1000.0 / (1 << min_n2));
#endif
return 0;
}
 
/* work out suitable timings */
best_diff = ffreq_in;
for (n2 = min_n2; n2 <= 3; n2++) {
for (n1 = 1 + 2; n1 <= 31 + 2; n1++) {
m = (int) (ffreq_in * n1 * (1 << n2) + 0.5);
if (m < 1 + 2 || m > 127 + 2)
continue;
ffreq_out = (double) (m) / (double) (n1);
if ((ffreq_out >= ffreq_min) && (ffreq_out <= ffreq_max)) {
diff = ffreq_in - ffreq_out / (1 << n2);
if (diff < 0.0)
diff = -diff;
if (diff < best_diff) {
best_diff = diff;
best_m = m;
best_n1 = n1;
best_n2 = n2;
}
}
}
}
 
#if DEBUG_FINDCLOCK
cprintf("S3dacsFindClock: clock wanted %1.6f MHz, found %1.6f MHz (m %d, n1 %d, n2 %d)\n",
freq_in / 1000.0,
best_m / ((double) best_n1 * (1 << best_n2)) * BASE_FREQ,
best_m, best_n1, best_n2);
#endif
*best_m_out = best_m;
*best_n1_out = best_n1;
*best_n2_out = best_n2;
return 1;
}
 
static int GENDAC_match_programmable_clock(int desiredclock)
{
int min_m, min_n1, n2;
/* Note: For ICS5342, min_n2 parameter should be one. */
if (!S3dacsFindClock(desiredclock, 0, 100000, 250000, &min_m, &min_n1, &n2))
return 0;
 
return ((float) (min_m) / (float) (min_n1) / (1 << n2)) * BASE_FREQ * 1000;
}
 
static void GENDAC_initialize_clock_state(unsigned char *regs, int freq)
{
int min_m, min_n1, n2;
int n, m;
 
if (!S3dacsFindClock(freq, 0, 100000, 250000, &min_m, &min_n1, &n2)) {
cprintf("Bad dot clock %0.3f MHz.\n", freq / 1000.0);
return;
}
n = (min_n1 - 2) | (n2 << 5);
m = min_m - 2;
regs[SDAC_PLL_M] = m;
regs[SDAC_PLL_N1_N2] = n;
#if 0
if (__svgalib_driver_report)
cprintf("Initializing DAC PLL values; 0x%02X, 0x%02X.\n", m, n);
#endif
}
 
static void GENDAC_savestate(unsigned char *regs)
{
unsigned char tmp;
tmp = __svgalib_inSR(0x1c);
__svgalib_outSR(0x1c, tmp | 0x80);
 
regs[SDAC_COMMAND] = inb(0x3c6);
regs[SDAC_PLL_WRITEINDEX] = inb(0x3c8); /* PLL write index */
regs[SDAC_PLL_READINDEX] = inb(0x3c7); /* PLL read index */
outb(0x3c7, 2); /* index to f2 reg */
regs[SDAC_PLL_M] = inb(0x3c9); /* f2 PLL M divider */
regs[SDAC_PLL_N1_N2] = inb(0x3c9); /* f2 PLL N1/N2 divider */
outb(0x3c7, 0x0e); /* index to PLL control */
regs[SDAC_PLL_CONTROL] = inb(0x3c9); /* PLL control */
 
__svgalib_outSR(0x1c, tmp & ~0x80);
}
 
static void GENDAC_restorestate(const unsigned char *regs)
{
unsigned char tmp;
 
tmp = __svgalib_inseq(0x1c);
__svgalib_outseq(0x1c, tmp | 0x80);
 
outb(0x3c6, regs[SDAC_COMMAND]);
outb(0x3c8, 2); /* index to f2 reg */
outb(0x3c9, regs[SDAC_PLL_M]); /* f2 PLL M divider */
outb(0x3c9, regs[SDAC_PLL_N1_N2]); /* f2 PLL N1/N2 divider */
outb(0x3c8, 0x0e); /* index to PLL control */
outb(0x3c9, regs[SDAC_PLL_CONTROL]); /* PLL control */
outb(0x3c8, regs[SDAC_PLL_WRITEINDEX]); /* PLL write index */
outb(0x3c7, regs[SDAC_PLL_READINDEX]); /* PLL read index */
 
__svgalib_outseq(0x1c, tmp);
}
 
/*
* SDAC: 16-bit DAC, 110 MHz raw clock limit.
*
* The 135 MHz version supports pixel multiplexing in 8bpp modes with a
* halved raw clock. (SL: at least mine doesn't.)
*/
 
static int GENDAC_probe(void)
{
int i;
inb(0x3c6);
inb(0x3c6);
inb(0x3c6);
i=inb(0x3c6);
if(i==177) return 1;
return 0;
}
 
static int GENDAC_map_clock(int bpp, int pixelclock)
{
if (bpp == 16)
return pixelclock * 2;
if (bpp == 24)
return pixelclock * 3;
if (bpp == 32)
return pixelclock * 4;
return pixelclock;
}
 
static int GENDAC_map_horizontal_crtc(int bpp, int pixelclock, int htiming)
{
/* XXXX Not sure. */
if (bpp == 24)
return htiming * 3;
if (bpp == 16)
return htiming * 2;
return htiming;
}
 
static void GENDAC_initializestate(unsigned char *regs, int bpp, int colormode,
int pixelclock)
{
int daccomm; /* DAC command register. */
daccomm = 0;
if (colormode == RGB16_555)
daccomm = 0x20;
else if (colormode == RGB16_565)
daccomm = 0x60;
else if (colormode == RGB24_888_B)
daccomm = 0x40;
regs[GENDAC_COMMAND] = daccomm;
GENDAC_initialize_clock_state(regs,
GENDAC_map_clock(bpp, pixelclock));
}
 
static void GENDAC_qualify_cardspecs(CardSpecs * cardspecs, int dacspeed)
{
dacspeed = __svgalib_setDacSpeed(dacspeed, 110000);
cardspecs->maxPixelClock4bpp = dacspeed;
cardspecs->maxPixelClock8bpp = dacspeed;
cardspecs->maxPixelClock16bpp = dacspeed / 2;
cardspecs->maxPixelClock24bpp = dacspeed / 3;
cardspecs->maxPixelClock32bpp = 0;
cardspecs->mapClock = GENDAC_map_clock;
cardspecs->matchProgrammableClock = GENDAC_match_programmable_clock;
cardspecs->mapHorizontalCrtc = GENDAC_map_horizontal_crtc;
cardspecs->flags |= CLOCK_PROGRAMMABLE;
}
 
DacMethods __svgalib_ICS_GENDAC_methods =
{
S3_GENDAC,
"ICS-GENDAC (5342)",
DAC_HAS_PROGRAMMABLE_CLOCKS,
GENDAC_probe,
GENDAC_init,
GENDAC_qualify_cardspecs,
GENDAC_savestate,
GENDAC_restorestate,
GENDAC_initializestate,
GENDAC_STATESIZE
};
/shark/tags/rel_0_5/drivers/svga/s3dacs.c
0,0 → 1,757
/*
* s3dacs.c:
*
* RAMDAC definitions for the S3-SDAC (86C716), S3-GENDAC, and Trio64.
*
* These contain S3-specific code.
*/
 
//#include <stdio.h>
#include "libvga.h"
#include "timing.h"
#include "vgaregs.h"
#include "driver.h" /* for __svgalib_driver_report */
#include "ramdac.h"
 
/* SDAC/GENDAC registers */
#if defined(INCLUDE_S3_SDAC_DAC) || defined(INCLUDE_S3_GENDAC_DAC)
#define SDAC_COMMAND 0 /* Register offsets into state. */
#define GENDAC_COMMAND 0
#define SDAC_PLL_WRITEINDEX 1
#define SDAC_PLL_READINDEX 2
#define SDAC_PLL_M 3 /* f2 programmed clock */
#define SDAC_PLL_N1_N2 4
#define SDAC_PLL_CONTROL 5
 
#define SDAC_STATESIZE 6 /* 6 registers. */
#define GENDAC_STATESIZE 6
#endif
 
#if defined(INCLUDE_S3_SDAC_DAC_TEST) || defined(INCLUDE_S3_GENDAC_DAC_TEST)
static int GENDAC_SDAC_probe(void)
{
/* Taken from XFree86, accel/s3.c. */
/* Return 1 if GENDAC found, 2 if SDAC, 0 otherwise. */
/* probe for S3 GENDAC or SDAC */
/*
* S3 GENDAC and SDAC have two fixed read only PLL clocks
* CLK0 f0: 25.255MHz M-byte 0x28 N-byte 0x61
* CLK0 f1: 28.311MHz M-byte 0x3d N-byte 0x62
* which can be used to detect GENDAC and SDAC since there is no chip-id
* for the GENDAC.
*
* NOTE: for the GENDAC on a MIRO 10SD (805+GENDAC) reading PLL values
* for CLK0 f0 and f1 always returns 0x7f (but is documented "read only")
*/
 
unsigned char saveCR55, savelut[6];
int i;
long clock01, clock23;
 
saveCR55 = __svgalib_inCR(0x55);
__svgalib_outbCR(0x55, saveCR55 & ~1);
 
outb(0x3c7, 0);
for (i = 0; i < 2 * 3; i++) /* save first two LUT entries */
savelut[i] = inb(0x3c9);
outb(0x3c8, 0);
for (i = 0; i < 2 * 3; i++) /* set first two LUT entries to zero */
outb(0x3c9, 0);
 
__svgalib_outbCR(0x55, saveCR55 | 1);
 
outb(0x3c7, 0);
for (i = clock01 = 0; i < 4; i++)
clock01 = (clock01 << 8) | (inb(0x3c9) & 0xff);
for (i = clock23 = 0; i < 4; i++)
clock23 = (clock23 << 8) | (inb(0x3c9) & 0xff);
 
__svgalib_outbCR(0x55, saveCR55 & ~1);
 
outb(0x3c8, 0);
for (i = 0; i < 2 * 3; i++) /* restore first two LUT entries */
outb(0x3c9, savelut[i]);
 
__svgalib_outbCR(0x55, saveCR55);
 
if (clock01 == 0x28613d62 ||
(clock01 == 0x7f7f7f7f && clock23 != 0x7f7f7f7f)) {
 
inb(0x3c8); /* dactopel */
 
inb(0x3c6);
inb(0x3c6);
inb(0x3c6);
 
/* the forth read will show the SDAC chip ID and revision */
if (((i = inb(0x3c6)) & 0xf0) == 0x70) {
return 2; /* SDAC found. */
} else {
return 1; /* GENDAC found. */
}
inb(0x3c8); /* dactopel */
}
return 0;
}
#endif
 
#if defined(INCLUDE_S3_SDAC_DAC) || defined(INCLUDE_S3_GENDAC_DAC)
static void GENDAC_SDAC_init(void)
{
unsigned char val;
int m, n, n1, n2, MCLK;
val = __svgalib_inCR(0x55);
__svgalib_outbCR(0x55, val | 0x01);
 
outb(0x3C7, 10); /* Read MCLK. */
m = inb(0x3C9);
n = inb(0x3C9);
 
__svgalib_outbCR(0x55, val); /* Restore CR55. */
 
m &= 0x7f;
n1 = n & 0x1f;
n2 = (n >> 5) & 0x03;
/* Calculate MCLK in kHz. */
MCLK = 14318 * (m + 2) / (n1 + 2) / (1 << n2);
if (__svgalib_driver_report)
printk(KERN_INFO "svgalib: S3-GENDAC/SDAC: MCLK = %d.%03d MHz\n",
MCLK / 1000, MCLK % 1000);
}
#endif
 
 
#if defined(INCLUDE_S3_SDAC_DAC) || defined(INCLUDE_S3_GENDAC_DAC) || defined(INCLUDE_S3_TRIO64_DAC)
/*
* From XFree86 common_hw/S3gendac.c and S3gendac.h.
*
* Progaming of the S3 gendac programable clocks, from the S3 Gendac
* programing documentation by S3 Inc.
* Jon Tombs <jon@esix2.us.es>
*
* Returns nonzero if success, 0 if failure.
*/
#define BASE_FREQ 14.31818 /* MHz */
 
#define DEBUG_FINDCLOCK 0
 
static int S3dacsFindClock(int freq_in, int min_n2, int freq_min, int freq_max,
int *best_m_out, int *best_n1_out, int *best_n2_out)
{
double ffreq_in, ffreq_min, ffreq_max;
double ffreq_out, diff, best_diff;
unsigned int m;
unsigned char n1, n2;
unsigned char best_n1 = 16 + 2, best_n2 = 2, best_m = 125 + 2;
 
#if DEBUG_FINDCLOCK
printk(KERN_INFO "S3dacsFindClock: Trying to match clock of %0.3f MHz\n", freq_in / 1000.0);
#endif
ffreq_in = freq_in / 1000.0 / BASE_FREQ;
ffreq_min = freq_min / 1000.0 / BASE_FREQ;
ffreq_max = freq_max / 1000.0 / BASE_FREQ;
 
/* Check if getting freq_in is possible at all */
if (freq_in < freq_min / 8) {
#if DEBUG_FINDCLOCK
printk(KERN_INFO "S3dacsFindClock: %0.3f MHz is too low (lowest is %0.3f MHz)\n",
freq_in / 1000.0, freq_min / 1000.0 / 8);
#endif
return 0;
}
if (freq_in > freq_max / (1 << min_n2)) {
#if DEBUG_FINDCLOCK
printk(KERN_INFO "S3dacsFindClock: %0.3f MHz is too high (highest is %0.3f MHz)\n",
freq_in / 1000.0, freq_max / 1000.0 / (1 << min_n2));
#endif
return 0;
}
 
/* work out suitable timings */
best_diff = ffreq_in;
for (n2 = min_n2; n2 <= 3; n2++) {
for (n1 = 1 + 2; n1 <= 31 + 2; n1++) {
m = (int) (ffreq_in * n1 * (1 << n2) + 0.5);
if (m < 1 + 2 || m > 127 + 2)
continue;
ffreq_out = (double) (m) / (double) (n1);
if ((ffreq_out >= ffreq_min) && (ffreq_out <= ffreq_max)) {
diff = ffreq_in - ffreq_out / (1 << n2);
if (diff < 0.0)
diff = -diff;
if (diff < best_diff) {
best_diff = diff;
best_m = m;
best_n1 = n1;
best_n2 = n2;
}
}
}
}
 
#if DEBUG_FINDCLOCK
printk(KERN_INFO "S3dacsFindClock: clock wanted %1.6f MHz, found %1.6f MHz (m %d, n1 %d, n2 %d)\n",
freq_in / 1000.0,
best_m / ((double) best_n1 * (1 << best_n2)) * BASE_FREQ,
best_m, best_n1, best_n2);
#endif
*best_m_out = best_m;
*best_n1_out = best_n1;
*best_n2_out = best_n2;
return 1;
}
#endif
 
#if defined(INCLUDE_S3_SDAC_DAC) || defined(INCLUDE_S3_GENDAC_DAC)
static int GENDAC_SDAC_match_programmable_clock(int desiredclock)
{
int min_m, min_n1, n2;
/* Note: For ICS5342, min_n2 parameter should be one. */
if (!S3dacsFindClock(desiredclock, 0, 100000, 250000, &min_m, &min_n1, &n2))
return 0;
 
return ((float) (min_m) / (float) (min_n1) / (1 << n2)) * BASE_FREQ * 1000;
}
 
#if 0 /* Retained for reference. */
static void setdacpll(reg, data1, data2)
int reg;
unsigned char data1;
unsigned char data2;
{
unsigned char tmp, tmp1;
int vgaCRIndex = vgaIOBase + 4;
int vgaCRReg = vgaIOBase + 5;
 
/* set RS2 via CR55, yuck */
tmp = __svgalib_inCR(0x55) & 0xFC;
__svgalib_outCR(tmp | 0x01);
tmp1 = inb(GENDAC_INDEX);
 
outb(GENDAC_INDEX, reg);
outb(GENDAC_DATA, data1);
outb(GENDAC_DATA, data2);
 
/* Now clean up our mess */
outb(GENDAC_INDEX, tmp1);
__svgalib_outbCR(0x55, tmp);
}
#endif
 
static void GENDAC_SDAC_initialize_clock_state(unsigned char *regs, int freq)
{
int min_m, min_n1, n2;
int n, m;
 
if (!S3dacsFindClock(freq, 0, 100000, 250000, &min_m, &min_n1, &n2)) {
printk(KERN_INFO "Bad dot clock %0.3f MHz.\n", freq / 1000.0);
return;
}
n = (min_n1 - 2) | (n2 << 5);
m = min_m - 2;
regs[SDAC_PLL_M] = m;
regs[SDAC_PLL_N1_N2] = n;
if (__svgalib_driver_report)
printk(KERN_INFO "Initializing DAC PLL values; 0x%02X, 0x%02X.\n", m, n);
}
 
static void GENDAC_SDAC_savestate(unsigned char *regs)
{
unsigned char tmp;
tmp = __svgalib_inCR(0x55);
__svgalib_outbCR(0x55, tmp | 1);
 
regs[SDAC_COMMAND] = inb(0x3c6);
regs[SDAC_PLL_WRITEINDEX] = inb(0x3c8); /* PLL write index */
regs[SDAC_PLL_READINDEX] = inb(0x3c7); /* PLL read index */
outb(0x3c7, 2); /* index to f2 reg */
regs[SDAC_PLL_M] = inb(0x3c9); /* f2 PLL M divider */
regs[SDAC_PLL_N1_N2] = inb(0x3c9); /* f2 PLL N1/N2 divider */
outb(0x3c7, 0x0e); /* index to PLL control */
regs[SDAC_PLL_CONTROL] = inb(0x3c9); /* PLL control */
 
__svgalib_outbCR(0x55, tmp & ~1);
}
 
static void GENDAC_SDAC_restorestate(const unsigned char *regs)
{
unsigned char tmp;
 
/* set RS2 via CR55, yuck */
tmp = __svgalib_inCR(0x55) & 0xFC;
__svgalib_outbCR(0x55, tmp | 0x01);
 
#ifdef DEBUG
do {
int m, n1, n2, clk;
 
m = regs[SDAC_PLL_M] & 0x7f;
n1 = regs[SDAC_PLL_N1_N2] & 0x1f;
n2 = (regs[SDAC_PLL_N1_N2] & 0x60) >> 5;
 
clk = 14318 * (m + 2) / (n1 + 2) / (1 << n2);
printk(KERN_INFO "SDAC.restorestate, setting clock 0x%02X 0x%02X (%d.%3dMHz)\n",
regs[SDAC_PLL_M],
regs[SDAC_PLL_N1_N2], clk / 1000, clk % 1000);
} while (0);
#endif
 
outb(0x3c6, regs[SDAC_COMMAND]);
outb(0x3c8, 2); /* index to f2 reg */
outb(0x3c9, regs[SDAC_PLL_M]); /* f2 PLL M divider */
outb(0x3c9, regs[SDAC_PLL_N1_N2]); /* f2 PLL N1/N2 divider */
outb(0x3c8, 0x0e); /* index to PLL control */
outb(0x3c9, regs[SDAC_PLL_CONTROL]); /* PLL control */
outb(0x3c8, regs[SDAC_PLL_WRITEINDEX]); /* PLL write index */
outb(0x3c7, regs[SDAC_PLL_READINDEX]); /* PLL read index */
 
__svgalib_outbCR(0x55, tmp);
}
 
#endif /* defined(INCLUDE_S3_SDAC_DAC) || defined(INCLUDE_S3_GENDAC_DAC) */
 
/*
* SDAC: 16-bit DAC, 110 MHz raw clock limit.
*
* The 135 MHz version supports pixel multiplexing in 8bpp modes with a
* halved raw clock. (SL: at least mine doesn't.)
*/
 
#ifdef INCLUDE_S3_SDAC_DAC_TEST
static int SDAC_probe(void)
{
return GENDAC_SDAC_probe() == 2;
}
#else
#define SDAC_probe 0
#endif
 
#ifdef INCLUDE_S3_SDAC_DAC
static int SDAC_map_clock(int bpp, int pixelclock)
{
switch (bpp) {
case 4:
case 8:
#ifdef SDAC_8BPP_PIXMUX /* SL: AFAIK it doesn't work */
if (pixelclock >= 67500)
/* Use pixel multiplexing. */
return pixelclock / 2;
#endif
break;
case 24:
return pixelclock * 3 / 2;
case 32:
return pixelclock * 2;
}
return pixelclock;
}
 
static int SDAC_map_horizontal_crtc(int bpp, int pixelclock, int htiming)
{
switch (bpp) {
case 16:
return htiming * 2;
case 24:
return htiming * 3;
case 32:
return htiming * 4;
}
return htiming;
}
 
static void SDAC_initializestate(unsigned char *regs, int bpp, int colormode,
int pixelclock)
{
int pixmux; /* SDAC command register. */
pixmux = 0;
switch (colormode) {
case CLUT8_6:
#ifdef SDAC_8BPP_PIXMUX
if (pixelclock >= 67500)
pixmux = 0x10;
#endif
break;
case RGB16_555:
pixmux = 0x30;
break;
case RGB16_565:
pixmux = 0x50;
break;
case RGB24_888_B:
/* Use 0x40 for 3 VCLK/pixel. Change SDAC_map_clock and CR67 as well. */
pixmux = 0x90;
break;
case RGB32_888_B:
pixmux = 0x70;
break;
}
regs[SDAC_COMMAND] = pixmux;
GENDAC_SDAC_initialize_clock_state(regs,
SDAC_map_clock(bpp, pixelclock));
}
 
static void SDAC_qualify_cardspecs(CardSpecs * cardspecs, int dacspeed)
{
dacspeed = __svgalib_setDacSpeed(dacspeed, 110000); /* most can do 135MHz. */
cardspecs->maxPixelClock4bpp = dacspeed;
cardspecs->maxPixelClock8bpp = dacspeed;
cardspecs->maxPixelClock16bpp = dacspeed;
cardspecs->maxPixelClock24bpp = dacspeed * 2 / 3;
cardspecs->maxPixelClock32bpp = dacspeed / 2;
cardspecs->mapClock = SDAC_map_clock;
cardspecs->matchProgrammableClock = GENDAC_SDAC_match_programmable_clock;
cardspecs->mapHorizontalCrtc = SDAC_map_horizontal_crtc;
cardspecs->flags |= CLOCK_PROGRAMMABLE;
}
 
DacMethods __svgalib_S3_SDAC_methods =
{
S3_SDAC,
"S3-SDAC (86C716)",
DAC_HAS_PROGRAMMABLE_CLOCKS,
SDAC_probe,
GENDAC_SDAC_init,
SDAC_qualify_cardspecs,
GENDAC_SDAC_savestate,
GENDAC_SDAC_restorestate,
SDAC_initializestate,
SDAC_STATESIZE
};
#endif
 
 
/* S3-GENDAC, 8-bit DAC. */
 
#ifdef INCLUDE_S3_GENDAC_DAC_TEST
static int GENDAC_probe(void)
{
return GENDAC_SDAC_probe() == 1;
}
#else
#define GENDAC_probe 0
#endif
 
#ifdef INCLUDE_S3_GENDAC_DAC
static int GENDAC_map_clock(int bpp, int pixelclock)
{
if (bpp == 16)
return pixelclock * 2;
if (bpp == 24)
return pixelclock * 3;
if (bpp == 32)
return pixelclock * 4;
return pixelclock;
}
 
static int GENDAC_map_horizontal_crtc(int bpp, int pixelclock, int htiming)
{
/* XXXX Not sure. */
if (bpp == 24)
return htiming * 3;
if (bpp == 16)
return htiming * 2;
return htiming;
}
 
static void GENDAC_initializestate(unsigned char *regs, int bpp, int colormode,
int pixelclock)
{
int daccomm; /* DAC command register. */
daccomm = 0;
if (colormode == RGB16_555)
daccomm = 0x20;
else if (colormode == RGB16_565)
daccomm = 0x60;
else if (colormode == RGB24_888_B)
daccomm = 0x40;
regs[GENDAC_COMMAND] = daccomm;
GENDAC_SDAC_initialize_clock_state(regs,
GENDAC_map_clock(bpp, pixelclock));
}
 
static void GENDAC_qualify_cardspecs(CardSpecs * cardspecs, int dacspeed)
{
dacspeed = __svgalib_setDacSpeed(dacspeed, 110000);
cardspecs->maxPixelClock4bpp = dacspeed;
cardspecs->maxPixelClock8bpp = dacspeed;
cardspecs->maxPixelClock16bpp = dacspeed / 2;
cardspecs->maxPixelClock24bpp = dacspeed / 3;
cardspecs->maxPixelClock32bpp = 0;
cardspecs->mapClock = GENDAC_map_clock;
cardspecs->matchProgrammableClock = GENDAC_SDAC_match_programmable_clock;
cardspecs->mapHorizontalCrtc = GENDAC_map_horizontal_crtc;
cardspecs->flags |= CLOCK_PROGRAMMABLE;
}
 
DacMethods __svgalib_S3_GENDAC_methods =
{
S3_GENDAC,
"S3-GENDAC (86C708)",
DAC_HAS_PROGRAMMABLE_CLOCKS,
GENDAC_probe,
GENDAC_SDAC_init,
GENDAC_qualify_cardspecs,
GENDAC_SDAC_savestate,
GENDAC_SDAC_restorestate,
GENDAC_initializestate,
GENDAC_STATESIZE
};
#endif
 
 
#ifdef INCLUDE_S3_TRIO64_DAC
/* S3-Trio64, 16-bit integrated DAC. */
 
#define TRIO64_SR15 0
#define TRIO64_SR18 1
#define TRIO64_PLL_N1_N2 2
#define TRIO64_PLL_M 3
#define TRIO64_CR67 4
#define TRIO64_SRB 5
#define TRIO64_STATESIZE 6
 
/* Note: s3.c also defines CR67, but doesn't use it for the Trio64. */
 
extern int __svgalib_s3_s3Mclk;
 
static int Trio64_get_mclk(void)
{
unsigned char sr8;
int m, n, n1, n2;
 
outb(0x3c4, 0x08);
sr8 = inb(0x3c5);
outb(0x3c5, 0x06);
 
outb(0x3c4, 0x11);
m = inb(0x3c5);
outb(0x3c4, 0x10);
n = inb(0x3c5);
 
outb(0x3c4, 0x08);
outb(0x3c5, sr8);
 
m &= 0x7f;
n1 = n & 0x1f;
n2 = (n >> 5) & 0x03;
/* Calculate MCLK in kHz. */
return ((1431818 * (m + 2)) / (n1 + 2) / (1 << n2) + 50) / 100;
}
 
#if 0
static void Trio64_set_mclk(int khz)
/* Doesn't work. Locks computer up. Why? */
{
int sr8;
int min_m, min_n1, n2;
if (!S3dacsFindClock(khz, 0, 40000, 70000, &min_m, &min_n1, &n2)) {
printk(KERN_INFO "Bad MCLK %0.3f MHz.\n", khz / 1000.0);
return;
}
 
printk(KERN_INFO "%0.3f MHz MCLK, m = %d, n = %d, r = %d\n", khz / 1000.0, min_m - 2, min_n1 - 2, n2);
outb(0x3C4, 0x08);
sr8 = inb(0x3C5);
outb(0x3C5, 0x06); /* Unlock. */
 
outb(0x3c4, 0x15);
outb(0x3c5, inb(0x3c5) & ~0x20);
 
/* MCLK. */
__svgalib_outSR(0x10, (min_n1 - 2) | (n2 << 5));
__svgalib_outSR(0x11, min_m - 2);
 
outb(0x3c4, 0x15);
outb(0x3c5, inb(0x3c5) | 0x20);
outb(0x3c5, inb(0x3c5) & ~0x20);
__svgalib_outSR(0x08, sr8);
}
#endif
 
static void Trio64_init(void)
{
int mclk;
 
mclk = Trio64_get_mclk();
if (__svgalib_driver_report)
printk(KERN_INFO "svgalib: RAMDAC: Trio64: MCLK = %0.3f MHz\n",
mclk / 1000.0);
__svgalib_s3_s3Mclk = mclk;
}
 
static int Trio64_map_clock(int bpp, int pixelclock)
{
if (bpp == 8 && pixelclock >= 67500) /* use pixel doubling */
return pixelclock / 2;
if (bpp == 24)
return pixelclock * 3;
return pixelclock;
}
 
static int Trio64_map_horizontal_crtc(int bpp, int pixelclock, int htiming)
{
if (bpp == 16)
return htiming * 2;
/* Normal mapping for 8bpp and 32bpp. */
return htiming;
}
 
static void Trio64_initialize_clock_state(unsigned char *regs, int freq)
{
int min_m, min_n1, n2;
int n, m;
if (!S3dacsFindClock(freq, 0, 130000, 270000, &min_m, &min_n1, &n2)) {
printk(KERN_INFO "Bad dot clock %0.3f MHz.\n", freq / 1000.0);
return;
}
n = (min_n1 - 2) | (n2 << 5);
m = min_m - 2;
regs[TRIO64_PLL_M] = m;
regs[TRIO64_PLL_N1_N2] = n;
}
 
static int Trio64_match_programmable_clock(int desiredclock)
{
int min_m, min_n1, n2;
 
if (!S3dacsFindClock(desiredclock, 0, 130000, 270000, &min_m, &min_n1, &n2))
return 0;
return ((float) (min_m) / (float) (min_n1) / (1 << n2)) * BASE_FREQ * 1000;
}
 
static void Trio64_initializestate(unsigned char *regs, int bpp, int colormode,
int pixelclock)
{
int pixmux, reserved_CR67_1;
regs[TRIO64_SR15] &= ~0x50;
regs[TRIO64_SR18] &= ~0x80;
pixmux = 0;
reserved_CR67_1 = 0;
if (bpp == 8 && pixelclock >= 67500) {
pixmux = 0x10;
reserved_CR67_1 = 2;
regs[TRIO64_SR15] |= 0x50;
regs[TRIO64_SR18] |= 0x80;
} else if (bpp == 16) {
/* moderegs[S3_CR33] |= 0x08; *//* done in s3.c. */
if (colormode == RGB16_555)
pixmux = 0x30;
else
pixmux = 0x50;
reserved_CR67_1 = 2;
} else if (colormode == RGB24_888_B) {
/* remember to adjust SRB as well. */
pixmux = 0x00;
} else if (colormode == RGB32_888_B) {
pixmux = 0xD0; /* 32-bit color, 2 VCLKs/pixel. */
reserved_CR67_1 = 2;
}
regs[TRIO64_CR67] = pixmux | reserved_CR67_1;
 
Trio64_initialize_clock_state(regs, pixelclock);
}
 
static void Trio64_savestate(unsigned char *regs)
{
unsigned char sr8;
outb(0x3C4, 0x08);
sr8 = inb(0x3C5);
outb(0x3C5, 0x06); /* Unlock. */
 
regs[TRIO64_SR15] = __svgalib_inSR(0x15);
regs[TRIO64_SR18] = __svgalib_inSR(0x18);
regs[TRIO64_PLL_N1_N2] = __svgalib_inSR(0x12);
regs[TRIO64_PLL_M] = __svgalib_inSR(0x13);
regs[TRIO64_CR67] = __svgalib_inCR(0x67);
 
__svgalib_outSR(0x08, sr8);
}
 
static void Trio64_restorestate(const unsigned char *regs)
{
unsigned char sr8, tmp;
 
outb(0x3C4, 0x08);
sr8 = inb(0x3C5);
outb(0x3C5, 0x06); /* Unlock. */
 
__svgalib_outCR(0x67, regs[TRIO64_CR67]);
 
__svgalib_outSR(0x15, regs[TRIO64_SR15]);
__svgalib_outSR(0x18, regs[TRIO64_SR18]);
 
/* Clock. */
__svgalib_outSR(0x12, regs[TRIO64_PLL_N1_N2]);
__svgalib_outSR(0x13, regs[TRIO64_PLL_M]);
 
#if 0
/*
* XFree86 XF86_S3 (common_hw/gendac.c) has this, but it looks
* incorrect, it should flip the bit by writing to 0x3c5, not
* 0x3c4.
*/
outb(0x3c4, 0x15);
tmp = inb(0x3c5);
outb(0x3c4, tmp & ~0x20);
outb(0x3c4, tmp | 0x20);
outb(0x3c4, tmp & ~0x20);
#else
outb(0x3c4, 0x15);
tmp = inb(0x3c5);
outb(0x3c5, tmp & ~0x20);
outb(0x3c5, tmp | 0x20);
outb(0x3c5, tmp & ~0x20);
#endif
__svgalib_outSR(0x08, sr8);
}
 
 
static void Trio64_qualify_cardspecs(CardSpecs * cardspecs, int dacspeed)
{
if (dacspeed) {
if (__svgalib_driver_report)
printk(KERN_INFO "svgalib: using 'dacspeed' not recommended for this RAMDAC.\n");
cardspecs->maxPixelClock4bpp = dacspeed;
cardspecs->maxPixelClock8bpp = 135000;
cardspecs->maxPixelClock16bpp = dacspeed;
cardspecs->maxPixelClock24bpp = 0; /* dacspeed / 3; *//* How to program? */
cardspecs->maxPixelClock32bpp = 50000;
} else {
cardspecs->maxPixelClock4bpp = 80000;
cardspecs->maxPixelClock8bpp = 135000;
cardspecs->maxPixelClock16bpp = 80000;
cardspecs->maxPixelClock24bpp = 0; /* 25000; *//* How to program? */
cardspecs->maxPixelClock32bpp = 50000;
}
cardspecs->mapClock = Trio64_map_clock;
cardspecs->matchProgrammableClock = Trio64_match_programmable_clock;
cardspecs->mapHorizontalCrtc = Trio64_map_horizontal_crtc;
cardspecs->flags |= CLOCK_PROGRAMMABLE;
}
 
DacMethods __svgalib_Trio64_methods =
{
TRIO64,
"S3-Trio64 internal DAC",
DAC_HAS_PROGRAMMABLE_CLOCKS,
NULL, /* probe */
Trio64_init,
Trio64_qualify_cardspecs,
Trio64_savestate,
Trio64_restorestate,
Trio64_initializestate,
TRIO64_STATESIZE
};
#endif
/shark/tags/rel_0_5/drivers/svga/attdacs.c
0,0 → 1,224
/*
* attdacs.c:
*
* RAMDAC definition for industry-standard AT&T20C490/498 DACs and
* compatibles.
*/
 
#include <stdlib.h>
#include <stdio.h>
#include "libvga.h"
 
#include "timing.h"
#include "vgaregs.h"
#include "driver.h" /* for __svgalib_driver_report */
#include "ramdac.h"
 
/*
* RAMDAC definition for industry-standard AT&T20C490 DAC with 8-bit pixel
* port, and compatibles.
* These RAMDACs can do 32K and 64K color mode (16bpp) with doubled VCLK
* and 16M (8-8-8) truecolor with tripled VCLK.
* 0xA0 is written to the Hidden DAC register for 32K, 0xC0 for 64K and
* 0xE0 for 16M.
*/
 
#ifdef INCLUDE_ATT20C490_DAC_TEST
static int att20c490_probe(void)
{
unsigned char oldcomm, notcomm, oldpel, v;
int flag = 0;
 
_ramdac_dactocomm();
oldcomm = inb(PEL_MSK);
_ramdac_dactopel();
oldpel = inb(PEL_MSK);
 
notcomm = ~oldcomm;
outb(PEL_MSK, notcomm);
_ramdac_dactocomm();
v = inb(PEL_MSK);
if (v != notcomm) {
if ((_ramdac_setcomm(0xe0) & 0xe0) == 0xe0) {
if ((_ramdac_setcomm(0x60) & 0xe0) == 0) {
if ((_ramdac_setcomm(2) & 2) > 0)
flag = 1; /* 20c490 */
else
flag = 1; /* 20c493 */
} else {
_ramdac_setcomm(oldcomm);
if (inb(PEL_MSK) == notcomm)
if (_ramdac_setcomm(0xFF) == 0xFF)
flag = 1; /* 20c491/20c492 */
}
}
}
_ramdac_dactocomm();
outb(PEL_MSK, oldcomm);
_ramdac_dactopel();
outb(PEL_MSK, oldpel);
return flag;
}
#else
#define att20c490_probe 0
#endif
 
#ifdef INCLUDE_ATT20C490_DAC
static void att20c490_init(void)
{
if (__svgalib_driver_report)
cprintf("svgalib: Using AT&T20C490-compatible truecolor DAC.\n");
#if 0
dactocomm();
inb(PEL_MSK); /* Skip command register. */
cprintf("svgalib: DAC Manufacturer ID = 0x%02X, ", inb(PEL_MSK));
cprintf("Device ID = 0x%02X.\n", inb(PEL_MSK));
#endif
}
 
static int __svgalib_att20c490_map_clock(int bpp, int pixelclock)
{
if (bpp == 16)
return pixelclock * 2;
if (bpp == 24)
return pixelclock * 3;
return pixelclock;
}
 
static int __svgalib_att20c490_map_horizontal_crtc(int bpp, int pixelclock, int htiming)
{
if (bpp == 16)
return htiming * 2;
if (bpp == 24)
return htiming * 3;
return htiming;
}
 
 
static void att20c490_initializestate(unsigned char *regs, int bpp, int colormode,
int pixelclock)
{
regs[0] = 0;
if (colormode == RGB16_555)
regs[0] = 0xA0;
if (colormode == RGB16_565)
regs[0] = 0xC0;
if (colormode == RGB24_888_B)
regs[0] = 0xE0;
}
 
static void att20c490_qualify_cardspecs(CardSpecs * cardspecs, int dacspeed)
{
dacspeed = __svgalib_setDacSpeed(dacspeed, 80000);
cardspecs->maxPixelClock4bpp = dacspeed;
cardspecs->maxPixelClock8bpp = dacspeed;
cardspecs->maxPixelClock16bpp = dacspeed / 2;
cardspecs->maxPixelClock24bpp = dacspeed / 3;
cardspecs->maxPixelClock32bpp = 0;
cardspecs->mapClock = __svgalib_att20c490_map_clock;
cardspecs->mapHorizontalCrtc = __svgalib_att20c490_map_horizontal_crtc;
}
 
DacMethods __svgalib_ATT20C490_methods =
{
ATT20C490,
"AT&T-compatible truecolor DAC, 80 MHz rated",
0,
att20c490_probe,
att20c490_init,
att20c490_qualify_cardspecs,
__svgalib_Sierra_32K_savestate,
__svgalib_Sierra_32K_restorestate,
att20c490_initializestate,
1 /* State size. */
};
#endif
 
/*
* RAMDAC definition for industry-standard AT&T20C498 DAC with 16-bit
* pixel port, and compatibles.
* Differently rated versions exist, such as 80, 110, 135 and 170 MHz.
* This code assumes the DAC is actually connected with a 16-bit path.
* (an example of a 498-compatible DAC being used with a 8-bit path
* is the Hercules Stingray Pro/V with the IC Works ZoomDAC).
*/
 
#ifdef INCLUDE_ATT20C498_DAC_TEST
static int att20c498_probe(void)
{
return 0;
}
#else
#define att20c498_probe 0
#endif
 
#ifdef INCLUDE_ATT20C498_DAC
static void att20c498_init(void)
{
if (__svgalib_driver_report)
cprintf("svgalib: Using AT&T20C498-compatible DAC, 80 MHz rated.\n");
}
 
static int att20c498_map_clock(int bpp, int pixelclock)
{
if (bpp == 8 && pixelclock > 80000)
/* Use 16-bit path, clock doubling at RAMDAC. */
return pixelclock / 2;
if (bpp == 16)
return pixelclock;
if (bpp == 32)
return pixelclock * 2;
return pixelclock;
}
 
static int att20c498_map_horizontal_crtc(int bpp, int pixelclock, int htiming)
{
/* Not sure. */
if (bpp == 8 && pixelclock > 80000)
/* Use 16-bit path, clock doubling at RAMDAC. */
return htiming / 2;
if (bpp == 32)
return htiming * 2;
return htiming;
}
 
static void att20c498_initializestate(unsigned char *regs, int bpp, int colormode,
int pixelclock)
{
regs[0] = 0;
if (colormode == CLUT8_8)
regs[0] = 0x02;
if (colormode == RGB16_555)
regs[0] = 0x10;
if (colormode == RGB16_565)
regs[0] = 0x30;
if (colormode == RGB32_888_B)
regs[0] = 0x50;
}
 
static void att20c498_qualify_cardspecs(CardSpecs * cardspecs, int dacspeed)
{
dacspeed = __svgalib_setDacSpeed(dacspeed, 110000);
cardspecs->maxPixelClock4bpp = 0;
cardspecs->maxPixelClock8bpp = dacspeed;
cardspecs->maxPixelClock16bpp = dacspeed;
cardspecs->maxPixelClock24bpp = 0;
cardspecs->maxPixelClock32bpp = dacspeed / 2;
cardspecs->mapClock = att20c498_map_clock;
cardspecs->mapHorizontalCrtc = att20c498_map_horizontal_crtc;
}
 
DacMethods __svgalib_ATT20C498_methods =
{
ATT20C498,
"AT&T20C498 DAC",
0,
att20c498_probe,
att20c498_init,
att20c498_qualify_cardspecs,
__svgalib_Sierra_32K_savestate,
__svgalib_Sierra_32K_restorestate,
att20c498_initializestate,
1 /* State size. */
};
#endif
/shark/tags/rel_0_5/drivers/svga/sierra.c
0,0 → 1,368
/*
* sierra.c:
*
* RAMDAC definition for basic Sierra, SC15025 and SC1148x.
*/
 
#include <stdlib.h>
#include <stdio.h>
#include "libvga.h"
 
#include "timing.h"
#include "vgaregs.h"
#include "driver.h" /* for __svgalib_driver_report */
#include "ramdac.h"
 
/*
* RAMDAC definition for basic Sierra-type DAC
* that can do 32K (5-5-5) color mode (16bpp) with doubled VCLK.
* A value of 0x80 is written to the Hidden DAC register for this mode.
*/
 
#ifdef INCLUDE_SIERRA_DAC_TEST
static int Sierra_32K_probe(void)
{
/* Should return 1 for any Sierra-type DAC. */
return 0;
}
#else
#define Sierra_32K_probe 0
#endif
 
#ifdef INCLUDE_SIERRA_DAC
static void Sierra_32K_init(void)
{
/* Should probe the exact DAC type. */
if (__svgalib_driver_report)
cprintf("svgalib: Using Sierra 32K DAC.\n");
}
 
static int Sierra_32K_map_clock(int bpp, int pixelclock)
{
if (bpp == 16)
return pixelclock * 2;
return pixelclock;
}
 
static int Sierra_32K_map_horizontal_crtc(int bpp, int pixelclock, int htiming)
{
if (bpp == 16)
return htiming * 2;
return htiming;
}
#endif
 
#if defined(INCLUDE_SIERRA_DAC) || defined(INCLUDE_ICW_DAC) || \
defined(INCLUDE_ATT20C490_DAC) || defined(INCLUDE_ATT20C498_DAC)
void __svgalib_Sierra_32K_savestate(unsigned char *regs)
{
_ramdac_dactocomm();
regs[0] = inb(PEL_MSK);
}
 
void __svgalib_Sierra_32K_restorestate(const unsigned char *regs)
{
_ramdac_dactocomm();
outb(PEL_MSK, regs[0]);
}
 
#endif
 
#ifdef INCLUDE_SIERRA_DAC
static void Sierra_32K_initializestate(unsigned char *regs, int bpp, int colormode,
int pixelclock)
{
regs[0] = 0;
if (colormode == RGB16_555)
regs[0] = 0x80;
}
 
static void Sierra_32K_qualify_cardspecs(CardSpecs * cardspecs, int dacspeed)
{
dacspeed = __svgalib_setDacSpeed(dacspeed, 80000);
cardspecs->maxPixelClock4bpp = dacspeed;
cardspecs->maxPixelClock8bpp = dacspeed;
cardspecs->maxPixelClock16bpp = dacspeed / 2;
cardspecs->maxPixelClock24bpp = 0;
cardspecs->maxPixelClock32bpp = 0;
cardspecs->mapClock = Sierra_32K_map_clock;
cardspecs->mapHorizontalCrtc = Sierra_32K_map_horizontal_crtc;
cardspecs->flags |= NO_RGB16_565;
}
 
DacMethods __svgalib_Sierra_32K_methods =
{
SIERRA_32K,
"Sierra 32K colors VGA DAC",
0,
Sierra_32K_probe,
Sierra_32K_init,
Sierra_32K_qualify_cardspecs,
__svgalib_Sierra_32K_savestate,
__svgalib_Sierra_32K_restorestate,
Sierra_32K_initializestate,
1 /* State size. */
};
#endif
 
 
/*
* RAMDAC definition for Sierra 15025/26
*/
 
#ifdef INCLUDE_SC15025_DAC_TEST
static unsigned char SC15025_Rev;
 
static int SC15025_probe(void)
{
unsigned char c, id[4];
int i, flag = 0;
 
_ramdac_dactocomm();
c = inb(PEL_MSK);
_ramdac_setcomm(c | 0x10);
for (i = 0; i < 4; i++) {
outb(PEL_IR, 0x9 + i);
id[i] = inb(PEL_IW);
}
_ramdac_setcomm(c);
_ramdac_dactopel();
if (id[0] == 'S' && /* Sierra */
((id[1] << 8) | id[2]) == 15025) { /* unique for the SC 15025/26 */
flag = 1;
SC15025_Rev = id[3];
}
return flag;
}
#else
#define SC15025_probe 0
#define SC15025_Rev ' '
#endif
 
#ifdef INCLUDE_SC15025_DAC
static void SC15025_init(void)
{
if (__svgalib_driver_report)
cprintf("svgalib: Using Sierra 15025/26%c truecolor DAC.\n", SC15025_Rev);
}
 
static void SC15025_initializestate(unsigned char *regs, int bpp, int colormode,
int pixelclock)
{
regs[0] = 0;
regs[1] = 0;
regs[2] = 0;
if (colormode == RGB16_555) {
regs[0] = 0x80;
regs[1] = 1;
} else if (colormode == RGB16_565) {
regs[0] = 0xC0;
regs[1] = 1;
} else if (colormode == RGB32_888_B) {
regs[0] = 0x40;
regs[1] = 1;
regs[2] = 1;
}
/* ARI: FIXME: regs[1] should be 1 for CLUT8_8 */
/* also: OR 8 to regs[0] to enable gamma correction */
}
 
static void SC15025_savestate(unsigned char *regs)
{
_ramdac_dactocomm();
regs[0] = inb(PEL_MSK);
_ramdac_setcomm(regs[0] | 0x10);
_ramdac_dactocomm();
outb(PEL_IR, 8);
regs[1] = inb(PEL_IW); /* Aux control */
outb(PEL_IR, 16);
regs[2] = inb(PEL_IW); /* Pixel Repack */
_ramdac_setcomm(regs[0]);
}
 
static void SC15025_restorestate(const unsigned char *regs)
{
unsigned char c;
 
_ramdac_dactocomm();
c = inb(PEL_MSK);
_ramdac_setcomm(c | 0x10);
_ramdac_dactocomm();
outb(PEL_IR, 8);
outb(PEL_IW, regs[1]); /* Aux control */
outb(PEL_IR, 16);
outb(PEL_IW, regs[2]); /* Pixel Repack */
_ramdac_setcomm(c);
_ramdac_setcomm(regs[0]);
}
 
static int SC15025_map_clock(int bpp, int pixelclock)
{
if (bpp == 32)
return pixelclock * 2;
return pixelclock;
}
 
static int SC15025_map_horizontal_crtc(int bpp, int pixelclock, int htiming)
{
if (bpp == 16)
return htiming * 2;
if (bpp == 32)
return htiming * 4;
return htiming;
}
 
static void SC15025_qualify_cardspecs(CardSpecs * cardspecs, int dacspeed)
{
dacspeed = __svgalib_setDacSpeed(dacspeed, 110000);
cardspecs->maxPixelClock4bpp = dacspeed;
cardspecs->maxPixelClock8bpp = dacspeed;
cardspecs->maxPixelClock16bpp = dacspeed / 2;
cardspecs->maxPixelClock24bpp = 0;
cardspecs->maxPixelClock32bpp = dacspeed / 3;
cardspecs->mapClock = SC15025_map_clock;
cardspecs->mapHorizontalCrtc = SC15025_map_horizontal_crtc;
}
 
DacMethods __svgalib_SC15025_methods =
{
SIERRA_15025,
"Sierra SC15025/6 DAC",
0,
SC15025_probe,
SC15025_init,
SC15025_qualify_cardspecs,
SC15025_savestate,
SC15025_restorestate,
SC15025_initializestate,
3 /* State size. */
};
#endif
 
/*
* RAMDAC definition for Sierra 1148x Series.
* 11482, 83, and 84 (Mark 2) can do 32K (5-5-5) color mode (16bpp).
* 11485, 87, and 89 (Mark 3) additionally can do 64K (5-6-5) color mode,
* but are not autodetected since they cannot be distinguished from Mark 2.
* 11486 really is a Sierra 32K dac, and should have been set by user.
*
* Note that these dacs are different from 'Sierra 32K', since they can be
* detected as such, while there are clones that work compatible to the
* Sierra dacs, but cannot be autodetected. To avoid such dacs to fail
* the type 'Sierra 32K' still refers to them, while this new type
* 'SC1148x Series' refers to original Sierra dacs.
*
* ATTENTION: THIS TEST MUST BE LAST IN CHAIN, SINCE MANY BETTER DACS
* IMPLEMENT 32K MODES COMPATIBLE TO THIS ONE AND WOULD BE DETECTED AS
* SIERRA!
*
*/
 
#ifdef INCLUDE_SC1148X_DAC_TEST
static int SC1148X_probe(void)
{
unsigned char oc, op, tmp, tmp2;
int flag = 0;
 
_ramdac_dactopel();
tmp = inb(PEL_MSK);
do {
tmp2 = tmp;
tmp = inb(PEL_MSK);
} while (tmp2 != tmp);
inb(PEL_IW);
inb(PEL_MSK);
inb(PEL_MSK);
inb(PEL_MSK);
for (tmp2 = 9; tmp != 0x8E && tmp2 > 0; tmp2--)
tmp = inb(PEL_MSK);
if (tmp != 0x8E) {
_ramdac_dactocomm();
oc = inb(PEL_MSK);
_ramdac_dactopel();
op = inb(PEL_MSK);
tmp = oc ^ 0xFF;
outb(PEL_MSK, tmp);
_ramdac_dactocomm();
tmp2 = inb(PEL_MSK);
if (tmp2 != tmp) {
tmp = _ramdac_setcomm(tmp = oc ^ 0x60);
if ((tmp & 0xe0) == (tmp2 & 0xe0)) {
tmp = inb(PEL_MSK);
_ramdac_dactopel();
if (tmp != inb(PEL_MSK))
flag = 1; /* Sierra Mark 2 or 3 */
} else {
/* We have a Sierra SC11486 */
#ifdef INCLUDE_SIERRA_DAC
flag = 1;
/* We do some ugly trickery here to patch SC1148X Series
descriptor with values from Sierra 32K descriptor, since
this is what whe really have detected! */
__svgalib_SC1148X_methods.id = SIERRA_32K;
__svgalib_SC1148X_methods.name = __svgalib_Sierra_32K_methods.name;
__svgalib_SC1148X_methods.initialize = __svgalib_Sierra_32K_methods.initialize;
__svgalib_SC1148X_methods.qualifyCardSpecs = __svgalib_Sierra_32K_methods.qualifyCardSpecs ;
__svgalib_SC1148X_methods.initializeState = __svgalib_Sierra_32K_methods.initializeState ;
#endif
}
_ramdac_dactocomm();
outb(PEL_MSK, oc);
}
_ramdac_dactopel();
outb(PEL_MSK, op);
} else {
_ramdac_dactopel();
/* Diamond SS2410 */
}
return flag;
}
#else
#define SC1148x_probe 0
#endif
 
#ifdef INCLUDE_SC1148X_DAC
static void SC1148X_init(void)
{
if (__svgalib_driver_report)
cprintf("svgalib: Using Sierra 1148x series 32K DAC.\n");
}
 
static void SC1148X_initializestate(unsigned char *regs, int bpp, int colormode,
int pixelclock)
{
regs[0] = 0;
if (colormode == RGB16_555)
regs[0] = 0xA0;
/* Mark 3 (not autodetected) */
else if (colormode == RGB16_565)
regs[0] = 0xE0;
}
 
static void SC1148X_qualify_cardspecs(CardSpecs * cardspecs, int dacspeed)
{
dacspeed = __svgalib_setDacSpeed(dacspeed, 110000);
cardspecs->maxPixelClock4bpp = dacspeed;
cardspecs->maxPixelClock8bpp = dacspeed;
cardspecs->maxPixelClock16bpp = dacspeed / 2;
cardspecs->maxPixelClock24bpp = 0;
cardspecs->maxPixelClock32bpp = 0;
cardspecs->mapClock = Sierra_32K_map_clock;
cardspecs->mapHorizontalCrtc = Sierra_32K_map_horizontal_crtc;
cardspecs->flags |= NO_RGB16_565; /* Mark 3 (11485,87, and higher) can */
}
 
DacMethods __svgalib_SC1148X_methods =
{
SIERRA_1148X,
"Sierra SC1148x series 32K colors VGA DAC",
0,
SC1148X_probe,
SC1148X_init,
SC1148X_qualify_cardspecs,
__svgalib_Sierra_32K_savestate,
__svgalib_Sierra_32K_restorestate,
SC1148X_initializestate,
1 /* State size. */
};
#endif
/shark/tags/rel_0_5/drivers/svga/vgamisc.c
0,0 → 1,95
/* VGAlib version 1.2 - (c) 1993 Tommy Frandsen */
/* */
/* This library is free software; you can redistribute it and/or */
/* modify it without any restrictions. This library is distributed */
/* in the hope that it will be useful, but without any warranty. */
 
/* Multi-chipset support Copyright 1993 Harm Hanemaayer */
/* partially copyrighted (C) 1993 by Hartmut Schirmer */
 
#include <stdlib.h>
 
#include "vga.h"
#include "libvga.h"
#include "driver.h"
#include "svgalib_helper.h"
 
vga_cardinfo *vga_getcardinfo(void) {
vga_cardinfo *vci;
vci = malloc(sizeof(vga_cardinfo));
if(vci==NULL) return vci;
vci->version = 0x100;
vci->size = sizeof(vga_cardinfo);
vci->chipset = __svgalib_chipset;
vci->physmem = __svgalib_linear_mem_base;
return vci;
}
 
void vga_waitretrace(void)
{
if (__svgalib_driverspecs->emul && __svgalib_driverspecs->emul->waitretrace) {
__svgalib_driverspecs->emul->waitretrace();
} else {
while (!(__svgalib_inis1() & 8));
while (__svgalib_inis1() & 8);
}
}
 
static void *__svgalib_linearframebuffer;
/*
* The way IS_LINEAR gets indicated is rather convoluted; if the driver
* has EXT_INFO_AVAILABLE, setlinearaddressing will enable
* the flag in __svgalib_linearset which gets set in the modeinfo by
* vga_getmodeinfo(). The driver must turn off the flag in
* __svgalib_linearset if linear addressing gets disabled (e.g. when
* setting another mode).
*
* For any driver, the chipset getmodeinfo flag can examine a hardware
* register and set the IS_LINEAR flag if linear addressing is enabled.
*/
 
unsigned char *
vga_getgraphmem(void)
{
 
DTP(("getgraphmem\n"));
 
if (__svgalib_modeinfo_linearset & LINEAR_MODE )
return __svgalib_linearframebuffer;
return GM;
}
 
/*
* This function is to be called after a SVGA graphics mode set
* in banked mode. Probing in VGA-compatible textmode is not a good
* idea.
*/
 
/* cf. vga_waitretrace, M.Weller */
int vga_setlinearaddressing(void)
{
int (*lfn) (int op, int param) = __svgalib_driverspecs->linear;
vga_modeinfo *modeinfo;
 
printk(KERN_INFO "Setlinearaddressing\n");
 
modeinfo = vga_getmodeinfo(CM);
if (!(modeinfo->flags&CAPABLE_LINEAR)) return -1;
 
(*lfn) (LINEAR_ENABLE, 0);
__svgalib_linearframebuffer = LINEAR_POINTER;
 
if ((long) __svgalib_linearframebuffer == -1) {
/* Shouldn't happen. */
(*lfn) (LINEAR_DISABLE, 0);
return -1;
}
__svgalib_modeinfo_linearset |= IS_LINEAR | LINEAR_MODE;
 
graph_mem = LINEAR_POINTER;
 
return __svgalib_linear_mem_size; /* Who cares? */
}
/shark/tags/rel_0_5/drivers/svga/makefile.cfg
0,0 → 1,21
#MAJOR_VER = 1
#MINOR_VER = 9.17
 
INCLUDE_S3_SDAC_DAC = y
INCLUDE_S3_GENDAC_DAC = y
INCLUDE_S3_TRIO64_DAC = y
INCLUDE_SIERRA_DAC = y
INCLUDE_SC15025_DAC = y
INCLUDE_ATT20C490_DAC = y
INCLUDE_ATT20C498_DAC = y
INCLUDE_ICW_DAC = y
INCLUDE_IBMRGB52x_DAC = y
INCLUDE_SC1148X_DAC = y
INCLUDE_ICS_GENDAC_DAC = y
INCLUDE_S3_GENDAC_DAC_TEST = y
INCLUDE_SC15025_DAC_TEST = y
INCLUDE_ATT20C490_DAC_TEST = y
INCLUDE_IBMRGB52x_DAC_TEST = y
INCLUDE_SC1148X_DAC_TEST = y
INCLUDE_ICS_GENDAC_DAC_TEST = y
 
/shark/tags/rel_0_5/drivers/svga/btdacs.c
0,0 → 1,109
/*
* btdacs.c:
*
* RAMDAC definition for Bt485
*
* NON-FUNCTIONAL
*/
 
#include <stdlib.h>
#include <stdio.h>
#include "libvga.h"
 
#include "timing.h"
#include "vgaregs.h"
#include "driver.h" /* for __svgalib_driver_report */
#include "ramdac.h"
 
/*
* RAMDAC definition for industry-standard AT&T20C498 DAC with 16-bit
* pixel port, and compatibles.
* Differently rated versions exist, such as 80, 110, 135 and 170 MHz.
* This code assumes the DAC is actually connected with a 16-bit path.
* (an example of a 498-compatible DAC being used with a 8-bit path
* is the Hercules Stingray Pro/V with the IC Works ZoomDAC).
*/
 
#ifdef INCLUDE_BT485_DAC_TEST
static int bt485_probe(void)
{
return 0;
}
#else
#define bt485_probe 0
#endif
 
#ifdef INCLUDE_BT485_DAC
static void bt485_init(void)
{
if (__svgalib_driver_report)
cprintf("svgalib: Using BT485 DAC, 135 MHz rated.\n");
}
 
static int bt485_map_clock(int bpp, int pixelclock)
{
return pixelclock;
if (bpp == 8 && pixelclock > 80000)
/* Use 16-bit path, clock doubling at RAMDAC. */
return pixelclock / 2;
if (bpp == 16)
return pixelclock;
if (bpp == 32)
return pixelclock * 2;
return pixelclock;
}
 
static int bt485_map_horizontal_crtc(int bpp, int pixelclock, int htiming)
{
return htiming
 
/* Not sure. */
if (bpp == 8 && pixelclock > 80000)
/* Use 16-bit path, clock doubling at RAMDAC. */
return htiming / 2;
if (bpp == 32)
return htiming * 2;
return htiming;
}
 
static void bt485_initializestate(unsigned char *regs, int bpp, int colormode,
int pixelclock)
{
regs[0] = 0;
if (colormode == CLUT8_8)
regs[0] = 0x02;
if (colormode == RGB16_555)
regs[0] = 0x10;
if (colormode == RGB16_565)
regs[0] = 0x30;
if (colormode == RGB32_888_B)
regs[0] = 0x50;
}
 
static void 485_qualify_cardspecs(CardSpecs * cardspecs, int dacspeed)
{
dacspeed = __svgalib_setDacSpeed(dacspeed, 135000);
cardspecs->maxPixelClock4bpp = 0;
cardspecs->maxPixelClock8bpp = dacspeed;
cardspecs->maxPixelClock16bpp = dacspeed;
cardspecs->maxPixelClock24bpp = 0;
cardspecs->maxPixelClock32bpp = dacspeed ;
cardspecs->mapClock = bt485_map_clock;
cardspecs->mapHorizontalCrtc = att20c498_map_horizontal_crtc;
}
 
DacMethods __svgalib_BT485_methods =
{
BT485,
"BT485 DAC",
0,
bt485_probe,
bt485_init,
bt485_qualify_cardspecs,
__svgalib_Sierra_32K_savestate,
__svgalib_Sierra_32K_restorestate,
bt485_initializestate,
1 /* State size. */
};
#endif
/shark/tags/rel_0_5/drivers/svga/IBMRGB52x.c
0,0 → 1,405
/*
* IBMRGB52x.c:
*
* RAMDAC definitions for IBM's RGB52x PaletteDAC.
*
* Portion of this file is derived from XFree86's source code.
* [insert XFree86's copyright here].
*/
 
#include <stdio.h>
#include "libvga.h"
 
#include "timing.h"
#include "vgaregs.h"
#include "driver.h" /* for __svgalib_driver_report */
#include "ramdac.h"
 
#include "IBMRGB52x.h"
 
#define IBMRGB52x_STATESIZE 0x101
 
static int IBMRGB52x_dacspeed = 170000; /* assuming 170MHz DAC */
static int IBMRGB52x_fref = 16000; /* assuming 16MHz refclock */
static int IBMRGB52x_clk = 2; /* use clock 2 */
 
#ifdef INCLUDE_IBMRGB52x_DAC_TEST
/*
* s3IBMRGB_Probe() from XFree86.
*
* returns 0x01xx for 525, 0x02xx for 524/528, where xx = revision.
*/
static int IBMRGB52x_probe(void)
{
unsigned char CR43, CR55, dac[3], lut[6];
unsigned char ilow, ihigh, id, rev, id2, rev2;
int i, j;
int ret = 0;
 
port_out(0x43, 0x3D4);
CR43 = port_in(0x3D5);
port_out(CR43 & ~0x02, 0x3D5);
 
port_out(0x55, 0x3D4);
CR55 = port_in(0x3D5);
port_out(CR55 & ~0x03, 0x3D5);
 
/* save DAC and first LUT entries */
for (i = 0; i < 3; i++)
dac[i] = port_in(IBMRGB_PIXEL_MASK + i);
for (i = j = 0; i < 2; i++) {
port_out(i, IBMRGB_READ_ADDR);
lut[j++] = port_in(IBMRGB_RAMDAC_DATA);
lut[j++] = port_in(IBMRGB_RAMDAC_DATA);
lut[j++] = port_in(IBMRGB_RAMDAC_DATA);
}
 
port_out(0x55, 0x3D4);
port_out((CR55 & ~0x03) | 0x01, 0x3D5); /* set RS2 */
 
/* read ID and revision */
ilow = port_in(IBMRGB_INDEX_LOW);
ihigh = port_in(IBMRGB_INDEX_HIGH);
port_out(0, IBMRGB_INDEX_HIGH); /* index high */
port_out(IBMRGB_rev, IBMRGB_INDEX_LOW);
rev = port_in(IBMRGB_INDEX_DATA);
port_out(IBMRGB_id, IBMRGB_INDEX_LOW);
id = port_in(IBMRGB_INDEX_DATA);
 
/* known IDs:
1 = RGB525
2 = RGB524, RGB528
*/
 
if (id >= 1 && id <= 2) {
/* check if ID and revision are read only */
port_out(IBMRGB_rev, IBMRGB_INDEX_LOW);
port_out(~rev, IBMRGB_INDEX_DATA);
port_out(IBMRGB_id, IBMRGB_INDEX_LOW);
port_out(~id, IBMRGB_INDEX_DATA);
port_out(IBMRGB_rev, IBMRGB_INDEX_LOW);
rev2 = port_in(IBMRGB_INDEX_DATA);
port_out(IBMRGB_id, IBMRGB_INDEX_LOW);
id2 = port_in(IBMRGB_INDEX_DATA);
 
if (id == id2 && rev == rev2) { /* IBM RGB52x found */
ret = (id << 8) | rev;
} else {
port_out(IBMRGB_rev, IBMRGB_INDEX_LOW);
port_out(rev, IBMRGB_INDEX_DATA);
port_out(IBMRGB_id, IBMRGB_INDEX_LOW);
port_out(id, IBMRGB_INDEX_DATA);
}
}
port_out(ilow, IBMRGB_INDEX_LOW);
port_out(ihigh, IBMRGB_INDEX_HIGH);
 
port_out(0x55, 0x3D4);
port_out(CR55 & ~0x03, 0x3D5); /* reset RS2 */
 
/* restore DAC and first LUT entries */
for (i = j = 0; i < 2; i++) {
port_out(i, IBMRGB_WRITE_ADDR);
port_out(lut[j++], IBMRGB_RAMDAC_DATA);
port_out(lut[j++], IBMRGB_RAMDAC_DATA);
port_out(lut[j++], IBMRGB_RAMDAC_DATA);
}
for (i = 0; i < 3; i++)
port_out(dac[i], IBMRGB_PIXEL_MASK + i);
 
port_out(0x43, 0x3D4);
port_out(CR43, 0x3D5);
port_out(0x55, 0x3D4);
port_out(CR55, 0x3D5);
 
return ret;
}
#else
#define IBMRGB52x_probe 0
#endif
 
#ifdef INCLUDE_IBMRGB52x_DAC
static void IBMRGBSetClock(long freq, int clk, long dacspeed, long fref,
int *best_m_out, int *best_n_out, int *best_df_out)
{
volatile double ffreq, fdacspeed, ffref;
volatile int df, n, m, max_n, min_df;
volatile int best_m = 69, best_n = 17, best_df = 0;
volatile double diff, mindiff;
 
#define FREQ_MIN 16250 /* 1000 * (0+65) / 4 */
#define FREQ_MAX dacspeed
 
if (freq < FREQ_MIN)
ffreq = FREQ_MIN / 1000.0;
else if (freq > FREQ_MAX)
ffreq = FREQ_MAX / 1000.0;
else
ffreq = freq / 1000.0;
 
fdacspeed = dacspeed / 1e3;
ffref = fref / 1e3;
 
ffreq /= ffref;
ffreq *= 16;
mindiff = ffreq;
 
if (freq <= dacspeed / 4)
min_df = 0;
else if (freq <= dacspeed / 2)
min_df = 1;
else
min_df = 2;
 
for (df = 0; df < 4; df++) {
ffreq /= 2;
mindiff /= 2;
if (df < min_df)
continue;
 
/* the remaining formula is ffreq = (m+65) / n */
 
if (df < 3)
max_n = fref / 1000 / 2;
else
max_n = fref / 1000;
if (max_n > 31)
max_n = 31;
 
for (n = 2; n <= max_n; n++) {
m = (int) (ffreq * n + 0.5) - 65;
if (m < 0)
m = 0;
else if (m > 63)
m = 63;
 
diff = (m + 65.0) / n - ffreq;
if (diff < 0)
diff = -diff;
 
if (diff < mindiff) {
mindiff = diff;
best_n = n;
best_m = m;
best_df = df;
}
}
}
 
#ifdef DEBUG
cprintf("clk %d, setting to %f, m 0x%02x %d, n 0x%02x %d, df %d\n", clk,
((best_m + 65.0) / best_n) / (8 >> best_df) * ffref,
best_m, best_m, best_n, best_n, best_df);
#endif
*best_m_out = best_m;
*best_n_out = best_n;
*best_df_out = best_df;
}
 
static void IBMRGB52x_init(void)
{
unsigned char tmp, CR55;
#ifdef INCLUDE_IBMRGB52x_DAC_TEST
int idrev;
 
idrev = IBMRGB52x_probe();
if (__svgalib_driver_report)
cprintf("svgalib: Using IBM RGB 52%d PaletteDAC, revision %d.\n",
(idrev >> 8) == 1 ? 5 : 4,
idrev & 0xff);
#else
if (__svgalib_driver_report)
cprintf("svgalib: Using IBM RGB 52x PaletteDAC.\n");
#endif
/* set RS2 */
port_out(0x55, 0x3D4);
CR55 = port_in(0x3D5) & 0xFC;
port_out(CR55 | 0x01, 0x3D5);
 
tmp = port_in(IBMRGB_INDEX_CONTROL);
port_out(tmp & ~0x01, IBMRGB_INDEX_CONTROL); /* turn off auto-increment */
port_out(0, IBMRGB_INDEX_HIGH); /* reset index high */
 
__svgalib_outCR(0x55, CR55);
}
 
static int IBMRGB52x_match_programmable_clock(int desiredclock)
{
int m, n, df;
 
IBMRGBSetClock(desiredclock, IBMRGB52x_clk, IBMRGB52x_dacspeed,
IBMRGB52x_fref, &m, &n, &df);
 
return ((m + 65.0) / n) / (8 >> df) * IBMRGB52x_fref;
}
 
static void IBMRGB52x_initialize_clock_state(unsigned char *regs, int freq)
{
int m, n, df;
 
IBMRGBSetClock(freq, IBMRGB52x_clk, IBMRGB52x_dacspeed,
IBMRGB52x_fref, &m, &n, &df);
 
if (__svgalib_driver_report)
cprintf("clk %d, setting to %.3f, m 0x%02x %d, n 0x%02x %d, df %d\n",
IBMRGB52x_clk, ((m + 65.0) / n) / (8 >> df) * IBMRGB52x_fref / 1000,
m, m, n, n, df);
 
regs[IBMRGB_misc_clock] |= 0x01;
regs[IBMRGB_m0 + 2 * IBMRGB52x_clk] = (df << 6) | (m & 0x3f);
regs[IBMRGB_n0 + 2 * IBMRGB52x_clk] = n;
regs[IBMRGB_pll_ctrl2] &= 0xf0;
regs[IBMRGB_pll_ctrl2] |= IBMRGB52x_clk;
regs[IBMRGB_pll_ctrl1] &= 0xf8;
regs[IBMRGB_pll_ctrl1] |= 0x03;
}
 
static void IBMRGB52x_savestate(unsigned char *regs)
{
int i;
unsigned char tmp;
 
/* set RS2 */
port_out(0x55, 0x3D4);
tmp = port_in(0x3D5) & 0xFC;
port_out(tmp | 0x01, 0x3D5);
 
for (i = 0; i < 0x100; i++) {
port_out(i, IBMRGB_INDEX_LOW); /* high index is set to 0 */
regs[i] = port_in(IBMRGB_INDEX_DATA);
}
regs[0x100] = __svgalib_inCR(0x22);
 
__svgalib_outCR(0x55, tmp);
}
 
/* SL: not complete, need more work for 525. */
static void IBMRGB52x_restorestate(const unsigned char *regs)
{
int i;
unsigned char tmp;
 
/* set RS2 */
port_out(0x55, 0x3D4);
tmp = port_in(0x3D5) & 0xFC;
port_out(tmp | 0x01, 0x3D5);
 
for (i = 0; i < 0x100; i++) {
port_out(i, IBMRGB_INDEX_LOW); /* high index is set to 0 */
port_out(regs[i], IBMRGB_INDEX_DATA);
}
__svgalib_outCR(0x22, regs[0x100]);
 
__svgalib_outCR(0x55, tmp);
}
 
static int IBMRGB52x_map_clock(int bpp, int pixelclock)
{
return pixelclock;
}
 
static int IBMRGB52x_map_horizontal_crtc(int bpp, int pixelclock, int htiming)
{
#ifdef PIXEL_MULTIPLEXING
switch (bpp) {
case 4:
break;
case 8:
return htiming / 2;
case 16:
break;
case 24:
return htiming * 3 / 2;
case 32:
return htiming * 2;
}
#endif
return htiming;
}
 
static void IBMRGB52x_initializestate(unsigned char *regs, int bpp, int colormode,
int pixelclock)
{
unsigned char tmp;
 
regs[IBMRGB_misc_clock] = (regs[IBMRGB_misc_clock] & 0xf0) | 0x03;
regs[IBMRGB_sync] = 0;
regs[IBMRGB_hsync_pos] = 0;
regs[IBMRGB_pwr_mgmt] = 0;
regs[IBMRGB_dac_op] &= ~0x08; /* no sync on green */
regs[IBMRGB_dac_op] |= 0x02; /* fast slew */
regs[IBMRGB_pal_ctrl] = 0;
regs[IBMRGB_misc1] &= ~0x43;
regs[IBMRGB_misc1] |= 1;
#ifdef PIXEL_MULTIPLEXING
if (bpp >= 8)
regs[IBMRGB_misc2] = 0x43; /* use SID bus? 0x47 for DAC_8_BIT */
#endif
tmp = __svgalib_inCR(0x22);
if (bpp <= 8) /* and 968 */
__svgalib_outCR(0x22, tmp | 0x08);
else
__svgalib_outCR(0x22, tmp & ~0x08);
 
regs[IBMRGB_pix_fmt] &= ~0x07;
switch (bpp) {
case 4:
case 8:
regs[IBMRGB_pix_fmt] |= 0x03;
regs[IBMRGB_8bpp] = 0x00;
break;
case 15:
regs[IBMRGB_pix_fmt] |= 0x04;
regs[IBMRGB_16bpp] = 0x02;
break;
case 16:
regs[IBMRGB_pix_fmt] |= 0x04;
regs[IBMRGB_16bpp] = 0x00;
break;
case 24:
regs[IBMRGB_pix_fmt] |= 0x05; /* SL: guess */
regs[IBMRGB_24bpp] = 0x00;
break;
case 32:
regs[IBMRGB_pix_fmt] |= 0x06;
regs[IBMRGB_32bpp] = 0x00;
break;
}
IBMRGB52x_initialize_clock_state(regs,
IBMRGB52x_map_clock(bpp, pixelclock));
}
 
static void IBMRGB52x_qualify_cardspecs(CardSpecs * cardspecs, int dacspeed)
{
IBMRGB52x_dacspeed = __svgalib_setDacSpeed(dacspeed, 170000); /* 220 MHz version exist also */
cardspecs->maxPixelClock4bpp = IBMRGB52x_dacspeed;
cardspecs->maxPixelClock8bpp = IBMRGB52x_dacspeed;
#ifdef PIXEL_MULTIPLEXING
cardspecs->maxPixelClock16bpp = IBMRGB52x_dacspeed;
cardspecs->maxPixelClock24bpp = IBMRGB52x_dacspeed * 3 / 2;
cardspecs->maxPixelClock32bpp = IBMRGB52x_dacspeed / 2;
#else
cardspecs->maxPixelClock16bpp = 0;
cardspecs->maxPixelClock24bpp = 0;
cardspecs->maxPixelClock32bpp = 0;
#endif
cardspecs->mapClock = IBMRGB52x_map_clock;
cardspecs->matchProgrammableClock = IBMRGB52x_match_programmable_clock;
cardspecs->mapHorizontalCrtc = IBMRGB52x_map_horizontal_crtc;
cardspecs->flags |= CLOCK_PROGRAMMABLE;
}
 
DacMethods __svgalib_IBMRGB52x_methods =
{
IBMRGB52x,
"IBM RGB 52x PaletteDAC",
DAC_HAS_PROGRAMMABLE_CLOCKS,
IBMRGB52x_probe,
IBMRGB52x_init,
IBMRGB52x_qualify_cardspecs,
IBMRGB52x_savestate,
IBMRGB52x_restorestate,
IBMRGB52x_initializestate,
IBMRGB52x_STATESIZE
};
#endif
/shark/tags/rel_0_5/drivers/svga/libvga.h
0,0 → 1,285
 
/* SVGAlib, Copyright 1993 Harm Hanemaayer */
/* VGAlib version 1.2 - (c) 1993 Tommy Frandsen */
/* partially copyrighted (C) 1993 by Hartmut Schirmer */
 
/* Internal definitions. */
 
#ifndef _LIBVGA_H
#define _LIBVGA_H
 
#include <string.h>
 
#include <stdint.h>
#include "ll/sys/cdefs.h"
 
__BEGIN_DECLS
 
//typedef unsigned int CARD32;
//typedef unsigned short CARD16;
//typedef unsigned char CARD8;
 
/* --------------------- Macro definitions shared by library modules */
 
/* VGA index register ports */
#define CRT_IC 0x3D4 /* CRT Controller Index - color emulation */
#define CRT_IM 0x3B4 /* CRT Controller Index - mono emulation */
#define ATT_IW 0x3C0 /* Attribute Controller Index & Data Write Register */
#define GRA_I 0x3CE /* Graphics Controller Index */
#define SEQ_I 0x3C4 /* Sequencer Index */
#define PEL_IW 0x3C8 /* PEL Write Index */
#define PEL_IR 0x3C7 /* PEL Read Index */
 
/* VGA data register ports */
#define CRT_DC 0x3D5 /* CRT Controller Data Register - color emulation */
#define CRT_DM 0x3B5 /* CRT Controller Data Register - mono emulation */
#define ATT_R 0x3C1 /* Attribute Controller Data Read Register */
#define GRA_D 0x3CF /* Graphics Controller Data Register */
#define SEQ_D 0x3C5 /* Sequencer Data Register */
#define MIS_R 0x3CC /* Misc Output Read Register */
#define MIS_W 0x3C2 /* Misc Output Write Register */
#define IS1_RC 0x3DA /* Input Status Register 1 - color emulation */
#define IS1_RM 0x3BA /* Input Status Register 1 - mono emulation */
#define PEL_D 0x3C9 /* PEL Data Register */
#define PEL_MSK 0x3C6 /* PEL mask register */
 
/* 8514/MACH regs we need outside of the mach32 driver.. */
#define PEL8514_D 0x2ED
#define PEL8514_IW 0x2EC
#define PEL8514_IR 0x2EB
#define PEL8514_MSK 0x2EA
 
/* EGA-specific registers */
 
#define GRA_E0 0x3CC /* Graphics enable processor 0 */
#define GRA_E1 0x3CA /* Graphics enable processor 1 */
 
/* standard VGA indexes max counts */
#define CRT_C 24 /* 24 CRT Controller Registers */
#define ATT_C 21 /* 21 Attribute Controller Registers */
#define GRA_C 9 /* 9 Graphics Controller Registers */
#define SEQ_C 5 /* 5 Sequencer Registers */
#define MIS_C 1 /* 1 Misc Output Register */
 
/* VGA registers saving indexes */
#define CRT 0 /* CRT Controller Registers start */
#define ATT (CRT+CRT_C) /* Attribute Controller Registers start */
#define GRA (ATT+ATT_C) /* Graphics Controller Registers start */
#define SEQ (GRA+GRA_C) /* Sequencer Registers */
#define MIS (SEQ+SEQ_C) /* General Registers */
#define EXT (MIS+MIS_C) /* SVGA Extended Registers */
 
/* Shorthands for chipset (driver) specific calls */
#define chipset_saveregs __svgalib_driverspecs->saveregs
#define chipset_setregs __svgalib_driverspecs->setregs
#define chipset_unlock __svgalib_driverspecs->unlock
#define chipset_test __svgalib_driverspecs->test
#define chipset_setpage __svgalib_driverspecs->__svgalib_setpage
#define chipset_setmode __svgalib_driverspecs->setmode
#define chipset_modeavailable __svgalib_driverspecs->modeavailable
#define chipset_getmodeinfo __svgalib_driverspecs->getmodeinfo
#define chipset_cursor __svgalib_driverspecs->cursor
 
/* Shorthands for internal variables and functions */
#define CI __svgalib_cur_info
#define SM __svgalib_sparse_mem
#define GM __svgalib_graph_mem
#define CM __svgalib_cur_mode
#define VMEM __svgalib_videomemoryused
#define DREP __svgalib_driver_report
#define CRITICAL __svgalib_critical
#define COL __svgalib_cur_color
#define CHIPSET __svgalib_chipset
#define SCREENON __svgalib_screenon
#define MODEX __svgalib_modeX
#define MODEFLAGS __svgalib_modeflags
#define infotable __svgalib_infotable
 
#define SVGADRV 2
#define STDVGADRV 1
#define STDVGAMODE(mode) (chipset_modeavailable(mode) == STDVGADRV)
#define SVGAMODE(mode) (chipset_modeavailable(mode) == SVGADRV)
 
#define GRAPH_BASE 0xA0000
#define FONT_BASE 0xA0000
#define GRAPH_SIZE 0x10000
#define FONT_SIZE (0x2000 * 4) /* 2.0.x kernel can use 2 512 char. fonts */
#define GPLANE16 G640x350x16
 
/* graphics mode information */
struct info {
int xdim;
int ydim;
int colors;
int xbytes;
int bytesperpixel;
};
 
/* --------------------- Variable definitions shared by library modules */
 
#define BANKED_POINTER __svgalib_banked_pointer
#define LINEAR_POINTER __svgalib_linear_pointer
#define MMIO_POINTER __svgalib_mmio_pointer
 
extern int __svgalib_CRT_I; /* current CRT index register address */
extern int __svgalib_CRT_D; /* current CRT data register address */
extern int __svgalib_IS1_R; /* current input status register address */
extern uint8_t * BANKED_POINTER, * LINEAR_POINTER;
extern uint8_t *MMIO_POINTER;
extern uint8_t *SPARSE_MMIO;
extern unsigned long __svgalib_banked_mem_base, __svgalib_banked_mem_size;
extern unsigned long __svgalib_mmio_base, __svgalib_mmio_size;
extern unsigned long __svgalib_linear_mem_base, __svgalib_linear_mem_size;
extern unsigned long __svgalib_mmio_base, __svgalib_mmio_size;
extern struct info CI; /* current video parameters */
extern int COL; /* current color */
extern int CM; /* current video mode */
extern struct info infotable[];
extern int SCREENON; /* screen visible if != 0 */
extern unsigned long __svgalib_graph_base;
extern unsigned char *GM; /* graphics memory frame */
extern int MODEX; /* TRUE after vga_setmodeX() */
extern int MODEFLAGS; /* copy of flags of current modeinfo->flags */
 
extern int __svgalib_mem_fd;
extern int __svgalib_tty_fd;
extern int __svgalib_nosigint;
extern int __svgalib_mouse_fd;
extern int __svgalib_kbd_fd;
extern int __svgalib_runinbackground;
extern int __svgalib_vgacolormode;
 
extern unsigned char __svgalib_novga;
extern unsigned char __svgalib_textprog;
extern unsigned char __svgalib_secondary;
extern unsigned char __svgalib_emulatepage;
extern unsigned char __svgalib_novccontrol;
extern unsigned char __svgalib_m_ignore_dx;
extern unsigned char __svgalib_m_ignore_dy;
extern unsigned char __svgalib_m_ignore_dz;
 
extern char *__joystick_devicenames[4];
 
extern int __svgalib_cursor_status;
 
/* --------------------- Function definitions shared by library modules */
 
extern int (*__svgalib_inmisc)(void);
extern void (*__svgalib_outmisc)(int);
extern int (*__svgalib_incrtc)(int);
extern void (*__svgalib_outcrtc)(int,int);
extern int (*__svgalib_inseq)(int);
extern void (*__svgalib_outseq)(int,int);
extern int (*__svgalib_ingra)(int);
extern void (*__svgalib_outgra)(int,int);
extern int (*__svgalib_inatt)(int);
extern void (*__svgalib_outatt)(int,int);
extern void (*__svgalib_attscreen)(int);
extern void (*__svgalib_inpal)(int,int*,int*,int*);
extern void (*__svgalib_outpal)(int,int,int,int);
extern int (*__svgalib_inis1)(void);
 
extern int __svgalib_setregs(const unsigned char *regs);
extern int __svgalib_saveregs(unsigned char *regs);
extern void __svgalib_dumpregs(const unsigned char regs[], int n);
extern void __svgalib_get_perm(void);
extern int __svgalib_getchipset(int set_chipset);
extern int __svgalib_name2number(char *modename);
extern void __svgalib_delay(void);
extern int __svgalib_addmode(int xdim, int ydim, int cols, int xbytes, int bytespp);
extern void __svgalib_waitvtactive(void);
extern void __svgalib_open_devconsole(void);
extern void (*__svgalib_mouse_eventhandler) (int, int, int, int, int, int, int);
extern void (*__svgalib_keyboard_eventhandler) (int, int);
extern void __joystick_flip_vc(int acquire);
extern char *__svgalib_TextProg_argv[16]; /* should be enough */
extern char *__svgalib_TextProg;
extern int __svgalib_VESA_savebitmap;
extern int __svgalib_VESA_textmode;
extern unsigned char __svgalib_vesatext;
extern int __svgalib_mapkeyname(const char *keyname);
extern void __svgalib_mouse_update_keymap(void);
extern int __svgalib_vgacolor(void);
extern void __svgalib_cursor_restore(void);
extern void map_mmio(void);
extern void map_mem(void);
extern void map_linear(unsigned long, unsigned long);
extern void unmap_linear(unsigned long);
extern void __svgalib_emul_setpage(int);
 
#if 0
/* remove this part ? */
extern void __svgalib_releasevt_signal(int n);
extern void __svgalib_acquirevt_signal(int n);
#endif
 
#define gr_readb(off) (((volatile uint8_t *)GM)[(off)])
#define gr_readw(off) (*(volatile uint16_t*)((GM)+(off)))
#define gr_readl(off) (*(volatile uint32_t*)((GM)+(off)))
#define gr_writeb(v,off) (GM[(off)] = (v))
#define gr_writew(v,off) (*(uint16_t*)((GM)+(off)) = (v))
#define gr_writel(v,off) (*(uint32_t*)((GM)+(off)) = (v))
 
extern void port_out(int value, int port);
extern void port_outw(int value, int port);
extern void port_outl(int value, int port);
extern void port_rep_outb(unsigned char* string, int length, int port);
 
extern int port_in(int port);
extern int port_inw(int port);
extern int port_inl(int port);
 
/* Note that the arguments of outb/w are reversed compared with the */
/* kernel sources. The XFree86 drivers also use this format. */
#undef inb
#undef inw
#undef inl
#undef outb
#undef outw
#undef outl
 
#define inb port_in
#define inw port_inw
#define inl port_inl
#define outb(port, value) port_out(value, port)
#define outw(port, value) port_outw(value, port)
#define outl(port, value) port_outl(value, port)
 
/* Background things */
 
extern unsigned char *__svgalib_give_graph_red(void);
extern unsigned char *__svgalib_give_graph_green(void);
extern unsigned char *__svgalib_give_graph_blue(void);
#define zero_sa_mask(maskptr) memset(maskptr, 0, sizeof(sigset_t))
 
#if 1
 
#define SVGALIB_ACQUIRE_SIG SIGUSR2
#define SVGALIB_RELEASE_SIG SIGUSR1
 
#else
 
#define SVGALIB_ACQUIRE_SIG SIGUNUSED
#define SVGALIB_RELEASE_SIG SIGPROF
 
#endif
 
//#define DEBUG_TRACE
 
#ifdef DEBUG_TRACE
#define DTP(x) cprintf x
#else
#define DTP(x)
#endif
 
#ifdef DEBUG
#define DPRINTF cprintf
#else
#define DPRINTF
#endif
 
__END_DECLS
 
#endif /* _LIBVGA_H */
 
/shark/tags/rel_0_5/drivers/svga/icd2061a.c
0,0 → 1,283
/*
* icd2061a.c
*
* support for the ICD 2061A programmable clockchip and compatibles
* outside of the DAC
*
* Rev history:
* Andreas Arens Dec 95: Created
*
* Andreas Arens Feb 15 1996: A few minor fixes
*/
 
#include "timing.h"
#include "libvga.h"
#include "ramdac.h"
#include "clockchip.h"
#include "driver.h"
#include "vga.h"
 
/*
* ATTENTION: The ICD 2061A does not support reading of the currently selected
* pixelclock. XFree86 also fails to restore this value correctly, but always
* estores a 45 MHz pixelclock. My standard text mode (132x25) uses 40 MHz,
* which is the value selected here.
* You can use the SVGATextMode-1.0 'clockprobe' tool right after boot to
* determine the value used with your card and modify here, but since 40 MHz
* is the VESA suggested pixelclock for a 70 Hz 132x25 mode, the value here
* seems fine. Note that 80xXX modes use 25 or 28 MHz clocks, which are fixed
* and not affected by this. This might not be true for Diamond boards using
* the DCS2824-0 clockchip, which is an ICD 2061A clone.
*/
#define I2061A_DEFAULT_TEXT_FREQUENCY (40000L) /* kHz */
 
/*
* Clockchip code is derived from I2051Aalt.c in XFree86/common_hw which
* in turn is derived from code available from the STB bulletin board.
* A number of modifications have been made to fit this into SVGAlib.
*/
 
#define I2061A_CRYSTAL_FREQUENCY (14.31818 * 2.0)
 
static double I2061A_range[15] =
{50.0, 51.0, 53.2, 58.5, 60.7, 64.4, 66.8, 73.5,
75.6, 80.9, 83.2, 91.5, 100.0, 120.0, 120.0000001};
 
static long I2061A_SelectClock(long frequency)
/* in KHz */
{
unsigned int m;
int i;
double freq, fvco;
double dev, devx;
double delta, deltax;
double f0;
unsigned int p, q;
unsigned int bestp = 0, bestq = 0, bestm = 0, besti = 0;
 
freq = ((double) frequency) / 1000.0;
if (freq > I2061A_range[13])
freq = I2061A_range[13];
else if (freq < 7.0)
freq = 7.0;
 
/*
* Calculate values to load into ICD 2061A clock chip to set frequency
*/
delta = 999.0;
dev = 999.0;
 
for (m = 0; m < 8; m++) {
fvco = freq * (1 << m);
if (fvco < 50.0 || fvco > 120.0)
continue;
 
f0 = fvco / I2061A_CRYSTAL_FREQUENCY;
 
for (q = 14; q <= 71; q++) { /* q={15..71}:Constraint 2 on page 14 */
p = (int) (f0 * q + 0.5);
if (p < 4 || p > 130) /* p={4..130}:Constraint 5 on page 14 */
continue;
deltax = (double) (p) / (double) (q) - f0;
if (deltax < 0)
deltax = -deltax;
if (deltax <= delta) {
for (i = 13; i >= 0; i--)
if (fvco >= I2061A_range[i])
break;
devx = (fvco - (I2061A_range[i] + I2061A_range[i + 1]) / 2) / fvco;
if (devx < 0)
devx = -devx;
if (deltax < delta || devx < dev) {
delta = deltax;
dev = devx;
bestp = p;
bestq = q;
bestm = m;
besti = i;
}
}
}
}
return ((((((long) besti << 7) | (bestp - 3)) << 3) | bestm) << 7) | (bestq - 2);
}
 
static int I2061A_GetClock(long dwv)
{
int clock_q = (dwv & 0x7f) + 2;
int clock_m = (dwv >> 7) & 7;
int clock_p = ((dwv >> 10) & 0x7f) + 3;
double fvco;
 
fvco = I2061A_CRYSTAL_FREQUENCY / (1 << clock_m);
return (int) (((fvco * clock_p) / clock_q) * 1000);
}
 
/* needs some delay for really fast cpus */
#define wrt_clk_bit(v) outb(MIS_W, v), (void)inb(crtcaddr), (void)inb(crtcaddr)
 
/* ATTENTION: This assumes CRTC registers and S3 registers to be UNLOCKED! */
static void I2061A_init_clock(unsigned long setup)
{
unsigned char nclk[2], clk[2];
unsigned short restore42;
unsigned short oldclk;
unsigned short bitval;
int i;
unsigned char c;
unsigned short crtcaddr = (inb(MIS_R) & 0x01) ? CRT_IC : CRT_IM;
 
oldclk = inb(MIS_R);
 
outb(crtcaddr, 0x42);
restore42 = inb(crtcaddr + 1);
 
outw(SEQ_I, 0x0100);
 
outb(SEQ_I, 1);
c = inb(SEQ_D);
outb(SEQ_D, 0x20 | c);
 
outb(crtcaddr, 0x42);
outb(crtcaddr + 1, 0x03);
 
outw(SEQ_I, 0x0300);
 
nclk[0] = oldclk & 0xF3;
nclk[1] = nclk[0] | 0x08;
clk[0] = nclk[0] | 0x04;
clk[1] = nclk[0] | 0x0C;
 
outb(crtcaddr, 0x42);
(void) inb(crtcaddr + 1);
 
outw(SEQ_I, 0x0100);
 
wrt_clk_bit(oldclk | 0x08);
wrt_clk_bit(oldclk | 0x0C);
for (i = 0; i < 5; i++) {
wrt_clk_bit(nclk[1]);
wrt_clk_bit(clk[1]);
}
wrt_clk_bit(nclk[1]);
wrt_clk_bit(nclk[0]);
wrt_clk_bit(clk[0]);
wrt_clk_bit(nclk[0]);
wrt_clk_bit(clk[0]);
for (i = 0; i < 24; i++) {
bitval = setup & 0x01;
setup >>= 1;
wrt_clk_bit(clk[1 - bitval]);
wrt_clk_bit(nclk[1 - bitval]);
wrt_clk_bit(nclk[bitval]);
wrt_clk_bit(clk[bitval]);
}
wrt_clk_bit(clk[1]);
wrt_clk_bit(nclk[1]);
wrt_clk_bit(clk[1]);
 
outb(SEQ_I, 1);
c = inb(SEQ_D);
outb(SEQ_D, 0xDF & c);
 
outb(crtcaddr, 0x42);
outb(crtcaddr + 1, restore42);
 
outb(MIS_W, oldclk);
 
outw(SEQ_I, 0x0300);
 
vga_waitretrace();
vga_waitretrace();
vga_waitretrace();
vga_waitretrace();
vga_waitretrace();
vga_waitretrace();
vga_waitretrace(); /* 0.10 second delay... */
}
 
static int I2061A_match_programmable_clock(int desiredclock)
{
long dvw;
 
dvw = I2061A_SelectClock((long) desiredclock);
if (dvw)
return I2061A_GetClock(dvw);
return 0;
}
 
static void I2061A_saveState(unsigned char *regs)
{
long *dvwp;
 
if (__svgalib_I2061A_clockchip_methods.DAC_saveState)
__svgalib_I2061A_clockchip_methods.DAC_saveState(regs);
 
dvwp = (long *) (regs + __svgalib_I2061A_clockchip_methods.DAC_stateSize);
*dvwp = I2061A_SelectClock(__svgalib_I2061A_clockchip_methods.TextFrequency);
}
 
static void I2061A_restoreState(const unsigned char *regs)
{
unsigned int clknum = 2;
long *dvwp;
 
if (__svgalib_I2061A_clockchip_methods.DAC_restoreState)
__svgalib_I2061A_clockchip_methods.DAC_restoreState(regs);
dvwp = (long *) (regs + __svgalib_I2061A_clockchip_methods.DAC_stateSize);
if (*dvwp) {
/*
* Write ICD 2061A clock chip - assumes S3 to be unlocked!
*/
I2061A_init_clock(((unsigned long) *dvwp) | (((long) clknum) << 21));
}
}
 
static void I2061A_initializeState(unsigned char *regs, int bpp, int colormode, int pixelclock)
{
long *dvwp;
 
if (__svgalib_I2061A_clockchip_methods.DAC_initializeState)
__svgalib_I2061A_clockchip_methods.DAC_initializeState(regs, bpp, colormode, pixelclock);
 
dvwp = (long *) (regs + __svgalib_I2061A_clockchip_methods.DAC_stateSize);
 
if (bpp > 16)
pixelclock *= 4;
else if (bpp > 8)
pixelclock *= 2;
 
*dvwp = I2061A_SelectClock((long) pixelclock);
}
 
/* This functions patches the DacMethod to route through the ClockChip Method */
static void I2061A_init(CardSpecs * cardspecs, DacMethods * DAC)
{
if (DAC && !__svgalib_I2061A_clockchip_methods.DAC_initializeState) {
if (__svgalib_driver_report)
cprintf("svgalib: Using ICD2061A or compatible clockchip.\n");
__svgalib_I2061A_clockchip_methods.DAC_initializeState = DAC->initializeState;
__svgalib_I2061A_clockchip_methods.DAC_saveState = DAC->saveState;
__svgalib_I2061A_clockchip_methods.DAC_restoreState = DAC->restoreState;
__svgalib_I2061A_clockchip_methods.DAC_stateSize = DAC->stateSize;
DAC->initializeState = I2061A_initializeState;
DAC->saveState = I2061A_saveState;
DAC->restoreState = I2061A_restoreState;
DAC->stateSize += sizeof(long);
cardspecs->matchProgrammableClock = I2061A_match_programmable_clock;
cardspecs->flags |= CLOCK_PROGRAMMABLE;
}
}
 
ClockChipMethods __svgalib_I2061A_clockchip_methods =
{
I2061A_init,
I2061A_saveState,
I2061A_restoreState,
I2061A_initializeState,
NULL, /* DAC function save area */
NULL,
NULL,
I2061A_DEFAULT_TEXT_FREQUENCY,
0,
};
/shark/tags/rel_0_5/drivers/svga/icw.c
0,0 → 1,119
/*
* icw.c:
*
* RAMDAC definition for IC Works DACs.
* This version only supports the 16-bit ZoomDAC (w30C516), which
* is compatible with the AT&T 20C498.
* This DAC exists in 110, 135 and 170 MHz versions.
* It can do packed 24-bit color (BG-RB-GR).
* The 170 MHz version has a PCLK limit of 135 MHz
* (170 pixel clock for 16-bit path for 8bpp LUT).
*/
 
#include <stdlib.h>
#include <stdio.h>
#include "libvga.h"
 
#include "timing.h"
#include "vgaregs.h"
#include "driver.h" /* for __svgalib_driver_report */
#include "ramdac.h"
 
#ifdef INCLUDE_ICW_DAC_TEST
static int ICW_probe(void)
{
unsigned char mi, di;
 
_ramdac_dactocomm();
inb(PEL_MSK); /* Control register 0. */
mi = inb(PEL_MSK); /* Manufacturer ID. */
di = inb(PEL_MSK); /* Device ID. */
if (mi == 0x84) {
if (di == 0x98)
return 1;
cprintf("svgalib: ICW_probe: Unknown IC Works DAC.\n");
}
return 0;
}
#else
#define ICW_probe 0
#endif
 
#ifdef INCLUDE_ICW_DAC
static void ICW_init(void)
{
if (__svgalib_driver_report)
cprintf("svgalib: Using IC Works DAC (AT&T20C498-compatible).\n");
}
 
static int ICW_map_clock(int bpp, int pixelclock)
{
if (bpp == 8 && pixelclock > 80000)
/* Use 16-bit path, clock doubling at RAMDAC. */
return pixelclock / 2;
if (bpp == 16)
return pixelclock;
if (bpp == 24)
/* Use the packed 24-bit mode. */
return pixelclock * 3 / 2;
if (bpp == 32)
return pixelclock * 2;
return pixelclock;
}
 
static int ICW_map_horizontal_crtc(int bpp, int pixelclock, int htiming)
{
/* Not sure. */
if (bpp == 8 && pixelclock > 80000)
/* Use 16-bit path, clock doubling at RAMDAC. */
return htiming / 2;
if (bpp == 24)
return htiming * 3 / 2;
if (bpp == 32)
return htiming * 2;
return htiming;
}
 
static void ICW_initializestate(unsigned char *regs, int bpp, int colormode,
int pixelclock)
{
regs[0] = 0;
if (colormode == CLUT8_8)
regs[0] = 0x02;
if (colormode == RGB16_555)
regs[0] = 0x10;
if (colormode == RGB16_565)
regs[0] = 0x30;
if (colormode == RGB24_888_B)
/* Packed mode. */
regs[0] = 0xB0;
if (colormode == RGB32_888_B)
regs[0] = 0x50;
}
 
static void ICW_qualify_cardspecs(CardSpecs * cardspecs, int dacspeed)
{
dacspeed = __svgalib_setDacSpeed(dacspeed, 110000);
cardspecs->maxPixelClock4bpp = 0;
cardspecs->maxPixelClock8bpp = dacspeed;
cardspecs->maxPixelClock16bpp = dacspeed;
cardspecs->maxPixelClock24bpp = dacspeed * 2 / 3;
cardspecs->maxPixelClock32bpp = dacspeed / 2;
cardspecs->mapClock = ICW_map_clock;
cardspecs->mapHorizontalCrtc = ICW_map_horizontal_crtc;
}
 
DacMethods __svgalib_ICW_methods =
{
IC_WORKS,
"IC Works DAC",
0,
ICW_probe,
ICW_init,
ICW_qualify_cardspecs,
__svgalib_Sierra_32K_savestate,
__svgalib_Sierra_32K_restorestate,
ICW_initializestate,
1 /* State size. */
};
#endif
/shark/tags/rel_0_5/drivers/svga/vgadrv.c
0,0 → 1,322
/* VGAlib version 1.2 - (c) 1993 Tommy Frandsen */
/* */
/* This library is free software; you can redistribute it and/or */
/* modify it without any restrictions. This library is distributed */
/* in the hope that it will be useful, but without any warranty. */
 
/* Multi-chipset support Copyright 1993 Harm Hanemaayer */
/* partially copyrighted (C) 1993 by Hartmut Schirmer */
 
 
#include <stdlib.h> /* for NULL */
#include "vga.h"
#include "libvga.h"
#include "driver.h"
 
/* BIOS mode 0Dh - 320x200x16 */
static const unsigned char g320x200x16_regs[60] =
{
0x2D, 0x27, 0x28, 0x90, 0x2B, 0x80, 0xBF, 0x1F, 0x00, 0xC0, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x9C, 0x8E, 0x8F, 0x14, 0x00, 0x96, 0xB9, 0xE3,
0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B,
0x0C, 0x0D, 0x0E, 0x0F, 0x01, 0x00, 0x0F, 0x00, 0x00,
0x00, 0x0F, 0x00, 0x20, 0x00, 0x00, 0x05, 0x0F, 0xFF,
0x03, 0x09, 0x0F, 0x00, 0x06,
0x63
};
 
/* BIOS mode 0Eh - 640x200x16 */
static const unsigned char g640x200x16_regs[60] =
{
0x5F, 0x4F, 0x50, 0x82, 0x54, 0x80, 0xBF, 0x1F, 0x00, 0xC0, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x9C, 0x8E, 0x8F, 0x28, 0x00, 0x96, 0xB9, 0xE3,
0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B,
0x0C, 0x0D, 0x0E, 0x0F, 0x01, 0x00, 0x0F, 0x00, 0x00,
0x00, 0x0F, 0x00, 0x20, 0x00, 0x00, 0x05, 0x0F, 0xFF,
0x03, 0x01, 0x0F, 0x00, 0x06,
0x63
};
 
/* BIOS mode 10h - 640x350x16 */
static const unsigned char g640x350x16_regs[60] =
{
0x5F, 0x4F, 0x50, 0x82, 0x54, 0x80, 0xBF, 0x1F, 0x00, 0x40, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x83, 0x85, 0x5D, 0x28, 0x0F, 0x63, 0xBA, 0xE3,
0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B,
0x0C, 0x0D, 0x0E, 0x0F, 0x01, 0x00, 0x0F, 0x00, 0x00,
0x00, 0x0F, 0x00, 0x20, 0x00, 0x00, 0x05, 0x0F, 0xFF,
0x03, 0x01, 0x0F, 0x00, 0x06,
0xA3
};
 
/* BIOS mode 12h - 640x480x16 */
static const unsigned char g640x480x16_regs[60] =
{
0x5F, 0x4F, 0x50, 0x82, 0x54, 0x80, 0x0B, 0x3E, 0x00, 0x40, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0xEA, 0x8C, 0xDF, 0x28, 0x00, 0xE7, 0x04, 0xE3,
0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B,
0x0C, 0x0D, 0x0E, 0x0F, 0x01, 0x00, 0x0F, 0x00, 0x00,
0x00, 0x0F, 0x00, 0x20, 0x00, 0x00, 0x05, 0x0F, 0xFF,
0x03, 0x01, 0x0F, 0x00, 0x06,
0xE3
};
 
/* BIOS mode 13h - 320x200x256 */
static const unsigned char g320x200x256_regs[60] =
{
0x5F, 0x4F, 0x50, 0x82, 0x54, 0x80, 0xBF, 0x1F, 0x00, 0x41, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x9C, 0x8E, 0x8F, 0x28, 0x40, 0x96, 0xB9, 0xA3,
0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B,
0x0C, 0x0D, 0x0E, 0x0F, 0x41, 0x00, 0x0F, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0F, 0xFF,
0x03, 0x01, 0x0F, 0x00, 0x0E,
0x63
};
 
/* non-BIOS mode - 320x240x256 */
static const unsigned char g320x240x256_regs[60] =
{
0x5F, 0x4F, 0x50, 0x82, 0x54, 0x80, 0x0D, 0x3E, 0x00, 0x41, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0xEA, 0xAC, 0xDF, 0x28, 0x00, 0xE7, 0x06, 0xE3,
0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B,
0x0C, 0x0D, 0x0E, 0x0F, 0x41, 0x00, 0x0F, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0F, 0xFF,
0x03, 0x01, 0x0F, 0x00, 0x06,
0xE3
};
 
/* non-BIOS mode - 320x400x256 */
static const unsigned char g320x400x256_regs[60] =
{
0x5F, 0x4F, 0x50, 0x82, 0x54, 0x80, 0xBF, 0x1F, 0x00, 0x40, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x9C, 0x8E, 0x8F, 0x28, 0x00, 0x96, 0xB9, 0xE3,
0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B,
0x0C, 0x0D, 0x0E, 0x0F, 0x41, 0x00, 0x0F, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0F, 0xFF,
0x03, 0x01, 0x0F, 0x00, 0x06,
0x63
};
 
/* non-BIOS mode - 360x480x256 */
static const unsigned char g360x480x256_regs[60] =
{
0x6B, 0x59, 0x5A, 0x8E, 0x5E, 0x8A, 0x0D, 0x3E, 0x00, 0x40, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0xEA, 0xAC, 0xDF, 0x2D, 0x00, 0xE7, 0x06, 0xE3,
0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B,
0x0C, 0x0D, 0x0E, 0x0F, 0x41, 0x00, 0x0F, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0F, 0xFF,
0x03, 0x01, 0x0F, 0x00, 0x06,
0xE7
};
 
/* monochrome mode based on BIOS mode 12h - 640x480x2 */
#define g640x480x2_regs g640x480x16_regs
 
/* non BIOS mode - 720x348x2 based on mode 10h */
static const unsigned char g720x348x2_regs[60] =
{
0x6B, 0x59, 0x5A, 0x8E, 0x5E, 0x8A, 0xBF, 0x1F, 0x00, 0x40, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x83, 0x85, 0x5D, 0x2D, 0x0F, 0x63, 0xBA, 0xE3,
0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B,
0x0C, 0x0D, 0x0E, 0x0F, 0x01, 0x00, 0x0F, 0x00, 0x00,
0x00, 0x0F, 0x00, 0x20, 0x00, 0x00, 0x05, 0x0F, 0xFF,
0x03, 0x01, 0x0F, 0x00, 0x06,
0xA7
};
 
/* non-BIOS mode - 400x300x256 - added by Ark 28-JAN-2001 */
static const unsigned char g400x300x256X_regs[60] =
{
0x71, 0x63, 0x64, 0x92, 0x65, 0x82, 0x46, 0x1F, 0x00, 0x40, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x31, 0x80, 0x2B, 0x32, 0x00, 0x2F, 0x44, 0xE3,
0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B,
0x0C, 0x0D, 0x0E, 0x0F, 0x41, 0x00, 0x0F, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0F, 0xFF,
0x03, 0x01, 0x0F, 0x00, 0x06,
0xA7
};
 
 
/* Mode table */
static ModeTable vga_modes[] =
{
/* *INDENT-OFF* */
OneModeEntry(640x480x2),
OneModeEntry(720x348x2),
OneModeEntry(320x200x16),
OneModeEntry(640x200x16),
OneModeEntry(640x350x16),
OneModeEntry(640x480x16),
OneModeEntry(320x200x256),
OneModeEntry(320x240x256),
OneModeEntry(320x400x256),
OneModeEntry(360x480x256),
OneModeEntry(400x300x256X),
#ifdef G720x350x16
OneModeEntry(720x350x16),
#endif
END_OF_MODE_TABLE
/* *INDENT-ON* */
};
 
 
/* Fill in chipset-specific modeinfo */
 
static void getmodeinfo(int mode, vga_modeinfo * modeinfo)
{
if (modeinfo->bytesperpixel == 1) { /* 320x200x256 linear mode */
modeinfo->maxpixels = 65536;
modeinfo->startaddressrange = 0xffff;
} else
switch (modeinfo->colors) {
case 16: /* 4-plane 16 color mode */
modeinfo->maxpixels = 65536 * 8;
modeinfo->startaddressrange = 0x7ffff;
break;
case 256: /* 4-plane 256 color mode */
modeinfo->maxpixels = 65536 * 4;
modeinfo->startaddressrange = 0x3ffff;
break;
}
modeinfo->maxlogicalwidth = 2040;
modeinfo->haveblit = 0;
modeinfo->flags &= ~(IS_INTERLACED | HAVE_RWPAGE);
}
 
static void nothing(void)
{
}
 
static int saveregs(unsigned char regs[])
{
return 0;
}
 
static void setregs(const unsigned char regs[], int mode)
{
}
 
/* Return nonzero if mode available */
 
static int modeavailable(int mode)
{
const unsigned char *regs;
 
regs = LOOKUPMODE(vga_modes, mode);
if (regs != NULL && regs != DISABLE_MODE)
return STDVGADRV;
return 0;
}
 
 
/* Set a mode */
 
static int lastmode;
 
static int setmode(int mode, int prv_mode)
{
/* standard VGA driver: setmode */
const unsigned char *regs;
 
if (mode == TEXT)
return 0; /* Do nothing. */
 
regs = LOOKUPMODE(vga_modes, mode);
if (regs == NULL || regs == DISABLE_MODE)
return 1;
lastmode = mode;
__svgalib_setregs(regs);
return 0;
}
 
/* Set display start */
 
static void setdisplaystart(int address)
{
vga_modeinfo *modeinfo;
modeinfo = vga_getmodeinfo(lastmode);
if (modeinfo->bytesperpixel == 0) /* not 320x200x256 linear */
switch (modeinfo->colors) {
case 16: /* planar 16-color mode */
__svgalib_outatt(0x33,(__svgalib_inatt(0x33)&0xf0) | (address & 7));
/* write sa0-2 to bits 0-2 */
address >>= 3;
break;
case 256: /* planar 256-color mode */
/* write sa0-1 to bits 1-2 */
__svgalib_outatt(0x33,(__svgalib_inatt(0x33)&0xf0) | ((address & 3)<<1) );
address >>= 2;
break;
}
__svgalib_outcrtc(0x0d, address & 0x00ff);
__svgalib_outcrtc(0x0c, (address & 0xff00) >> 8);
}
 
static void setlogicalwidth(int width)
{
__svgalib_outcrtc(0x13, width >> 3);
}
 
static int vgadrv_init(int, int, int);
 
static int vga_test(void)
{
unsigned char save, back;
 
/* Check if a DAC is present */
save = port_in(PEL_IW);
__svgalib_delay();
outb(PEL_IW, ~save);
__svgalib_delay();
back = port_in(PEL_IW);
__svgalib_delay();
outb(PEL_IW, save);
save = ~save;
if (back == save) {
vgadrv_init(0, 0, 0);
return 1;
}
return 0;
}
 
 
DriverSpecs __svgalib_vga_driverspecs =
{ /* standard VGA */
saveregs,
setregs,
nothing, /* unlock */
nothing, /* lock */
vga_test,
vgadrv_init,
(void (*)(int)) nothing, /* __svgalib_setpage */
(void (*)(int)) nothing, /* __svgalib_setrdpage */
(void (*)(int)) nothing, /* __svgalib_setwrpage */
setmode,
modeavailable,
setdisplaystart,
setlogicalwidth,
getmodeinfo,
0, /* bitblt */
0, /* imageblt */
0, /* fillblt */
0, /* hlinelistblt */
0, /* bltwait */
0, /* extset */
0,
0, /* linear */
NULL, /* Accelspecs */
NULL, /* Emulation */
};
 
/* Initialize chipset (called after detection) */
 
static int vgadrv_init(int force, int par1, int par2)
{
if (__svgalib_driver_report)
cprintf("Using VGA driver.\n");
__svgalib_driverspecs = &__svgalib_vga_driverspecs;
__svgalib_banked_mem_base=0xa0000;
__svgalib_banked_mem_size=0x10000;
 
return 0;
}
/shark/tags/rel_0_5/drivers/svga/makefile
0,0 → 1,100
# The Frame Buffer Device
 
ifndef BASE
BASE=../..
endif
 
include $(BASE)/config/config.mk
include makefile.cfg
 
LIBRARY = svga
 
OBJS_PATH = $(BASE)/drivers/svga
 
MODULES = timing.o vgaregs.o interface.o accel.o modetab.o interrupt.o\
vgapci.o vga_helper.o nv3.o vga.o vgadrv.o vgaio.o vgapal.o\
vgaclear.o vgadraw.o vgaaccel.o vgaline.o icd2061a.o\
./grx/glib.o vgammvgaio.o vgarelvgaio.o savage.o r128.o
RAMDAC = ramdac.o normal.o attdacs.o sierra.o vgamisc.o\
icw.o s3dacs.o IBMRGB52x.o ics_gendac.o
 
OBJS = $(MODULES) $(RAMDAC)
 
# defines for ramdac.c, ramdac.h (and files including it) only.
ifdef INCLUDE_NORMAL_DAC
RAMDAC_DEFINES += -DINCLUDE_NORMAL_DAC
ifdef INCLUDE_NORMAL_DAC_TEST
RAMDAC_DEFINES += -DINCLUDE_NORMAL_DAC_TEST
endif
endif
ifdef INCLUDE_S3_SDAC_DAC
RAMDAC_DEFINES += -DINCLUDE_S3_SDAC_DAC
ifdef INCLUDE_S3_SDAC_DAC_TEST
RAMDAC_DEFINES += -DINCLUDE_S3_SDAC_DAC_TEST
endif
endif
ifdef INCLUDE_S3_GENDAC_DAC
RAMDAC_DEFINES += -DINCLUDE_S3_GENDAC_DAC
ifdef INCLUDE_S3_GENDAC_DAC_TEST
RAMDAC_DEFINES += -DINCLUDE_S3_GENDAC_DAC_TEST
endif
endif
ifdef INCLUDE_S3_TRIO64_DAC
RAMDAC_DEFINES += -DINCLUDE_S3_TRIO64_DAC
ifdef INCLUDE_S3_TRIO64_DAC_TEST
RAMDAC_DEFINES += -DINCLUDE_S3_TRIO64_DAC_TEST
endif
endif
ifdef INCLUDE_SIERRA_DAC
RAMDAC_DEFINES += -DINCLUDE_SIERRA_DAC
ifdef INCLUDE_SIERRA_DAC_TEST
RAMDAC_DEFINES += -DINCLUDE_SIERRA_DAC_TEST
endif
endif
ifdef INCLUDE_SC15025_DAC
RAMDAC_DEFINES += -DINCLUDE_SC15025_DAC
ifdef INCLUDE_SC15025_DAC_TEST
RAMDAC_DEFINES += -DINCLUDE_SC15025_DAC_TEST
endif
endif
ifdef INCLUDE_ATT20C490_DAC
RAMDAC_DEFINES += -DINCLUDE_ATT20C490_DAC
ifdef INCLUDE_ATT20C490_DAC_TEST
RAMDAC_DEFINES += -DINCLUDE_ATT20C490_DAC_TEST
endif
endif
ifdef INCLUDE_ATT20C498_DAC
RAMDAC_DEFINES += -DINCLUDE_ATT20C498_DAC
ifdef INCLUDE_ATT20C498_DAC_TEST
RAMDAC_DEFINES += -DINCLUDE_ATT20C498_DAC_TEST
endif
endif
ifdef INCLUDE_ICW_DAC
RAMDAC_DEFINES += -DINCLUDE_ICW_DAC
ifdef INCLUDE_ICW_DAC_TEST
RAMDAC_DEFINES += -DINCLUDE_ICW_DAC_TEST
endif
endif
ifdef INCLUDE_IBMRGB52x_DAC
RAMDAC_DEFINES += -DINCLUDE_IBMRGB52x_DAC
ifdef INCLUDE_IBMRGB52x_DAC_TEST
RAMDAC_DEFINES += -DINCLUDE_IBMRGB52x_DAC_TEST
endif
endif
ifdef INCLUDE_SC1148X_DAC
RAMDAC_DEFINES += -DINCLUDE_SC1148X_DAC
ifdef INCLUDE_SC1148X_DAC_TEST
RAMDAC_DEFINES += -DINCLUDE_SC1148X_DAC_TEST
endif
endif
ifdef INCLUDE_ICS_GENDAC_DAC
RAMDAC_DEFINES += -DINCLUDE_ICS_GENDAC_DAC
ifdef INCLUDE_ICS_GENDAC_DAC_TEST
RAMDAC_DEFINES += -DINCLUDE_ICS_GENDAC_DAC_TEST
endif
endif
 
C_OPT += -I../linuxc24/include -D__KERNEL__ $(RAMDAC_DEFINES) $(VGA_DEFINES) $(DEFINES)
 
include $(BASE)/config/lib.mk
 
/shark/tags/rel_0_5/drivers/svga/vgammvgaio.h
0,0 → 1,6
#include "ll/sys/cdefs.h"
 
__BEGIN_DECLS
extern unsigned long __svgalib_vgammbase;
extern void __svgalib_mm_io_mapio(void);
__END_DECLS
/shark/tags/rel_0_5/drivers/svga/interface.h
0,0 → 1,27
#include "ll/sys/cdefs.h"
 
__BEGIN_DECLS
 
 
/* Prototypes of functions defined in interface.c. */
 
/*
* This is a temporary function that allocates and fills in a ModeInfo
* structure based on a svgalib mode number.
*/
 
ModeInfo *__svgalib_createModeInfoStructureForSvgalibMode(int mode);
 
/*
* This function converts a number of significant color bits to a matching
* DAC mode type as defined in the RAMDAC interface.
*/
 
int __svgalib_colorbits_to_colormode(int bpp, int colorbits);
 
/*
* Clear the accelspecs structure (disable acceleration).
*/
 
void __svgalib_clear_accelspecs(AccelSpecs * accelspecs);
__END_DECLS
/shark/tags/rel_0_5/drivers/svga/vgarelvgaio.h
0,0 → 1,6
#include "ll/sys/cdefs.h"
 
__BEGIN_DECLS
extern int __svgalib_io_reloc;
extern void __svgalib_rel_io_mapio(void);
__END_DECLS
/shark/tags/rel_0_5/drivers/svga/io.h
0,0 → 1,74
#include <stdint.h>
#include "ll/sys/cdefs.h"
 
__BEGIN_DECLS
 
#ifndef __alpha__
 
#define v_readb(addr) (*(volatile uint8_t *) (MMIO_POINTER+(addr)))
#define v_readw(addr) (*(volatile uint16_t *) (MMIO_POINTER+(addr)))
#define v_readl(addr) (*(volatile uint32_t *) (MMIO_POINTER+(addr)))
 
#define v_writeb(b,addr) (*(volatile uint8_t *) (MMIO_POINTER+(addr)) = (b))
#define v_writew(b,addr) (*(volatile uint16_t *) (MMIO_POINTER+(addr)) = (b))
#define v_writel(b,addr) (*(volatile uint32_t *) (MMIO_POINTER+(addr)) = (b))
 
#else
 
#define vip volatile int *
#define vuip volatile unsigned int *
#define vulp volatile unsigned long *
 
#define mb() \
__asm__ __volatile__("mb": : :"memory")
 
#define __kernel_extbl(val, shift) \
({ unsigned long __kir; \
__asm__("extbl %2,%1,%0" : "=r"(__kir) : "rI"(shift), "r"(val)); \
__kir; })
#define __kernel_extwl(val, shift) \
({ unsigned long __kir; \
__asm__("extwl %2,%1,%0" : "=r"(__kir) : "rI"(shift), "r"(val)); \
__kir; })
 
static inline uint8_t v_readb(unsigned long addr)
{
unsigned long result;
 
result = *(vip) ((addr << 5) + SPARSE_MMIO + 0x00);
return __kernel_extbl(result, addr & 3);
}
 
static inline uint16_t v_readw(unsigned long addr)
{
unsigned long result;
 
result = *(vip) ((addr << 5) + SPARSE_MMIO + 0x08);
return __kernel_extwl(result, addr & 3);
}
 
static inline uint32_t v_readl(unsigned long addr)
{
return *(vuip) ((addr << 5) + SPARSE_MMIO + 0x18);
}
 
static inline void v_writeb(uint8_t b, unsigned long addr)
{
*(vuip) ((addr << 5) + SPARSE_MMIO + 0x00) = b * 0x01010101;
mb();
}
 
static inline void v_writew(uint16_t b, unsigned long addr)
{
*(vuip) ((addr << 5) + SPARSE_MMIO + 0x08) = b * 0x00010001;
mb();
}
 
static inline void v_writel(uint32_t b, unsigned long addr)
{
*(vuip) ((addr << 5) + SPARSE_MMIO + 0x18) = b;
mb();
}
 
__END_DECLS
#endif /* __alpha__ */
/shark/tags/rel_0_5/drivers/svga/accel.h
0,0 → 1,209
 
#ifndef ACCEL_H
#define ACCEL_H
 
#include "ll/sys/cdefs.h"
 
__BEGIN_DECLS
 
/*
* New accelerator interface sketch.
* As of svgalib 1.23, this isn't used yet.
*
* The main goal is to define functions that can be used as part of
* certain kinds of interesting graphical operations (not necessarily
* interesting primitives on their own). Obvious useful primitives
* in their own are FillBox, ScreenCopy, DrawHLineList (solid polygon),
* DrawLine.
*
* An interesting purpose is the fast drawing of color bitmaps, both
* straight and transparent (masked, certain color not written). For
* masked bitmaps ("sprites"), there is a number of possible methods,
* the availability of which depends on the chips. Caching in
* non-visible video memory is often useful. One way is to use a
* transparency color compare feature of a BITBLT chip, either
* transferring the image from system memory or cached in video memory.
* If transparency compare is not available, it may be possible to first
* clear (zeroes) the mask in the destination area, and then use BITBLT
* raster-operation to OR the image into the destination (this requires
* the mask color to be 0). A higher level (library) interface should
* control this kind of operation.
*/
 
 
typedef struct {
/* Graphics mode-independent fields. */
int flags;
/*
* The following fields define lists of linewidths in pixel
* units that the accelerator supports for each depth. Each
* list is terminated by 0. These fields are only relevant
* if the ACCELERATE_ANY_LINEWIDTH flag is not set.
*/
int *supportedLineWidths8bpp;
int *supportedLineWidths16bpp;
int *supportedLineWidths24bpp;
int *supportedLineWidths32bpp;
/*
* The following function sets up the accelerator interface for
* pixels of size bpp and scanline width of width_in_pixels.
*/
void (*initAccelerator) (int bpp, int width_in_pixels);
/* Fields that are initialized after setting a graphics mode. */
/*
* The following field defines which accelerated primitives are
* available in the selected graphics mode.
*/
int operations;
/*
* The following field defines which accelerated primitives are
* available with special raster-ops in the selected graphics mode.
*/
int ropOperations;
/*
* The following field defines which special raster operations are
* available in the selected graphics mode.
*/
int ropModes;
/*
* The following field defines which accelerated primitives are
* available with transparency in the selected graphics mode.
*/
int transparencyOperations;
/*
* The following field defines which special transparency modes are
* available in the selected graphics mode.
*/
int transparencyModes;
/* Acceleration primitive functions. */
void (*FillBox) (int x, int y, int width, int height);
void (*ScreenCopy) (int x1, int y1, int x2, int y2, int width,
int height);
void (*PutImage) (int x, int y, int width, int height, void *image);
void (*DrawLine) (int x1, int y1, int x2, int y2);
void (*SetFGColor) (int c);
void (*SetBGColor) (int c);
void (*SetRasterOp) (int rop);
void (*SetTransparency) (int mode, int color);
void (*PutBitmap) (int x, int y, int w, int h, void *bitmap);
void (*ScreenCopyBitmap) (int x1, int y1, int x2, int y2, int width,
int height);
void (*DrawHLineList) (int ymin, int n, int *xmin, int *xmax);
void (*SetMode) (void);
void (*Sync) (void);
} AccelSpecs;
 
/* Flags: */
/* Every programmable scanline width is supported by the accelerator. */
#define ACCELERATE_ANY_LINEWIDTH 0x1
/* Bitmap (1-bit-per-pixel) operations support transparency (bit = 0). */
#define BITMAP_TRANSPARENCY 0x2
/* For bitmaps (1 bpp) stored in video memory, the most-significant bit */
/* within a byte is the leftmost pixel. */
#define BITMAP_ORDER_MSB_FIRST 0x4
 
/* Operation flags: see vga.h. */
 
/*
* Acceleration primitive description:
*
* FillBox Simple solid fill of rectangle with a single color.
* ScreenCopy Screen-to-screen BLT (BitBlt), handles overlapping areas.
* PutImage Straight image transfer (PutImage). Advantage over
* framebuffer writes is mainly in alignment handling.
* DrawLine Draw general line ("zero-pixel wide").
* SetFGColor Set foreground color for some operations (FillBox, DrawLine,
* PutBitmap).
* SetBGColor Set background color for some operations (PutBitmap).
* SetRasterOp Set the raster operation for drawing operations that support
* raster ops as defined in ropOperations.
* SetTransparency
* Set the transparency mode for some operations (enable/disable,
* and the transparency pixel value). Source pixels equal to
* the transparency color are not written. Operations supported
* are ScreenCopy and PutImage, subject to their flags being set
* in the transparencyOperations field.
* PutBitmap Color-expand a bit-wise (bit-per-pixel, each byte is 8 pixels)
* image to the screen with the foreground and background color.
* The lowest order bit of each byte is leftmost on the screen
* (contrary to the VGA tradition), irrespective of the bitmap
* bit order flag. Each scanline is aligned to a multiple of
* 32-bits.
* If the transparency mode is enabled (irrespective of the
* transparency color), then bits that are zero in the bitmap
* are not written (the background color is not used).
* ScreenCopyBitmap
* Color-expand bit-wise bitmap stored in video memory
* (may also support transparency).
* DrawHLineList
* Draw a set of horizontal line segments from top to bottom
* in the foreground color.
* SetMode Set the acceleration mode, e.g. let blits go
* on in the background (program must not access video memory
* when blits can be running).
* Sync Wait for any background blits to finish.
*
* It is not the intention to have alternative non-accelerated routines
* available for each possible operation (library functions should
* take advantage of accelerator functions, rather than the accelerator
* functions being primitives on their own right). If something like
* bit-order reversal is required to implement an accelerated primitive,
* it's still worthwhile if it's still much quicker than similar
* unaccelerated functionality would be.
*
* Strategy for accelerator registers in accelerated functions:
* Foreground color, background color, raster operation and transparency
* compare setting are preserved, source and destination pitch is always
* set to screen pitch (may be temporarily changed and then restored).
*/
 
 
/* Macros. */
 
#define BLTBYTEADDRESS(x, y) \
(y * __svgalib_accel_screenpitchinbytes + x * __svgalib_accel_bytesperpixel)
 
#define BLTPIXADDRESS(x, y) \
(y * __svgalib_accel_screenpitch + x)
 
#define SIGNALBLOCK \
{ \
sigset_t sig2block; \
sigemptyset(&sig2block); \
sigaddset(&sig2block,SIGINT); \
sigprocmask(SIG_BLOCK, &sig2block, (sigset_t *)NULL); \
}
 
#define SIGNALUNBLOCK \
{ \
sigset_t sig2block; \
sigemptyset(&sig2block); \
sigaddset(&sig2block,SIGINT); \
sigprocmask(SIG_UNBLOCK, &sig2block, (sigset_t *)NULL);\
}
 
/* Variables defined in accel.c */
 
extern int __svgalib_accel_screenpitch;
extern int __svgalib_accel_bytesperpixel;
extern int __svgalib_accel_screenpitchinbytes;
extern int __svgalib_accel_mode;
extern int __svgalib_accel_bitmaptransparency;
 
/*
* The following function should be called when the mode is set.
* This is currently done in the setmode driver functions.
*/
 
void __svgalib_InitializeAcceleratorInterface(ModeInfo * modeinfo);
 
/*
* The following driver function fills in available accelerator
* primitives for a graphics mode (operations etc.). It could be part
* of the setmode driver function.
*
* void initOperations( AccelSpecs *accelspecs, int bpp, int width_in_pixels );
*/
 
__END_DECLS
#endif
/shark/tags/rel_0_5/drivers/svga/endianess.h
0,0 → 1,19
#include <endian.h>
#include <byteswap.h>
#include "ll/sys/cdefs.h"
 
__BEGIN_DECLS
 
#if __BYTE_ORDER == __BIG_ENDIAN
 
#define LE32(x) bswap_32(x)
#define BE32(x) (x)
 
#else /* little endian */
 
#define LE32(x) (x)
#define BE32(x) bswap_32(x)
 
#endif
 
__END_DECLS
/shark/tags/rel_0_5/drivers/svga/vgapci.h
0,0 → 1,15
#include "ll/sys/cdefs.h"
 
__BEGIN_DECLS
extern int __svgalib_pci_find_vendor_vga(unsigned int vendor, unsigned long *conf, int cont);
extern int __svgalib_pci_find_vendor_vga_pos(unsigned int vendor, unsigned long *conf, int cont);
extern int __svgalib_pci_idev;
extern void __svgalib_pci_write_config_byte(int pos, int address, unsigned char data);
extern void __svgalib_pci_write_config_word(int pos, int address, unsigned short data);
extern void __svgalib_pci_write_config_dword(int pos, int address, unsigned int data);
extern int __svgalib_pci_read_config_byte(int pos, int address);
extern int __svgalib_pci_read_config_word(int pos, int address);
extern int __svgalib_pci_read_config_dword(int pos, int address);
extern int __svgalib_pci_read_aperture_len(int pos, int address);
extern int memorytest(unsigned char *m, int max_mem);
__END_DECLS
/shark/tags/rel_0_5/drivers/svga/grx/glib.h
0,0 → 1,73
/*
* Project: S.Ha.R.K.
*
* Coordinators:
* Giorgio Buttazzo <giorgio@sssup.it>
* Paolo Gai <pj@gandalf.sssup.it>
*
* Authors :
* Paolo Gai <pj@gandalf.sssup.it>
* Massimiliano Giorgi <massy@gandalf.sssup.it>
* Luca Abeni <luca@gandalf.sssup.it>
* (see the web pages for full authors list)
*
* ReTiS Lab (Scuola Superiore S.Anna - Pisa - Italy)
*
* http://www.sssup.it
* http://retis.sssup.it
* http://shark.sssup.it
*/
 
/**
------------
CVS : $Id: glib.h,v 1.3 2003-03-13 13:46:08 pj Exp $
 
File: $File$
Revision: $Revision: 1.3 $
Last update: $Date: 2003-03-13 13:46:08 $
------------
 
**/
 
/*
* Copyright (C) 2000 Luca Abeni
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
 
#ifndef __GLIB_H__
#define __GLIB_H__
 
#include <ll/sys/types.h>
#include "ll/sys/cdefs.h"
 
__BEGIN_DECLS
 
int grx_setbuffer(BYTE *vbuf,WORD w, WORD h);
 
void grx_plot(WORD x, WORD y, DWORD color);
DWORD grx_getpixel(WORD x, WORD y);
//void grx_getimage(WORD x1, WORD y1, WORD x2, WORD y2, BYTE *buf);
//void grx_putimage(WORD x1, WORD y1, WORD x2, WORD y2, BYTE *buf);
void grx_box(WORD x1, WORD y1, WORD x2, WORD y2, DWORD color);
void grx_rect(WORD x1, WORD y1, WORD x2, WORD y2, DWORD color);
void grx_line(WORD x1, WORD y1, WORD x2, WORD y2, DWORD color);
void grx_text(char *text, WORD x, WORD y, DWORD fg, DWORD bg);
void grx_circle(WORD x, WORD y, WORD r, DWORD col);
void grx_disc(WORD x, WORD y, WORD r, DWORD col);
void grx_clear(DWORD color);
__END_DECLS
#endif
/shark/tags/rel_0_5/drivers/svga/grx/glib.c
0,0 → 1,241
#include "glib.h"
#include <stdlib.h>
 
#include "../vga.h"
 
#define fontaddr 0xffa6eL /* indirizzo set caratteri */
 
BYTE * flbaddr;
WORD bpr;
WORD height, width;
 
inline void memsetw(void *dst, unsigned int c, unsigned long int memdiv2)
{
__asm__ __volatile__("push %%edi
push %%eax
push %%ecx
movl %2, %%edi
cld
rep
stosw
pop %%ecx
pop %%eax
pop %%edi"
:
: "c" (memdiv2), "a" (c), "b" (dst));
 
}
 
 
static void circlepixels(WORD x, WORD y, WORD sx, WORD sy, DWORD c)
{
grx_plot(sx + x, sy + y, c);
grx_plot(sx - x, sy + y, c);
grx_plot(sx + x, sy - y, c);
grx_plot(sx - x, sy - y, c);
grx_plot(sx + y, sy + x, c);
grx_plot(sx - y, sy + x, c);
grx_plot(sx + y, sy - x, c);
grx_plot(sx - y, sy - x, c);
}
 
void grx_circle(WORD sx, WORD sy, WORD r, DWORD c)
{
int x, y, d;
if (r < 1) {
grx_plot(sx, sy, c);
return;
}
x = 0;
y = r;
d = 1 - r;
circlepixels(x, y, sx, sy, c);
while (x < y) {
if (d < 0)
d += x * 2 + 3;
else {
d += x * 2 - y * 2 + 5;
y--;
}
x++;
circlepixels(x, y, sx, sy, c);
}
}
 
/* grx_disc by Massy */
 
static __inline__ void discpixels(WORD x, WORD y, WORD sx, WORD sy, DWORD c)
{
grx_line(sx + x, sy + y, sx + x, sy - y, c);
grx_line(sx - x, sy + y, sx - x, sy - y, c);
grx_line(sx + y, sy + x, sx + y, sy - x , c);
grx_line(sx - y, sy + x, sx - y, sy - x , c);
}
 
void grx_disc(WORD sx, WORD sy, WORD r, DWORD c)
{
int x, y, d;
if (r < 1) {
grx_plot(sx, sy, c);
return;
}
x = 0;
y = r;
d = 1 - r;
discpixels(x, y, sx, sy, c);
while (x < y) {
if (d < 0)
d += x * 2 + 3;
else {
d += x * 2 - y * 2 + 5;
y--;
}
x++;
discpixels(x, y, sx, sy, c);
}
}
 
int grx_setbuffer(BYTE *vbuf, WORD w, WORD h)
{
 
//This functions are designed to work only whit 16 bpp
flbaddr = vbuf;
width = w;
height = h;
bpr = 2 * w;
return 1;
}
 
void grx_clear(DWORD color)
{
 
grx_box(0, 0, width, height, color);
 
}
 
void grx_putimage(WORD x1, WORD y1, WORD x2, WORD y2, BYTE *buf)
{
}
 
void grx_box(WORD x1, WORD y1, WORD x2, WORD y2, DWORD color)
{
BYTE * addr;
int dx, y;
addr = flbaddr + (x1 << 1) + bpr * y1;
dx = (x2 - x1 + 1) << 1;
 
for (y = y1; y <= y2; y++) {
memsetw(addr,color,(dx>>1));
addr += bpr;
}
}
 
void grx_rect(WORD x1, WORD y1, WORD x2, WORD y2, DWORD color)
{
BYTE * addr;
int dx, y;
addr = flbaddr + (x1 << 1) + bpr * y1;
dx = (x2 - x1) << 1;
 
memsetw(addr,color,(dx>>1)+1);
addr += bpr;
 
for (y = y1 + 1; y <= y2 - 1; y++) {
*(WORD *)(addr) = (WORD)(color);
*(WORD *)(addr + dx) = (WORD)(color);
addr += bpr;
}
memsetw(addr,color,(dx>>1)+1);
}
 
void grx_text(char *text, WORD x, WORD y, DWORD fg, DWORD bg)
{
BYTE * fp;
BYTE * addr;
int r, c, bits;
 
addr = flbaddr;
while (*text) {
fp = (BYTE *)(fontaddr + (8 * *(BYTE *)text));
for (r=0; r<8; r++) {
bits = *(BYTE *)(fp++);
for (c=0; c<8; c++)
if (bits & (0x80>>c))
*(WORD *)(addr + (y + r) * bpr + ((x + c) << 1)) = (WORD)(fg);
else
*(WORD *)(addr + (y + r) * bpr + ((x + c) << 1)) = (WORD)(bg);
}
text++;
x += 8;
}
}
 
void grx_line(WORD x1, WORD y1, WORD x2, WORD y2, DWORD color)
{
register int t, distance;
BYTE * addr;
int xerr=0, yerr=0, deltax, deltay;
int incx, incy;
 
addr = flbaddr;;
deltax = x2 - x1; /* compute both distances */
deltay = y2 - y1;
 
if (deltax > 0) /* compute increments */
incx = 1;
else if (deltax == 0)
incx = 0;
else
incx = -1;
 
if (deltay > 0)
incy = 1;
else if (deltay == 0)
incy = 0;
else
incy = -1;
 
deltax = abs(deltax); /* determine greater distance */
deltay = abs(deltay);
if (deltax > deltay)
distance = deltax;
else
distance = deltay;
 
for (t=0; t<=distance+1; t++) { /* draw the line */
*(WORD *)(addr + y1 * bpr + (x1 << 1)) = (WORD)color;
xerr += deltax;
yerr += deltay;
if (xerr > distance) {
xerr -= distance;
x1 += incx;
}
if (yerr > distance) {
yerr -= distance;
y1 += incy;
}
}
}
 
void grx_plot(WORD x, WORD y, DWORD color)
{
*(WORD *)(flbaddr + y * bpr + (x << 1)) = (WORD)color;
}
 
DWORD grx_getpixel(WORD x, WORD y)
{
DWORD rv;
 
(DWORD)rv = *(WORD *)(flbaddr + y * bpr + (x << 1));
return rv;
}
 
/shark/tags/rel_0_5/drivers/svga/nvreg.h
0,0 → 1,183
/* $XConsortium: nvreg.h /main/2 1996/10/28 05:13:41 kaleb $ */
/*
* Copyright 1996-1997 David J. McKay
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* DAVID J. MCKAY BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
 
/* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/nv/nvreg.h,v 3.2.2.1 1998/01/18 10:35:36 hohndel Exp $ */
 
#ifndef __NVREG_H_
#define __NVREG_H_
 
#include "ll/sys/cdefs.h"
 
__BEGIN_DECLS
 
/* Little macro to construct bitmask for contiguous ranges of bits */
#define BITMASK(t,b) (((unsigned)(1U << (((t)-(b)+1)))-1) << (b))
#define MASKEXPAND(mask) BITMASK(1?mask,0?mask)
 
/* Macro to set specific bitfields (mask has to be a macro x:y) ! */
#define SetBF(mask,value) ((value) << (0?mask))
#define GetBF(var,mask) (((unsigned)((var) & MASKEXPAND(mask))) >> (0?mask) )
 
#define MaskAndSetBF(var,mask,value) (var)=(((var)&(~MASKEXPAND(mask)) \
| SetBF(mask,value)))
 
#define DEVICE_BASE(device) (0?NV##_##device)
#define DEVICE_SIZE(device) ((1?NV##_##device) - DEVICE_BASE(device)+1)
 
/* This is where we will have to have conditional compilation */
#define DEVICE_ACCESS(device,reg) \
nv##device##Port[((NV_##device##_##reg)-DEVICE_BASE(device))/4]
 
#define DEVICE_WRITE(device,reg,value) DEVICE_ACCESS(device,reg)=(value)
#define DEVICE_READ(device,reg) DEVICE_ACCESS(device,reg)
#define DEVICE_PRINT(device,reg) \
ErrorF("NV_"#device"_"#reg"=#%08lx\n",DEVICE_ACCESS(device,reg))
#define DEVICE_DEF(device,mask,value) \
SetBF(NV_##device##_##mask,NV_##device##_##mask##_##value)
#define DEVICE_VALUE(device,mask,value) SetBF(NV_##device##_##mask,value)
#define DEVICE_MASK(device,mask) MASKEXPAND(NV_##device##_##mask)
 
#define PDAC_Write(reg,value) DEVICE_WRITE(PDAC,reg,value)
#define PDAC_Read(reg) DEVICE_READ(PDAC,reg)
#define PDAC_Print(reg) DEVICE_PRINT(PDAC,reg)
#define PDAC_Def(mask,value) DEVICE_DEF(PDAC,mask,value)
#define PDAC_Val(mask,value) DEVICE_VALUE(PDAC,mask,value)
#define PDAC_Mask(mask) DEVICE_MASK(PDAC,mask)
 
#define PFB_Write(reg,value) DEVICE_WRITE(PFB,reg,value)
#define PFB_Read(reg) DEVICE_READ(PFB,reg)
#define PFB_Print(reg) DEVICE_PRINT(PFB,reg)
#define PFB_Def(mask,value) DEVICE_DEF(PFB,mask,value)
#define PFB_Val(mask,value) DEVICE_VALUE(PFB,mask,value)
#define PFB_Mask(mask) DEVICE_MASK(PFB,mask)
 
#define PRM_Write(reg,value) DEVICE_WRITE(PRM,reg,value)
#define PRM_Read(reg) DEVICE_READ(PRM,reg)
#define PRM_Print(reg) DEVICE_PRINT(PRM,reg)
#define PRM_Def(mask,value) DEVICE_DEF(PRM,mask,value)
#define PRM_Val(mask,value) DEVICE_VALUE(PRM,mask,value)
#define PRM_Mask(mask) DEVICE_MASK(PRM,mask)
 
#define PGRAPH_Write(reg,value) DEVICE_WRITE(PGRAPH,reg,value)
#define PGRAPH_Read(reg) DEVICE_READ(PGRAPH,reg)
#define PGRAPH_Print(reg) DEVICE_PRINT(PGRAPH,reg)
#define PGRAPH_Def(mask,value) DEVICE_DEF(PGRAPH,mask,value)
#define PGRAPH_Val(mask,value) DEVICE_VALUE(PGRAPH,mask,value)
#define PGRAPH_Mask(mask) DEVICE_MASK(PGRAPH,mask)
 
#define PDMA_Write(reg,value) DEVICE_WRITE(PDMA,reg,value)
#define PDMA_Read(reg) DEVICE_READ(PDMA,reg)
#define PDMA_Print(reg) DEVICE_PRINT(PDMA,reg)
#define PDMA_Def(mask,value) DEVICE_DEF(PDMA,mask,value)
#define PDMA_Val(mask,value) DEVICE_VALUE(PDMA,mask,value)
#define PDMA_Mask(mask) DEVICE_MASK(PDMA,mask)
 
#define PFIFO_Write(reg,value) DEVICE_WRITE(PFIFO,reg,value)
#define PFIFO_Read(reg) DEVICE_READ(PFIFO,reg)
#define PFIFO_Print(reg) DEVICE_PRINT(PFIFO,reg)
#define PFIFO_Def(mask,value) DEVICE_DEF(PFIFO,mask,value)
#define PFIFO_Val(mask,value) DEVICE_VALUE(PFIFO,mask,value)
#define PFIFO_Mask(mask) DEVICE_MASK(PFIFO,mask)
 
#define PRAM_Write(reg,value) DEVICE_WRITE(PRAM,reg,value)
#define PRAM_Read(reg) DEVICE_READ(PRAM,reg)
#define PRAM_Print(reg) DEVICE_PRINT(PRAM,reg)
#define PRAM_Def(mask,value) DEVICE_DEF(PRAM,mask,value)
#define PRAM_Val(mask,value) DEVICE_VALUE(PRAM,mask,value)
#define PRAM_Mask(mask) DEVICE_MASK(PRAM,mask)
 
#define PRAMFC_Write(reg,value) DEVICE_WRITE(PRAMFC,reg,value)
#define PRAMFC_Read(reg) DEVICE_READ(PRAMFC,reg)
#define PRAMFC_Print(reg) DEVICE_PRINT(PRAMFC,reg)
#define PRAMFC_Def(mask,value) DEVICE_DEF(PRAMFC,mask,value)
#define PRAMFC_Val(mask,value) DEVICE_VALUE(PRAMFC,mask,value)
#define PRAMFC_Mask(mask) DEVICE_MASK(PRAMFC,mask)
 
#define PMC_Write(reg,value) DEVICE_WRITE(PMC,reg,value)
#define PMC_Read(reg) DEVICE_READ(PMC,reg)
#define PMC_Print(reg) DEVICE_PRINT(PMC,reg)
#define PMC_Def(mask,value) DEVICE_DEF(PMC,mask,value)
#define PMC_Val(mask,value) DEVICE_VALUE(PMC,mask,value)
#define PMC_Mask(mask) DEVICE_MASK(PMC,mask)
 
#define PMC_Write(reg,value) DEVICE_WRITE(PMC,reg,value)
#define PMC_Read(reg) DEVICE_READ(PMC,reg)
#define PMC_Print(reg) DEVICE_PRINT(PMC,reg)
#define PMC_Def(mask,value) DEVICE_DEF(PMC,mask,value)
#define PMC_Val(mask,value) DEVICE_VALUE(PMC,mask,value)
#define PMC_Mask(mask) DEVICE_MASK(PMC,mask)
 
 
#define PBUS_Write(reg,value) DEVICE_WRITE(PBUS,reg,value)
#define PBUS_Read(reg) DEVICE_READ(PBUS,reg)
#define PBUS_Print(reg) DEVICE_PRINT(PBUS,reg)
#define PBUS_Def(mask,value) DEVICE_DEF(PBUS,mask,value)
#define PBUS_Val(mask,value) DEVICE_VALUE(PBUS,mask,value)
#define PBUS_Mask(mask) DEVICE_MASK(PBUS,mask)
 
 
#define PRAMDAC_Write(reg,value) DEVICE_WRITE(PRAMDAC,reg,value)
#define PRAMDAC_Read(reg) DEVICE_READ(PRAMDAC,reg)
#define PRAMDAC_Print(reg) DEVICE_PRINT(PRAMDAC,reg)
#define PRAMDAC_Def(mask,value) DEVICE_DEF(PRAMDAC,mask,value)
#define PRAMDAC_Val(mask,value) DEVICE_VALUE(PRAMDAC,mask,value)
#define PRAMDAC_Mask(mask) DEVICE_MASK(PRAMDAC,mask)
 
 
#define PDAC_ReadExt(reg) \
((PDAC_Write(INDEX_LO,(NV_PDAC_EXT_##reg) & 0xff)),\
(PDAC_Write(INDEX_HI,((NV_PDAC_EXT_##reg) >> 8) & 0xff)),\
(PDAC_Read(INDEX_DATA)))
 
#define PDAC_WriteExt(reg,value)\
((PDAC_Write(INDEX_LO,(NV_PDAC_EXT_##reg) & 0xff)),\
(PDAC_Write(INDEX_HI,((NV_PDAC_EXT_##reg) >> 8) & 0xff)),\
(PDAC_Write(INDEX_DATA,(value))))
 
#define CRTC_Write(index,value) outb(CRT_IC,(index));outb(CRT_DC,value)
#define CRTC_Read(index) (outb(CRT_IC,index),inb(CRT_DC))
 
#define PCRTC_Write(index,value) __svgalib_outcrtc(NV_PCRTC_##index,value)
#define PCRTC_Read(index) __svgalib_incrtc(NV_PCRTC_##index)
 
#define PCRTC_Def(mask,value) DEVICE_DEF(PCRTC,mask,value)
#define PCRTC_Val(mask,value) DEVICE_VALUE(PCRTC,mask,value)
#define PCRTC_Mask(mask) DEVICE_MASK(PCRTC,mask)
 
#define SR_Write(index,value) outb(SEQ_I,(index));outb(SEQ_D,value)
#define SR_Read(index) (outb(SEQ_I,index),inb(SEQ_D))
 
#define PEXTDEV_Read(reg) DEVICE_READ(PEXTDEV,reg)
 
/* These are the variables which actually point at the register blocks */
 
/*typedef enum {NV1,NV3,NumNVChips} NVChipType;
 
NVChipType GetChipType(void);
*/
 
__END_DECLS
 
#endif
 
 
/shark/tags/rel_0_5/drivers/svga/vgaversion.h
0,0 → 1,7
#include "ll/sys/cdefs.h"
 
__BEGIN_DECLS
int vga_version=0x1917;
static char versionstr[32]="1.9.17";
__END_DECLS
 
/shark/tags/rel_0_5/drivers/svga/driver.h
0,0 → 1,199
/* VGAlib version 1.2 - (c) 1993 Tommy Frandsen */
/* */
/* This library is free software; you can redistribute it and/or */
/* modify it without any restrictions. This library is distributed */
/* in the hope that it will be useful, but without any warranty. */
 
/* Multi-chipset support Copyright (c) 1993 Harm Hanemaayer */
/* partially copyrighted (C) 1993 by Hartmut Schirmer */
 
#ifndef _DRIVER_H
#define _DRIVER_H
 
#include <stdio.h>
#include <stdarg.h>
#include "vga.h"
#include "libvga.h"
#include "timing.h"
#include "accel.h"
#include "io.h"
#include "ll/sys/cdefs.h"
 
__BEGIN_DECLS
 
#define MAX_REGS 5000 /* VESA needs a lot of storage space */
 
extern int inrestore;
 
typedef struct {
void (*savepalette)(unsigned char *red, unsigned char *green, unsigned char *blue);
void (*restorepalette)(const unsigned char *red,
const unsigned char *green, const unsigned char *blue);
int (*setpalette)(int index, int red, int green, int blue);
void (*getpalette)(int index, int *red, int *green, int *blue);
void (*savefont)(void);
void (*restorefont)(void);
int (*screenoff)(void);
int (*screenon)(void);
void (*waitretrace)(void);
} Emulation;
 
typedef struct {
/* Basic functions. */
int (*saveregs) (unsigned char regs[]);
void (*setregs) (const unsigned char regs[], int mode);
void (*unlock) (void);
void (*lock) (void);
int (*test) (void);
int (*init) (int force, int par1, int par2);
void (*__svgalib_setpage) (int page);
void (*__svgalib_setrdpage) (int page);
void (*__svgalib_setwrpage) (int page);
int (*setmode) (int mode, int prv_mode);
int (*modeavailable) (int mode);
void (*setdisplaystart) (int address);
void (*setlogicalwidth) (int width);
void (*getmodeinfo) (int mode, vga_modeinfo * modeinfo);
/* Obsolete blit functions. */
void (*bitblt) (int srcaddr, int destaddr, int w, int h, int pitch);
void (*imageblt) (void *srcaddr, int destaddr, int w, int h, int pitch);
void (*fillblt) (int destaddr, int w, int h, int pitch, int c);
void (*hlinelistblt) (int ymin, int n, int *xmin, int *xmax, int pitch, int c);
void (*bltwait) (void);
/* Other functions. */
int (*ext_set) (unsigned what, va_list params);
int (*accel) (unsigned operation, va_list params);
int (*linear) (int op, int param);
AccelSpecs *accelspecs;
Emulation *emul;
int (*cursor)(int cmd, int p1, int p2, int p3, int p4, void *p5);
} DriverSpecs;
 
extern DriverSpecs __svgalib_vga_driverspecs;
extern DriverSpecs __svgalib_neo_driverspecs;
extern DriverSpecs __svgalib_cirrus_driverspecs;
extern DriverSpecs __svgalib_et4000_driverspecs;
extern DriverSpecs __svgalib_tvga8900_driverspecs;
extern DriverSpecs __svgalib_oak_driverspecs;
extern DriverSpecs __svgalib_ega_driverspecs;
extern DriverSpecs __svgalib_s3_driverspecs;
extern DriverSpecs __svgalib_r128_driverspecs;
extern DriverSpecs __svgalib_mach32_driverspecs;
extern DriverSpecs __svgalib_et3000_driverspecs;
extern DriverSpecs __svgalib_gvga6400_driverspecs;
extern DriverSpecs __svgalib_ark_driverspecs;
extern DriverSpecs __svgalib_ati_driverspecs;
extern DriverSpecs __svgalib_ali_driverspecs;
extern DriverSpecs __svgalib_mach64_driverspecs;
extern DriverSpecs __svgalib_chips_driverspecs;
extern DriverSpecs __svgalib_apm_driverspecs;
extern DriverSpecs __svgalib_nv3_driverspecs;
extern DriverSpecs __svgalib_et6000_driverspecs;
extern DriverSpecs __svgalib_vesa_driverspecs;
extern DriverSpecs __svgalib_mx_driverspecs;
extern DriverSpecs __svgalib_paradise_driverspecs;
extern DriverSpecs __svgalib_rage_driverspecs;
extern DriverSpecs __svgalib_banshee_driverspecs;
extern DriverSpecs __svgalib_sis_driverspecs;
extern DriverSpecs __svgalib_i740_driverspecs;
extern DriverSpecs __svgalib_i810_driverspecs;
extern DriverSpecs __svgalib_laguna_driverspecs;
extern DriverSpecs __svgalib_fbdev_driverspecs;
extern DriverSpecs __svgalib_r128_driverspecs;
extern DriverSpecs __svgalib_g400_driverspecs;
extern DriverSpecs __svgalib_savage_driverspecs;
extern DriverSpecs __svgalib_mil_driverspecs;
extern DriverSpecs __svgalib_trident_driverspecs;
extern DriverSpecs __svgalib_rendition_driverspecs;
extern DriverSpecs __svgalib_g450c2_driverspecs;
extern DriverSpecs __svgalib_pm2_driverspecs;
 
extern DriverSpecs *__svgalib_driverspecs;
extern DriverSpecs *__svgalib_driverspecslist[];
 
enum {
CHIPSET_SAVEREGS = 0, CHIPSET_SETREGS, CHIPSET_UNLOCK, CHIPSET_LOCK,
CHIPSET_TEST, CHIPSET_INIT, CHIPSET_SETPAGE, CHIPSET_SETRDPAGE,
CHIPSET_SETWRPAGE, CHIPSET_SETMODE,
CHIPSET_MODEAVAILABLE, CHIPSET_SETDISPLAYSTART,
CHIPSET_SETLOGICALWIDTH, CHIPSET_GETMODEINFO,
CHIPSET_BITBLT, CHIPSET_IMAGEBLT, CHIPSET_FILLBLT,
CHIPSET_HLINELISTBLT, CHIPSET_BLTWAIT,
CHIPSET_EXT_SET, CHIPSET_ACCEL, CHIPSET_LINEAR
};
 
enum {
LINEAR_QUERY_BASE, LINEAR_QUERY_GRANULARITY, LINEAR_QUERY_RANGE,
LINEAR_ENABLE, LINEAR_DISABLE
};
 
enum { CURSOR_INIT, CURSOR_HIDE, CURSOR_SHOW, CURSOR_POSITION,
CURSOR_SELECT, CURSOR_IMAGE, CURSOR_SAVE
};
 
typedef struct {
/* refresh ranges in Hz */
unsigned min;
unsigned max;
} RefreshRange;
 
extern int __svgalib_CRT_I;
extern int __svgalib_CRT_D;
extern int __svgalib_IS1_R;
extern int __svgalib_driver_report; /* driverreport */
extern int __svgalib_videomemoryused; /* videomemoryused */
extern int __svgalib_critical;
extern int __svgalib_chipset;
extern RefreshRange __svgalib_horizsync;
extern RefreshRange __svgalib_vertrefresh;
extern int __svgalib_bandwidth;
extern int __svgalib_grayscale;
extern int __svgalib_modeinfo_linearset;
extern const int __svgalib_max_modes;
 
void __svgalib_read_options(char **commands, char *(*func) (int ind, int mode, char **nptr));
char *__svgalib_token(char **nptr);
/* ----------------------------------------------------------------------
** A modetable holds a pair of values
** for each mode :
**
** <mode number> <pointer to registers>
**
** the last entry is marked by
**
** <any number> <NULL>
*/
 
typedef struct {
unsigned short mode_number;
const unsigned char *regs;
} ModeTable;
 
#define DISABLE_MODE ((unsigned char *)1)
#define OneModeEntry(res) {G##res,g##res##_regs}
#define DisableEntry(res) {G##res,DISABLE_MODE}
#define END_OF_MODE_TABLE { 0, NULL }
 
extern const unsigned char *__svgalib_mode_in_table(const ModeTable * modes, int mode);
#define LOOKUPMODE __svgalib_mode_in_table
 
/* ---------------------------------------------------------------------- */
 
extern int __svgalib_hicolor(int dac_type, int mode);
/* Enters hicolor mode - 0 for no hi, 1 for 15 bit, 2 for 16, 3 for 24 */
/* For any modes it doesn't know about, etc, it attempts to turn hicolor off. */
 
#define STD_DAC 0
#define HI15_DAC 1
#define HI16_DAC 2
#define TC24_DAC 3
 
/* ----------------------------------------------------------------------
** regextr.h - extract graphics modes and register information
** from C source file
*/
 
extern void __svgalib_readmodes(FILE * inp, ModeTable ** modes, int *dac, unsigned *clocks);
 
__END_DECLS
#endif
/shark/tags/rel_0_5/drivers/svga/interrupt.h
0,0 → 1,8
#include "ll/sys/cdefs.h"
 
__BEGIN_DECLS
void vga_init_vsync(struct sh_pci_device *);
int vga_test_vsync(struct sh_pci_device *);
void vga_ack_vsync(struct sh_pci_device *);
void vga_enable_vsync(struct sh_pci_device *);
__END_DECLS
/shark/tags/rel_0_5/drivers/svga/clockchip.h
0,0 → 1,38
#include "ll/sys/cdefs.h"
 
__BEGIN_DECLS
 
/*
* clockchip.h
*/
 
/* ClockChipMethods type. */
 
typedef struct {
/*
* The following function initializes the ClockChip; it is usually
* called once after detection.
*/
void (*initialize) (CardSpecs * cardspecs, DacMethods * DAC);
/*
* ClockChip functions that override DAC methods.
*/
void (*saveState) (unsigned char *regs);
void (*restoreState) (const unsigned char *regs);
void (*initializeState) (unsigned char *regs, int bpp, int colormode,
int pixelclock);
/*
* Original DAC save and restore functions,
* to be called before clock manipulation.
*/
void (*DAC_saveState) (unsigned char *regs);
void (*DAC_restoreState) (const unsigned char *regs);
void (*DAC_initializeState) (unsigned char *regs, int bpp, int colormode,
int pixelclock);
long TextFrequency;
int DAC_stateSize;
} ClockChipMethods;
 
extern ClockChipMethods __svgalib_I2061A_clockchip_methods;
 
__END_DECLS
/shark/tags/rel_0_5/drivers/svga/8514a.h
0,0 → 1,95
/*
* 8514a.h: common header for 8514/A-like (S3, Mach) graphic engines
*
* Extracted from:
*
* ATI Mach32 driver Copyright 1995 Michael Weller
* eowmob@exp-math.uni-essen.de mat42b@aixrs1.hrz.uni-essen.de
* eowmob@pollux.exp-math.uni-essen.de
*/
 
#ifndef _8514A_H
#define _8514A_H
#include "ll/sys/cdefs.h"
 
__BEGIN_DECLS
 
#define CMD 0x9AE8
#define ALU_FG_FN 0xBAEE
#define ALU_BG_FN 0xB6EE
#define EXT_SCISSOR_B 0xE6EE
#define EXT_SCISSOR_L 0xD2EE
#define EXT_SCISSOR_R 0xE2EE
#define EXT_SCISSOR_T 0xDEEE
#define DP_CONFIG 0xCEEE
#define FRGD_MIX 0xBAE8
#define BKGD_MIX 0xB6E8
#define FRGD_COLOR 0xA6E8
#define BKGD_COLOR 0xA2E8
#define CUR_X 0x86E8
#define CUR_Y 0x82E8
#define MAJ_AXIS_PCNT 0x96E8
#define MULTI_FUNC_CNTL 0xBEE8
#define EXT_FIFO_STATUS 0x9AEE
#define ADVFUNC_CNTL 0x4AE8 /* S3 */
#define SUBSYS_CNTL 0x42E8
#define SUBSYS_STAT 0x42E8
#define SCRATCH_PAD_0 0x52EE
#define DESTX_DIASTP 0x8EE8
#define DESTY_AXSTP 0x8AE8
#define R_SRC_X 0xDAEE
#define SRC_X 0x8EE8
#define SRC_Y 0x8AE8
#define SRC_X_START 0xB2EE
#define SRC_X_END 0xBEEE
#define SRC_Y_DIR 0xC2EE
#define SCAN_TO_X 0xCAEE
#define DEST_X_START 0xA6EE
#define DEST_X_END 0xAAEE
#define DEST_Y_END 0xAEEE
#define GE_STAT 0x9AE8
#define CONF_STAT1 0x12EE
#define CONF_STAT2 0x16EE
#define MISC_OPTIONS 0x36EE
#define MEM_CFG 0x5EEE
#define MEM_BNDRY 0x42EE
#define LOCAL_CNTL 0x32EE
#define CHIP_ID 0xFAEE
#define EXT_GE_CONF 0x7AEE
#define R_EXT_GE_CONF 0x8EEE
#define DISP_CNTL 0x22E8
#define CLOCK_SEL 0x4AEE
#define GE_PITCH 0x76EE
#define GE_OFFSET_HI 0x72EE
#define GE_OFFSET_LO 0x6EEE
#define CRT_PITCH 0x26EE
#define CRT_OFFSET_HI 0x2EEE
#define CRT_OFFSET_LO 0x2AEE
#define H_DISP 0x06E8
#define H_TOTAL 0x02E8
#define H_SYNC_WID 0x0EE8
#define H_SYNC_STRT 0x0AE8
#define V_DISP 0x16E8
#define V_SYNC_STRT 0x1AE8
#define V_SYNC_WID 0x1EE8
#define V_TOTAL 0x12E8
#define R_H_TOTAL 0xB2EE
#define R_H_SYNC_STRT 0xB6EE
#define R_H_SYNC_WID 0xBAEE
#define R_V_TOTAL 0xC2EE
#define R_V_DISP 0xC6EE
#define R_V_SYNC_STRT 0xCAEE
#define R_V_SYNC_WID 0xD2EE
#define SHADOW_SET 0x5AEE
#define SHADOW_CTL 0x46EE
#define MISC_CTL 0x7EEE
#define R_MISC_CTL 0x92EE
#define LINEDRAW 0xFEEE
#define LINEDRAW_INDEX 0x9AEE
#define LINEDRAW_OPT 0xA2EE
#define PIX_TRANS 0xE2E8
#define DEST_CMP_FN 0xEEEE
#define CMP_COLOR 0xB2E8
#define RD_MASK 0xAEE8
__END_DECLS
#endif /* _8514A_H */
/shark/tags/rel_0_5/drivers/svga/lrmi.h
0,0 → 1,60
/*
Linux Real Mode Interface - A library of DPMI-like functions for Linux.
 
Copyright (C) 1998 by Josh Vanderhoof
 
You are free to distribute and modify this file, as long as you
do not remove this copyright notice and clearly label modified
versions as being modified.
 
This software has NO WARRANTY. Use it at your own risk.
*/
 
#ifndef LRMI_H
#define LRMI_H
 
#include "ll/sys/cdefs.h"
 
__BEGIN_DECLS
 
struct LRMI_regs
{
unsigned int edi;
unsigned int esi;
unsigned int ebp;
unsigned int reserved;
unsigned int ebx;
unsigned int edx;
unsigned int ecx;
unsigned int eax;
unsigned short int flags;
unsigned short int es;
unsigned short int ds;
unsigned short int fs;
unsigned short int gs;
unsigned short int ip;
unsigned short int cs;
unsigned short int sp;
unsigned short int ss;
};
 
 
#ifndef LRMI_PREFIX
#define LRMI_PREFIX __svgalib_LRMI_
#endif
 
#define LRMI_CONCAT2(a, b) a ## b
#define LRMI_CONCAT(a, b) LRMI_CONCAT2(a, b)
#define LRMI_MAKENAME(a) LRMI_CONCAT(LRMI_PREFIX, a)
 
/*
Simulate a 16 bit interrupt
returns 1 if sucessful, 0 for failure
*/
#define LRMI_int LRMI_MAKENAME(int)
int
LRMI_int(int interrupt, struct LRMI_regs *r);
 
__END_DECLS
 
#endif
/shark/tags/rel_0_5/drivers/svga/vgaio.h
0,0 → 1,19
#include "libvga.h"
#include "ll/sys/cdefs.h"
 
__BEGIN_DECLS
extern int __svgalib_vga_inmisc(void);
extern void __svgalib_vga_outmisc(int i);
extern int __svgalib_vga_incrtc(int i);
extern void __svgalib_vga_outcrtc(int i, int d);
extern int __svgalib_vga_inseq(int i);
extern void __svgalib_vga_outseq(int i, int d);
extern int __svgalib_vga_ingra(int i);
extern void __svgalib_vga_outgra(int i, int d);
extern int __svgalib_vga_inis1(void);
extern int __svgalib_vga_inatt(int i);
extern void __svgalib_vga_outatt(int i, int d);
extern void __svgalib_vga_attscreen(int i);
extern void __svgalib_vga_inpal(int i, int *r, int *g, int *b);
extern void __svgalib_vga_outpal(int i, int r, int g, int b);
__END_DECLS
/shark/tags/rel_0_5/drivers/svga/vga.h
0,0 → 1,589
/* VGAlib version 1.2 - (c) 1993 Tommy Frandsen */
/* */
/* This library is free software; you can redistribute it and/or */
/* modify it without any restrictions. This library is distributed */
/* in the hope that it will be useful, but without any warranty. */
 
/* Extended for svgalib by Harm Hanemaayer and Hartmut Schirmer */
 
#ifndef VGA_H
#define VGA_H
 
#include <sys/types.h>
#include <sys/time.h>
#include <drivers/grxsvga/glib.h>
#include <kernel/log.h>
 
#include "ll/sys/cdefs.h"
 
__BEGIN_DECLS
#define rgb15(r, g, b) ((((WORD)(r & 0xF8)>>3) << 10) | (((WORD)(g & 0xF8)>>3) << 5) | ((WORD)(b & 0xF8)>>3))
#define rgb16(r, g, b) ((((WORD)(r & 0xF8)>>3) << 11) | (((WORD)(g & 0xFC)>>2) << 5) | ((WORD)(b & 0xF8)>>3))
#define rgb24(r, g, b) (((DWORD)(r & 0xFF) << 16) | ((DWORD)(g & 0xFF) << 8) | (DWORD)(b & 0xFF))
#define rgb32(r, g, b) (((DWORD)(r & 0xFF) << 16) | ((DWORD)(g & 0xFF) << 8) | (DWORD)(b & 0xFF))
#define rgba(r, g, b) (((DWORD)(b & 0xFF) << 16) | ((DWORD)(g & 0xFF) << 8) | (DWORD)(r & 0xFF))
#define SVGALIB_VER 0x010900
 
#define TEXT 0 /* Compatible with VGAlib v1.2 */
#define G320x200x16 1
#define G640x200x16 2
#define G640x350x16 3
#define G640x480x16 4
#define G320x200x256 5
#define G320x240x256 6
#define G320x400x256 7
#define G360x480x256 8
#define G640x480x2 9
 
#define G640x480x256 10
#define G800x600x256 11
#define G1024x768x256 12
 
#define G1280x1024x256 13 /* Additional modes. */
 
#define G320x200x32K 14
#define G320x200x64K 15
#define G320x200x16M 16
#define G640x480x32K 17
#define G640x480x64K 18
#define G640x480x16M 19
#define G800x600x32K 20
#define G800x600x64K 21
#define G800x600x16M 22
#define G1024x768x32K 23
#define G1024x768x64K 24
#define G1024x768x16M 25
#define G1280x1024x32K 26
#define G1280x1024x64K 27
#define G1280x1024x16M 28
 
#define G800x600x16 29
#define G1024x768x16 30
#define G1280x1024x16 31
 
#define G720x348x2 32 /* Hercules emulation mode */
 
#define G320x200x16M32 33 /* 32-bit per pixel modes. */
#define G640x480x16M32 34
#define G800x600x16M32 35
#define G1024x768x16M32 36
#define G1280x1024x16M32 37
 
/* additional resolutions */
#define G1152x864x16 38
#define G1152x864x256 39
#define G1152x864x32K 40
#define G1152x864x64K 41
#define G1152x864x16M 42
#define G1152x864x16M32 43
 
#define G1600x1200x16 44
#define G1600x1200x256 45
#define G1600x1200x32K 46
#define G1600x1200x64K 47
#define G1600x1200x16M 48
#define G1600x1200x16M32 49
 
#define G320x240x256V 50
#define G320x240x32K 51
#define G320x240x64K 52
#define G320x240x16M 53
#define G320x240x16M32 54
 
#define G400x300x256 55
#define G400x300x32K 56
#define G400x300x64K 57
#define G400x300x16M 58
#define G400x300x16M32 59
 
#define G512x384x256 60
#define G512x384x32K 61
#define G512x384x64K 62
#define G512x384x16M 63
#define G512x384x16M32 64
 
#define G960x720x256 65
#define G960x720x32K 66
#define G960x720x64K 67
#define G960x720x16M 68
#define G960x720x16M32 69
 
#define G1920x1440x256 70
#define G1920x1440x32K 71
#define G1920x1440x64K 72
#define G1920x1440x16M 73
#define G1920x1440x16M32 74
 
/* The following modes have been introduced by SciTech Display Doctor */
 
#define G320x400x256V 75
#define G320x400x32K 76
#define G320x400x64K 77
#define G320x400x16M 78
#define G320x400x16M32 79
 
#define G640x400x256 80
#define G640x400x32K 81
#define G640x400x64K 82
#define G640x400x16M 83
#define G640x400x16M32 84
 
#define G320x480x256 85
#define G320x480x32K 86
#define G320x480x64K 87
#define G320x480x16M 88
#define G320x480x16M32 89
 
#define G720x540x256 90
#define G720x540x32K 91
#define G720x540x64K 92
#define G720x540x16M 93
#define G720x540x16M32 94
 
#define G848x480x256 95
#define G848x480x32K 96
#define G848x480x64K 97
#define G848x480x16M 98
#define G848x480x16M32 99
 
#define G1072x600x256 100
#define G1072x600x32K 101
#define G1072x600x64K 102
#define G1072x600x16M 103
#define G1072x600x16M32 104
 
#define G1280x720x256 105
#define G1280x720x32K 106
#define G1280x720x64K 107
#define G1280x720x16M 108
#define G1280x720x16M32 109
 
#define G1360x768x256 110
#define G1360x768x32K 111
#define G1360x768x64K 112
#define G1360x768x16M 113
#define G1360x768x16M32 114
 
#define G1800x1012x256 115
#define G1800x1012x32K 116
#define G1800x1012x64K 117
#define G1800x1012x16M 118
#define G1800x1012x16M32 119
 
#define G1920x1080x256 120
#define G1920x1080x32K 121
#define G1920x1080x64K 122
#define G1920x1080x16M 123
#define G1920x1080x16M32 124
 
#define G2048x1152x256 125
#define G2048x1152x32K 126
#define G2048x1152x64K 127
#define G2048x1152x16M 128
#define G2048x1152x16M32 129
 
#define G2048x1536x256 130
#define G2048x1536x32K 131
#define G2048x1536x64K 132
#define G2048x1536x16M 133
#define G2048x1536x16M32 134
 
#define G512x480x256 135
#define G512x480x32K 136
#define G512x480x64K 137
#define G512x480x16M 138
#define G512x480x16M32 139
 
#define G400x600x256 140
#define G400x600x32K 141
#define G400x600x64K 142
#define G400x600x16M 143
#define G400x600x16M32 144
 
#define G400x300x256X 145
 
#define G320x200x256V 146
 
#define __GLASTMODE G320x200x256V
#define GLASTMODE vga_lastmodenumber()
 
#define IS_IN_STANDARD_VGA_DRIVER(mode) ( \
((mode) < G640x480x256) || ((mode) == G720x348x2) || \
( ((mode) >= G400x300x256X) && ((mode) <= G400x300x256X) ) )
 
extern int vga_version;
extern int __svgalib_chipset;
 
extern int vga_setmode(int mode, int set_chipset);
extern int vga_hasmode(int mode);
extern int vga_setflipchar(int c);
 
extern int vga_clear(void);
extern int vga_flip(void);
 
extern int vga_getxdim(void);
extern int vga_getydim(void);
extern int vga_getcolors(void);
 
extern int vga_setpalette(int index, int red, int green, int blue);
extern int vga_getpalette(int index, int *red, int *green, int *blue);
extern int vga_setpalvec(int start, int num, int *pal);
extern int vga_getpalvec(int start, int num, int *pal);
 
extern int vga_screenoff(void);
extern int vga_screenon(void);
 
extern int vga_setcolor(int color);
extern int vga_drawpixel(int x, int y);
extern int vga_drawline(int x1, int y1, int x2, int y2);
extern int vga_drawscanline(int line, unsigned char *colors);
extern int vga_drawscansegment(unsigned char *colors, int x, int y, int length);
extern int vga_getpixel(int x, int y); /* Added. */
extern int vga_getscansegment(unsigned char *colors, int x, int y, int length);
 
extern int vga_getch(void);
 
extern int vga_dumpregs(void);
 
 
/* Extensions to VGAlib v1.2: */
 
/* blit flags */
#define HAVE_BITBLIT 1
#define HAVE_FILLBLIT 2
#define HAVE_IMAGEBLIT 4
#define HAVE_HLINELISTBLIT 8
#define HAVE_BLITWAIT 16
 
/* other flags */
#define HAVE_RWPAGE 1 /* vga_setreadpage() / vga_setwritepage() available */
#define IS_INTERLACED 2 /* mode is interlaced */
#define IS_MODEX 4 /* ModeX style 256 colors */
#define IS_DYNAMICMODE 8 /* Dynamic defined mode */
#define CAPABLE_LINEAR 16 /* Can go to linear addressing mode. */
#define IS_LINEAR 32 /* Linear addressing can be used. */
#define LINEAR_MODE 512 /* Linear mode is enabled */
#define EXT_INFO_AVAILABLE 64 /* Returned modeinfo contains valid extended fields */
#define RGB_MISORDERED 128 /* Mach32 32bpp uses 0BGR instead of BGR0. */
/* As of this version 1.25 also used to signal if real RGB
(red first in memory) is used instead of BGR (Mach32 DAC 4) */
#define HAVE_EXT_SET 256 /* vga_ext_set() available */
 
typedef struct {
int width;
int height;
int bytesperpixel;
int colors;
int linewidth; /* scanline width in bytes */
int maxlogicalwidth; /* maximum logical scanline width */
int startaddressrange; /* changeable bits set */
int maxpixels; /* video memory / bytesperpixel */
int haveblit; /* mask of blit functions available */
int flags; /* other flags */
 
/* Extended fields: */
 
int chiptype; /* Chiptype detected */
int memory; /* videomemory in KB */
int linewidth_unit; /* Use only a multiple of this as parameter for set_logicalwidth and
set_displaystart */
char *linear_aperture; /* points to mmap secondary mem aperture of card (NULL if unavailable) */
int aperture_size; /* size of aperture in KB if size>=videomemory. 0 if unavail */
void (*set_aperture_page) (int page);
/* if aperture_size<videomemory select a memory page */
void *extensions; /* points to copy of eeprom for mach32 */
/* depends from actual driver/chiptype.. etc. */
} vga_modeinfo;
 
typedef struct {
int version;
int size;
int chipset;
int physmem;
} vga_cardinfo;
 
extern vga_cardinfo *vga_getcardinfo(void);
extern vga_modeinfo *vga_getmodeinfo(int mode);
extern int vga_getdefaultmode(void);
extern int vga_getcurrentmode(void);
extern int vga_getcurrentchipset(void);
extern char *vga_getmodename(int mode);
extern int vga_getmodenumber(char *name);
extern int vga_lastmodenumber(void);
extern int vga_getoptmode(int x, int y, int colors, int bytesperpixel, int c);
 
extern unsigned char *graph_mem;
extern unsigned char *vga_getgraphmem(void);
 
extern void vga_setpage(int p);
extern void vga_setreadpage(int p);
extern void vga_setwritepage(int p);
extern void vga_setlogicalwidth(int w);
extern void vga_setdisplaystart(int a);
extern void vga_waitretrace(void);
extern int vga_claimvideomemory(int n);
extern void vga_disabledriverreport(void);
extern int vga_setmodeX(void);
extern int vga_init(void); /* Used to return void in svgalib <= 1.12. */
extern int vga_initf(int);
extern int vga_getmousetype(void);
extern int vga_getmonitortype(void);
extern void vga_setmousesupport(int s);
extern void vga_lockvc(void);
extern void vga_unlockvc(void);
extern int vga_getkey(void);
extern int vga_oktowrite(void);
extern void vga_copytoplanar256(unsigned char *virtualp, int pitch,
int voffset, int vpitch, int w, int h);
extern void vga_copytoplanar16(unsigned char *virtualp, int pitch,
int voffset, int vpitch, int w, int h);
extern void vga_copytoplane(unsigned char *virtualp, int pitch,
int voffset, int vpitch, int w, int h, int plane);
extern int vga_setlinearaddressing(void);
extern void vga_safety_fork(void (*shutdown_routine) (void));
 
extern int vga_simple_init(void);
extern void vga_chipset_saveregs(unsigned char *);
extern void vga_chipset_setregs(unsigned char *);
 
#ifdef EGA /* Kernel headers may define this. */
#undef EGA
#endif
 
#define UNDEFINED 0
#define VGA 1
#define ET4000 2
#define CIRRUS 3
#define TVGA8900 4
#define OAK 5
#define EGA 6
#define S3 7
#define ET3000 8
#define MACH32 9
#define GVGA6400 10
#define ARK 11
#define ATI 12
#define ALI 13
#define MACH64 14
#define CHIPS 15
#define APM 16
#define NV3 17
#define ET6000 18
#define VESA 19
#define MX 20
#define PARADISE 21
#define RAGE 22
#define BANSHEE 23
#define SIS 24
#define I740 25
#define NEOMAGIC 26
#define LAGUNA 27
#define FBDEV 28
#define G400 29
#define R128 30
#define SAVAGE 31
#define MILLENNIUM 32
#define I810 33
#define TRIDENT 34
#define RENDITION 35
#define G450C2 36
#define PM2 37
/* Hor. sync: */
#define MON640_60 0 /* 31.5 KHz (standard VGA) */
#define MON800_56 1 /* 35.1 KHz (old SVGA) */
#define MON1024_43I 2 /* 35.5 KHz (low-end SVGA, 8514) */
#define MON800_60 3 /* 37.9 KHz (SVGA) */
#define MON1024_60 4 /* 48.3 KHz (SVGA non-interlaced) */
#define MON1024_70 5 /* 56.0 KHz (SVGA high frequency) */
#define MON1024_72 6
 
extern void vga_setchipset(int c);
extern void vga_setchipsetandfeatures(int c, int par1, int par2);
extern void vga_gettextfont(void *font);
extern void vga_puttextfont(void *font);
extern void vga_settextmoderegs(void *regs);
extern void vga_gettextmoderegs(void *regs);
 
extern int vga_white(void);
extern int vga_setegacolor(int c);
extern int vga_setrgbcolor(int r, int g, int b);
 
extern void vga_bitblt(int srcaddr, int destaddr, int w, int h, int pitch);
extern void vga_imageblt(void *srcaddr, int destaddr, int w, int h, int pitch);
extern void vga_fillblt(int destaddr, int w, int h, int pitch, int c);
extern void vga_hlinelistblt(int ymin, int n, int *xmin, int *xmax, int pitch, int c);
extern void vga_blitwait(void);
extern int vga_ext_set(unsigned what,...);
extern int vga_accel(unsigned operation,...);
 
extern int vga_initcursor(int);
extern void vga_showcursor(int);
extern void vga_setcursorposition(int, int);
extern void vga_selectcursor(int);
extern void vga_setcursorimage(int, int, int, int, unsigned char *);
 
inline void copy_videomem_32to16(void *src, void *dst, unsigned long int memdiv2);
inline void copy_videomem_16to16(void *src, void *dst, unsigned long int memdiv4);
 
extern int vga_setcrtcregs(unsigned char *);
extern int vga_getcrtcregs(unsigned char *);
 
extern int vga_addtiming(int pixelClock,
int HDisplay,
int HSyncStart,
int HSyncEnd,
int HTotal,
int VDisplay,
int VSyncStart,
int VSyncEnd,
int VTotal,
int flags);
 
extern int vga_changetiming(int pixelClock,
int HDisplay,
int HSyncStart,
int HSyncEnd,
int HTotal,
int VDisplay,
int VSyncStart,
int VSyncEnd,
int VTotal,
int flags);
 
extern int vga_getcurrenttiming(int *pixelClock,
int *HDisplay,
int *HSyncStart,
int *HSyncEnd,
int *HTotal,
int *VDisplay,
int *VSyncStart,
int *VSyncEnd,
int *VTotal,
int *flags);
 
extern int vga_addmode(int xdim, int ydim, int cols,
int xbytes, int bytespp);
 
extern int vga_guesstiming(int x, int y, int clue, int arg);
 
extern void vga_dpms(int mode);
 
/* Valid values for what in vga_ext_set: */
#define VGA_EXT_AVAILABLE 0 /* supported flags */
#define VGA_EXT_SET 1 /* set flag(s) */
#define VGA_EXT_CLEAR 2 /* clear flag(s) */
#define VGA_EXT_RESET 3 /* set/clear flag(s) */
#define VGA_EXT_PAGE_OFFSET 4 /* set an offset for all subsequent vga_set*page() calls */
/* Like: vga_ext_set(VGA_EXT_PAGE_OFFSET, 42); */
/* returns the previous offset value. */
#define VGA_EXT_FONT_SIZE 5 /* the (maximal) size of the font buffer */
 
/* Valid params for VGA_EXT_AVAILABLE: */
#define VGA_AVAIL_SET 0 /* vga_ext_set sub funcs */
#define VGA_AVAIL_ACCEL 1 /* vga_accel sub funcs */
#define VGA_AVAIL_FLAGS 2 /* known flags for VGA_EXT_SET */
#define VGA_AVAIL_ROP 3 /* vga_accel ROP sub funcs */
#define VGA_AVAIL_TRANSPARENCY 4 /* vga_accel TRANSPARENCY sub funcs */
#define VGA_AVAIL_ROPMODES 5 /* vga_accel ROP modes supported funcs */
#define VGA_AVAIL_TRANSMODES 6 /* vga_accel TRANSPARENCY modes supported */
 
/* Known flags to vga_ext_set() */
#define VGA_CLUT8 1 /* 8 bit DAC entries */
 
/* Acceleration interface. */
 
/* Accel operations. */
#define ACCEL_FILLBOX 1 /* Simple solid fill. */
#define ACCEL_SCREENCOPY 2 /* Simple screen-to-screen BLT. */
#define ACCEL_PUTIMAGE 3 /* Straight image transfer. */
#define ACCEL_DRAWLINE 4 /* General line draw. */
#define ACCEL_SETFGCOLOR 5 /* Set foreground color. */
#define ACCEL_SETBGCOLOR 6 /* Set background color. */
#define ACCEL_SETTRANSPARENCY 7 /* Set transparency mode. */
#define ACCEL_SETRASTEROP 8 /* Set raster-operation. */
#define ACCEL_PUTBITMAP 9 /* Color-expand bitmap. */
#define ACCEL_SCREENCOPYBITMAP 10 /* Color-expand from screen. */
#define ACCEL_DRAWHLINELIST 11 /* Draw horizontal spans. */
#define ACCEL_SETMODE 12 /* Set blit strategy. */
#define ACCEL_SYNC 13 /* Wait for blits to finish. */
#define ACCEL_SETOFFSET 14 /* Set screen offset */
#define ACCEL_SCREENCOPYMONO 15 /* Monochrome screen-to-screen BLT. */
#define ACCEL_POLYLINE 16 /* Draw multiple lines. */
#define ACCEL_POLYHLINE 17 /* Draw multiple horizontal spans. */
#define ACCEL_POLYFILLMODE 18 /* Set polygon mode. */
 
/* Corresponding bitmask. */
#define ACCELFLAG_FILLBOX 0x1 /* Simple solid fill. */
#define ACCELFLAG_SCREENCOPY 0x2 /* Simple screen-to-screen BLT. */
#define ACCELFLAG_PUTIMAGE 0x4 /* Straight image transfer. */
#define ACCELFLAG_DRAWLINE 0x8 /* General line draw. */
#define ACCELFLAG_SETFGCOLOR 0x10 /* Set foreground color. */
#define ACCELFLAG_SETBGCOLOR 0x20 /* Set background color. */
#define ACCELFLAG_SETTRANSPARENCY 0x40 /* Set transparency mode. */
#define ACCELFLAG_SETRASTEROP 0x80 /* Set raster-operation. */
#define ACCELFLAG_PUTBITMAP 0x100 /* Color-expand bitmap. */
#define ACCELFLAG_SCREENCOPYBITMAP 0x200 /* Color-exand from screen. */
#define ACCELFLAG_DRAWHLINELIST 0x400 /* Draw horizontal spans. */
#define ACCELFLAG_SETMODE 0x800 /* Set blit strategy. */
#define ACCELFLAG_SYNC 0x1000 /* Wait for blits to finish. */
#define ACCELFLAG_SETOFFSET 0x2000 /* Set screen offset */
#define ACCELFLAG_SCREENCOPYMONO 0x4000 /* Monochrome screen-to-screen BLT. */
#define ACCELFLAG_POLYLINE 0x8000 /* Draw multiple lines. */
#define ACCELFLAG_POLYHLINE 0x10000 /* Draw multiple horizontal spans. */
#define ACCELFLAG_POLYFILLMODE 0x20000 /* Set polygon mode. */
 
/* Mode for SetTransparency. */
#define DISABLE_TRANSPARENCY_COLOR 0
#define ENABLE_TRANSPARENCY_COLOR 1
#define DISABLE_BITMAP_TRANSPARENCY 2
#define ENABLE_BITMAP_TRANSPARENCY 3
 
/* Flags for SetMode (accelerator interface). */
#define BLITS_SYNC 0
#define BLITS_IN_BACKGROUND 0x1
 
/* Raster ops. */
#define ROP_COPY 0 /* Straight copy. */
#define ROP_OR 1 /* Source OR destination. */
#define ROP_AND 2 /* Source AND destination. */
#define ROP_XOR 3 /* Source XOR destination. */
#define ROP_INVERT 4 /* Invert destination. */
 
/* For the poly funcs */
#define ACCEL_START 1
#define ACCEL_END 2
 
/*
* wait for keypress, mousemove, I/O, timeout. cf. select (3) for details on
* all parameters execept which.
* NULL is a valid argument for any of the ptrs.
*/
 
// extern int vga_waitevent(int which, fd_set * in, fd_set * out, fd_set * except, //SHARK
// struct timeval *timeout); //SHARK
 
/*
* valid values for what ( | is valid to combine them )
*/
#define VGA_MOUSEEVENT 1
#define VGA_KEYEVENT 2
 
/*
* return value >= has bits set for mouse/keyboard events detected.
* mouse and raw keyboard events are already handled and their bits removed
* from *in when vga_waitevent returns.
* VGA_KEYEVENT relates to vga_getch NOT vga_getkey.
* return values < 0 signal errors. In this case check errno.
*/
 
/* Background running */
extern void vga_runinbackground(int stat, ...);
#define VGA_GOTOBACK -1
#define VGA_COMEFROMBACK -2
extern int vga_runinbackground_version(void);
 
__END_DECLS
 
#endif /* VGA_H */
/shark/tags/rel_0_5/drivers/svga/svgalib_helper.h
0,0 → 1,96
#ifndef __SVGALIB_HELPER__
#define __SVGALIB_HELPER__
 
#include "ll/sys/cdefs.h"
 
__BEGIN_DECLS
 
#ifdef __KERNEL__
 
#define MAX_NR_DEVICES 15
 
#define address_t unsigned long
 
struct sh_pci_device {
unsigned short vendor;
unsigned short id;
unsigned char revision;
struct pci_dev *dev;
address_t mem[6];
address_t len[6];
address_t mask[6];
int flags[6];
unsigned long iobase;
int (*test_vsync)(struct sh_pci_device *);
void (*ack_vsync)(struct sh_pci_device *);
void (*enable_vsync)(struct sh_pci_device *);
};
 
#endif
 
typedef struct {
int port;
int length;
unsigned char* string;
} io_string_t;
 
typedef struct {
int port;
unsigned int val;
} io_t;
 
typedef struct {
int pcipos;
unsigned int address;
unsigned long val;
} pcic_t;
 
typedef struct {
void *win;
void *lfb;
} windowing_t;
 
#define SVGALIB_HELPER_IOC_MAGIC 0xB3
 
#define SVGALIB_HELPER_IOCSOUTB _IOR(SVGALIB_HELPER_IOC_MAGIC,1,io_t)
#define SVGALIB_HELPER_IOCSOUTW _IOR(SVGALIB_HELPER_IOC_MAGIC,2,io_t)
#define SVGALIB_HELPER_IOCSOUTL _IOR(SVGALIB_HELPER_IOC_MAGIC,3,io_t)
#define SVGALIB_HELPER_IOCGINB _IOW(SVGALIB_HELPER_IOC_MAGIC,4,io_t)
#define SVGALIB_HELPER_IOCGINW _IOW(SVGALIB_HELPER_IOC_MAGIC,5,io_t)
#define SVGALIB_HELPER_IOCGINL _IOW(SVGALIB_HELPER_IOC_MAGIC,6,io_t)
 
#define SVGALIB_HELPER_IOCSPCIOUTB _IOR(SVGALIB_HELPER_IOC_MAGIC,11,pcic_t)
#define SVGALIB_HELPER_IOCSPCIOUTW _IOR(SVGALIB_HELPER_IOC_MAGIC,12,pcic_t)
#define SVGALIB_HELPER_IOCSPCIOUTL _IOR(SVGALIB_HELPER_IOC_MAGIC,13,pcic_t)
#define SVGALIB_HELPER_IOCGPCIINB _IOW(SVGALIB_HELPER_IOC_MAGIC,14,pcic_t)
#define SVGALIB_HELPER_IOCGPCIINW _IOW(SVGALIB_HELPER_IOC_MAGIC,15,pcic_t)
#define SVGALIB_HELPER_IOCGPCIINL _IOW(SVGALIB_HELPER_IOC_MAGIC,16,pcic_t)
#define SVGALIB_HELPER_IOCGPCIAPLEN _IOW(SVGALIB_HELPER_IOC_MAGIC,17,pcic_t)
 
#define SVGALIB_HELPER_IOCDVMA _IO(SVGALIB_HELPER_IOC_MAGIC,7)
#define SVGALIB_HELPER_IOCSWIND _IOR(SVGALIB_HELPER_IOC_MAGIC,8,windowing_t)
 
#define SVGALIB_HELPER_IOCIOPERM _IO(SVGALIB_HELPER_IOC_MAGIC,9)
#define SVGALIB_HELPER_IOCSREPOUTB _IOR(SVGALIB_HELPER_IOC_MAGIC,10,io_t)
 
#define SVGALIB_HELPER_IOCGI810GTT _IOW(SVGALIB_HELPER_IOC_MAGIC,128,unsigned int *)
#define SVGALIB_HELPER_IOCGI810GTTE _IOW(SVGALIB_HELPER_IOC_MAGIC,129,unsigned int *)
 
#define SVGALIB_HELPER_IOCSWRITEB _IOR(SVGALIB_HELPER_IOC_MAGIC,21,io_t)
#define SVGALIB_HELPER_IOCSWRITEW _IOR(SVGALIB_HELPER_IOC_MAGIC,22,io_t)
#define SVGALIB_HELPER_IOCSWRITEL _IOR(SVGALIB_HELPER_IOC_MAGIC,23,io_t)
#define SVGALIB_HELPER_IOCGREADB _IOW(SVGALIB_HELPER_IOC_MAGIC,24,io_t)
#define SVGALIB_HELPER_IOCGREADW _IOW(SVGALIB_HELPER_IOC_MAGIC,25,io_t)
#define SVGALIB_HELPER_IOCGREADL _IOW(SVGALIB_HELPER_IOC_MAGIC,26,io_t)
 
#define SVGALIB_HELPER_IOCWAITRETRACE _IO(SVGALIB_HELPER_IOC_MAGIC,31)
 
struct inode {};
 
int svgalib_helper_ioctl( struct inode *inode, unsigned int cmd, unsigned long arg);
 
__END_DECLS
 
#endif
 
 
/shark/tags/rel_0_5/drivers/svga/ramdac.h
0,0 → 1,172
/*
* ramdac.h:
*
* Structures and functions for programmable ramdac support.
*/
 
#include "ll/sys/cdefs.h"
 
__BEGIN_DECLS
 
/* DacMethods type. */
 
typedef struct {
int id;
char *name;
int flags;
/*
* The following function tries to detect the DAC;
* returns nonzero if succesful.
*/
int (*probe) (void);
/*
* The following function initializes the DAC; it is usually
* called once after detection.
*/
void (*initialize) (void);
/*
* The following function fills in dot clock limits, and
* mapping functions for the raw clock and horizontal
* CRTC timing, in the cardspecs structure.
*
* dacspeed is the max pixel clock in kHz the dac can handle,
* or 0 for default.
*/
void (*qualifyCardSpecs) (CardSpecs * cardspecs, int dacspeed);
/*
* The following function saves RAMDAC registers into regs.
*/
void (*saveState) (unsigned char *regs);
/*
* The following function sets the RAMDAC registers with the
* values from regs.
*/
void (*restoreState) (const unsigned char *regs);
/*
* The following function sets up the RAMDAC register values
* for the desired color operating mode. If the DAC has
* programmable clocks, it should also program the clock.
*/
void (*initializeState) (unsigned char *regs, int bpp, int colormode,
int pixelclock);
int stateSize; /* Size in bytes of the state (saved registers). */
} DacMethods;
 
/* IDs */
 
#define NORMAL_DAC 1
#define S3_GENDAC 2 /* S3-GenDAC (8-bit DAC). */
#define S3_SDAC 3 /* S3-SDAC (16-bit DAC). */
#define TRIO64 4 /* Trio64 internal DAC. */
#define SIERRA_32K 5 /* Basic DAC with 32K color mode support. */
#define ATT20C490 6 /* Standard AT&T 8-bit DAC with truecolor. */
#define ATT20C498 7 /* Standard AT&T 16-bit DAC. */
#define IC_WORKS 8 /* IC Works DAC (16-bit ZoomDac). */
#define SIERRA_15025 9 /* Sierra SC15025/26 DAC. */
#define IBMRGB52x 10 /* IBM RGB52x Palette DAC. */
#define SIERRA_1148X 11 /* Sierra SC1148x DAC. */
 
/* Flags. */
 
#define DAC_HAS_PROGRAMMABLE_CLOCKS 0x1
 
/* Color modes. */
 
#define CLUT8_6 0
#define CLUT8_8 1
#define RGB16_555 2
#define RGB16_565 3
#define RGB24_888_B 4 /* 3 bytes per pixel, blue byte first. */
#define RGB32_888_B 5 /* 4 bytes per pixel. */
 
/* State size */
#define MAX_DAC_STATE 0x101 /* IBMRGB has this many */
 
/* RAMDAC methods */
 
#ifdef INCLUDE_NORMAL_DAC
extern DacMethods __svgalib_normal_dac_methods;
#endif
#ifdef INCLUDE_S3_SDAC_DAC
extern DacMethods __svgalib_S3_SDAC_methods;
#endif
#ifdef INCLUDE_S3_GENDAC_DAC
extern DacMethods __svgalib_S3_GENDAC_methods;
#endif
#ifdef INCLUDE_S3_TRIO64_DAC
extern DacMethods __svgalib_Trio64_methods;
#endif
#ifdef INCLUDE_SIERRA_DAC
extern DacMethods __svgalib_Sierra_32K_methods;
#endif
#ifdef INCLUDE_SC15025_DAC
extern DacMethods __svgalib_SC15025_methods;
#endif
#ifdef INCLUDE_ATT20C490_DAC
extern DacMethods __svgalib_ATT20C490_methods;
#endif
#ifdef INCLUDE_ATT20C498_DAC
extern DacMethods __svgalib_ATT20C498_methods;
#endif
#ifdef INCLUDE_ICW_DAC
extern DacMethods __svgalib_ICW_methods;
#endif
#ifdef INCLUDE_IBMRGB52x_DAC
extern DacMethods __svgalib_IBMRGB52x_methods;
#endif
#ifdef INCLUDE_SC1148X_DAC
extern DacMethods __svgalib_SC1148X_methods;
#endif
#ifdef INCLUDE_ICS_GENDAC_DAC
extern DacMethods __svgalib_ICS_GENDAC_methods;
#endif
 
extern DacMethods *__svgalib_all_dacs[]; /* List of all defined DACs. */
 
/* Functions defined in ramdac.c. */
 
/*
* The following function probes the DACs in daclist, which must be
* terminated by NULL. It returns the detected DAC if succesful, NULL
* otherwise. The detected DAC is also initialized.
*/
 
DacMethods *__svgalib_probeDacs(DacMethods ** daclist);
 
/*
* Internal functions (not meant for export, but no such mechanism in C)
*/
int __svgalib_setDacSpeed(int dacspeed, int defspeed);
 
void __svgalib_Sierra_32K_savestate(unsigned char *regs);
void __svgalib_Sierra_32K_restorestate(const unsigned char *regs);
 
#ifdef __OPTIMIZE__
static __inline__ void _ramdac_dactocomm(void)
{
inb(PEL_IW);
inb(PEL_MSK);
inb(PEL_MSK);
inb(PEL_MSK);
inb(PEL_MSK);
}
 
static __inline__ void _ramdac_dactopel(void)
{
inb(PEL_IW);
}
 
static __inline__ unsigned char _ramdac_setcomm(unsigned char data)
{
_ramdac_dactocomm();
outb(PEL_MSK, data);
_ramdac_dactocomm();
return inb(PEL_MSK);
}
#else
void _ramdac_dactocomm(void);
void _ramdac_dactopel(void);
unsigned char _ramdac_setcomm(unsigned char data);
#endif
 
__END_DECLS
/shark/tags/rel_0_5/drivers/svga/timing.h
0,0 → 1,176
 
#ifndef TIMING_H
#define TIMING_H
 
#include "ll/sys/cdefs.h"
 
__BEGIN_DECLS
 
/*
* Generic mode timing module.
*/
 
/* This is the type of a basic (monitor-oriented) mode timing. */
typedef struct _MMT_S MonitorModeTiming;
struct _MMT_S {
int pixelClock; /* Pixel clock in kHz. */
int HDisplay; /* Horizontal Timing. */
int HSyncStart;
int HSyncEnd;
int HTotal;
int VDisplay; /* Vertical Timing. */
int VSyncStart;
int VSyncEnd;
int VTotal;
int flags;
MonitorModeTiming *next;
};
 
/* This is for the hardware (card)-adjusted mode timing. */
typedef struct {
int pixelClock; /* Pixel clock in kHz. */
int HDisplay; /* Horizontal Timing. */
int HSyncStart;
int HSyncEnd;
int HTotal;
int VDisplay; /* Vertical Timing. */
int VSyncStart;
int VSyncEnd;
int VTotal;
int flags;
/* The following field are optionally filled in according to card */
/* specific parameters. */
int programmedClock; /* Actual clock to be programmed. */
int selectedClockNo; /* Index number of fixed clock used. */
int CrtcHDisplay; /* Actual programmed horizontal CRTC timing. */
int CrtcHSyncStart;
int CrtcHSyncEnd;
int CrtcHTotal;
int CrtcVDisplay; /* Actual programmed vertical CRTC timing. */
int CrtcVSyncStart;
int CrtcVSyncEnd;
int CrtcVTotal;
} ModeTiming;
 
/* Flags in ModeTiming. */
#define PHSYNC 0x1 /* Positive hsync polarity. */
#define NHSYNC 0x2 /* Negative hsync polarity. */
#define PVSYNC 0x4 /* Positive vsync polarity. */
#define NVSYNC 0x8 /* Negative vsync polarity. */
#define INTERLACED 0x10 /* Mode has interlaced timing. */
#define DOUBLESCAN 0x20 /* Mode uses VGA doublescan (see note). */
#define HADJUSTED 0x40 /* Horizontal CRTC timing adjusted. */
#define VADJUSTED 0x80 /* Vertical CRTC timing adjusted. */
#define USEPROGRCLOCK 0x100 /* A programmable clock is used. */
#define TVMODE 0x200
#define TVPAL 0x400
#define TVNTSC 0x800
 
/*
* Note: Double scan implies that each scanline is displayed twice. The
* vertical CRTC timings are programmed to double the effective vertical
* resolution (the CRT still displays 400 scanlines for a 200 line
* resolution).
*/
 
/* Cards specifications. */
typedef struct {
int videoMemory; /* Video memory in kilobytes. */
int maxPixelClock4bpp; /* Maximum pixel clocks in kHz for each depth. */
int maxPixelClock8bpp;
int maxPixelClock16bpp;
int maxPixelClock24bpp;
int maxPixelClock32bpp;
int flags; /* Flags (e.g. programmable clocks). */
int nClocks; /* Number of fixed clocks. */
int *clocks; /* Pointer to array of fixed clock values. */
int maxHorizontalCrtc;
/*
* The following function maps from a pixel clock and depth to
* the raw clock frequency required.
*/
int (*mapClock) (int bpp, int pixelclock);
/*
* The following function maps from a requested clock value
* to the closest clock that the programmable clock device
* can produce.
*/
int (*matchProgrammableClock) (int desiredclock);
/*
* The following function maps from a pixel clock, depth and
* horizontal CRTC timing parameter to the horizontal timing
* that has to be programmed.
*/
int (*mapHorizontalCrtc) (int bpp, int pixelclock, int htiming);
} CardSpecs;
 
/* Card flags. */
/* The card has programmable clocks (matchProgrammableClock is valid). */
#define CLOCK_PROGRAMMABLE 0x1
/* For interlaced modes, the vertical timing must be divided by two. */
#define INTERLACE_DIVIDE_VERT 0x2
/* For modes with vertical timing greater or equal to 1024, vertical */
/* timing must be divided by two. */
#define GREATER_1024_DIVIDE_VERT 0x4
/* The DAC doesn't support 64K colors (5-6-5) at 16bpp, just 5-5-5. */
#define NO_RGB16_565 0x8
/* Card (or driver) can't do interlaced modes */
#define NO_INTERLACE 0x10
/* Don't have banked memory - emulated with mmap from linear memory */
#define EMULATE_BANK 0x20
 
/* Mode info. */
typedef struct {
/* Basic properties. */
short width; /* Width of the screen in pixels. */
short height; /* Height of the screen in pixels. */
char bytesPerPixel; /* Number of bytes per pixel. */
char bitsPerPixel; /* Number of bits per pixel. */
char colorBits; /* Number of significant bits in pixel. */
char __padding1;
/* Truecolor pixel specification. */
char redWeight; /* Number of significant red bits. */
char greenWeight; /* Number of significant green bits. */
char blueWeight; /* Number of significant blue bits. */
char __padding2;
char redOffset; /* Offset in bits of red value into pixel. */
char blueOffset; /* Offset of green value. */
char greenOffset; /* Offset of blue value. */
char __padding3;
unsigned redMask; /* Pixel mask of read value. */
unsigned blueMask; /* Pixel mask of green value. */
unsigned greenMask; /* Pixel mask of blue value. */
/* Structural properties of the mode. */
int lineWidth; /* Offset in bytes between scanlines. */
short realWidth; /* Real on-screen resolution. */
short realHeight; /* Real on-screen resolution. */
int flags;
} ModeInfo;
 
 
/* Prototypes of functions defined in timing.c. */
 
/*
* This function will look up mode timings for a mode matching ModeInfo
* that is within monitor spec and matches the capabilities (clocks etc.)
* of the card.
*/
 
int __svgalib_getmodetiming(
ModeTiming *, /* Resulting mode timing. */
ModeInfo *, /* Structural mode info. */
CardSpecs * /* Card specs (dot clocks etc.). */
);
 
void __svgalib_addusertiming(
MonitorModeTiming *
);
 
/* GTF constants */
#define GTF_lockVF 1 /* Lock to vertical frequency */
#define GTF_lockHF 2 /* Lock to horizontal frequency */
#define GTF_lockPF 3 /* Lock to pixel clock frequency*/
 
__END_DECLS
 
#endif
/shark/tags/rel_0_5/drivers/svga/readme
0,0 → 1,31
Project: S.Ha.R.K.
SVGA support from SVGAlib (1.9.17)
 
Coordinators:
 
Giorgio Buttazzo <giorgio@sssup.it>
Paolo Gai <pj@gandalf.sssup.it>
 
Authors:
 
Giacomo Guidi <giacomo@gandalf.sssup.it>
 
The current graphics drivers supported are:
 
NV3 (GEFORCE TNT TNT2)
SAVAGE (VIRGE SAVAGE)
R128 (RAGE128 RADEON)
 
More drivers will be added in the future.
 
Init function to call:
 
setmode(GRAPHICS_MODE,GRAPHICS_DRIVER);
 
ex: setmode(G640x480x64K,NV3);
(see svgademo example in the demos directory)
 
Note: Mesa and high-level graphics functions use a
linear frame buffer.
 
/shark/tags/rel_0_5/drivers/svga/r128_reg.h
0,0 → 1,1504
/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/r128_reg.h,v 1.6 2000/12/12 17:17:13 dawes Exp $ */
/*
* Copyright 1999, 2000 ATI Technologies Inc., Markham, Ontario,
* Precision Insight, Inc., Cedar Park, Texas, and
* VA Linux Systems Inc., Fremont, California.
*
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation on the rights to use, copy, modify, merge,
* publish, distribute, sublicense, and/or sell copies of the Software,
* and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial
* portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NON-INFRINGEMENT. IN NO EVENT SHALL ATI, PRECISION INSIGHT, VA LINUX
* SYSTEMS AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
 
/*
* Authors:
* Rickard E. Faith <faith@valinux.com>
* Kevin E. Martin <martin@valinux.com>
* Gareth Hughes <gareth@valinux.com>
*
* References:
*
* RAGE 128 VR/ RAGE 128 GL Register Reference Manual (Technical
* Reference Manual P/N RRG-G04100-C Rev. 0.04), ATI Technologies: April
* 1999.
*
* RAGE 128 Software Development Manual (Technical Reference Manual P/N
* SDK-G04000 Rev. 0.01), ATI Technologies: June 1999.
*
*/
 
#ifndef _R128_REG_H_
#define _R128_REG_H_
 
#define R128_TIMEOUT 2000000
 
#define MMIO_IN8(dummy, addr) v_readb(addr)
#define MMIO_IN16(dummy, addr) v_readw(addr)
#define MMIO_IN32(dummy, addr) LE32(v_readl(addr))
 
#define MMIO_OUT8(dummy, addr, val) v_writeb(val, addr)
#define MMIO_OUT16(dummy, addr, val) v_writew(val, addr)
#define MMIO_OUT32(dummy, addr, val) v_writel(LE32(val), addr)
 
/* Memory mapped register access macros */
#define INREG8(addr) MMIO_IN8(R128MMIO, addr)
#define INREG16(addr) MMIO_IN16(R128MMIO, addr)
#define INREG(addr) MMIO_IN32(R128MMIO, addr)
#define OUTREG8(addr, val) MMIO_OUT8(R128MMIO, addr, val)
#define OUTREG16(addr, val) MMIO_OUT16(R128MMIO, addr, val)
#define OUTREG(addr, val) MMIO_OUT32(R128MMIO, addr, val)
 
#if 0
#define R128_BIOS8(v) (VBIOS[v])
#define R128_BIOS16(v) (VBIOS[v] | \
(VBIOS[(v) + 1] << 8))
#define R128_BIOS32(v) (VBIOS[v] | \
(VBIOS[(v) + 1] << 8) | \
(VBIOS[(v) + 2] << 16) | \
(VBIOS[(v) + 3] << 24))
#endif
#define OUTREGP(addr, val, mask) \
do { \
uint32_t tmp = INREG(addr); \
tmp &= (mask); \
tmp |= (val); \
OUTREG(addr, tmp); \
} while (0)
 
#define INPLL(addr) R128INPLL(addr)
 
#define OUTPLL(addr, val) \
do { \
OUTREG8(R128_CLOCK_CNTL_INDEX, ((addr) & 0x1f) | R128_PLL_WR_EN); \
OUTREG(R128_CLOCK_CNTL_DATA, val); \
} while (0)
 
#define OUTPLLP(addr, val, mask) \
do { \
uint32_t tmp = INPLL(addr); \
tmp &= (mask); \
tmp |= (val); \
OUTPLL(addr, tmp); \
} while (0)
 
#define OUTPAL_START(idx) \
do { \
OUTREG8(R128_PALETTE_INDEX, (idx)); \
} while (0)
 
#define OUTPAL_NEXT(r, g, b) \
do { \
OUTREG(R128_PALETTE_DATA, ((r) << 16) | ((g) << 8) | (b)); \
} while (0)
 
#define OUTPAL_NEXT_uint32_t(v) \
do { \
OUTREG(R128_PALETTE_DATA, (v & 0x00ffffff)); \
} while (0)
 
#define OUTPAL(idx, r, g, b) \
do { \
OUTPAL_START((idx)); \
OUTPAL_NEXT((r), (g), (b)); \
} while (0)
 
#define INPAL_START(idx) \
do { \
OUTREG(R128_PALETTE_INDEX, (idx) << 16); \
} while (0)
 
#define INPAL_NEXT() INREG(R128_PALETTE_DATA)
 
#define PAL_SELECT(idx) \
do { \
if (idx) { \
OUTREG(R128_DAC_CNTL, INREG(R128_DAC_CNTL) | \
R128_DAC_PALETTE_ACC_CTL); \
} else { \
OUTREG(R128_DAC_CNTL, INREG(R128_DAC_CNTL) & \
~R128_DAC_PALETTE_ACC_CTL); \
} \
} while (0)
 
#define R128_ADAPTER_ID 0x0f2c /* PCI */
#define R128_AGP_APER_OFFSET 0x0178
#define R128_AGP_BASE 0x0170
#define R128_AGP_CNTL 0x0174
# define R128_AGP_APER_SIZE_256MB (0x00 << 0)
# define R128_AGP_APER_SIZE_128MB (0x20 << 0)
# define R128_AGP_APER_SIZE_64MB (0x30 << 0)
# define R128_AGP_APER_SIZE_32MB (0x38 << 0)
# define R128_AGP_APER_SIZE_16MB (0x3c << 0)
# define R128_AGP_APER_SIZE_8MB (0x3e << 0)
# define R128_AGP_APER_SIZE_4MB (0x3f << 0)
# define R128_AGP_APER_SIZE_MASK (0x3f << 0)
#define R128_AGP_CNTL_B 0x0b44
#define R128_AGP_COMMAND 0x0f58 /* PCI */
#define R128_AGP_PLL_CNTL 0x0010 /* PLL */
#define R128_AGP_STATUS 0x0f54 /* PCI */
# define R128_AGP_1X_MODE 0x01
# define R128_AGP_2X_MODE 0x02
# define R128_AGP_4X_MODE 0x04
# define R128_AGP_MODE_MASK 0x07
#define R128_AMCGPIO_A_REG 0x01a0
#define R128_AMCGPIO_EN_REG 0x01a8
#define R128_AMCGPIO_MASK 0x0194
#define R128_AMCGPIO_Y_REG 0x01a4
#define R128_ATTRDR 0x03c1 /* VGA */
#define R128_ATTRDW 0x03c0 /* VGA */
#define R128_ATTRX 0x03c0 /* VGA */
#define R128_AUX_SC_CNTL 0x1660
# define R128_AUX1_SC_EN (1 << 0)
# define R128_AUX1_SC_MODE_OR (0 << 1)
# define R128_AUX1_SC_MODE_NAND (1 << 1)
# define R128_AUX2_SC_EN (1 << 2)
# define R128_AUX2_SC_MODE_OR (0 << 3)
# define R128_AUX2_SC_MODE_NAND (1 << 3)
# define R128_AUX3_SC_EN (1 << 4)
# define R128_AUX3_SC_MODE_OR (0 << 5)
# define R128_AUX3_SC_MODE_NAND (1 << 5)
#define R128_AUX1_SC_BOTTOM 0x1670
#define R128_AUX1_SC_LEFT 0x1664
#define R128_AUX1_SC_RIGHT 0x1668
#define R128_AUX1_SC_TOP 0x166c
#define R128_AUX2_SC_BOTTOM 0x1680
#define R128_AUX2_SC_LEFT 0x1674
#define R128_AUX2_SC_RIGHT 0x1678
#define R128_AUX2_SC_TOP 0x167c
#define R128_AUX3_SC_BOTTOM 0x1690
#define R128_AUX3_SC_LEFT 0x1684
#define R128_AUX3_SC_RIGHT 0x1688
#define R128_AUX3_SC_TOP 0x168c
#define R128_AUX_WINDOW_HORZ_CNTL 0x02d8
#define R128_AUX_WINDOW_VERT_CNTL 0x02dc
 
#define R128_BASE_CODE 0x0f0b
#define R128_BIOS_0_SCRATCH 0x0010
#define R128_BIOS_1_SCRATCH 0x0014
#define R128_BIOS_2_SCRATCH 0x0018
#define R128_BIOS_3_SCRATCH 0x001c
#define R128_BIOS_ROM 0x0f30 /* PCI */
#define R128_BIST 0x0f0f /* PCI */
#define R128_BRUSH_DATA0 0x1480
#define R128_BRUSH_DATA1 0x1484
#define R128_BRUSH_DATA10 0x14a8
#define R128_BRUSH_DATA11 0x14ac
#define R128_BRUSH_DATA12 0x14b0
#define R128_BRUSH_DATA13 0x14b4
#define R128_BRUSH_DATA14 0x14b8
#define R128_BRUSH_DATA15 0x14bc
#define R128_BRUSH_DATA16 0x14c0
#define R128_BRUSH_DATA17 0x14c4
#define R128_BRUSH_DATA18 0x14c8
#define R128_BRUSH_DATA19 0x14cc
#define R128_BRUSH_DATA2 0x1488
#define R128_BRUSH_DATA20 0x14d0
#define R128_BRUSH_DATA21 0x14d4
#define R128_BRUSH_DATA22 0x14d8
#define R128_BRUSH_DATA23 0x14dc
#define R128_BRUSH_DATA24 0x14e0
#define R128_BRUSH_DATA25 0x14e4
#define R128_BRUSH_DATA26 0x14e8
#define R128_BRUSH_DATA27 0x14ec
#define R128_BRUSH_DATA28 0x14f0
#define R128_BRUSH_DATA29 0x14f4
#define R128_BRUSH_DATA3 0x148c
#define R128_BRUSH_DATA30 0x14f8
#define R128_BRUSH_DATA31 0x14fc
#define R128_BRUSH_DATA32 0x1500
#define R128_BRUSH_DATA33 0x1504
#define R128_BRUSH_DATA34 0x1508
#define R128_BRUSH_DATA35 0x150c
#define R128_BRUSH_DATA36 0x1510
#define R128_BRUSH_DATA37 0x1514
#define R128_BRUSH_DATA38 0x1518
#define R128_BRUSH_DATA39 0x151c
#define R128_BRUSH_DATA4 0x1490
#define R128_BRUSH_DATA40 0x1520
#define R128_BRUSH_DATA41 0x1524
#define R128_BRUSH_DATA42 0x1528
#define R128_BRUSH_DATA43 0x152c
#define R128_BRUSH_DATA44 0x1530
#define R128_BRUSH_DATA45 0x1534
#define R128_BRUSH_DATA46 0x1538
#define R128_BRUSH_DATA47 0x153c
#define R128_BRUSH_DATA48 0x1540
#define R128_BRUSH_DATA49 0x1544
#define R128_BRUSH_DATA5 0x1494
#define R128_BRUSH_DATA50 0x1548
#define R128_BRUSH_DATA51 0x154c
#define R128_BRUSH_DATA52 0x1550
#define R128_BRUSH_DATA53 0x1554
#define R128_BRUSH_DATA54 0x1558
#define R128_BRUSH_DATA55 0x155c
#define R128_BRUSH_DATA56 0x1560
#define R128_BRUSH_DATA57 0x1564
#define R128_BRUSH_DATA58 0x1568
#define R128_BRUSH_DATA59 0x156c
#define R128_BRUSH_DATA6 0x1498
#define R128_BRUSH_DATA60 0x1570
#define R128_BRUSH_DATA61 0x1574
#define R128_BRUSH_DATA62 0x1578
#define R128_BRUSH_DATA63 0x157c
#define R128_BRUSH_DATA7 0x149c
#define R128_BRUSH_DATA8 0x14a0
#define R128_BRUSH_DATA9 0x14a4
#define R128_BRUSH_SCALE 0x1470
#define R128_BRUSH_Y_X 0x1474
#define R128_BUS_CNTL 0x0030
# define R128_BUS_MASTER_DIS (1 << 6)
# define R128_BUS_RD_DISCARD_EN (1 << 24)
# define R128_BUS_RD_ABORT_EN (1 << 25)
# define R128_BUS_MSTR_DISCONNECT_EN (1 << 28)
# define R128_BUS_WRT_BURST (1 << 29)
# define R128_BUS_READ_BURST (1 << 30)
#define R128_BUS_CNTL1 0x0034
# define R128_BUS_WAIT_ON_LOCK_EN (1 << 4)
 
#define R128_CACHE_CNTL 0x1724
#define R128_CACHE_LINE 0x0f0c /* PCI */
#define R128_CAP0_TRIG_CNTL 0x0950 /* ? */
#define R128_CAP1_TRIG_CNTL 0x09c0 /* ? */
#define R128_CAPABILITIES_ID 0x0f50 /* PCI */
#define R128_CAPABILITIES_PTR 0x0f34 /* PCI */
#define R128_CLK_PIN_CNTL 0x0001 /* PLL */
#define R128_CLOCK_CNTL_DATA 0x000c
#define R128_CLOCK_CNTL_INDEX 0x0008
# define R128_PLL_WR_EN (1 << 7)
# define R128_PLL_DIV_SEL (3 << 8)
#define R128_CLR_CMP_CLR_3D 0x1a24
#define R128_CLR_CMP_CLR_DST 0x15c8
#define R128_CLR_CMP_CLR_SRC 0x15c4
#define R128_CLR_CMP_CNTL 0x15c0
# define R128_SRC_CMP_EQ_COLOR (4 << 0)
# define R128_SRC_CMP_NEQ_COLOR (5 << 0)
# define R128_CLR_CMP_SRC_SOURCE (1 << 24)
#define R128_CLR_CMP_MASK 0x15cc
# define R128_CLR_CMP_MSK 0xffffffff
#define R128_CLR_CMP_MASK_3D 0x1A28
#define R128_COMMAND 0x0f04 /* PCI */
#define R128_COMPOSITE_SHADOW_ID 0x1a0c
#define R128_CONFIG_APER_0_BASE 0x0100
#define R128_CONFIG_APER_1_BASE 0x0104
#define R128_CONFIG_APER_SIZE 0x0108
#define R128_CONFIG_BONDS 0x00e8
#define R128_CONFIG_CNTL 0x00e0
# define APER_0_BIG_ENDIAN_16BPP_SWAP (1 << 0)
# define APER_0_BIG_ENDIAN_32BPP_SWAP (2 << 0)
# define R128_CFG_VGA_RAM_EN (1 << 8)
#define R128_CONFIG_MEMSIZE 0x00f8
#define R128_CONFIG_MEMSIZE_EMBEDDED 0x0114
#define R128_CONFIG_REG_1_BASE 0x010c
#define R128_CONFIG_REG_APER_SIZE 0x0110
#define R128_CONFIG_XSTRAP 0x00e4
#define R128_CONSTANT_COLOR_C 0x1d34
# define R128_CONSTANT_COLOR_MASK 0x00ffffff
# define R128_CONSTANT_COLOR_ONE 0x00ffffff
# define R128_CONSTANT_COLOR_ZERO 0x00000000
#define R128_CRC_CMDFIFO_ADDR 0x0740
#define R128_CRC_CMDFIFO_DOUT 0x0744
#define R128_CRTC_CRNT_FRAME 0x0214
#define R128_CRTC_DEBUG 0x021c
#define R128_CRTC_EXT_CNTL 0x0054
# define R128_CRTC_VGA_XOVERSCAN (1 << 0)
# define R128_VGA_ATI_LINEAR (1 << 3)
# define R128_XCRT_CNT_EN (1 << 6)
# define R128_CRTC_HSYNC_DIS (1 << 8)
# define R128_CRTC_VSYNC_DIS (1 << 9)
# define R128_CRTC_DISPLAY_DIS (1 << 10)
# define R128_CRTC_CRT_ON (1 << 15)
# define R128_VGA_MEM_PS_EN (1 << 19)
#define R128_CRTC_EXT_CNTL_DPMS_BYTE 0x0055
# define R128_CRTC_HSYNC_DIS_BYTE (1 << 0)
# define R128_CRTC_VSYNC_DIS_BYTE (1 << 1)
# define R128_CRTC_DISPLAY_DIS_BYTE (1 << 2)
#define R128_CRTC_GEN_CNTL 0x0050
# define R128_CRTC_DBL_SCAN_EN (1 << 0)
# define R128_CRTC_INTERLACE_EN (1 << 1)
# define R128_CRTC_CSYNC_EN (1 << 4)
# define R128_CRTC_CUR_EN (1 << 16)
# define R128_CRTC_CUR_MODE_MASK (7 << 17)
# define R128_CRTC_ICON_EN (1 << 20)
# define R128_CRTC_EXT_DISP_EN (1 << 24)
# define R128_CRTC_EN (1 << 25)
# define R128_CRTC_DISP_REQ_EN_B (1 << 26)
#define R128_CRTC_GUI_TRIG_VLINE 0x0218
#define R128_CRTC_H_SYNC_STRT_WID 0x0204
# define R128_CRTC_H_SYNC_STRT_PIX (0x07 << 0)
# define R128_CRTC_H_SYNC_STRT_CHAR (0x1ff << 3)
# define R128_CRTC_H_SYNC_STRT_CHAR_SHIFT 3
# define R128_CRTC_H_SYNC_WID (0x3f << 16)
# define R128_CRTC_H_SYNC_WID_SHIFT 16
# define R128_CRTC_H_SYNC_POL (1 << 23)
#define R128_CRTC_H_TOTAL_DISP 0x0200
# define R128_CRTC_H_TOTAL (0x01ff << 0)
# define R128_CRTC_H_TOTAL_SHIFT 0
# define R128_CRTC_H_DISP (0x00ff << 16)
# define R128_CRTC_H_DISP_SHIFT 16
#define R128_CRTC_OFFSET 0x0224
#define R128_CRTC_OFFSET_CNTL 0x0228
#define R128_CRTC_PITCH 0x022c
#define R128_CRTC_STATUS 0x005c
# define R128_CRTC_VBLANK_SAVE (1 << 1)
#define R128_CRTC_V_SYNC_STRT_WID 0x020c
# define R128_CRTC_V_SYNC_STRT (0x7ff << 0)
# define R128_CRTC_V_SYNC_STRT_SHIFT 0
# define R128_CRTC_V_SYNC_WID (0x1f << 16)
# define R128_CRTC_V_SYNC_WID_SHIFT 16
# define R128_CRTC_V_SYNC_POL (1 << 23)
#define R128_CRTC_V_TOTAL_DISP 0x0208
# define R128_CRTC_V_TOTAL (0x07ff << 0)
# define R128_CRTC_V_TOTAL_SHIFT 0
# define R128_CRTC_V_DISP (0x07ff << 16)
# define R128_CRTC_V_DISP_SHIFT 16
#define R128_CRTC_VLINE_CRNT_VLINE 0x0210
# define R128_CRTC_CRNT_VLINE_MASK (0x7ff << 16)
#define R128_CRTC2_CRNT_FRAME 0x0314
#define R128_CRTC2_DEBUG 0x031c
#define R128_CRTC2_GEN_CNTL 0x03f8
#define R128_CRTC2_GUI_TRIG_VLINE 0x0318
#define R128_CRTC2_H_SYNC_STRT_WID 0x0304
#define R128_CRTC2_H_TOTAL_DISP 0x0300
#define R128_CRTC2_OFFSET 0x0324
#define R128_CRTC2_OFFSET_CNTL 0x0328
#define R128_CRTC2_PITCH 0x032c
#define R128_CRTC2_STATUS 0x03fc
#define R128_CRTC2_V_SYNC_STRT_WID 0x030c
#define R128_CRTC2_V_TOTAL_DISP 0x0308
#define R128_CRTC2_VLINE_CRNT_VLINE 0x0310
#define R128_CRTC8_DATA 0x03d5 /* VGA, 0x3b5 */
#define R128_CRTC8_IDX 0x03d4 /* VGA, 0x3b4 */
#define R128_CUR_CLR0 0x026c
#define R128_CUR_CLR1 0x0270
#define R128_CUR_HORZ_VERT_OFF 0x0268
#define R128_CUR_HORZ_VERT_POSN 0x0264
#define R128_CUR_OFFSET 0x0260
# define R128_CUR_LOCK (1 << 31)
 
#define R128_DAC_CNTL 0x0058
# define R128_DAC_RANGE_CNTL (3 << 0)
# define R128_DAC_BLANKING (1 << 2)
# define R128_DAC_CRT_SEL_CRTC2 (1 << 4)
# define R128_DAC_PALETTE_ACC_CTL (1 << 5)
# define R128_DAC_8BIT_EN (1 << 8)
# define R128_DAC_VGA_ADR_EN (1 << 13)
# define R128_DAC_MASK_ALL (0xff << 24)
#define R128_DAC_CRC_SIG 0x02cc
#define R128_DAC_DATA 0x03c9 /* VGA */
#define R128_DAC_MASK 0x03c6 /* VGA */
#define R128_DAC_R_INDEX 0x03c7 /* VGA */
#define R128_DAC_W_INDEX 0x03c8 /* VGA */
#define R128_DDA_CONFIG 0x02e0
#define R128_DDA_ON_OFF 0x02e4
#define R128_DEFAULT_OFFSET 0x16e0
#define R128_DEFAULT_PITCH 0x16e4
#define R128_DEFAULT_SC_BOTTOM_RIGHT 0x16e8
# define R128_DEFAULT_SC_RIGHT_MAX (0x1fff << 0)
# define R128_DEFAULT_SC_BOTTOM_MAX (0x1fff << 16)
#define R128_DESTINATION_3D_CLR_CMP_VAL 0x1820
#define R128_DESTINATION_3D_CLR_CMP_MSK 0x1824
#define R128_DEVICE_ID 0x0f02 /* PCI */
#define R128_DP_BRUSH_BKGD_CLR 0x1478
#define R128_DP_BRUSH_FRGD_CLR 0x147c
#define R128_DP_CNTL 0x16c0
# define R128_DST_X_LEFT_TO_RIGHT (1 << 0)
# define R128_DST_Y_TOP_TO_BOTTOM (1 << 1)
#define R128_DP_CNTL_XDIR_YDIR_YMAJOR 0x16d0
# define R128_DST_Y_MAJOR (1 << 2)
# define R128_DST_Y_DIR_TOP_TO_BOTTOM (1 << 15)
# define R128_DST_X_DIR_LEFT_TO_RIGHT (1 << 31)
#define R128_DP_DATATYPE 0x16c4
# define R128_HOST_BIG_ENDIAN_EN (1 << 29)
#define R128_DP_GUI_MASTER_CNTL 0x146c
# define R128_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0)
# define R128_GMC_DST_PITCH_OFFSET_CNTL (1 << 1)
# define R128_GMC_SRC_CLIPPING (1 << 2)
# define R128_GMC_DST_CLIPPING (1 << 3)
# define R128_GMC_BRUSH_DATATYPE_MASK (0x0f << 4)
# define R128_GMC_BRUSH_8X8_MONO_FG_BG (0 << 4)
# define R128_GMC_BRUSH_8X8_MONO_FG_LA (1 << 4)
# define R128_GMC_BRUSH_1X8_MONO_FG_BG (4 << 4)
# define R128_GMC_BRUSH_1X8_MONO_FG_LA (5 << 4)
# define R128_GMC_BRUSH_32x1_MONO_FG_BG (6 << 4)
# define R128_GMC_BRUSH_32x1_MONO_FG_LA (7 << 4)
# define R128_GMC_BRUSH_32x32_MONO_FG_BG (8 << 4)
# define R128_GMC_BRUSH_32x32_MONO_FG_LA (9 << 4)
# define R128_GMC_BRUSH_8x8_COLOR (10 << 4)
# define R128_GMC_BRUSH_1X8_COLOR (12 << 4)
# define R128_GMC_BRUSH_SOLID_COLOR (13 << 4)
# define R128_GMC_BRUSH_NONE (15 << 4)
# define R128_GMC_DST_8BPP_CI (2 << 8)
# define R128_GMC_DST_15BPP (3 << 8)
# define R128_GMC_DST_16BPP (4 << 8)
# define R128_GMC_DST_24BPP (5 << 8)
# define R128_GMC_DST_32BPP (6 << 8)
# define R128_GMC_DST_8BPP_RGB (7 << 8)
# define R128_GMC_DST_Y8 (8 << 8)
# define R128_GMC_DST_RGB8 (9 << 8)
# define R128_GMC_DST_VYUY (11 << 8)
# define R128_GMC_DST_YVYU (12 << 8)
# define R128_GMC_DST_AYUV444 (14 << 8)
# define R128_GMC_DST_ARGB4444 (15 << 8)
# define R128_GMC_DST_DATATYPE_MASK (0x0f << 8)
# define R128_GMC_DST_DATATYPE_SHIFT 8
# define R128_GMC_SRC_DATATYPE_MASK (3 << 12)
# define R128_GMC_SRC_DATATYPE_MONO_FG_BG (0 << 12)
# define R128_GMC_SRC_DATATYPE_MONO_FG_LA (1 << 12)
# define R128_GMC_SRC_DATATYPE_COLOR (3 << 12)
# define R128_GMC_BYTE_PIX_ORDER (1 << 14)
# define R128_GMC_BYTE_MSB_TO_LSB (0 << 14)
# define R128_GMC_BYTE_LSB_TO_MSB (1 << 14)
# define R128_GMC_CONVERSION_TEMP (1 << 15)
# define R128_GMC_CONVERSION_TEMP_6500 (0 << 15)
# define R128_GMC_CONVERSION_TEMP_9300 (1 << 15)
# define R128_GMC_ROP3_MASK (0xff << 16)
# define R128_DP_SRC_SOURCE_MASK (7 << 24)
# define R128_DP_SRC_SOURCE_MEMORY (2 << 24)
# define R128_DP_SRC_SOURCE_HOST_DATA (3 << 24)
# define R128_GMC_3D_FCN_EN (1 << 27)
# define R128_GMC_CLR_CMP_CNTL_DIS (1 << 28)
# define R128_GMC_AUX_CLIP_DIS (1 << 29)
# define R128_GMC_WR_MSK_DIS (1 << 30)
# define R128_GMC_LD_BRUSH_Y_X (1 << 31)
# define R128_ROP3_ZERO 0x00000000
# define R128_ROP3_DSa 0x00880000
# define R128_ROP3_SDna 0x00440000
# define R128_ROP3_S 0x00cc0000
# define R128_ROP3_DSna 0x00220000
# define R128_ROP3_D 0x00aa0000
# define R128_ROP3_DSx 0x00660000
# define R128_ROP3_DSo 0x00ee0000
# define R128_ROP3_DSon 0x00110000
# define R128_ROP3_DSxn 0x00990000
# define R128_ROP3_Dn 0x00550000
# define R128_ROP3_SDno 0x00dd0000
# define R128_ROP3_Sn 0x00330000
# define R128_ROP3_DSno 0x00bb0000
# define R128_ROP3_DSan 0x00770000
# define R128_ROP3_ONE 0x00ff0000
# define R128_ROP3_DPa 0x00a00000
# define R128_ROP3_PDna 0x00500000
# define R128_ROP3_P 0x00f00000
# define R128_ROP3_DPna 0x000a0000
# define R128_ROP3_D 0x00aa0000
# define R128_ROP3_DPx 0x005a0000
# define R128_ROP3_DPo 0x00fa0000
# define R128_ROP3_DPon 0x00050000
# define R128_ROP3_PDxn 0x00a50000
# define R128_ROP3_PDno 0x00f50000
# define R128_ROP3_Pn 0x000f0000
# define R128_ROP3_DPno 0x00af0000
# define R128_ROP3_DPan 0x005f0000
 
 
#define R128_DP_GUI_MASTER_CNTL_C 0x1c84
#define R128_DP_MIX 0x16c8
#define R128_DP_SRC_BKGD_CLR 0x15dc
#define R128_DP_SRC_FRGD_CLR 0x15d8
#define R128_DP_WRITE_MASK 0x16cc
#define R128_DST_BRES_DEC 0x1630
#define R128_DST_BRES_ERR 0x1628
#define R128_DST_BRES_INC 0x162c
#define R128_DST_BRES_LNTH 0x1634
#define R128_DST_BRES_LNTH_SUB 0x1638
#define R128_DST_HEIGHT 0x1410
#define R128_DST_HEIGHT_WIDTH 0x143c
#define R128_DST_HEIGHT_WIDTH_8 0x158c
#define R128_DST_HEIGHT_WIDTH_BW 0x15b4
#define R128_DST_HEIGHT_Y 0x15a0
#define R128_DST_OFFSET 0x1404
#define R128_DST_PITCH 0x1408
#define R128_DST_PITCH_OFFSET 0x142c
#define R128_DST_PITCH_OFFSET_C 0x1c80
# define R128_PITCH_SHIFT 21
# define R128_DST_TILE (1 << 31)
#define R128_DST_WIDTH 0x140c
#define R128_DST_WIDTH_HEIGHT 0x1598
#define R128_DST_WIDTH_X 0x1588
#define R128_DST_WIDTH_X_INCY 0x159c
#define R128_DST_X 0x141c
#define R128_DST_X_SUB 0x15a4
#define R128_DST_X_Y 0x1594
#define R128_DST_Y 0x1420
#define R128_DST_Y_SUB 0x15a8
#define R128_DST_Y_X 0x1438
 
#define R128_EXT_MEM_CNTL 0x0144
 
#define R128_FCP_CNTL 0x0012 /* PLL */
#define R128_FLUSH_1 0x1704
#define R128_FLUSH_2 0x1708
#define R128_FLUSH_3 0x170c
#define R128_FLUSH_4 0x1710
#define R128_FLUSH_5 0x1714
#define R128_FLUSH_6 0x1718
#define R128_FLUSH_7 0x171c
#define R128_FOG_3D_TABLE_START 0x1810
#define R128_FOG_3D_TABLE_END 0x1814
#define R128_FOG_3D_TABLE_DENSITY 0x181c
#define R128_FOG_TABLE_INDEX 0x1a14
#define R128_FOG_TABLE_DATA 0x1a18
#define R128_FP_CRTC_H_TOTAL_DISP 0x0250
#define R128_FP_CRTC_V_TOTAL_DISP 0x0254
#define R128_FP_GEN_CNTL 0x0284
# define R128_FP_FPON (1 << 0)
# define R128_FP_TDMS_EN (1 << 2)
# define R128_FP_DETECT_SENSE (1 << 8)
# define R128_FP_SEL_CRTC2 (1 << 13)
# define R128_FP_CRTC_DONT_SHADOW_VPAR (1 << 16)
# define R128_FP_CRTC_USE_SHADOW_VEND (1 << 18)
# define R128_FP_CRTC_HORZ_DIV2_EN (1 << 20)
# define R128_FP_CRTC_HOR_CRT_DIV2_DIS (1 << 21)
# define R128_FP_USE_SHADOW_EN (1 << 24)
#define R128_FP_H_SYNC_STRT_WID 0x02c4
#define R128_FP_HORZ_STRETCH 0x028c
# define R128_HORZ_STRETCH_RATIO_MASK 0xffff
# define R128_HORZ_STRETCH_RATIO_SHIFT 0
# define R128_HORZ_STRETCH_RATIO_MAX 4096
# define R128_HORZ_PANEL_SIZE (0xff << 16)
# define R128_HORZ_PANEL_SHIFT 16
# define R128_HORZ_STRETCH_PIXREP (0 << 25)
# define R128_HORZ_STRETCH_BLEND (1 << 25)
# define R128_HORZ_STRETCH_ENABLE (1 << 26)
# define R128_HORZ_FP_LOOP_STRETCH (0x7 << 27)
# define R128_HORZ_STRETCH_RESERVED (1 << 30)
# define R128_HORZ_AUTO_RATIO_FIX_EN (1 << 31)
 
#define R128_FP_PANEL_CNTL 0x0288
# define R128_FP_DIGON (1 << 0)
# define R128_FP_BLON (1 << 1)
#define R128_FP_V_SYNC_STRT_WID 0x02c8
#define R128_FP_VERT_STRETCH 0x0290
# define R128_VERT_PANEL_SIZE (0x7ff << 0)
# define R128_VERT_PANEL_SHIFT 0
# define R128_VERT_STRETCH_RATIO_MASK 0x3ff
# define R128_VERT_STRETCH_RATIO_SHIFT 11
# define R128_VERT_STRETCH_RATIO_MAX 1024
# define R128_VERT_STRETCH_ENABLE (1 << 24)
# define R128_VERT_STRETCH_LINEREP (0 << 25)
# define R128_VERT_STRETCH_BLEND (1 << 25)
# define R128_VERT_AUTO_RATIO_EN (1 << 26)
# define R128_VERT_STRETCH_RESERVED 0xf8e00000
 
#define R128_GEN_INT_CNTL 0x0040
#define R128_GEN_INT_STATUS 0x0044
# define R128_VSYNC_INT_AK (1 << 2)
# define R128_VSYNC_INT (1 << 2)
#define R128_GEN_RESET_CNTL 0x00f0
# define R128_SOFT_RESET_GUI (1 << 0)
# define R128_SOFT_RESET_VCLK (1 << 8)
# define R128_SOFT_RESET_PCLK (1 << 9)
# define R128_SOFT_RESET_DISPENG_XCLK (1 << 11)
# define R128_SOFT_RESET_MEMCTLR_XCLK (1 << 12)
#define R128_GENENB 0x03c3 /* VGA */
#define R128_GENFC_RD 0x03ca /* VGA */
#define R128_GENFC_WT 0x03da /* VGA, 0x03ba */
#define R128_GENMO_RD 0x03cc /* VGA */
#define R128_GENMO_WT 0x03c2 /* VGA */
#define R128_GENS0 0x03c2 /* VGA */
#define R128_GENS1 0x03da /* VGA, 0x03ba */
#define R128_GPIO_MONID 0x0068
# define R128_GPIO_MONID_A_0 (1 << 0)
# define R128_GPIO_MONID_A_1 (1 << 1)
# define R128_GPIO_MONID_A_2 (1 << 2)
# define R128_GPIO_MONID_A_3 (1 << 3)
# define R128_GPIO_MONID_Y_0 (1 << 8)
# define R128_GPIO_MONID_Y_1 (1 << 9)
# define R128_GPIO_MONID_Y_2 (1 << 10)
# define R128_GPIO_MONID_Y_3 (1 << 11)
# define R128_GPIO_MONID_EN_0 (1 << 16)
# define R128_GPIO_MONID_EN_1 (1 << 17)
# define R128_GPIO_MONID_EN_2 (1 << 18)
# define R128_GPIO_MONID_EN_3 (1 << 19)
# define R128_GPIO_MONID_MASK_0 (1 << 24)
# define R128_GPIO_MONID_MASK_1 (1 << 25)
# define R128_GPIO_MONID_MASK_2 (1 << 26)
# define R128_GPIO_MONID_MASK_3 (1 << 27)
#define R128_GPIO_MONIDB 0x006c
#define R128_GRPH8_DATA 0x03cf /* VGA */
#define R128_GRPH8_IDX 0x03ce /* VGA */
#define R128_GUI_DEBUG0 0x16a0
#define R128_GUI_DEBUG1 0x16a4
#define R128_GUI_DEBUG2 0x16a8
#define R128_GUI_DEBUG3 0x16ac
#define R128_GUI_DEBUG4 0x16b0
#define R128_GUI_DEBUG5 0x16b4
#define R128_GUI_DEBUG6 0x16b8
#define R128_GUI_PROBE 0x16bc
#define R128_GUI_SCRATCH_REG0 0x15e0
#define R128_GUI_SCRATCH_REG1 0x15e4
#define R128_GUI_SCRATCH_REG2 0x15e8
#define R128_GUI_SCRATCH_REG3 0x15ec
#define R128_GUI_SCRATCH_REG4 0x15f0
#define R128_GUI_SCRATCH_REG5 0x15f4
#define R128_GUI_STAT 0x1740
# define R128_GUI_FIFOCNT_MASK 0x0fff
# define R128_GUI_ACTIVE (1 << 31)
 
#define R128_HEADER 0x0f0e /* PCI */
#define R128_HOST_DATA0 0x17c0
#define R128_HOST_DATA1 0x17c4
#define R128_HOST_DATA2 0x17c8
#define R128_HOST_DATA3 0x17cc
#define R128_HOST_DATA4 0x17d0
#define R128_HOST_DATA5 0x17d4
#define R128_HOST_DATA6 0x17d8
#define R128_HOST_DATA7 0x17dc
#define R128_HOST_DATA_LAST 0x17e0
#define R128_HOST_PATH_CNTL 0x0130
#define R128_HTOTAL_CNTL 0x0009 /* PLL */
#define R128_HW_DEBUG 0x0128
#define R128_HW_DEBUG2 0x011c
 
#define R128_I2C_CNTL_1 0x0094 /* ? */
#define R128_INTERRUPT_LINE 0x0f3c /* PCI */
#define R128_INTERRUPT_PIN 0x0f3d /* PCI */
#define R128_IO_BASE 0x0f14 /* PCI */
 
#define R128_LATENCY 0x0f0d /* PCI */
#define R128_LEAD_BRES_DEC 0x1608
#define R128_LEAD_BRES_ERR 0x1600
#define R128_LEAD_BRES_INC 0x1604
#define R128_LEAD_BRES_LNTH 0x161c
#define R128_LEAD_BRES_LNTH_SUB 0x1624
#define R128_LVDS_GEN_CNTL 0x02d0
# define R128_LVDS_ON (1 << 0)
# define R128_LVDS_BLON (1 << 19)
# define R128_LVDS_SEL_CRTC2 (1 << 23)
# define R128_HSYNC_DELAY_SHIFT 28
# define R128_HSYNC_DELAY_MASK (0xf << 28)
 
#define R128_MAX_LATENCY 0x0f3f /* PCI */
#define R128_MCLK_CNTL 0x000f /* PLL */
# define R128_FORCE_GCP (1 << 16)
# define R128_FORCE_PIPE3D_CP (1 << 17)
# define R128_FORCE_RCP (1 << 18)
#define R128_MDGPIO_A_REG 0x01ac
#define R128_MDGPIO_EN_REG 0x01b0
#define R128_MDGPIO_MASK 0x0198
#define R128_MDGPIO_Y_REG 0x01b4
#define R128_MEM_ADDR_CONFIG 0x0148
#define R128_MEM_BASE 0x0f10 /* PCI */
#define R128_MEM_CNTL 0x0140
#define R128_MEM_INIT_LAT_TIMER 0x0154
#define R128_MEM_INTF_CNTL 0x014c
#define R128_MEM_SDRAM_MODE_REG 0x0158
#define R128_MEM_STR_CNTL 0x0150
#define R128_MEM_VGA_RP_SEL 0x003c
#define R128_MEM_VGA_WP_SEL 0x0038
#define R128_MIN_GRANT 0x0f3e /* PCI */
#define R128_MM_DATA 0x0004
#define R128_MM_INDEX 0x0000
#define R128_MPLL_CNTL 0x000e /* PLL */
#define R128_MPP_TB_CONFIG 0x01c0 /* ? */
#define R128_MPP_GP_CONFIG 0x01c8 /* ? */
 
#define R128_N_VIF_COUNT 0x0248
 
#define R128_OVR_CLR 0x0230
#define R128_OVR_WID_LEFT_RIGHT 0x0234
#define R128_OVR_WID_TOP_BOTTOM 0x0238
 
/* first overlay unit (there is only one) */
 
#define R128_OV0_Y_X_START 0x0400
#define R128_OV0_Y_X_END 0x0404
#define R128_OV0_EXCLUSIVE_HORZ 0x0408
# define R128_EXCL_HORZ_START_MASK 0x000000ff
# define R128_EXCL_HORZ_END_MASK 0x0000ff00
# define R128_EXCL_HORZ_BACK_PORCH_MASK 0x00ff0000
# define R128_EXCL_HORZ_EXCLUSIVE_EN 0x80000000
#define R128_OV0_EXCLUSIVE_VERT 0x040C
# define R128_EXCL_VERT_START_MASK 0x000003ff
# define R128_EXCL_VERT_END_MASK 0x03ff0000
#define R128_OV0_REG_LOAD_CNTL 0x0410
# define R128_REG_LD_CTL_LOCK 0x00000001L
# define R128_REG_LD_CTL_VBLANK_DURING_LOCK 0x00000002L
# define R128_REG_LD_CTL_STALL_GUI_UNTIL_FLIP 0x00000004L
# define R128_REG_LD_CTL_LOCK_READBACK 0x00000008L
#define R128_OV0_SCALE_CNTL 0x0420
# define R128_SCALER_PIX_EXPAND 0x00000001L
# define R128_SCALER_Y2R_TEMP 0x00000002L
# define R128_SCALER_HORZ_PICK_NEAREST 0x00000003L
# define R128_SCALER_VERT_PICK_NEAREST 0x00000004L
# define R128_SCALER_SIGNED_UV 0x00000010L
# define R128_SCALER_GAMMA_SEL_MASK 0x00000060L
# define R128_SCALER_GAMMA_SEL_BRIGHT 0x00000000L
# define R128_SCALER_GAMMA_SEL_G22 0x00000020L
# define R128_SCALER_GAMMA_SEL_G18 0x00000040L
# define R128_SCALER_GAMMA_SEL_G14 0x00000060L
# define R128_SCALER_COMCORE_SHIFT_UP_ONE 0x00000080L
# define R128_SCALER_SURFAC_FORMAT 0x00000f00L
# define R128_SCALER_SOURCE_15BPP 0x00000300L
# define R128_SCALER_SOURCE_16BPP 0x00000400L
# define R128_SCALER_SOURCE_32BPP 0x00000600L
# define R128_SCALER_SOURCE_YUV9 0x00000900L
# define R128_SCALER_SOURCE_YUV12 0x00000A00L
# define R128_SCALER_SOURCE_VYUY422 0x00000B00L
# define R128_SCALER_SOURCE_YVYU422 0x00000C00L
# define R128_SCALER_SMART_SWITCH 0x00008000L
# define R128_SCALER_BURST_PER_PLANE 0x00ff0000L
# define R128_SCALER_DOUBLE_BUFFER 0x01000000L
# define R128_SCALER_DIS_LIMIT 0x08000000L
# define R128_SCALER_PRG_LOAD_START 0x10000000L
# define R128_SCALER_INT_EMU 0x20000000L
# define R128_SCALER_ENABLE 0x40000000L
# define R128_SCALER_SOFT_RESET 0x80000000L
#define R128_OV0_V_INC 0x0424
#define R128_OV0_P1_V_ACCUM_INIT 0x0428
# define R128_OV0_P1_MAX_LN_IN_PER_LN_OUT 0x00000003L
# define R128_OV0_P1_V_ACCUM_INIT_MASK 0x01ff8000L
#define R128_OV0_P23_V_ACCUM_INIT 0x042C
#define R128_OV0_P1_BLANK_LINES_AT_TOP 0x0430
# define R128_P1_BLNK_LN_AT_TOP_M1_MASK 0x00000fffL
# define R128_P1_ACTIVE_LINES_M1 0x0fff0000L
#define R128_OV0_P23_BLANK_LINES_AT_TOP 0x0434
# define R128_P23_BLNK_LN_AT_TOP_M1_MASK 0x000007ffL
# define R128_P23_ACTIVE_LINES_M1 0x07ff0000L
#define R128_OV0_VID_BUF0_BASE_ADRS 0x0440
# define R128_VIF_BUF0_PITCH_SEL 0x00000001L
# define R128_VIF_BUF0_TILE_ADRS 0x00000002L
# define R128_VIF_BUF0_BASE_ADRS_MASK 0x03fffff0L
# define R128_VIF_BUF0_1ST_LINE_LSBS_MASK 0x48000000L
#define R128_OV0_VID_BUF1_BASE_ADRS 0x0444
# define R128_VIF_BUF1_PITCH_SEL 0x00000001L
# define R128_VIF_BUF1_TILE_ADRS 0x00000002L
# define R128_VIF_BUF1_BASE_ADRS_MASK 0x03fffff0L
# define R128_VIF_BUF1_1ST_LINE_LSBS_MASK 0x48000000L
#define R128_OV0_VID_BUF2_BASE_ADRS 0x0448
# define R128_VIF_BUF2_PITCH_SEL 0x00000001L
# define R128_VIF_BUF2_TILE_ADRS 0x00000002L
# define R128_VIF_BUF2_BASE_ADRS_MASK 0x03fffff0L
# define R128_VIF_BUF2_1ST_LINE_LSBS_MASK 0x48000000L
#define R128_OV0_VID_BUF3_BASE_ADRS 0x044C
#define R128_OV0_VID_BUF4_BASE_ADRS 0x0450
#define R128_OV0_VID_BUF5_BASE_ADRS 0x0454
#define R128_OV0_VID_BUF_PITCH0_VALUE 0x0460
#define R128_OV0_VID_BUF_PITCH1_VALUE 0x0464
#define R128_OV0_AUTO_FLIP_CNTL 0x0470
#define R128_OV0_DEINTERLACE_PATTERN 0x0474
#define R128_OV0_H_INC 0x0480
#define R128_OV0_STEP_BY 0x0484
#define R128_OV0_P1_H_ACCUM_INIT 0x0488
#define R128_OV0_P23_H_ACCUM_INIT 0x048C
#define R128_OV0_P1_X_START_END 0x0494
#define R128_OV0_P2_X_START_END 0x0498
#define R128_OV0_P3_X_START_END 0x049C
#define R128_OV0_FILTER_CNTL 0x04A0
#define R128_OV0_FOUR_TAP_COEF_0 0x04B0
#define R128_OV0_FOUR_TAP_COEF_1 0x04B4
#define R128_OV0_FOUR_TAP_COEF_2 0x04B8
#define R128_OV0_FOUR_TAP_COEF_3 0x04BC
#define R128_OV0_FOUR_TAP_COEF_4 0x04C0
#define R128_OV0_COLOUR_CNTL 0x04E0
#define R128_OV0_VIDEO_KEY_CLR 0x04E4
#define R128_OV0_VIDEO_KEY_MSK 0x04E8
#define R128_OV0_GRAPHICS_KEY_CLR 0x04EC
#define R128_OV0_GRAPHICS_KEY_MSK 0x04F0
#define R128_OV0_KEY_CNTL 0x04F4
# define R128_VIDEO_KEY_FN_MASK 0x00000007L
# define R128_VIDEO_KEY_FN_FALSE 0x00000000L
# define R128_VIDEO_KEY_FN_TRUE 0x00000001L
# define R128_VIDEO_KEY_FN_EQ 0x00000004L
# define R128_VIDEO_KEY_FN_NE 0x00000005L
# define R128_GRAPHIC_KEY_FN_MASK 0x00000070L
# define R128_GRAPHIC_KEY_FN_FALSE 0x00000000L
# define R128_GRAPHIC_KEY_FN_TRUE 0x00000010L
# define R128_GRAPHIC_KEY_FN_EQ 0x00000040L
# define R128_GRAPHIC_KEY_FN_NE 0x00000050L
# define R128_CMP_MIX_MASK 0x00000100L
# define R128_CMP_MIX_OR 0x00000000L
# define R128_CMP_MIX_AND 0x00000100L
#define R128_OV0_TEST 0x04F8
 
 
#define R128_PALETTE_DATA 0x00b4
#define R128_PALETTE_INDEX 0x00b0
#define R128_PC_DEBUG_MODE 0x1760
#define R128_PC_GUI_CTLSTAT 0x1748
#define R128_PC_GUI_MODE 0x1744
# define R128_PC_IGNORE_UNIFY (1 << 5)
#define R128_PC_MISC_CNTL 0x0188
#define R128_PC_NGUI_CTLSTAT 0x0184
# define R128_PC_FLUSH_GUI (3 << 0)
# define R128_PC_RI_GUI (1 << 2)
# define R128_PC_FLUSH_ALL 0x00ff
# define R128_PC_BUSY (1 << 31)
#define R128_PC_NGUI_MODE 0x0180
#define R128_PCI_GART_PAGE 0x017c
#define R128_PLANE_3D_MASK_C 0x1d44
#define R128_PLL_TEST_CNTL 0x0013 /* PLL */
#define R128_PMI_CAP_ID 0x0f5c /* PCI */
#define R128_PMI_DATA 0x0f63 /* PCI */
#define R128_PMI_NXT_CAP_PTR 0x0f5d /* PCI */
#define R128_PMI_PMC_REG 0x0f5e /* PCI */
#define R128_PMI_PMCSR_REG 0x0f60 /* PCI */
#define R128_PMI_REGISTER 0x0f5c /* PCI */
#define R128_PPLL_CNTL 0x0002 /* PLL */
# define R128_PPLL_RESET (1 << 0)
# define R128_PPLL_SLEEP (1 << 1)
# define R128_PPLL_ATOMIC_UPDATE_EN (1 << 16)
# define R128_PPLL_VGA_ATOMIC_UPDATE_EN (1 << 17)
#define R128_PPLL_DIV_0 0x0004 /* PLL */
#define R128_PPLL_DIV_1 0x0005 /* PLL */
#define R128_PPLL_DIV_2 0x0006 /* PLL */
#define R128_PPLL_DIV_3 0x0007 /* PLL */
# define R128_PPLL_FB3_DIV_MASK 0x07ff
# define R128_PPLL_POST3_DIV_MASK 0x00070000
#define R128_PPLL_REF_DIV 0x0003 /* PLL */
# define R128_PPLL_REF_DIV_MASK 0x03ff
# define R128_PPLL_ATOMIC_UPDATE_R (1 << 15) /* same as _W */
# define R128_PPLL_ATOMIC_UPDATE_W (1 << 15) /* same as _R */
#define R128_PWR_MNGMT_CNTL_STATUS 0x0f60 /* PCI */
#define R128_REG_BASE 0x0f18 /* PCI */
#define R128_REGPROG_INF 0x0f09 /* PCI */
#define R128_REVISION_ID 0x0f08 /* PCI */
 
#define R128_SC_BOTTOM 0x164c
#define R128_SC_BOTTOM_RIGHT 0x16f0
#define R128_SC_BOTTOM_RIGHT_C 0x1c8c
#define R128_SC_LEFT 0x1640
#define R128_SC_RIGHT 0x1644
#define R128_SC_TOP 0x1648
#define R128_SC_TOP_LEFT 0x16ec
#define R128_SC_TOP_LEFT_C 0x1c88
#define R128_SEQ8_DATA 0x03c5 /* VGA */
#define R128_SEQ8_IDX 0x03c4 /* VGA */
#define R128_SNAPSHOT_F_COUNT 0x0244
#define R128_SNAPSHOT_VH_COUNTS 0x0240
#define R128_SNAPSHOT_VIF_COUNT 0x024c
#define R128_SRC_OFFSET 0x15ac
#define R128_SRC_PITCH 0x15b0
#define R128_SRC_PITCH_OFFSET 0x1428
#define R128_SRC_SC_BOTTOM 0x165c
#define R128_SRC_SC_BOTTOM_RIGHT 0x16f4
#define R128_SRC_SC_RIGHT 0x1654
#define R128_SRC_X 0x1414
#define R128_SRC_X_Y 0x1590
#define R128_SRC_Y 0x1418
#define R128_SRC_Y_X 0x1434
#define R128_STATUS 0x0f06 /* PCI */
#define R128_SUBPIC_CNTL 0x0540 /* ? */
#define R128_SUB_CLASS 0x0f0a /* PCI */
#define R128_SURFACE_DELAY 0x0b00
#define R128_SURFACE0_INFO 0x0b0c
#define R128_SURFACE0_LOWER_BOUND 0x0b04
#define R128_SURFACE0_UPPER_BOUND 0x0b08
#define R128_SURFACE1_INFO 0x0b1c
#define R128_SURFACE1_LOWER_BOUND 0x0b14
#define R128_SURFACE1_UPPER_BOUND 0x0b18
#define R128_SURFACE2_INFO 0x0b2c
#define R128_SURFACE2_LOWER_BOUND 0x0b24
#define R128_SURFACE2_UPPER_BOUND 0x0b28
#define R128_SURFACE3_INFO 0x0b3c
#define R128_SURFACE3_LOWER_BOUND 0x0b34
#define R128_SURFACE3_UPPER_BOUND 0x0b38
#define R128_SW_SEMAPHORE 0x013c
 
#define R128_TEST_DEBUG_CNTL 0x0120
#define R128_TEST_DEBUG_MUX 0x0124
#define R128_TEST_DEBUG_OUT 0x012c
#define R128_TMDS_CRC 0x02a0
#define R128_TRAIL_BRES_DEC 0x1614
#define R128_TRAIL_BRES_ERR 0x160c
#define R128_TRAIL_BRES_INC 0x1610
#define R128_TRAIL_X 0x1618
#define R128_TRAIL_X_SUB 0x1620
 
#define R128_VCLK_ECP_CNTL 0x0008 /* PLL */
#define R128_VENDOR_ID 0x0f00 /* PCI */
#define R128_VGA_DDA_CONFIG 0x02e8
#define R128_VGA_DDA_ON_OFF 0x02ec
#define R128_VID_BUFFER_CONTROL 0x0900
#define R128_VIDEOMUX_CNTL 0x0190
#define R128_VIPH_CONTROL 0x01D0 /* ? */
 
#define R128_WAIT_UNTIL 0x1720
 
#define R128_X_MPLL_REF_FB_DIV 0x000a /* PLL */
#define R128_XCLK_CNTL 0x000d /* PLL */
#define R128_XDLL_CNTL 0x000c /* PLL */
#define R128_XPLL_CNTL 0x000b /* PLL */
 
/* Registers for CCE and Microcode Engine */
#define R128_PM4_MICROCODE_ADDR 0x07d4
#define R128_PM4_MICROCODE_RADDR 0x07d8
#define R128_PM4_MICROCODE_DATAH 0x07dc
#define R128_PM4_MICROCODE_DATAL 0x07e0
 
#define R128_PM4_BUFFER_OFFSET 0x0700
#define R128_PM4_BUFFER_CNTL 0x0704
# define R128_PM4_NONPM4 (0 << 28)
# define R128_PM4_192PIO (1 << 28)
# define R128_PM4_192BM (2 << 28)
# define R128_PM4_128PIO_64INDBM (3 << 28)
# define R128_PM4_128BM_64INDBM (4 << 28)
# define R128_PM4_64PIO_128INDBM (5 << 28)
# define R128_PM4_64BM_128INDBM (6 << 28)
# define R128_PM4_64PIO_64VCBM_64INDBM (7 << 28)
# define R128_PM4_64BM_64VCBM_64INDBM (8 << 28)
# define R128_PM4_64PIO_64VCPIO_64INDPIO (15 << 28)
#define R128_PM4_BUFFER_WM_CNTL 0x0708
# define R128_WMA_SHIFT 0
# define R128_WMB_SHIFT 8
# define R128_WMC_SHIFT 16
# define R128_WB_WM_SHIFT 24
#define R128_PM4_BUFFER_DL_RPTR_ADDR 0x070c
#define R128_PM4_BUFFER_DL_RPTR 0x0710
#define R128_PM4_BUFFER_DL_WPTR 0x0714
# define R128_PM4_BUFFER_DL_DONE (1 << 31)
#define R128_PM4_BUFFER_DL_WPTR_DELAY 0x0718
# define R128_PRE_WRITE_TIMER_SHIFT 0
# define R128_PRE_WRITE_LIMIT_SHIFT 23
#define R128_PM4_VC_FPU_SETUP 0x071c
# define R128_FRONT_DIR_CW (0 << 0)
# define R128_FRONT_DIR_CCW (1 << 0)
# define R128_FRONT_DIR_MASK (1 << 0)
# define R128_BACKFACE_CULL (0 << 1)
# define R128_BACKFACE_POINTS (1 << 1)
# define R128_BACKFACE_LINES (2 << 1)
# define R128_BACKFACE_SOLID (3 << 1)
# define R128_BACKFACE_MASK (3 << 1)
# define R128_FRONTFACE_CULL (0 << 3)
# define R128_FRONTFACE_POINTS (1 << 3)
# define R128_FRONTFACE_LINES (2 << 3)
# define R128_FRONTFACE_SOLID (3 << 3)
# define R128_FRONTFACE_MASK (3 << 3)
# define R128_FPU_COLOR_SOLID (0 << 5)
# define R128_FPU_COLOR_FLAT (1 << 5)
# define R128_FPU_COLOR_GOURAUD (2 << 5)
# define R128_FPU_COLOR_GOURAUD2 (3 << 5)
# define R128_FPU_COLOR_MASK (3 << 5)
# define R128_FPU_SUB_PIX_2BITS (0 << 7)
# define R128_FPU_SUB_PIX_4BITS (1 << 7)
# define R128_FPU_MODE_2D (0 << 8)
# define R128_FPU_MODE_3D (1 << 8)
# define R128_TRAP_BITS_DISABLE (1 << 9)
# define R128_EDGE_ANTIALIAS (1 << 10)
# define R128_SUPERSAMPLE (1 << 11)
# define R128_XFACTOR_2 (0 << 12)
# define R128_XFACTOR_4 (1 << 12)
# define R128_YFACTOR_2 (0 << 13)
# define R128_YFACTOR_4 (1 << 13)
# define R128_FLAT_SHADE_VERTEX_D3D (0 << 14)
# define R128_FLAT_SHADE_VERTEX_OGL (1 << 14)
# define R128_FPU_ROUND_TRUNCATE (0 << 15)
# define R128_FPU_ROUND_NEAREST (1 << 15)
# define R128_WM_SEL_8DW (0 << 16)
# define R128_WM_SEL_16DW (1 << 16)
# define R128_WM_SEL_32DW (2 << 16)
#define R128_PM4_VC_DEBUG_CONFIG 0x07a4
#define R128_PM4_VC_STAT 0x07a8
#define R128_PM4_VC_TIMESTAMP0 0x07b0
#define R128_PM4_VC_TIMESTAMP1 0x07b4
#define R128_PM4_STAT 0x07b8
# define R128_PM4_FIFOCNT_MASK 0x0fff
# define R128_PM4_BUSY (1 << 16)
# define R128_PM4_GUI_ACTIVE (1 << 31)
#define R128_PM4_BUFFER_ADDR 0x07f0
#define R128_PM4_MICRO_CNTL 0x07fc
# define R128_PM4_MICRO_FREERUN (1 << 30)
#define R128_PM4_FIFO_DATA_EVEN 0x1000
#define R128_PM4_FIFO_DATA_ODD 0x1004
 
#define R128_SCALE_3D_CNTL 0x1a00
# define R128_SCALE_DITHER_ERR_DIFF (0 << 1)
# define R128_SCALE_DITHER_TABLE (1 << 1)
# define R128_TEX_CACHE_SIZE_FULL (0 << 2)
# define R128_TEX_CACHE_SIZE_HALF (1 << 2)
# define R128_DITHER_INIT_CURR (0 << 3)
# define R128_DITHER_INIT_RESET (1 << 3)
# define R128_ROUND_24BIT (1 << 4)
# define R128_TEX_CACHE_DISABLE (1 << 5)
# define R128_SCALE_3D_NOOP (0 << 6)
# define R128_SCALE_3D_SCALE (1 << 6)
# define R128_SCALE_3D_TEXMAP_SHADE (2 << 6)
# define R128_SCALE_PIX_BLEND (0 << 8)
# define R128_SCALE_PIX_REPLICATE (1 << 8)
# define R128_TEX_CACHE_SPLIT (1 << 9)
# define R128_APPLE_YUV_MODE (1 << 10)
# define R128_TEX_CACHE_PALLETE_MODE (1 << 11)
# define R128_ALPHA_COMB_ADD_CLAMP (0 << 12)
# define R128_ALPHA_COMB_ADD_NCLAMP (1 << 12)
# define R128_ALPHA_COMB_SUB_DST_SRC_CLAMP (2 << 12)
# define R128_ALPHA_COMB_SUB_DST_SRC_NCLAMP (3 << 12)
# define R128_FOG_TABLE (1 << 14)
# define R128_SIGNED_DST_CLAMP (1 << 15)
# define R128_ALPHA_BLEND_SRC_ZERO (0 << 16)
# define R128_ALPHA_BLEND_SRC_ONE (1 << 16)
# define R128_ALPHA_BLEND_SRC_SRCCOLOR (2 << 16)
# define R128_ALPHA_BLEND_SRC_INVSRCCOLOR (3 << 16)
# define R128_ALPHA_BLEND_SRC_SRCALPHA (4 << 16)
# define R128_ALPHA_BLEND_SRC_INVSRCALPHA (5 << 16)
# define R128_ALPHA_BLEND_SRC_DSTALPHA (6 << 16)
# define R128_ALPHA_BLEND_SRC_INVDSTALPHA (7 << 16)
# define R128_ALPHA_BLEND_SRC_DSTCOLOR (8 << 16)
# define R128_ALPHA_BLEND_SRC_INVDSTCOLOR (9 << 16)
# define R128_ALPHA_BLEND_SRC_SAT (10 << 16)
# define R128_ALPHA_BLEND_SRC_BLEND (11 << 16)
# define R128_ALPHA_BLEND_SRC_INVBLEND (12 << 16)
# define R128_ALPHA_BLEND_DST_ZERO (0 << 20)
# define R128_ALPHA_BLEND_DST_ONE (1 << 20)
# define R128_ALPHA_BLEND_DST_SRCCOLOR (2 << 20)
# define R128_ALPHA_BLEND_DST_INVSRCCOLOR (3 << 20)
# define R128_ALPHA_BLEND_DST_SRCALPHA (4 << 20)
# define R128_ALPHA_BLEND_DST_INVSRCALPHA (5 << 20)
# define R128_ALPHA_BLEND_DST_DSTALPHA (6 << 20)
# define R128_ALPHA_BLEND_DST_INVDSTALPHA (7 << 20)
# define R128_ALPHA_BLEND_DST_DSTCOLOR (8 << 20)
# define R128_ALPHA_BLEND_DST_INVDSTCOLOR (9 << 20)
# define R128_ALPHA_TEST_NEVER (0 << 24)
# define R128_ALPHA_TEST_LESS (1 << 24)
# define R128_ALPHA_TEST_LESSEQUAL (2 << 24)
# define R128_ALPHA_TEST_EQUAL (3 << 24)
# define R128_ALPHA_TEST_GREATEREQUAL (4 << 24)
# define R128_ALPHA_TEST_GREATER (5 << 24)
# define R128_ALPHA_TEST_NEQUAL (6 << 24)
# define R128_ALPHA_TEST_ALWAYS (7 << 24)
# define R128_COMPOSITE_SHADOW_CMP_EQUAL (0 << 28)
# define R128_COMPOSITE_SHADOW_CMP_NEQUAL (1 << 28)
# define R128_COMPOSITE_SHADOW (1 << 29)
# define R128_TEX_MAP_ALPHA_IN_TEXTURE (1 << 30)
# define R128_TEX_CACHE_LINE_SIZE_8QW (0 << 31)
# define R128_TEX_CACHE_LINE_SIZE_4QW (1 << 31)
#define R128_SCALE_3D_DATATYPE 0x1a20
 
#define R128_SETUP_CNTL 0x1bc4
# define R128_DONT_START_TRIANGLE (1 << 0)
# define R128_Z_BIAS (0 << 1)
# define R128_DONT_START_ANY_ON (1 << 2)
# define R128_COLOR_SOLID_COLOR (0 << 3)
# define R128_COLOR_FLAT_VERT_1 (1 << 3)
# define R128_COLOR_FLAT_VERT_2 (2 << 3)
# define R128_COLOR_FLAT_VERT_3 (3 << 3)
# define R128_COLOR_GOURAUD (4 << 3)
# define R128_PRIM_TYPE_TRI (0 << 7)
# define R128_PRIM_TYPE_LINE (1 << 7)
# define R128_PRIM_TYPE_POINT (2 << 7)
# define R128_PRIM_TYPE_POLY_EDGE (3 << 7)
# define R128_TEXTURE_ST_MULT_W (0 << 9)
# define R128_TEXTURE_ST_DIRECT (1 << 9)
# define R128_STARTING_VERTEX_1 (1 << 14)
# define R128_STARTING_VERTEX_2 (2 << 14)
# define R128_STARTING_VERTEX_3 (3 << 14)
# define R128_ENDING_VERTEX_1 (1 << 16)
# define R128_ENDING_VERTEX_2 (2 << 16)
# define R128_ENDING_VERTEX_3 (3 << 16)
# define R128_SU_POLY_LINE_LAST (0 << 18)
# define R128_SU_POLY_LINE_NOT_LAST (1 << 18)
# define R128_SUB_PIX_2BITS (0 << 19)
# define R128_SUB_PIX_4BITS (1 << 19)
# define R128_SET_UP_CONTINUE (1 << 31)
 
#define R128_WINDOW_XY_OFFSET 0x1bcc
# define R128_WINDOW_Y_SHIFT 4
# define R128_WINDOW_X_SHIFT 20
 
#define R128_Z_OFFSET_C 0x1c90
#define R128_Z_PITCH_C 0x1c94
# define R128_Z_TILE (1 << 16)
#define R128_Z_STEN_CNTL_C 0x1c98
# define R128_Z_PIX_WIDTH_16 (0 << 1)
# define R128_Z_PIX_WIDTH_24 (1 << 1)
# define R128_Z_PIX_WIDTH_32 (2 << 1)
# define R128_Z_PIX_WIDTH_MASK (3 << 1)
# define R128_Z_TEST_NEVER (0 << 4)
# define R128_Z_TEST_LESS (1 << 4)
# define R128_Z_TEST_LESSEQUAL (2 << 4)
# define R128_Z_TEST_EQUAL (3 << 4)
# define R128_Z_TEST_GREATEREQUAL (4 << 4)
# define R128_Z_TEST_GREATER (5 << 4)
# define R128_Z_TEST_NEQUAL (6 << 4)
# define R128_Z_TEST_ALWAYS (7 << 4)
# define R128_Z_TEST_MASK (7 << 4)
# define R128_STENCIL_TEST_NEVER (0 << 12)
# define R128_STENCIL_TEST_LESS (1 << 12)
# define R128_STENCIL_TEST_LESSEQUAL (2 << 12)
# define R128_STENCIL_TEST_EQUAL (3 << 12)
# define R128_STENCIL_TEST_GREATEREQUAL (4 << 12)
# define R128_STENCIL_TEST_GREATER (5 << 12)
# define R128_STENCIL_TEST_NEQUAL (6 << 12)
# define R128_STENCIL_TEST_ALWAYS (7 << 12)
# define R128_STENCIL_S_FAIL_KEEP (0 << 16)
# define R128_STENCIL_S_FAIL_ZERO (1 << 16)
# define R128_STENCIL_S_FAIL_REPLACE (2 << 16)
# define R128_STENCIL_S_FAIL_INC (3 << 16)
# define R128_STENCIL_S_FAIL_DEC (4 << 16)
# define R128_STENCIL_S_FAIL_INV (5 << 16)
# define R128_STENCIL_ZPASS_KEEP (0 << 20)
# define R128_STENCIL_ZPASS_ZERO (1 << 20)
# define R128_STENCIL_ZPASS_REPLACE (2 << 20)
# define R128_STENCIL_ZPASS_INC (3 << 20)
# define R128_STENCIL_ZPASS_DEC (4 << 20)
# define R128_STENCIL_ZPASS_INV (5 << 20)
# define R128_STENCIL_ZFAIL_KEEP (0 << 24)
# define R128_STENCIL_ZFAIL_ZERO (1 << 24)
# define R128_STENCIL_ZFAIL_REPLACE (2 << 24)
# define R128_STENCIL_ZFAIL_INC (3 << 24)
# define R128_STENCIL_ZFAIL_DEC (4 << 24)
# define R128_STENCIL_ZFAIL_INV (5 << 24)
#define R128_TEX_CNTL_C 0x1c9c
# define R128_Z_ENABLE (1 << 0)
# define R128_Z_WRITE_ENABLE (1 << 1)
# define R128_STENCIL_ENABLE (1 << 3)
# define R128_SHADE_ENABLE (0 << 4)
# define R128_TEXMAP_ENABLE (1 << 4)
# define R128_SEC_TEXMAP_ENABLE (1 << 5)
# define R128_FOG_ENABLE (1 << 7)
# define R128_DITHER_ENABLE (1 << 8)
# define R128_ALPHA_ENABLE (1 << 9)
# define R128_ALPHA_TEST_ENABLE (1 << 10)
# define R128_SPEC_LIGHT_ENABLE (1 << 11)
# define R128_TEX_CHROMA_KEY_ENABLE (1 << 12)
# define R128_ALPHA_IN_TEX_COMPLETE_A (0 << 13)
# define R128_ALPHA_IN_TEX_LSB_A (1 << 13)
# define R128_LIGHT_DIS (0 << 14)
# define R128_LIGHT_COPY (1 << 14)
# define R128_LIGHT_MODULATE (2 << 14)
# define R128_LIGHT_ADD (3 << 14)
# define R128_LIGHT_BLEND_CONSTANT (4 << 14)
# define R128_LIGHT_BLEND_TEXTURE (5 << 14)
# define R128_LIGHT_BLEND_VERTEX (6 << 14)
# define R128_LIGHT_BLEND_CONST_COLOR (7 << 14)
# define R128_ALPHA_LIGHT_DIS (0 << 18)
# define R128_ALPHA_LIGHT_COPY (1 << 18)
# define R128_ALPHA_LIGHT_MODULATE (2 << 18)
# define R128_ALPHA_LIGHT_ADD (3 << 18)
# define R128_ANTI_ALIAS (1 << 21)
# define R128_TEX_CACHE_FLUSH (1 << 23)
# define R128_LOD_BIAS_SHIFT 24
# define R128_LOD_BIAS_MASK (0xff << 24)
#define R128_MISC_3D_STATE_CNTL_REG 0x1ca0
# define R128_REF_ALPHA_MASK 0xff
# define R128_MISC_SCALE_3D_NOOP (0 << 8)
# define R128_MISC_SCALE_3D_SCALE (1 << 8)
# define R128_MISC_SCALE_3D_TEXMAP_SHADE (2 << 8)
# define R128_MISC_SCALE_PIX_BLEND (0 << 10)
# define R128_MISC_SCALE_PIX_REPLICATE (1 << 10)
# define R128_ALPHA_COMB_ADD_CLAMP (0 << 12)
# define R128_ALPHA_COMB_ADD_NO_CLAMP (1 << 12)
# define R128_ALPHA_COMB_SUB_SRC_DST_CLAMP (2 << 12)
# define R128_ALPHA_COMB_SUB_SRC_DST_NO_CLAMP (3 << 12)
# define R128_FOG_VERTEX (0 << 14)
# define R128_FOG_TABLE (1 << 14)
# define R128_ALPHA_BLEND_SRC_ZERO (0 << 16)
# define R128_ALPHA_BLEND_SRC_ONE (1 << 16)
# define R128_ALPHA_BLEND_SRC_SRCCOLOR (2 << 16)
# define R128_ALPHA_BLEND_SRC_INVSRCCOLOR (3 << 16)
# define R128_ALPHA_BLEND_SRC_SRCALPHA (4 << 16)
# define R128_ALPHA_BLEND_SRC_INVSRCALPHA (5 << 16)
# define R128_ALPHA_BLEND_SRC_DESTALPHA (6 << 16)
# define R128_ALPHA_BLEND_SRC_INVDESTALPHA (7 << 16)
# define R128_ALPHA_BLEND_SRC_DESTCOLOR (8 << 16)
# define R128_ALPHA_BLEND_SRC_INVDESTCOLOR (9 << 16)
# define R128_ALPHA_BLEND_SRC_SRCALPHASAT (10 << 16)
# define R128_ALPHA_BLEND_SRC_BOTHSRCALPHA (11 << 16)
# define R128_ALPHA_BLEND_SRC_BOTHINVSRCALPHA (12 << 16)
# define R128_ALPHA_BLEND_SRC_MASK (15 << 16)
# define R128_ALPHA_BLEND_DST_ZERO (0 << 20)
# define R128_ALPHA_BLEND_DST_ONE (1 << 20)
# define R128_ALPHA_BLEND_DST_SRCCOLOR (2 << 20)
# define R128_ALPHA_BLEND_DST_INVSRCCOLOR (3 << 20)
# define R128_ALPHA_BLEND_DST_SRCALPHA (4 << 20)
# define R128_ALPHA_BLEND_DST_INVSRCALPHA (5 << 20)
# define R128_ALPHA_BLEND_DST_DESTALPHA (6 << 20)
# define R128_ALPHA_BLEND_DST_INVDESTALPHA (7 << 20)
# define R128_ALPHA_BLEND_DST_DESTCOLOR (8 << 20)
# define R128_ALPHA_BLEND_DST_INVDESTCOLOR (9 << 20)
# define R128_ALPHA_BLEND_DST_SRCALPHASAT (10 << 20)
# define R128_ALPHA_BLEND_DST_MASK (15 << 20)
# define R128_ALPHA_TEST_NEVER (0 << 24)
# define R128_ALPHA_TEST_LESS (1 << 24)
# define R128_ALPHA_TEST_LESSEQUAL (2 << 24)
# define R128_ALPHA_TEST_EQUAL (3 << 24)
# define R128_ALPHA_TEST_GREATEREQUAL (4 << 24)
# define R128_ALPHA_TEST_GREATER (5 << 24)
# define R128_ALPHA_TEST_NEQUAL (6 << 24)
# define R128_ALPHA_TEST_ALWAYS (7 << 24)
# define R128_ALPHA_TEST_MASK (7 << 24)
#define R128_TEXTURE_CLR_CMP_CLR_C 0x1ca4
#define R128_TEXTURE_CLR_CMP_MSK_C 0x1ca8
#define R128_FOG_COLOR_C 0x1cac
# define R128_FOG_BLUE_SHIFT 0
# define R128_FOG_GREEN_SHIFT 8
# define R128_FOG_RED_SHIFT 16
#define R128_PRIM_TEX_CNTL_C 0x1cb0
# define R128_MIN_BLEND_NEAREST (0 << 1)
# define R128_MIN_BLEND_LINEAR (1 << 1)
# define R128_MIN_BLEND_MIPNEAREST (2 << 1)
# define R128_MIN_BLEND_MIPLINEAR (3 << 1)
# define R128_MIN_BLEND_LINEARMIPNEAREST (4 << 1)
# define R128_MIN_BLEND_LINEARMIPLINEAR (5 << 1)
# define R128_MIN_BLEND_MASK (7 << 1)
# define R128_MAG_BLEND_NEAREST (0 << 4)
# define R128_MAG_BLEND_LINEAR (1 << 4)
# define R128_MAG_BLEND_MASK (7 << 4)
# define R128_MIP_MAP_DISABLE (1 << 7)
# define R128_TEX_CLAMP_S_WRAP (0 << 8)
# define R128_TEX_CLAMP_S_MIRROR (1 << 8)
# define R128_TEX_CLAMP_S_CLAMP (2 << 8)
# define R128_TEX_CLAMP_S_BORDER_COLOR (3 << 8)
# define R128_TEX_CLAMP_S_MASK (3 << 8)
# define R128_TEX_WRAP_S (1 << 10)
# define R128_TEX_CLAMP_T_WRAP (0 << 11)
# define R128_TEX_CLAMP_T_MIRROR (1 << 11)
# define R128_TEX_CLAMP_T_CLAMP (2 << 11)
# define R128_TEX_CLAMP_T_BORDER_COLOR (3 << 11)
# define R128_TEX_CLAMP_T_MASK (3 << 11)
# define R128_TEX_WRAP_T (1 << 13)
# define R128_TEX_PERSPECTIVE_DISABLE (1 << 14)
# define R128_DATATYPE_VQ (0 << 16)
# define R128_DATATYPE_CI4 (1 << 16)
# define R128_DATATYPE_CI8 (2 << 16)
# define R128_DATATYPE_ARGB1555 (3 << 16)
# define R128_DATATYPE_RGB565 (4 << 16)
# define R128_DATATYPE_RGB888 (5 << 16)
# define R128_DATATYPE_ARGB8888 (6 << 16)
# define R128_DATATYPE_RGB332 (7 << 16)
# define R128_DATATYPE_Y8 (8 << 16)
# define R128_DATATYPE_RGB8 (9 << 16)
# define R128_DATATYPE_CI16 (10 << 16)
# define R128_DATATYPE_YUV422 (11 << 16)
# define R128_DATATYPE_YUV422_2 (12 << 16)
# define R128_DATATYPE_AYUV444 (14 << 16)
# define R128_DATATYPE_ARGB4444 (15 << 16)
# define R128_PALLETE_EITHER (0 << 20)
# define R128_PALLETE_1 (1 << 20)
# define R128_PALLETE_2 (2 << 20)
# define R128_PSEUDOCOLOR_DT_RGB565 (0 << 24)
# define R128_PSEUDOCOLOR_DT_ARGB1555 (1 << 24)
# define R128_PSEUDOCOLOR_DT_ARGB4444 (2 << 24)
#define R128_PRIM_TEXTURE_COMBINE_CNTL_C 0x1cb4
# define R128_COMB_DIS (0 << 0)
# define R128_COMB_COPY (1 << 0)
# define R128_COMB_COPY_INP (2 << 0)
# define R128_COMB_MODULATE (3 << 0)
# define R128_COMB_MODULATE2X (4 << 0)
# define R128_COMB_MODULATE4X (5 << 0)
# define R128_COMB_ADD (6 << 0)
# define R128_COMB_ADD_SIGNED (7 << 0)
# define R128_COMB_BLEND_VERTEX (8 << 0)
# define R128_COMB_BLEND_TEXTURE (9 << 0)
# define R128_COMB_BLEND_CONST (10 << 0)
# define R128_COMB_BLEND_PREMULT (11 << 0)
# define R128_COMB_BLEND_PREV (12 << 0)
# define R128_COMB_BLEND_PREMULT_INV (13 << 0)
# define R128_COMB_ADD_SIGNED2X (14 << 0)
# define R128_COMB_BLEND_CONST_COLOR (15 << 0)
# define R128_COMB_MASK (15 << 0)
# define R128_COLOR_FACTOR_TEX (4 << 4)
# define R128_COLOR_FACTOR_NTEX (5 << 4)
# define R128_COLOR_FACTOR_ALPHA (6 << 4)
# define R128_COLOR_FACTOR_NALPHA (7 << 4)
# define R128_COLOR_FACTOR_MASK (15 << 4)
# define R128_INPUT_FACTOR_CONST_COLOR (2 << 10)
# define R128_INPUT_FACTOR_CONST_ALPHA (3 << 10)
# define R128_INPUT_FACTOR_INT_COLOR (4 << 10)
# define R128_INPUT_FACTOR_INT_ALPHA (5 << 10)
# define R128_INPUT_FACTOR_MASK (15 << 10)
# define R128_COMB_ALPHA_DIS (0 << 14)
# define R128_COMB_ALPHA_COPY (1 << 14)
# define R128_COMB_ALPHA_COPY_INP (2 << 14)
# define R128_COMB_ALPHA_MODULATE (3 << 14)
# define R128_COMB_ALPHA_MODULATE2X (4 << 14)
# define R128_COMB_ALPHA_MODULATE4X (5 << 14)
# define R128_COMB_ALPHA_ADD (6 << 14)
# define R128_COMB_ALPHA_ADD_SIGNED (7 << 14)
# define R128_COMB_ALPHA_ADD_SIGNED2X (14 << 14)
# define R128_COMB_ALPHA_MASK (15 << 14)
# define R128_ALPHA_FACTOR_TEX_ALPHA (6 << 18)
# define R128_ALPHA_FACTOR_NTEX_ALPHA (7 << 18)
# define R128_ALPHA_FACTOR_MASK (15 << 18)
# define R128_INP_FACTOR_A_CONST_ALPHA (1 << 25)
# define R128_INP_FACTOR_A_INT_ALPHA (2 << 25)
# define R128_INP_FACTOR_A_MASK (7 << 25)
#define R128_TEX_SIZE_PITCH_C 0x1cb8
# define R128_TEX_PITCH_SHIFT 0
# define R128_TEX_SIZE_SHIFT 4
# define R128_TEX_HEIGHT_SHIFT 8
# define R128_TEX_MIN_SIZE_SHIFT 12
# define R128_SEC_TEX_PITCH_SHIFT 16
# define R128_SEC_TEX_SIZE_SHIFT 20
# define R128_SEC_TEX_HEIGHT_SHIFT 24
# define R128_SEC_TEX_MIN_SIZE_SHIFT 28
# define R128_TEX_PITCH_MASK (0x0f << 0)
# define R128_TEX_SIZE_MASK (0x0f << 4)
# define R128_TEX_HEIGHT_MASK (0x0f << 8)
# define R128_TEX_MIN_SIZE_MASK (0x0f << 12)
# define R128_SEC_TEX_PITCH_MASK (0x0f << 16)
# define R128_SEC_TEX_SIZE_MASK (0x0f << 20)
# define R128_SEC_TEX_HEIGHT_MASK (0x0f << 24)
# define R128_SEC_TEX_MIN_SIZE_MASK (0x0f << 28)
# define R128_TEX_SIZE_PITCH_SHIFT 0
# define R128_SEC_TEX_SIZE_PITCH_SHIFT 16
# define R128_TEX_SIZE_PITCH_MASK (0xffff << 0)
# define R128_SEC_TEX_SIZE_PITCH_MASK (0xffff << 16)
#define R128_PRIM_TEX_0_OFFSET_C 0x1cbc
#define R128_PRIM_TEX_1_OFFSET_C 0x1cc0
#define R128_PRIM_TEX_2_OFFSET_C 0x1cc4
#define R128_PRIM_TEX_3_OFFSET_C 0x1cc8
#define R128_PRIM_TEX_4_OFFSET_C 0x1ccc
#define R128_PRIM_TEX_5_OFFSET_C 0x1cd0
#define R128_PRIM_TEX_6_OFFSET_C 0x1cd4
#define R128_PRIM_TEX_7_OFFSET_C 0x1cd8
#define R128_PRIM_TEX_8_OFFSET_C 0x1cdc
#define R128_PRIM_TEX_9_OFFSET_C 0x1ce0
#define R128_PRIM_TEX_10_OFFSET_C 0x1ce4
# define R128_TEX_NO_TILE (0 << 30)
# define R128_TEX_TILED_BY_HOST (1 << 30)
# define R128_TEX_TILED_BY_STORAGE (2 << 30)
# define R128_TEX_TILED_BY_STORAGE2 (3 << 30)
 
#define R128_SEC_TEX_CNTL_C 0x1d00
# define R128_SEC_SELECT_PRIM_ST (0 << 0)
# define R128_SEC_SELECT_SEC_ST (1 << 0)
#define R128_SEC_TEX_COMBINE_CNTL_C 0x1d04
# define R128_INPUT_FACTOR_PREV_COLOR (8 << 10)
# define R128_INPUT_FACTOR_PREV_ALPHA (9 << 10)
# define R128_INP_FACTOR_A_PREV_ALPHA (4 << 25)
#define R128_SEC_TEX_0_OFFSET_C 0x1d08
#define R128_SEC_TEX_1_OFFSET_C 0x1d0c
#define R128_SEC_TEX_2_OFFSET_C 0x1d10
#define R128_SEC_TEX_3_OFFSET_C 0x1d14
#define R128_SEC_TEX_4_OFFSET_C 0x1d18
#define R128_SEC_TEX_5_OFFSET_C 0x1d1c
#define R128_SEC_TEX_6_OFFSET_C 0x1d20
#define R128_SEC_TEX_7_OFFSET_C 0x1d24
#define R128_SEC_TEX_8_OFFSET_C 0x1d28
#define R128_SEC_TEX_9_OFFSET_C 0x1d2c
#define R128_SEC_TEX_10_OFFSET_C 0x1d30
#define R128_CONSTANT_COLOR_C 0x1d34
# define R128_CONSTANT_BLUE_SHIFT 0
# define R128_CONSTANT_GREEN_SHIFT 8
# define R128_CONSTANT_RED_SHIFT 16
# define R128_CONSTANT_ALPHA_SHIFT 24
#define R128_PRIM_TEXTURE_BORDER_COLOR_C 0x1d38
# define R128_PRIM_TEX_BORDER_BLUE_SHIFT 0
# define R128_PRIM_TEX_BORDER_GREEN_SHIFT 8
# define R128_PRIM_TEX_BORDER_RED_SHIFT 16
# define R128_PRIM_TEX_BORDER_ALPHA_SHIFT 24
#define R128_SEC_TEXTURE_BORDER_COLOR_C 0x1d3c
# define R128_SEC_TEX_BORDER_BLUE_SHIFT 0
# define R128_SEC_TEX_BORDER_GREEN_SHIFT 8
# define R128_SEC_TEX_BORDER_RED_SHIFT 16
# define R128_SEC_TEX_BORDER_ALPHA_SHIFT 24
#define R128_STEN_REF_MASK_C 0x1d40
# define R128_STEN_REFERENCE_SHIFT 0
# define R128_STEN_MASK_SHIFT 16
# define R128_STEN_WRITE_MASK_SHIFT 24
#define R128_PLANE_3D_MASK_C 0x1d44
#define R128_TEX_CACHE_STAT_COUNT 0x1974
 
 
/* Constants */
#define R128_AGP_TEX_OFFSET 0x02000000
 
#define R128_LAST_FRAME_REG R128_GUI_SCRATCH_REG0
 
/* CCE packet types */
#define R128_CCE_PACKET0 0x00000000
#define R128_CCE_PACKET0_ONE_REG_WR 0x00008000
#define R128_CCE_PACKET1 0x40000000
#define R128_CCE_PACKET2 0x80000000
#define R128_CCE_PACKET3 0xC0000000
#define R128_CCE_PACKET3_NOP 0xC0001000
#define R128_CCE_PACKET3_PAINT 0xC0001100
#define R128_CCE_PACKET3_BITBLT 0xC0001200
#define R128_CCE_PACKET3_SMALLTEXT 0xC0001300
#define R128_CCE_PACKET3_HOSTDATA_BLT 0xC0001400
#define R128_CCE_PACKET3_POLYLINE 0xC0001500
#define R128_CCE_PACKET3_SCALING 0xC0001600
#define R128_CCE_PACKET3_TRANS_SCALING 0xC0001700
#define R128_CCE_PACKET3_POLYSCANLINES 0xC0001800
#define R128_CCE_PACKET3_NEXT_CHAR 0xC0001900
#define R128_CCE_PACKET3_PAINT_MULTI 0xC0001A00
#define R128_CCE_PACKET3_BITBLT_MULTI 0xC0001B00
#define R128_CCE_PACKET3_PLY_NEXTSCAN 0xC0001D00
#define R128_CCE_PACKET3_SET_SCISSORS 0xC0001E00
#define R128_CCE_PACKET3_SET_MODE24BPP 0xC0001F00
#define R128_CCE_PACKET3_CNTL_PAINT 0xC0009100
#define R128_CCE_PACKET3_CNTL_BITBLT 0xC0009200
#define R128_CCE_PACKET3_CNTL_SMALLTEXT 0xC0009300
#define R128_CCE_PACKET3_CNTL_HOSTDATA_BLT 0xC0009400
#define R128_CCE_PACKET3_CNTL_POLYLINE 0xC0009500
#define R128_CCE_PACKET3_CNTL_SCALING 0xC0009600
#define R128_CCE_PACKET3_CNTL_TRANS_SCALING 0xC0009700
#define R128_CCE_PACKET3_CNTL_POLYSCANLINES 0xC0009800
#define R128_CCE_PACKET3_CNTL_NEXT_CHAR 0xC0009900
#define R128_CCE_PACKET3_CNTL_PAINT_MULTI 0xC0009A00
#define R128_CCE_PACKET3_CNTL_BITBLT_MULTI 0xC0009B00
#define R128_CCE_PACKET3_CNTL_TRANS_BITBLT 0xC0009C00
#define R128_CCE_PACKET3_3D_SAVE_CONTEXT 0xC0002000
#define R128_CCE_PACKET3_3D_PLAY_CONTEXT 0xC0002100
#define R128_CCE_PACKET3_3D_RNDR_GEN_INDX_PRIM 0xC0002300
#define R128_CCE_PACKET3_3D_RNDR_GEN_PRIM 0xC0002500
#define R128_CCE_PACKET3_LOAD_PALETTE 0xC0002C00
#define R128_CCE_PACKET3_PURGE 0xC0002D00
#define R128_CCE_PACKET3_NEXT_VERTEX_BUNDLE 0xC0002E00
# define R128_CCE_PACKET_MASK 0xC0000000
# define R128_CCE_PACKET_COUNT_MASK 0x3fff0000
# define R128_CCE_PACKET_MAX_DWORDS (1 << 12)
# define R128_CCE_PACKET0_REG_MASK 0x000007ff
# define R128_CCE_PACKET1_REG0_MASK 0x000007ff
# define R128_CCE_PACKET1_REG1_MASK 0x003ff800
 
#define R128_CCE_VC_FRMT_RHW 0x00000001
#define R128_CCE_VC_FRMT_DIFFUSE_BGR 0x00000002
#define R128_CCE_VC_FRMT_DIFFUSE_A 0x00000004
#define R128_CCE_VC_FRMT_DIFFUSE_ARGB 0x00000008
#define R128_CCE_VC_FRMT_SPEC_BGR 0x00000010
#define R128_CCE_VC_FRMT_SPEC_F 0x00000020
#define R128_CCE_VC_FRMT_SPEC_FRGB 0x00000040
#define R128_CCE_VC_FRMT_S_T 0x00000080
#define R128_CCE_VC_FRMT_S2_T2 0x00000100
#define R128_CCE_VC_FRMT_RHW2 0x00000200
 
#define R128_CCE_VC_CNTL_PRIM_TYPE_NONE 0x00000000
#define R128_CCE_VC_CNTL_PRIM_TYPE_POINT 0x00000001
#define R128_CCE_VC_CNTL_PRIM_TYPE_LINE 0x00000002
#define R128_CCE_VC_CNTL_PRIM_TYPE_POLY_LINE 0x00000003
#define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_LIST 0x00000004
#define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_FAN 0x00000005
#define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_STRIP 0x00000006
#define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_TYPE2 0x00000007
#define R128_CCE_VC_CNTL_PRIM_WALK_IND 0x00000010
#define R128_CCE_VC_CNTL_PRIM_WALK_LIST 0x00000020
#define R128_CCE_VC_CNTL_PRIM_WALK_RING 0x00000030
#define R128_CCE_VC_CNTL_NUM_SHIFT 16
 
#define RADEON_DAC_CNTL2 0x007c
#define RADEON_CRTC_MORE_CNTL 0x027c
#define RADEON_DAC_EXT_CNTL 0x0280
#define RADEON_GRPH_BUF_CNTL 0x02f0
#define RADEON_VGA_BUF_CNTL 0x02f4
 
#define RADEON_SURFACE_CNTL 0x0b00
 
#define RADEON_VCLK_SRC_SEL_MASK 0x0003
#define RADEON_VCLK_SRC_SEL_CPUCLK 0x0000
#define RADEON_VCLK_SRC_SEL_PPLLCLK 0x0003
 
#define RADEON_BUS_READ_BURST (1<<30)
#define RADEON_BUS_RD_DISCARD_EN (1<<24)
 
#define RADEON_SURF_TRANSLATION_DIS (1<<8)
#endif
/shark/tags/rel_0_5/drivers/svga/r128io.h
0,0 → 1,115
#include "libvga.h"
#include <stdio.h>
 
static int __svgalib_r128_inmisc(void)
{
return 0;
}
 
static void __svgalib_r128_outmisc(int i)
{
}
 
static int __svgalib_r128_incrtc(int i)
{
return 0;
}
 
static void __svgalib_r128_outcrtc(int i, int d)
{
}
 
static int __svgalib_r128_inseq(int index)
{
return 0;
}
 
static void __svgalib_r128_outseq(int index, int val)
{
}
 
static int __svgalib_r128_ingra(int index)
{
return 0;
}
 
static void __svgalib_r128_outgra(int index, int val)
{
}
 
static int __svgalib_r128_inis1(void)
{
return 0;
}
 
static int __svgalib_r128_inatt(int index)
{
return 0;
}
 
static void __svgalib_r128_outatt(int index, int val)
{
}
 
static void __svgalib_r128_attscreen(int i)
{
}
 
static void __svgalib_r128_inpal(int i, int *r, int *g, int *b)
{
volatile int rgb;
if(chiptype==Radeon) {
OUTREG(R128_PALETTE_INDEX, i );
rgb=INREG(R128_PALETTE_DATA);
*r=(rgb>>16) & 0xff;
*g=(rgb>>8) & 0xff;
*b=rgb & 0xff;
if(dac6bits) {
*r>>=2;
*g>>=2;
*b>>=2;
}
} else {
OUTREG(R128_PALETTE_INDEX, i<<16 );
rgb=INREG(R128_PALETTE_DATA);
*r=(rgb>>16) & 0xff;
*g=(rgb>>8) & 0xff;
*b=rgb & 0xff;
}
}
 
static void __svgalib_r128_outpal(int i, int r, int g, int b)
{
OUTREG(R128_PALETTE_INDEX, i );
if((chiptype==Radeon) && dac6bits) {
r<<=2;
g<<=2;
b<<=2;
}
OUTREG(R128_PALETTE_DATA, b | (g<<8) | (r<<16) );
}
 
static void r128_mapio(void)
{
#ifndef __PPC
if(__svgalib_secondary) {
#endif
__svgalib_inmisc=__svgalib_r128_inmisc;
__svgalib_outmisc=__svgalib_r128_outmisc;
__svgalib_incrtc=__svgalib_r128_incrtc;
__svgalib_outcrtc=__svgalib_r128_outcrtc;
__svgalib_inseq=__svgalib_r128_inseq;
__svgalib_outseq=__svgalib_r128_outseq;
__svgalib_ingra=__svgalib_r128_ingra;
__svgalib_outgra=__svgalib_r128_outgra;
__svgalib_inatt=__svgalib_r128_inatt;
__svgalib_outatt=__svgalib_r128_outatt;
__svgalib_attscreen=__svgalib_r128_attscreen;
__svgalib_inis1=__svgalib_r128_inis1;
#ifndef __PPC
}
#endif
__svgalib_inpal=__svgalib_r128_inpal;
__svgalib_outpal=__svgalib_r128_outpal;
}
 
/shark/tags/rel_0_5/drivers/svga/r128.c
0,0 → 1,1436
/*
Rage 128 chipset driver
*/
 
#include <stdlib.h>
//#include <stdio.h>
#include <string.h>
#include <unistd.h>
//#include <sys/mman.h>
#include <errno.h>
#include "vga.h"
#include "libvga.h"
#include "driver.h"
#include "timing.h"
#include "vgaregs.h"
#include "interface.h"
#include "vgapci.h"
#include "endianess.h"
#include "r128_reg.h"
 
#include <kernel/log.h>
 
static enum { Rage128=0, Radeon } chiptype; /* r128io needs to know */
static int dac6bits;
#include "r128io.h"
 
#ifdef __PPC
#define NO_BIOS
#else
#undef NO_BIOS
#endif
 
typedef int Bool;
 
static int r128_ramtype;
static int BusCntl, CRTOnly, HasPanelRegs;
 
typedef struct {
uint16_t reference_freq;
uint16_t reference_div;
uint32_t min_pll_freq;
uint32_t max_pll_freq;
uint16_t xclk;
} R128PLLRec, *R128PLLPtr;
 
typedef struct {
/* Common registers */
uint32_t ovr_clr;
uint32_t ovr_wid_left_right;
uint32_t ovr_wid_top_bottom;
uint32_t ov0_scale_cntl;
uint32_t mpp_tb_config;
uint32_t mpp_gp_config;
uint32_t subpic_cntl;
uint32_t viph_control;
uint32_t i2c_cntl_1;
uint32_t gen_int_cntl;
uint32_t cap0_trig_cntl;
uint32_t cap1_trig_cntl;
uint32_t bus_cntl;
uint32_t bus_cntl1;
uint32_t mem_cntl;
uint32_t config_cntl;
uint32_t mem_vga_wp_sel;
uint32_t mem_vga_rp_sel;
uint32_t surface_cntl;
uint32_t dac_cntl2;
uint32_t crtc_more_cntl;
uint32_t dac_ext_cntl;
uint32_t grph_buf_cntl;
uint32_t vga_buf_cntl;
 
/* Other registers to save for VT switches */
uint32_t dp_datatype;
uint32_t gen_reset_cntl;
uint32_t clock_cntl_index;
uint32_t amcgpio_en_reg;
uint32_t amcgpio_mask;
/* CRTC registers */
uint32_t crtc_gen_cntl;
uint32_t crtc_ext_cntl;
uint32_t dac_cntl;
uint32_t crtc_h_total_disp;
uint32_t crtc_h_sync_strt_wid;
uint32_t crtc_v_total_disp;
uint32_t crtc_v_sync_strt_wid;
uint32_t crtc_offset;
uint32_t crtc_offset_cntl;
uint32_t crtc_pitch;
/* CRTC2 registers */
uint32_t crtc2_gen_cntl;
/* Flat panel registers */
uint32_t fp_crtc_h_total_disp;
uint32_t fp_crtc_v_total_disp;
uint32_t fp_gen_cntl;
uint32_t fp_h_sync_strt_wid;
uint32_t fp_horz_stretch;
uint32_t fp_panel_cntl;
uint32_t fp_v_sync_strt_wid;
uint32_t fp_vert_stretch;
uint32_t lvds_gen_cntl;
uint32_t tmds_crc;
/* Computed values for PLL */
uint32_t dot_clock_freq;
uint32_t pll_output_freq;
int feedback_div;
int post_div;
/* PLL registers */
uint32_t ppll_ref_div;
uint32_t ppll_div_3;
uint32_t htotal_cntl;
/* DDA register */
uint32_t dda_config;
uint32_t dda_on_off;
uint32_t vga_dda_config;
uint32_t vga_dda_on_off;
/* Pallet */
Bool palette_valid;
uint32_t palette[256];
} R128SaveRec, *R128SavePtr;
 
typedef struct { /* All values in XCLKS */
int ML; /* Memory Read Latency */
int MB; /* Memory Burst Length */
int Trcd; /* RAS to CAS delay */
int Trp; /* RAS percentage */
int Twr; /* Write Recovery */
int CL; /* CAS Latency */
int Tr2w; /* Read to Write Delay */
int Rloop; /* Loop Latency */
int Rloop_fudge; /* Add to ML to get Rloop */
char *name;
} R128RAMRec, *R128RAMPtr;
 
#define R128_TOTAL_REGS (VGA_TOTAL_REGS + sizeof(R128SaveRec))
static int R128MinBits(int val)
{
int bits;
 
if (!val) return 1;
for (bits = 0; val; val >>= 1, ++bits);
return bits;
}
static int R128Div(int n, int d)
{
return (n + (d / 2)) / d;
}
static R128PLLRec pll;
 
static R128RAMRec ram[] = { /* Memory Specifications
From RAGE 128 Software Development
Manual (Technical Reference Manual P/N
SDK-G04000 Rev 0.01), page 3-21. */
{ 4, 4, 3, 3, 1, 3, 1, 16, 12, "128-bit SDR SGRAM 1:1" },
{ 4, 8, 3, 3, 1, 3, 1, 17, 13, "64-bit SDR SGRAM 1:1" },
{ 4, 4, 1, 2, 1, 2, 1, 16, 12, "64-bit SDR SGRAM 2:1" },
{ 4, 4, 3, 3, 2, 3, 1, 16, 12, "64-bit DDR SGRAM" },
};
 
static unsigned R128INPLL(int addr)
{
OUTREG8(R128_CLOCK_CNTL_INDEX, addr & 0x1f);
return INREG(R128_CLOCK_CNTL_DATA);
}
 
static void R128WaitForVerticalSync(void)
{
volatile int i;
 
OUTREG(R128_GEN_INT_STATUS, R128_VSYNC_INT_AK);
for (i = 0; i < R128_TIMEOUT; i++) {
if (INREG(R128_GEN_INT_STATUS) & R128_VSYNC_INT) break;
}
}
 
/* Blank screen. */
static void R128Blank(void)
{
OUTREGP(R128_CRTC_EXT_CNTL, R128_CRTC_DISPLAY_DIS, ~R128_CRTC_DISPLAY_DIS);
}
 
/* Unblank screen. */
static void R128Unblank(void)
{
OUTREGP(R128_CRTC_EXT_CNTL, 0, ~R128_CRTC_DISPLAY_DIS);
}
 
static void R128RestoreCommonRegisters(R128SavePtr restore)
{
OUTREG(R128_OVR_CLR, restore->ovr_clr);
OUTREG(R128_OVR_WID_LEFT_RIGHT, restore->ovr_wid_left_right);
OUTREG(R128_OVR_WID_TOP_BOTTOM, restore->ovr_wid_top_bottom);
OUTREG(R128_OV0_SCALE_CNTL, restore->ov0_scale_cntl);
OUTREG(R128_MPP_TB_CONFIG, restore->mpp_tb_config );
OUTREG(R128_MPP_GP_CONFIG, restore->mpp_gp_config );
OUTREG(R128_SUBPIC_CNTL, restore->subpic_cntl);
OUTREG(R128_VIPH_CONTROL, restore->viph_control);
OUTREG(R128_I2C_CNTL_1, restore->i2c_cntl_1);
OUTREG(R128_GEN_INT_CNTL, restore->gen_int_cntl);
OUTREG(R128_CAP0_TRIG_CNTL, restore->cap0_trig_cntl);
OUTREG(R128_CAP1_TRIG_CNTL, restore->cap1_trig_cntl);
OUTREG(R128_BUS_CNTL, restore->bus_cntl);
OUTREG(R128_BUS_CNTL1, restore->bus_cntl1);
OUTREG(R128_CONFIG_CNTL, restore->config_cntl);
OUTREG(R128_MEM_VGA_WP_SEL, restore->mem_vga_wp_sel);
OUTREG(R128_MEM_VGA_RP_SEL, restore->mem_vga_rp_sel);
 
if(chiptype == Rage128) {
OUTREG(RADEON_SURFACE_CNTL, restore->surface_cntl);
OUTREG(RADEON_DAC_CNTL2, restore->dac_cntl2);
OUTREG(RADEON_CRTC_MORE_CNTL,restore->crtc_more_cntl);
OUTREG(RADEON_DAC_EXT_CNTL, restore->dac_ext_cntl);
OUTREG(RADEON_GRPH_BUF_CNTL, restore->grph_buf_cntl);
OUTREG(RADEON_VGA_BUF_CNTL, restore->vga_buf_cntl);
}
 
}
 
/* Write CRTC registers. */
static void R128RestoreCrtcRegisters(R128SavePtr restore)
{
OUTREG(R128_CRTC_GEN_CNTL, restore->crtc_gen_cntl);
 
OUTREGP(R128_CRTC_EXT_CNTL, restore->crtc_ext_cntl,
R128_CRTC_VSYNC_DIS | R128_CRTC_HSYNC_DIS | R128_CRTC_DISPLAY_DIS);
 
OUTREGP(R128_DAC_CNTL, restore->dac_cntl,
R128_DAC_RANGE_CNTL | R128_DAC_BLANKING);
 
OUTREG(R128_CRTC_H_TOTAL_DISP, restore->crtc_h_total_disp);
OUTREG(R128_CRTC_H_SYNC_STRT_WID, restore->crtc_h_sync_strt_wid);
OUTREG(R128_CRTC_V_TOTAL_DISP, restore->crtc_v_total_disp);
OUTREG(R128_CRTC_V_SYNC_STRT_WID, restore->crtc_v_sync_strt_wid);
OUTREG(R128_CRTC_OFFSET, restore->crtc_offset);
OUTREG(R128_CRTC_OFFSET_CNTL, restore->crtc_offset_cntl);
OUTREG(R128_CRTC_PITCH, restore->crtc_pitch);
}
 
/* Write flat panel registers */
#if 0
static void R128RestoreFPRegisters(R128SavePtr restore)
{
uint32_t tmp;
 
OUTREG(R128_CRTC2_GEN_CNTL, restore->crtc2_gen_cntl);
OUTREG(R128_FP_CRTC_H_TOTAL_DISP, restore->fp_crtc_h_total_disp);
OUTREG(R128_FP_CRTC_V_TOTAL_DISP, restore->fp_crtc_v_total_disp);
OUTREG(R128_FP_GEN_CNTL, restore->fp_gen_cntl);
OUTREG(R128_FP_H_SYNC_STRT_WID, restore->fp_h_sync_strt_wid);
OUTREG(R128_FP_HORZ_STRETCH, restore->fp_horz_stretch);
OUTREG(R128_FP_PANEL_CNTL, restore->fp_panel_cntl);
OUTREG(R128_FP_V_SYNC_STRT_WID, restore->fp_v_sync_strt_wid);
OUTREG(R128_FP_VERT_STRETCH, restore->fp_vert_stretch);
OUTREG(R128_TMDS_CRC, restore->tmds_crc);
 
tmp = INREG(R128_LVDS_GEN_CNTL);
if ((tmp & (R128_LVDS_ON | R128_LVDS_BLON)) ==
(restore->lvds_gen_cntl & (R128_LVDS_ON | R128_LVDS_BLON))) {
OUTREG(R128_LVDS_GEN_CNTL, restore->lvds_gen_cntl);
} else {
if (restore->lvds_gen_cntl & (R128_LVDS_ON | R128_LVDS_BLON)) {
OUTREG(R128_LVDS_GEN_CNTL, restore->lvds_gen_cntl & ~R128_LVDS_BLON);
// usleep(R128PTR(pScrn)->PanelPwrDly * 1000);
OUTREG(R128_LVDS_GEN_CNTL, restore->lvds_gen_cntl);
} else {
OUTREG(R128_LVDS_GEN_CNTL, restore->lvds_gen_cntl | R128_LVDS_BLON);
// usleep(R128PTR(pScrn)->PanelPwrDly * 1000);
OUTREG(R128_LVDS_GEN_CNTL, restore->lvds_gen_cntl);
}
}
}
#endif
static void R128PLLWaitForReadUpdateComplete(void)
{
while (INPLL(R128_PPLL_REF_DIV) & R128_PPLL_ATOMIC_UPDATE_R);
}
 
static void R128PLLWriteUpdate(void)
{
OUTPLLP(R128_PPLL_REF_DIV, R128_PPLL_ATOMIC_UPDATE_W, 0xffff);
}
 
/* Write PLL registers. */
static void RADEONRestorePLLRegisters(R128SavePtr restore)
{
OUTPLLP(R128_VCLK_ECP_CNTL,
RADEON_VCLK_SRC_SEL_CPUCLK,
~(RADEON_VCLK_SRC_SEL_MASK));
 
OUTPLLP(R128_PPLL_CNTL,
R128_PPLL_RESET
| R128_PPLL_ATOMIC_UPDATE_EN
| R128_PPLL_VGA_ATOMIC_UPDATE_EN,
~(R128_PPLL_RESET
| R128_PPLL_ATOMIC_UPDATE_EN
| R128_PPLL_VGA_ATOMIC_UPDATE_EN));
 
OUTREGP(R128_CLOCK_CNTL_INDEX,
R128_PLL_DIV_SEL,
~(R128_PLL_DIV_SEL));
 
OUTPLLP(R128_PPLL_REF_DIV,
restore->ppll_ref_div,
~R128_PPLL_REF_DIV_MASK);
 
OUTPLLP(R128_PPLL_DIV_3,
restore->ppll_div_3,
~R128_PPLL_FB3_DIV_MASK);
 
OUTPLLP(R128_PPLL_DIV_3,
restore->ppll_div_3,
~R128_PPLL_POST3_DIV_MASK);
 
R128PLLWriteUpdate();
R128PLLWaitForReadUpdateComplete();
 
OUTPLL(R128_HTOTAL_CNTL, restore->htotal_cntl);
 
OUTPLLP(R128_PPLL_CNTL,
0,
~(R128_PPLL_RESET
| R128_PPLL_SLEEP
| R128_PPLL_ATOMIC_UPDATE_EN
| R128_PPLL_VGA_ATOMIC_UPDATE_EN));
 
sleep(1); /* Let the clock to lock */
 
OUTPLLP(R128_VCLK_ECP_CNTL,
RADEON_VCLK_SRC_SEL_PPLLCLK,
~(RADEON_VCLK_SRC_SEL_MASK));
}
 
static void R128RestorePLLRegisters(R128SavePtr restore)
{
OUTREGP(R128_CLOCK_CNTL_INDEX, R128_PLL_DIV_SEL, 0xffff);
 
OUTPLLP(
R128_PPLL_CNTL,
R128_PPLL_RESET
| R128_PPLL_ATOMIC_UPDATE_EN,
0xffff);
 
R128PLLWaitForReadUpdateComplete();
OUTPLLP(R128_PPLL_REF_DIV,
restore->ppll_ref_div, ~R128_PPLL_REF_DIV_MASK);
R128PLLWriteUpdate();
 
R128PLLWaitForReadUpdateComplete();
OUTPLLP(R128_PPLL_DIV_3,
restore->ppll_div_3, ~R128_PPLL_FB3_DIV_MASK);
R128PLLWriteUpdate();
OUTPLLP(R128_PPLL_DIV_3,
restore->ppll_div_3, ~R128_PPLL_POST3_DIV_MASK);
R128PLLWriteUpdate();
 
R128PLLWaitForReadUpdateComplete();
OUTPLL(R128_HTOTAL_CNTL, restore->htotal_cntl);
R128PLLWriteUpdate();
 
OUTPLLP( R128_PPLL_CNTL, 0, ~R128_PPLL_RESET);
 
}
 
/* Write DDA registers. */
static void R128RestoreDDARegisters(R128SavePtr restore)
{
OUTREG(R128_DDA_CONFIG, restore->dda_config);
OUTREG(R128_DDA_ON_OFF, restore->dda_on_off);
// OUTREG(R128_VGA_DDA_CONFIG, restore->vga_dda_config);
// OUTREG(R128_VGA_DDA_ON_OFF, restore->vga_dda_on_off);
}
 
/* Write palette data. */
static void R128RestorePalette( R128SavePtr restore)
{
int i;
 
if (!restore->palette_valid) return;
 
/* Select palette 0 (main CRTC) if using FP-enabled chip */
// if (info->HasPanelRegs) PAL_SELECT(0);
 
OUTPAL_START(0);
for (i = 0; i < 256; i++) OUTPAL_NEXT_uint32_t(restore->palette[i]);
}
 
/* Write out state to define a new video mode. */
static void R128RestoreMode(R128SavePtr restore)
{
R128Blank();
 
OUTREG(R128_AMCGPIO_MASK, restore->amcgpio_mask);
OUTREG(R128_AMCGPIO_EN_REG, restore->amcgpio_en_reg);
OUTREG(R128_CLOCK_CNTL_INDEX, restore->clock_cntl_index);
#if 0 /* works without, and it causes problems with it */
OUTREG(R128_GEN_RESET_CNTL, restore->gen_reset_cntl);
#endif
OUTREG(R128_DP_DATATYPE, restore->dp_datatype);
 
R128RestoreCommonRegisters( restore);
R128RestoreCrtcRegisters( restore);
// if (info->HasPanelRegs)
// R128RestoreFPRegisters(restore);
// if (!info->HasPanelRegs || info->CRTOnly)
switch(chiptype) {
case Rage128:
R128RestorePLLRegisters(restore);
break;
case Radeon:
RADEONRestorePLLRegisters(restore);
break;
}
if(chiptype == Rage128) {
R128RestoreDDARegisters(restore);
}
R128RestorePalette(restore);
}
 
/* Read common registers. */
static void R128SaveCommonRegisters(R128SavePtr save)
{
save->ovr_clr = INREG(R128_OVR_CLR);
save->ovr_wid_left_right = INREG(R128_OVR_WID_LEFT_RIGHT);
save->ovr_wid_top_bottom = INREG(R128_OVR_WID_TOP_BOTTOM);
save->ov0_scale_cntl = INREG(R128_OV0_SCALE_CNTL);
save->mpp_tb_config = INREG(R128_MPP_TB_CONFIG);
save->mpp_gp_config = INREG(R128_MPP_GP_CONFIG);
save->subpic_cntl = INREG(R128_SUBPIC_CNTL);
save->viph_control = INREG(R128_VIPH_CONTROL);
save->i2c_cntl_1 = INREG(R128_I2C_CNTL_1);
save->gen_int_cntl = INREG(R128_GEN_INT_CNTL);
save->cap0_trig_cntl = INREG(R128_CAP0_TRIG_CNTL);
save->cap1_trig_cntl = INREG(R128_CAP1_TRIG_CNTL);
save->bus_cntl = INREG(R128_BUS_CNTL);
save->bus_cntl1 = INREG(R128_BUS_CNTL1);
save->mem_cntl = INREG(R128_MEM_CNTL);
save->config_cntl = INREG(R128_CONFIG_CNTL);
save->mem_vga_wp_sel = INREG(R128_MEM_VGA_WP_SEL);
save->mem_vga_rp_sel = INREG(R128_MEM_VGA_RP_SEL);
 
if(chiptype==Radeon) {
save->surface_cntl = INREG(RADEON_SURFACE_CNTL);
save->dac_cntl2 = INREG(RADEON_DAC_CNTL2);
save->crtc_more_cntl = INREG(RADEON_CRTC_MORE_CNTL);
save->dac_ext_cntl = INREG(RADEON_DAC_EXT_CNTL);
save->grph_buf_cntl = INREG(RADEON_GRPH_BUF_CNTL);
save->vga_buf_cntl = INREG(RADEON_VGA_BUF_CNTL);
}
}
 
/* Read CRTC registers. */
static void R128SaveCrtcRegisters(R128SavePtr save)
{
save->crtc_gen_cntl = INREG(R128_CRTC_GEN_CNTL);
save->crtc_ext_cntl = INREG(R128_CRTC_EXT_CNTL);
save->dac_cntl = INREG(R128_DAC_CNTL);
save->crtc_h_total_disp = INREG(R128_CRTC_H_TOTAL_DISP);
save->crtc_h_sync_strt_wid = INREG(R128_CRTC_H_SYNC_STRT_WID);
save->crtc_v_total_disp = INREG(R128_CRTC_V_TOTAL_DISP);
save->crtc_v_sync_strt_wid = INREG(R128_CRTC_V_SYNC_STRT_WID);
save->crtc_offset = INREG(R128_CRTC_OFFSET);
save->crtc_offset_cntl = INREG(R128_CRTC_OFFSET_CNTL);
save->crtc_pitch = INREG(R128_CRTC_PITCH);
}
 
#if 0
/* Read flat panel registers */
static void R128SaveFPRegisters(R128SavePtr save)
{
save->crtc2_gen_cntl = INREG(R128_CRTC2_GEN_CNTL);
save->fp_crtc_h_total_disp = INREG(R128_FP_CRTC_H_TOTAL_DISP);
save->fp_crtc_v_total_disp = INREG(R128_FP_CRTC_V_TOTAL_DISP);
save->fp_gen_cntl = INREG(R128_FP_GEN_CNTL);
save->fp_h_sync_strt_wid = INREG(R128_FP_H_SYNC_STRT_WID);
save->fp_horz_stretch = INREG(R128_FP_HORZ_STRETCH);
save->fp_panel_cntl = INREG(R128_FP_PANEL_CNTL);
save->fp_v_sync_strt_wid = INREG(R128_FP_V_SYNC_STRT_WID);
save->fp_vert_stretch = INREG(R128_FP_VERT_STRETCH);
save->lvds_gen_cntl = INREG(R128_LVDS_GEN_CNTL);
save->tmds_crc = INREG(R128_TMDS_CRC);
}
#endif
 
/* Read PLL registers. */
static void R128SavePLLRegisters(R128SavePtr save)
{
save->ppll_ref_div = INPLL(R128_PPLL_REF_DIV);
save->ppll_div_3 = INPLL(R128_PPLL_DIV_3);
save->htotal_cntl = INPLL(R128_HTOTAL_CNTL);
}
 
/* Read DDA registers. */
static void R128SaveDDARegisters(R128SavePtr save)
{
save->dda_config = INREG(R128_DDA_CONFIG);
save->dda_on_off = INREG(R128_DDA_ON_OFF);
save->vga_dda_config = INREG(R128_VGA_DDA_CONFIG);
save->vga_dda_on_off = INREG(R128_VGA_DDA_ON_OFF);
}
 
/* Read palette data. */
static void R128SavePalette(R128SavePtr save)
{
int i;
 
/* Select palette 0 (main CRTC) if using FP-enabled chip */
// if (info->HasPanelRegs) PAL_SELECT(0);
 
INPAL_START(0);
for (i = 0; i < 256; i++) save->palette[i] = INPAL_NEXT();
save->palette_valid = 1;
}
 
/* Save state that defines current video mode. */
static void R128SaveMode(R128SavePtr save)
{
R128SaveCommonRegisters(save);
R128SaveCrtcRegisters(save);
// if (R128PTR(pScrn)->HasPanelRegs)
// R128SaveFPRegisters(save);
R128SavePLLRegisters(save);
if(chiptype == Rage128)
R128SaveDDARegisters(save);
R128SavePalette(save);
 
save->dp_datatype = INREG(R128_DP_DATATYPE);
save->gen_reset_cntl = INREG(R128_GEN_RESET_CNTL);
save->clock_cntl_index = INREG(R128_CLOCK_CNTL_INDEX);
save->amcgpio_en_reg = INREG(R128_AMCGPIO_EN_REG);
save->amcgpio_mask = INREG(R128_AMCGPIO_MASK);
}
 
static void R128InitCommonRegisters(R128SavePtr save)
{
save->ovr_clr = 0;
save->ovr_wid_left_right = 0;
save->ovr_wid_top_bottom = 0;
save->ov0_scale_cntl = 0;
save->mpp_tb_config = 0;
save->mpp_gp_config = 0;
save->subpic_cntl = 0;
save->viph_control = 0;
save->i2c_cntl_1 = 0;
save->gen_int_cntl = 0;
save->cap0_trig_cntl = 0;
save->cap1_trig_cntl = 0;
save->mem_vga_wp_sel = 0;
save->mem_vga_rp_sel = 0;
save->config_cntl = INREG(R128_CONFIG_CNTL);
save->bus_cntl = BusCntl;
save->bus_cntl1 = INREG(R128_BUS_CNTL1);
if(chiptype == Radeon) {
if(save->bus_cntl & RADEON_BUS_READ_BURST)
save->bus_cntl |=RADEON_BUS_RD_DISCARD_EN;
}
 
save->amcgpio_en_reg = INREG(R128_AMCGPIO_EN_REG);
save->amcgpio_mask = INREG(R128_AMCGPIO_MASK);
 
/*
* If bursts are enabled, turn on discards and aborts
*/
if (save->bus_cntl & (R128_BUS_WRT_BURST|R128_BUS_READ_BURST))
save->bus_cntl |= R128_BUS_RD_DISCARD_EN | R128_BUS_RD_ABORT_EN;
}
 
/* Define CRTC registers for requested video mode. */
static Bool R128InitCrtcRegisters(R128SavePtr save,
ModeTiming *mode, ModeInfo *info)
{
int format;
int hsync_start;
int hsync_wid;
int hsync_fudge;
int vsync_wid;
int bytpp;
int hsync_fudge_default[] = { 0x00, 0x12, 0x09, 0x09, 0x06, 0x05 };
int hsync_fudge_fp[] = { 0x12, 0x11, 0x09, 0x09, 0x05, 0x05 };
int hsync_fudge_fp_crt[] = { 0x12, 0x10, 0x08, 0x08, 0x04, 0x04 };
 
dac6bits=0;
 
switch (info->bitsPerPixel) {
case 4: format = 1; bytpp = 0; dac6bits = 1; break;
case 8: format = 2; bytpp = 1; dac6bits = 1; break;
case 16:
if(info->greenWeight==5)
format = 3; else format = 4;
bytpp = 2;
break;
case 24: format = 5; bytpp = 3; break; /* RGB */
case 32: format = 6; bytpp = 4; break; /* xRGB */
default:
return 0;
}
if (HasPanelRegs)
if (CRTOnly) hsync_fudge = hsync_fudge_fp_crt[format-1];
else hsync_fudge = hsync_fudge_fp[format-1];
else
hsync_fudge = hsync_fudge_default[format-1];
 
save->crtc_gen_cntl = (R128_CRTC_EXT_DISP_EN
| R128_CRTC_EN
| (format << 8)
| ((mode->flags & DOUBLESCAN)
? R128_CRTC_DBL_SCAN_EN
: 0)
| ((mode->flags & INTERLACED)
? R128_CRTC_INTERLACE_EN
: 0));
 
save->crtc_ext_cntl = R128_VGA_ATI_LINEAR | R128_XCRT_CNT_EN | R128_VGA_MEM_PS_EN;
if(chiptype == Radeon) save->crtc_ext_cntl |= R128_CRTC_CRT_ON;
save->dac_cntl = (R128_DAC_MASK_ALL
| R128_DAC_VGA_ADR_EN
| (dac6bits ? 0 : R128_DAC_8BIT_EN));
 
save->crtc_h_total_disp = ((((mode->CrtcHTotal / 8) - 1) & 0xffff)
| (((mode->CrtcHDisplay / 8) - 1) << 16));
 
hsync_wid = (mode->CrtcHSyncEnd - mode->CrtcHSyncStart) / 8;
if (!hsync_wid) hsync_wid = 1;
if (hsync_wid > 0x3f) hsync_wid = 0x3f;
 
hsync_start = mode->CrtcHSyncStart - 8 + hsync_fudge;
 
save->crtc_h_sync_strt_wid = ((hsync_start & 0xfff)
| (hsync_wid << 16)
| ((mode->flags & NHSYNC)
? R128_CRTC_H_SYNC_POL
: 0));
 
#if 1
/* This works for double scan mode. */
save->crtc_v_total_disp = (((mode->CrtcVTotal - 1) & 0xffff)
| ((mode->CrtcVDisplay - 1) << 16));
#else
/* This is what cce/nbmode.c example code
does -- is this correct? */
save->crtc_v_total_disp = (((mode->CrtcVTotal - 1) & 0xffff)
| ((mode->CrtcVDisplay
* ((mode->Flags & DOUBLESCAN) ? 2 : 1) - 1)
<< 16));
#endif
 
vsync_wid = mode->CrtcVSyncEnd - mode->CrtcVSyncStart;
if (!vsync_wid) vsync_wid = 1;
if (vsync_wid > 0x1f) vsync_wid = 0x1f;
 
save->crtc_v_sync_strt_wid = (((mode->CrtcVSyncStart - 1) & 0xfff)
| (vsync_wid << 16)
| ((mode->flags & NVSYNC)
? R128_CRTC_V_SYNC_POL
: 0));
save->crtc_offset = 0;
save->crtc_offset_cntl = 0;
save->crtc_pitch = info->width / 8;
 
save->config_cntl |= R128_CFG_VGA_RAM_EN;
if(chiptype == Radeon) {
save->crtc_pitch |= save->crtc_pitch<<16;
save->surface_cntl = RADEON_SURF_TRANSLATION_DIS;
 
save->dac_cntl2 = INREG(RADEON_DAC_CNTL2);
save->crtc_more_cntl = INREG(RADEON_CRTC_MORE_CNTL);
save->dac_ext_cntl = INREG(RADEON_DAC_EXT_CNTL);
save->grph_buf_cntl = INREG(RADEON_GRPH_BUF_CNTL);
save->vga_buf_cntl = INREG(RADEON_VGA_BUF_CNTL);
 
}
 
#ifdef __PPC
/* Change the endianness of the aperture */
switch (info->bitsPerPixel) {
case 15:
case 16: save->config_cntl |= APER_0_BIG_ENDIAN_16BPP_SWAP; break;
case 32: save->config_cntl |= APER_0_BIG_ENDIAN_32BPP_SWAP; break;
default: break;
}
#endif
 
return 1;
}
 
#if 0
/* Define CRTC registers for requested video mode. */
static void R128InitFPRegisters(R128SavePtr orig, R128SavePtr save,
ModeTiming *mode, ModeInfo *info)
{
#if 0
int xres = mode->CrtcHDisplay;
int yres = mode->CrtcVDisplay;
float Hratio, Vratio;
 
if (CRTOnly) {
save->crtc_ext_cntl |= R128_CRTC_CRT_ON;
save->crtc2_gen_cntl = 0;
save->fp_gen_cntl = orig->fp_gen_cntl;
save->fp_gen_cntl &= ~(R128_FP_FPON |
R128_FP_CRTC_USE_SHADOW_VEND |
R128_FP_CRTC_HORZ_DIV2_EN |
R128_FP_CRTC_HOR_CRT_DIV2_DIS |
R128_FP_USE_SHADOW_EN);
save->fp_gen_cntl |= (R128_FP_SEL_CRTC2 |
R128_FP_CRTC_DONT_SHADOW_VPAR);
save->fp_panel_cntl = orig->fp_panel_cntl & ~R128_FP_DIGON;
save->lvds_gen_cntl = orig->lvds_gen_cntl & ~(R128_LVDS_ON |
R128_LVDS_BLON);
return;
}
 
 
if (xres > info->PanelXRes) xres = info->PanelXRes;
if (yres > info->PanelYRes) yres = info->PanelYRes;
 
Hratio = (float)xres/(float)info->PanelXRes;
Vratio = (float)yres/(float)info->PanelYRes;
 
save->fp_horz_stretch =
(((((int)(Hratio * R128_HORZ_STRETCH_RATIO_MAX + 0.5))
& R128_HORZ_STRETCH_RATIO_MASK) << R128_HORZ_STRETCH_RATIO_SHIFT) |
(orig->fp_horz_stretch & (R128_HORZ_PANEL_SIZE |
R128_HORZ_FP_LOOP_STRETCH |
R128_HORZ_STRETCH_RESERVED)));
save->fp_horz_stretch &= ~R128_HORZ_AUTO_RATIO_FIX_EN;
if (Hratio == 1.0) save->fp_horz_stretch &= ~(R128_HORZ_STRETCH_BLEND |
R128_HORZ_STRETCH_ENABLE);
else save->fp_horz_stretch |= (R128_HORZ_STRETCH_BLEND |
R128_HORZ_STRETCH_ENABLE);
 
save->fp_vert_stretch =
(((((int)(Vratio * R128_VERT_STRETCH_RATIO_MAX + 0.5))
& R128_VERT_STRETCH_RATIO_MASK) << R128_VERT_STRETCH_RATIO_SHIFT) |
(orig->fp_vert_stretch & (R128_VERT_PANEL_SIZE |
R128_VERT_STRETCH_RESERVED)));
save->fp_vert_stretch &= ~R128_VERT_AUTO_RATIO_EN;
if (Vratio == 1.0) save->fp_vert_stretch &= ~(R128_VERT_STRETCH_ENABLE |
R128_VERT_STRETCH_BLEND);
else save->fp_vert_stretch |= (R128_VERT_STRETCH_ENABLE |
R128_VERT_STRETCH_BLEND);
 
save->fp_gen_cntl = (orig->fp_gen_cntl & ~(R128_FP_SEL_CRTC2 |
R128_FP_CRTC_USE_SHADOW_VEND |
R128_FP_CRTC_HORZ_DIV2_EN |
R128_FP_CRTC_HOR_CRT_DIV2_DIS |
R128_FP_USE_SHADOW_EN));
if (orig->fp_gen_cntl & R128_FP_DETECT_SENSE) {
save->fp_gen_cntl |= (R128_FP_CRTC_DONT_SHADOW_VPAR |
R128_FP_TDMS_EN);
}
 
save->fp_panel_cntl = orig->fp_panel_cntl;
save->lvds_gen_cntl = orig->lvds_gen_cntl;
 
save->tmds_crc = orig->tmds_crc;
 
/* Disable CRT output by disabling CRT output and setting the CRT
DAC to use CRTC2, which we set to 0's. In the future, we will
want to use the dual CRTC capabilities of the R128 to allow both
the flat panel and external CRT to either simultaneously display
the same image or display two different images. */
save->crtc_ext_cntl &= ~R128_CRTC_CRT_ON;
save->dac_cntl |= R128_DAC_CRT_SEL_CRTC2;
save->crtc2_gen_cntl = 0;
 
/* WARNING: Be careful about turning on the flat panel */
#if 1
save->lvds_gen_cntl |= (R128_LVDS_ON | R128_LVDS_BLON);
#else
save->fp_panel_cntl |= (R128_FP_DIGON | R128_FP_BLON);
save->fp_gen_cntl |= (R128_FP_FPON);
#endif
 
save->fp_crtc_h_total_disp = save->crtc_h_total_disp;
save->fp_crtc_v_total_disp = save->crtc_v_total_disp;
save->fp_h_sync_strt_wid = save->crtc_h_sync_strt_wid;
save->fp_v_sync_strt_wid = save->crtc_v_sync_strt_wid;
#endif
}
#endif
 
/* Define PLL registers for requested video mode. */
static void RADEONInitPLLRegisters(R128SavePtr save, R128PLLPtr pll,
double dot_clock)
{
unsigned long freq = dot_clock * 100;
struct {
int divider;
int bitvalue;
} *post_div,
post_divs[] = {
/* From RAGE 128 VR/RAGE 128 GL Register
Reference Manual (Technical Reference
Manual P/N RRG-G04100-C Rev. 0.04), page
3-17 (PLL_DIV_[3:0]). */
{ 1, 0 }, /* VCLK_SRC */
{ 2, 1 }, /* VCLK_SRC/2 */
{ 4, 2 }, /* VCLK_SRC/4 */
{ 8, 3 }, /* VCLK_SRC/8 */
 
{ 3, 4 }, /* VCLK_SRC/3 */
{ 16, 5 },
{ 6, 6 }, /* VCLK_SRC/6 */
{ 12, 7 }, /* VCLK_SRC/12 */
{ 0, 0 }
};
 
if (freq > pll->max_pll_freq) freq = pll->max_pll_freq;
if (freq * 12 < pll->min_pll_freq) freq = pll->min_pll_freq / 12;
 
for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
save->pll_output_freq = post_div->divider * freq;
if (save->pll_output_freq >= pll->min_pll_freq
&& save->pll_output_freq <= pll->max_pll_freq) break;
}
 
save->dot_clock_freq = freq;
save->feedback_div = R128Div(pll->reference_div * save->pll_output_freq,
pll->reference_freq);
save->post_div = post_div->divider;
 
save->ppll_ref_div = pll->reference_div;
save->ppll_div_3 = (save->feedback_div | (post_div->bitvalue << 16));
save->htotal_cntl = 0;
}
 
static void R128InitPLLRegisters(R128SavePtr save, R128PLLPtr pll,
double dot_clock)
{
unsigned long freq = dot_clock * 100;
struct {
int divider;
int bitvalue;
} *post_div,
post_divs[] = {
/* From RAGE 128 VR/RAGE 128 GL Register
Reference Manual (Technical Reference
Manual P/N RRG-G04100-C Rev. 0.04), page
3-17 (PLL_DIV_[3:0]). */
{ 1, 0 }, /* VCLK_SRC */
{ 2, 1 }, /* VCLK_SRC/2 */
{ 4, 2 }, /* VCLK_SRC/4 */
{ 8, 3 }, /* VCLK_SRC/8 */
 
{ 3, 4 }, /* VCLK_SRC/3 */
/* bitvalue = 5 is reserved */
{ 6, 6 }, /* VCLK_SRC/6 */
{ 12, 7 }, /* VCLK_SRC/12 */
{ 0, 0 }
};
 
if (freq > pll->max_pll_freq) freq = pll->max_pll_freq;
if (freq * 12 < pll->min_pll_freq) freq = pll->min_pll_freq / 12;
 
for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
save->pll_output_freq = post_div->divider * freq;
if (save->pll_output_freq >= pll->min_pll_freq
&& save->pll_output_freq <= pll->max_pll_freq) break;
}
 
save->dot_clock_freq = freq;
save->feedback_div = R128Div(pll->reference_div * save->pll_output_freq,
pll->reference_freq);
save->post_div = post_div->divider;
 
save->ppll_ref_div = pll->reference_div;
save->ppll_div_3 = (save->feedback_div | (post_div->bitvalue << 16));
save->htotal_cntl = 0;
}
 
/* Define DDA registers for requested video mode. */
static Bool R128InitDDARegisters(R128SavePtr save,
R128PLLPtr pll, ModeInfo *info)
{
int DisplayFifoWidth = 128;
int DisplayFifoDepth = 32;
int XclkFreq;
int VclkFreq;
int XclksPerTransfer;
int XclksPerTransferPrecise;
int UseablePrecision;
int Roff;
int Ron;
 
XclkFreq = pll->xclk;
 
VclkFreq = R128Div(pll->reference_freq * save->feedback_div,
pll->reference_div * save->post_div);
 
XclksPerTransfer = R128Div(XclkFreq * DisplayFifoWidth,
VclkFreq * (info->bytesPerPixel * 8));
 
UseablePrecision = R128MinBits(XclksPerTransfer) + 1;
 
XclksPerTransferPrecise = R128Div((XclkFreq * DisplayFifoWidth)
<< (11 - UseablePrecision),
VclkFreq * (info->bytesPerPixel * 8));
 
Roff = XclksPerTransferPrecise * (DisplayFifoDepth - 4);
 
Ron = (4 * ram[r128_ramtype].MB
+ 3 * (((ram[r128_ramtype].Trcd - 2)>0)?(ram[r128_ramtype].Trcd - 2):0)
+ 2 * ram[r128_ramtype].Trp
+ ram[r128_ramtype].Twr
+ ram[r128_ramtype].CL
+ ram[r128_ramtype].Tr2w
+ XclksPerTransfer) << (11 - UseablePrecision);
 
if (Ron + ram[r128_ramtype].Rloop >= Roff) {
return 0;
}
 
save->dda_config = (XclksPerTransferPrecise
| (UseablePrecision << 16)
| (ram[r128_ramtype].Rloop << 20));
 
save->dda_on_off = (Ron << 16) | Roff;
 
return 1;
}
 
 
/* Define initial palette for requested video mode. This doesn't do
anything for XFree86 4.0. */
static void R128InitPalette(R128SavePtr save)
{
int i;
save->palette_valid = 1;
for(i=0;i<256;i++) save->palette[i]=i | (i<<8) | (i<<16);
}
 
/* Define registers for a requested video mode. */
static Bool R128Init(ModeTiming *mode, ModeInfo *info, R128SavePtr save)
{
double dot_clock = mode->pixelClock/1000.0;
 
R128InitCommonRegisters(save);
if (!R128InitCrtcRegisters(save, mode, info)) return 0;
#if 0
if (HasPanelRegs)
R128InitFPRegisters(&info->SavedReg, save, mode, info);
#endif
switch(chiptype) {
case Rage128:
R128InitPLLRegisters(save, &pll, dot_clock);
break;
case Radeon:
RADEONInitPLLRegisters(save, &pll, dot_clock);
break;
}
if (!R128InitDDARegisters(save, &pll, info))
return 0;
// if (!info->PaletteSavedOnVT)
R128InitPalette(save);
 
return 1;
}
 
static int r128_init(int, int, int);
static void r128_unlock(void);
static void r128_lock(void);
 
static int r128_memory;
static int r128_is_linear, r128_linear_base, r128_mmio_base;
 
static CardSpecs *cardspecs;
 
static void r128_setpage(int page)
{
page*=2;
OUTREG(R128_MEM_VGA_WP_SEL, page | ((page+1)<<16));
OUTREG(R128_MEM_VGA_RP_SEL, page | ((page+1)<<16));
 
}
 
static int __svgalib_r128_inlinearmode(void)
{
return r128_is_linear;
}
 
/* Fill in chipset specific mode information */
 
static void r128_getmodeinfo(int mode, vga_modeinfo *modeinfo)
{
 
if(modeinfo->colors==16)return;
 
modeinfo->maxpixels = r128_memory*1024/modeinfo->bytesperpixel;
modeinfo->maxlogicalwidth = 4088;
modeinfo->startaddressrange = r128_memory * 1024 - 1;
modeinfo->haveblit = 0;
modeinfo->flags &= ~HAVE_RWPAGE;
modeinfo->flags |= HAVE_EXT_SET;
 
if (modeinfo->bytesperpixel >= 1) {
if(r128_linear_base)modeinfo->flags |= CAPABLE_LINEAR;
if (__svgalib_r128_inlinearmode())
modeinfo->flags |= IS_LINEAR | LINEAR_MODE;
}
}
 
/* Read and save chipset-specific registers */
 
static int r128_saveregs(unsigned char regs[])
{
r128_unlock();
R128SaveMode((R128SavePtr)(regs+VGA_TOTAL_REGS));
return R128_TOTAL_REGS - VGA_TOTAL_REGS;
}
 
/* Set chipset-specific registers */
 
static void r128_setregs(const unsigned char regs[], int mode)
{
r128_unlock();
R128RestoreMode((R128SavePtr)(regs+VGA_TOTAL_REGS));
 
R128Unblank();
}
/* Return nonzero if mode is available */
 
static int r128_modeavailable(int mode)
{
struct info *info;
ModeTiming *modetiming;
ModeInfo *modeinfo;
 
modeinfo = __svgalib_createModeInfoStructureForSvgalibMode(mode);
 
if (IS_IN_STANDARD_VGA_DRIVER(mode))
return __svgalib_vga_driverspecs.modeavailable(mode);
 
info = &__svgalib_infotable[mode];
if (r128_memory * 1024 < info->ydim * info->xbytes)
return 0;
 
modeinfo = __svgalib_createModeInfoStructureForSvgalibMode(mode);
 
modetiming = malloc(sizeof(ModeTiming));
if (__svgalib_getmodetiming(modetiming, modeinfo, cardspecs)) {
free(modetiming);
free(modeinfo);
return 0;
}
free(modetiming);
free(modeinfo);
 
return SVGADRV;
}
 
/* Local, called by r128_setmode(). */
 
static void r128_initializemode(unsigned char *moderegs,
ModeTiming * modetiming, ModeInfo * modeinfo, int mode)
{ /* long k; */
__svgalib_setup_VGA_registers(moderegs, modetiming, modeinfo);
 
R128Init(modetiming, modeinfo, (R128SavePtr)(moderegs+VGA_TOTAL_REGS));
 
return ;
}
 
 
static int r128_setmode(int mode, int prv_mode)
{
unsigned char *moderegs;
ModeTiming *modetiming;
ModeInfo *modeinfo;
 
if (IS_IN_STANDARD_VGA_DRIVER(mode)) {
return __svgalib_vga_driverspecs.setmode(mode, prv_mode);
}
if (!r128_modeavailable(mode))
return 1;
 
modeinfo = __svgalib_createModeInfoStructureForSvgalibMode(mode);
 
modetiming = malloc(sizeof(ModeTiming));
if (__svgalib_getmodetiming(modetiming, modeinfo, cardspecs)) {
free(modetiming);
free(modeinfo);
return 1;
}
 
moderegs = malloc(R128_TOTAL_REGS);
 
r128_initializemode(moderegs, modetiming, modeinfo, mode);
free(modetiming);
 
__svgalib_setregs(moderegs); /* Set standard regs. */
r128_setregs(moderegs, mode); /* Set extended regs. */
free(moderegs);
 
free(modeinfo);
return 0;
}
 
 
/* Unlock chipset-specific registers */
static void r128_unlock(void)
{
__svgalib_outcrtc(0x11, __svgalib_incrtc(0x11) & 0x7f);
}
 
static void r128_lock(void)
{
}
 
/* Indentify chipset, initialize and return non-zero if detected */
int r128_test(void)
{
return r128_init(0,0,0);
return 1;
}
 
 
/* Set display start address (not for 16 color modes) */
/* Cirrus supports any address in video memory (up to 2Mb) */
 
static void r128_setdisplaystart(int address)
{
int naddress=address >> 2;
__svgalib_outcrtc(0x0c,(naddress>>8)&0xff);
__svgalib_outcrtc(0x0d,(naddress)&0xff);
OUTREG(R128_CRTC_OFFSET, address);
}
 
/* Set logical scanline length (usually multiple of 8) */
/* Cirrus supports multiples of 8, up to 4088 */
 
static void r128_setlogicalwidth(int width)
{
int offset = width >> 3;
if(CI.bytesperpixel>1) {
offset = offset/CI.bytesperpixel;
}
__svgalib_outcrtc(0x13,offset&0xff);
OUTREG(R128_CRTC_PITCH, offset);
}
 
static int r128_linear(int op, int param)
{
if (op==LINEAR_ENABLE){r128_is_linear=1; return 0;};
if (op==LINEAR_DISABLE){r128_is_linear=0; return 0;};
if (op==LINEAR_QUERY_BASE) return r128_linear_base;
if (op == LINEAR_QUERY_RANGE || op == LINEAR_QUERY_GRANULARITY) return 0; /* No granularity or range. */
else return -1; /* Unknown function. */
}
 
static int r128_match_programmable_clock(int clock)
{
return clock ;
}
 
static int r128_map_clock(int bpp, int clock)
{
return clock ;
}
 
static int r128_map_horizontal_crtc(int bpp, int pixelclock, int htiming)
{
return htiming;
}
 
static unsigned int cur_colors[16*2];
 
static int r128_cursor( int cmd, int p1, int p2, int p3, int p4, void *p5) {
int i, j;
unsigned long *b3;
unsigned long l1, l2;
switch(cmd){
case CURSOR_INIT:
return 1;
case CURSOR_HIDE:
OUTREG(R128_CRTC_GEN_CNTL,INREG(R128_CRTC_GEN_CNTL) & ~R128_CRTC_CUR_EN );
break;
case CURSOR_SHOW:
OUTREG(R128_CRTC_GEN_CNTL,INREG(R128_CRTC_GEN_CNTL) | R128_CRTC_CUR_EN );
break;
case CURSOR_POSITION:
OUTREG(R128_CUR_HORZ_VERT_OFF, R128_CUR_LOCK | 0);
OUTREG(R128_CUR_HORZ_VERT_POSN, p2|(p1<<16));
break;
case CURSOR_SELECT:
i=r128_memory*1024-(p1+1)*4096;
OUTREG(R128_CUR_OFFSET,i);
OUTREG(R128_CUR_CLR0,cur_colors[p1*2]);
OUTREG(R128_CUR_CLR1,cur_colors[p1*2+1]);
break;
case CURSOR_IMAGE:
i=r128_memory*1024-(p1+1)*4096;
b3=(unsigned long *)p5;
switch(p2) {
case 0:
cur_colors[p1*2]=p3;
cur_colors[p1*2+1]=p4;
 
for(j=0;j<32;j++) {
l1=*(b3+j); /* source */
l2=*(b3+32+j); /* mask */
l1=BE32(l1);
l2=BE32(l2);
*(unsigned long *)(LINEAR_POINTER+i+16*j)=~l2;
*(unsigned long *)(LINEAR_POINTER+i+16*j+4)=0xffffffff;
*(unsigned long *)(LINEAR_POINTER+i+16*j+8)=l1&l2;
*(unsigned long *)(LINEAR_POINTER+i+16*j+12)=0;
*(unsigned long *)(LINEAR_POINTER+i+512+16*j)=0xffffffff;
*(unsigned long *)(LINEAR_POINTER+i+512+16*j+4)=0xffffffff;
*(unsigned long *)(LINEAR_POINTER+i+512+16*j+8)=0;
*(unsigned long *)(LINEAR_POINTER+i+512+16*j+12)=0;
}
break;
}
break;
}
return 0;
}
 
static Emulation r128_emul =
{
0,
0,
0,
0,
0,
0,
0, /* screenoff */
0, /* screenon */
R128WaitForVerticalSync, /* waitretrace */
};
 
static int r128_ext_set( unsigned what, va_list params )
{
int param2;
param2 = va_arg(params, int);
 
switch (what) {
case VGA_EXT_AVAILABLE:
switch (param2) {
case VGA_AVAIL_SET:
return VGA_EXT_AVAILABLE | VGA_EXT_SET | VGA_EXT_CLEAR | VGA_EXT_RESET;
case VGA_AVAIL_ACCEL:
return 0;
case VGA_AVAIL_FLAGS:
return VGA_CLUT8;
}
break;
case VGA_EXT_SET:
if (param2 & VGA_CLUT8) OUTREGP( R128_DAC_CNTL, R128_DAC_8BIT_EN, R128_DAC_MASK_ALL );
return 1;
break;
}
return 0;
}
 
/* Function table (exported) */
 
DriverSpecs __svgalib_r128_driverspecs =
{
r128_saveregs,
r128_setregs,
r128_unlock,
r128_lock,
r128_test,
r128_init,
r128_setpage,
NULL,
NULL,
r128_setmode,
r128_modeavailable,
r128_setdisplaystart,
r128_setlogicalwidth,
r128_getmodeinfo,
0, /* old blit funcs */
0,
0,
0,
0,
r128_ext_set, /* ext_set */
0, /* accel */
r128_linear,
0, /* accelspecs, filled in during init. */
&r128_emul, /* Emulation */
r128_cursor,
};
 
#define VENDOR_ID 0x1002
 
/* Initialize chipset (called after detection) */
static int r128_init(int force, int par1, int par2)
{
unsigned long buf[64];
int found=0, id, NOBIOS=0;
unsigned char *BIOS_POINTER;
char chipnames[2][9]={"Rage 128", "Radeon"};
 
if (force) {
r128_memory = par1;
chiptype = par2;
} else {
 
};
 
found=__svgalib_pci_find_vendor_vga(VENDOR_ID,buf,0);
 
if(found) return 0;
chiptype=-1;
id=(buf[0]>>16)&0xffff;
if( (id==0x4c45) ||
(id==0x4c56) ||
(id==0x4d46) ||
(id==0x4d4c) ||
((id>>8)==0x50) ||
((id>>8)==0x52) ||
((id>>8)==0x53) ||
((id>>8)==0x54))
chiptype=Rage128;
if( (id==0x4242) ||
(id==0x4c57) ||
(id==0x4c59) ||
(id==0x4c5a) ||
((id>>8)==0x51))
chiptype = Radeon;
if(chiptype==-1) return 0;
r128_linear_base=buf[4]&0xffffff00;
r128_mmio_base=buf[6]&0xffffff00;
 
MMIO_POINTER = (void *)r128_mmio_base;
 
r128_memory = INREG(R128_CONFIG_MEMSIZE) / 1024;
BusCntl = INREG(R128_BUS_CNTL);
HasPanelRegs = 0;
CRTOnly = 1;
r128_ramtype = 1;
 
#ifndef __PPC
if(__svgalib_secondary)
#endif
NOBIOS=1;
 
if(NOBIOS) {
int x_mpll_ref_fb_div, xclk_cntl, Nx, M;
int PostDivSet[] = {0, 1, 2, 4, 8, 3, 6, 12};
switch(chiptype) {
case Rage128:
pll.reference_freq = 2950;
pll.min_pll_freq = 12500;
pll.max_pll_freq = 25000;
pll.reference_div = INPLL(R128_PPLL_REF_DIV) & R128_PPLL_REF_DIV_MASK;
x_mpll_ref_fb_div = INPLL(R128_X_MPLL_REF_FB_DIV);
xclk_cntl = INPLL(R128_XCLK_CNTL) & 0x7;
Nx = (x_mpll_ref_fb_div & 0x00FF00) >> 8;
M = (x_mpll_ref_fb_div & 0x0000FF);
pll.xclk = R128Div((2 * Nx * pll.reference_freq),
(M * PostDivSet[xclk_cntl]));
break;
case Radeon:
pll.reference_freq = 2700;
pll.min_pll_freq = 12500;
pll.max_pll_freq = 35000;
pll.reference_div = 67;
pll.xclk = 16667;
break;
}
} else
#define R128_BIOS16(x) (*(unsigned short *)(BIOS_POINTER + x))
#define R128_BIOS32(x) (*(unsigned int *)(BIOS_POINTER + x))
{
uint16_t bios_header;
uint16_t pll_info_block;
BIOS_POINTER = (void *)0xc0000;
bios_header = R128_BIOS16(0x48);
pll_info_block = R128_BIOS16(bios_header + 0x30);
pll.reference_freq = R128_BIOS16(pll_info_block + 0x0e);
pll.reference_div = R128_BIOS16(pll_info_block + 0x10);
pll.min_pll_freq = R128_BIOS32(pll_info_block + 0x12);
pll.max_pll_freq = R128_BIOS32(pll_info_block + 0x16);
pll.xclk = R128_BIOS16(pll_info_block + 0x08);
}
#if 1
printk(KERN_INFO "pll: %i %i %i %i %i\n",pll.reference_freq,pll.reference_div,
pll.min_pll_freq, pll.max_pll_freq, pll.xclk);
#endif
 
r128_mapio();
if (__svgalib_driver_report) {
printk(KERN_INFO "Using ATI %s driver, %iKB.\n",chipnames[chiptype],r128_memory);
};
__svgalib_modeinfo_linearset |= IS_LINEAR;
cardspecs = malloc(sizeof(CardSpecs));
cardspecs->videoMemory = r128_memory;
cardspecs->maxPixelClock4bpp = 75000;
cardspecs->maxPixelClock8bpp = 250000;
cardspecs->maxPixelClock16bpp = 250000;
cardspecs->maxPixelClock24bpp = 250000;
cardspecs->maxPixelClock32bpp = 250000;
cardspecs->flags = INTERLACE_DIVIDE_VERT | CLOCK_PROGRAMMABLE;
cardspecs->maxHorizontalCrtc = 4080;
cardspecs->maxPixelClock4bpp = 0;
cardspecs->nClocks =0;
cardspecs->mapClock = r128_map_clock;
cardspecs->mapHorizontalCrtc = r128_map_horizontal_crtc;
cardspecs->matchProgrammableClock=r128_match_programmable_clock;
__svgalib_driverspecs = &__svgalib_r128_driverspecs;
__svgalib_banked_mem_base=0xa0000;
__svgalib_banked_mem_size=0x10000;
__svgalib_linear_mem_base=r128_linear_base;
__svgalib_linear_mem_size=r128_memory*0x400;
__svgalib_mmio_base=r128_mmio_base;
__svgalib_mmio_size=16*1024;
if(chiptype==Radeon) {
__svgalib_banked_mem_base=r128_linear_base;
__svgalib_r128_driverspecs.__svgalib_setpage = __svgalib_emul_setpage;
}
 
sleep(4);
return 1;
}
/shark/tags/rel_0_5/drivers/svga/vga.c
0,0 → 1,1414
/* SVGA Lib - Linker module to use the low level driver
* without the vga.c support
*
*/
 
/* variables used to shift between monchrome and color emulation */
#include <stdint.h>
#include <unistd.h>
 
#include <ll/i386/hw-data.h>
#include <ll/i386/mem.h>
#include <ll/i386/cons.h>
#include <ll/sys/ll/ll-func.h>
 
#include "libvga.h"
#include "vgaversion.h"
#include "vgaio.h"
#include "driver.h"
 
int __svgalib_CRT_I; /* current CRT index register address */
int __svgalib_CRT_D; /* current CRT data register address */
int __svgalib_IS1_R; /* current input status register address */
static int color_text; /* true if color text emulation */
 
uint8_t *BANKED_POINTER=NULL, *LINEAR_POINTER;
uint8_t *MMIO_POINTER;
uint8_t *SPARSE_MMIO;
static int mmio_mapped=0, mem_mapped=0;
static uint8_t *B8000_POINTER=NULL;
unsigned long __svgalib_banked_mem_base, __svgalib_banked_mem_size;
unsigned long __svgalib_mmio_base, __svgalib_mmio_size=0;
unsigned long __svgalib_linear_mem_base=0, __svgalib_linear_mem_size=0;
 
extern int init_vgapci(void);
extern int nv3_test(void);
extern int savage_test(void);
extern int r128_test(void);
 
/* If == 0 then nothing is defined by the user... */
int __svgalib_default_mode = 10;
 
struct info infotable[] =
{
{80, 25, 16, 160, 0}, /* VGAlib VGA modes */
{320, 200, 16, 40, 0},
{640, 200, 16, 80, 0},
{640, 350, 16, 80, 0},
{640, 480, 16, 80, 0},
{320, 200, 256, 320, 1},
{320, 240, 256, 80, 0},
{320, 400, 256, 80, 0},
{360, 480, 256, 90, 0},
{640, 480, 2, 80, 0},
 
{640, 480, 256, 640, 1}, /* VGAlib SVGA modes */
{800, 600, 256, 800, 1},
{1024, 768, 256, 1024, 1},
{1280, 1024, 256, 1280, 1},
 
{320, 200, 1 << 15, 640, 2}, /* Hicolor/truecolor modes */
{320, 200, 1 << 16, 640, 2},
{320, 200, 1 << 24, 320 * 3, 3},
{640, 480, 1 << 15, 640 * 2, 2},
{640, 480, 1 << 16, 640 * 2, 2},
{640, 480, 1 << 24, 640 * 3, 3},
{800, 600, 1 << 15, 800 * 2, 2},
{800, 600, 1 << 16, 800 * 2, 2},
{800, 600, 1 << 24, 800 * 3, 3},
{1024, 768, 1 << 15, 1024 * 2, 2},
{1024, 768, 1 << 16, 1024 * 2, 2},
{1024, 768, 1 << 24, 1024 * 3, 3},
{1280, 1024, 1 << 15, 1280 * 2, 2},
{1280, 1024, 1 << 16, 1280 * 2, 2},
{1280, 1024, 1 << 24, 1280 * 3, 3},
 
{800, 600, 16, 100, 0}, /* SVGA 16-color modes */
{1024, 768, 16, 128, 0},
{1280, 1024, 16, 160, 0},
 
{720, 348, 2, 90, 0}, /* Hercules emulation mode */
 
{320, 200, 1 << 24, 320 * 4, 4},
{640, 480, 1 << 24, 640 * 4, 4},
{800, 600, 1 << 24, 800 * 4, 4},
{1024, 768, 1 << 24, 1024 * 4, 4},
{1280, 1024, 1 << 24, 1280 * 4, 4},
 
{1152, 864, 16, 144, 0},
{1152, 864, 256, 1152, 1},
{1152, 864, 1 << 15, 1152 * 2, 2},
{1152, 864, 1 << 16, 1152 * 2, 2},
{1152, 864, 1 << 24, 1152 * 3, 3},
{1152, 864, 1 << 24, 1152 * 4, 4},
 
{1600, 1200, 16, 200, 0},
{1600, 1200, 256, 1600, 1},
{1600, 1200, 1 << 15, 1600 * 2, 2},
{1600, 1200, 1 << 16, 1600 * 2, 2},
{1600, 1200, 1 << 24, 1600 * 3, 3},
{1600, 1200, 1 << 24, 1600 * 4, 4},
 
{320, 240, 256, 320, 1},
{320, 240, 1<<15, 320*2, 2},
{320, 240, 1<<16, 320*2, 2},
{320, 240, 1<<24, 320*3, 3},
{320, 240, 1<<24, 320*4, 4},
{400, 300, 256, 400, 1},
{400, 300, 1<<15, 400*2, 2},
{400, 300, 1<<16, 400*2, 2},
{400, 300, 1<<24, 400*3, 3},
{400, 300, 1<<24, 400*4, 4},
{512, 384, 256, 512, 1},
{512, 384, 1<<15, 512*2, 2},
{512, 384, 1<<16, 512*2, 2},
{512, 384, 1<<24, 512*3, 3},
{512, 384, 1<<24, 512*4, 4},
 
{960, 720, 256, 960, 1},
{960, 720, 1<<15, 960*2, 2},
{960, 720, 1<<16, 960*2, 2},
{960, 720, 1<<24, 960*3, 3},
{960, 720, 1<<24, 960*4, 4},
 
{1920, 1440, 256, 1920, 1},
{1920, 1440, 1<<15, 1920*2, 2},
{1920, 1440, 1<<16, 1920*2, 2},
{1920, 1440, 1<<24, 1920*3, 3},
{1920, 1440, 1<<24, 1920*4, 4},
 
{320, 400, 1<<8, 320, 1},
{320, 400, 1<<15, 320*2, 2},
{320, 400, 1<<16, 320*2, 2},
{320, 400, 1<<24, 320*3, 3},
{320, 400, 1<<24, 320*4, 4},
 
{640, 400, 256, 640, 1},
{640, 400, 1<<15, 640*2, 2},
{640, 400, 1<<16, 640*2, 2},
{640, 400, 1<<24, 640*3, 3},
{640, 400, 1<<24, 640*4, 4},
 
{320, 480, 256, 320, 1},
{320, 480, 1<<15, 320*2, 2},
{320, 480, 1<<16, 320*2, 2},
{320, 480, 1<<24, 320*3, 3},
{320, 480, 1<<24, 320*4, 4},
 
{720, 540, 256, 720, 1},
{720, 540, 1<<15, 720*2, 2},
{720, 540, 1<<16, 720*2, 2},
{720, 540, 1<<24, 720*3, 3},
{720, 540, 1<<24, 720*4, 4},
 
{848, 480, 256, 848, 1},
{848, 480, 1<<15, 848*2, 2},
{848, 480, 1<<16, 848*2, 2},
{848, 480, 1<<24, 848*3, 3},
{848, 480, 1<<24, 848*4, 4},
 
{1072, 600, 256, 1072, 1},
{1072, 600, 1<<15, 1072*2, 2},
{1072, 600, 1<<16, 1072*2, 2},
{1072, 600, 1<<24, 1072*3, 3},
{1072, 600, 1<<24, 1072*4, 4},
 
{1280, 720, 256, 1280, 1},
{1280, 720, 1<<15, 1280*2, 2},
{1280, 720, 1<<16, 1280*2, 2},
{1280, 720, 1<<24, 1280*3, 3},
{1280, 720, 1<<24, 1280*4, 4},
 
{1360, 768, 256, 1360, 1},
{1360, 768, 1<<15, 1360*2, 2},
{1360, 768, 1<<16, 1360*2, 2},
{1360, 768, 1<<24, 1360*3, 3},
{1360, 768, 1<<24, 1360*4, 4},
 
{1800, 1012, 256, 1800, 1},
{1800, 1012, 1<<15, 1800*2, 2},
{1800, 1012, 1<<16, 1800*2, 2},
{1800, 1012, 1<<24, 1800*3, 3},
{1800, 1012, 1<<24, 1800*4, 4},
 
{1920, 1080, 256, 1920, 1},
{1920, 1080, 1<<15, 1920*2, 2},
{1920, 1080, 1<<16, 1920*2, 2},
{1920, 1080, 1<<24, 1920*3, 3},
{1920, 1080, 1<<24, 1920*4, 4},
 
{2048, 1152, 256, 2048, 1},
{2048, 1152, 1<<15, 2048*2, 2},
{2048, 1152, 1<<16, 2048*2, 2},
{2048, 1152, 1<<24, 2048*3, 3},
{2048, 1152, 1<<24, 2048*4, 4},
 
{2048, 1536, 256, 2048, 1},
{2048, 1536, 1<<15, 2048*2, 2},
{2048, 1536, 1<<16, 2048*2, 2},
{2048, 1536, 1<<24, 2048*3, 3},
{2048, 1536, 1<<24, 2048*4, 4},
 
{512, 480, 256, 512, 1},
{512, 480, 1<<15, 512*2, 2},
{512, 480, 1<<16, 512*2, 2},
{512, 480, 1<<24, 512*3, 3},
{512, 480, 1<<24, 512*4, 4},
 
{400, 600, 256, 400, 1},
{400, 600, 1<<15, 400*2, 2},
{400, 600, 1<<16, 400*2, 2},
{400, 600, 1<<24, 400*3, 3},
{400, 600, 1<<24, 400*4, 4},
 
{400, 300, 256, 100, 0},
{320, 200, 256, 320, 1},
{0, 0, 0, 0, 0},
{0, 0, 0, 0, 0},
{0, 0, 0, 0, 0},
{0, 0, 0, 0, 0},
{0, 0, 0, 0, 0},
{0, 0, 0, 0, 0},
{0, 0, 0, 0, 0},
{0, 0, 0, 0, 0},
{0, 0, 0, 0, 0},
{0, 0, 0, 0, 0},
{0, 0, 0, 0, 0},
{0, 0, 0, 0, 0},
{0, 0, 0, 0, 0},
{0, 0, 0, 0, 0},
{0, 0, 0, 0, 0}
};
 
#define MAX_MODES (sizeof(infotable) / sizeof(struct info))
 
void (*__svgalib_go_to_background) (void) = 0;
void (*__svgalib_come_from_background) (void) = 0;
static int release_acquire=0;
 
unsigned long __svgalib_graph_base = GRAPH_BASE;
 
unsigned char __svgalib_novga = 0; /* Does not have VGA circuitry on board */
unsigned char __svgalib_vesatext = 0;
unsigned char __svgalib_textprog = 0; /* run a program when returning to text mode */
unsigned char __svgalib_secondary = 0; /* this is not the main card with VC'S ) */
unsigned char __svgalib_emulatepage = 0; /* don't use 0xa0000 memory */
unsigned char __svgalib_novccontrol = 0; /* this is not the main card with VC'S */
unsigned char __svgalib_ragedoubleclock = 0;
unsigned char __svgalib_simple = 0;
 
/* default palette values */
static const unsigned char default_red[256]
=
{0, 0, 0, 0, 42, 42, 42, 42, 21, 21, 21, 21, 63, 63, 63, 63,
0, 5, 8, 11, 14, 17, 20, 24, 28, 32, 36, 40, 45, 50, 56, 63,
0, 16, 31, 47, 63, 63, 63, 63, 63, 63, 63, 63, 63, 47, 31, 16,
0, 0, 0, 0, 0, 0, 0, 0, 31, 39, 47, 55, 63, 63, 63, 63,
63, 63, 63, 63, 63, 55, 47, 39, 31, 31, 31, 31, 31, 31, 31, 31,
45, 49, 54, 58, 63, 63, 63, 63, 63, 63, 63, 63, 63, 58, 54, 49,
45, 45, 45, 45, 45, 45, 45, 45, 0, 7, 14, 21, 28, 28, 28, 28,
28, 28, 28, 28, 28, 21, 14, 7, 0, 0, 0, 0, 0, 0, 0, 0,
14, 17, 21, 24, 28, 28, 28, 28, 28, 28, 28, 28, 28, 24, 21, 17,
14, 14, 14, 14, 14, 14, 14, 14, 20, 22, 24, 26, 28, 28, 28, 28,
28, 28, 28, 28, 28, 26, 24, 22, 20, 20, 20, 20, 20, 20, 20, 20,
0, 4, 8, 12, 16, 16, 16, 16, 16, 16, 16, 16, 16, 12, 8, 4,
0, 0, 0, 0, 0, 0, 0, 0, 8, 10, 12, 14, 16, 16, 16, 16,
16, 16, 16, 16, 16, 14, 12, 10, 8, 8, 8, 8, 8, 8, 8, 8,
11, 12, 13, 15, 16, 16, 16, 16, 16, 16, 16, 16, 16, 15, 13, 12,
11, 11, 11, 11, 11, 11, 11, 11, 0, 0, 0, 0, 0, 0, 0, 0};
static const unsigned char default_green[256]
=
{0, 0, 42, 42, 0, 0, 21, 42, 21, 21, 63, 63, 21, 21, 63, 63,
0, 5, 8, 11, 14, 17, 20, 24, 28, 32, 36, 40, 45, 50, 56, 63,
0, 0, 0, 0, 0, 0, 0, 0, 0, 16, 31, 47, 63, 63, 63, 63,
63, 63, 63, 63, 63, 47, 31, 16, 31, 31, 31, 31, 31, 31, 31, 31,
31, 39, 47, 55, 63, 63, 63, 63, 63, 63, 63, 63, 63, 55, 47, 39,
45, 45, 45, 45, 45, 45, 45, 45, 45, 49, 54, 58, 63, 63, 63, 63,
63, 63, 63, 63, 63, 58, 54, 49, 0, 0, 0, 0, 0, 0, 0, 0,
0, 7, 14, 21, 29, 28, 28, 28, 28, 28, 28, 28, 28, 21, 14, 7,
14, 14, 14, 14, 14, 14, 14, 14, 14, 17, 21, 24, 28, 28, 28, 28,
28, 28, 28, 28, 28, 24, 21, 17, 20, 20, 20, 20, 20, 20, 20, 20,
20, 22, 24, 26, 28, 28, 28, 28, 28, 28, 28, 28, 28, 26, 24, 22,
0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 8, 12, 16, 16, 16, 16,
16, 16, 16, 16, 16, 12, 8, 4, 8, 8, 8, 8, 8, 8, 8, 8,
8, 10, 12, 14, 16, 16, 16, 16, 16, 16, 16, 16, 16, 14, 12, 10,
11, 11, 11, 11, 11, 11, 11, 11, 11, 12, 13, 15, 16, 16, 16, 16,
16, 16, 16, 16, 16, 15, 13, 12, 0, 0, 0, 0, 0, 0, 0, 0};
static const unsigned char default_blue[256]
=
{0, 42, 0, 42, 0, 42, 0, 42, 21, 63, 21, 63, 21, 63, 21, 63,
0, 5, 8, 11, 14, 17, 20, 24, 28, 32, 36, 40, 45, 50, 56, 63,
63, 63, 63, 63, 63, 47, 31, 16, 0, 0, 0, 0, 0, 0, 0, 0,
0, 16, 31, 47, 63, 63, 63, 63, 63, 63, 63, 63, 63, 55, 47, 39,
31, 31, 31, 31, 31, 31, 31, 31, 31, 39, 47, 55, 63, 63, 63, 63,
63, 63, 63, 63, 63, 58, 54, 49, 45, 45, 45, 45, 45, 45, 45, 45,
45, 49, 54, 58, 63, 63, 63, 63, 28, 28, 28, 28, 28, 21, 14, 7,
0, 0, 0, 0, 0, 0, 0, 0, 0, 7, 14, 21, 28, 28, 28, 28,
28, 28, 28, 28, 28, 24, 21, 17, 14, 14, 14, 14, 14, 14, 14, 14,
14, 17, 21, 24, 28, 28, 28, 28, 28, 28, 28, 28, 28, 26, 24, 22,
20, 20, 20, 20, 20, 20, 20, 20, 20, 22, 24, 26, 28, 28, 28, 28,
16, 16, 16, 16, 16, 12, 8, 4, 0, 0, 0, 0, 0, 0, 0, 0,
0, 4, 8, 12, 16, 16, 16, 16, 16, 16, 16, 16, 16, 14, 12, 10,
8, 8, 8, 8, 8, 8, 8, 8, 8, 10, 12, 14, 16, 16, 16, 16,
16, 16, 16, 16, 16, 15, 13, 12, 11, 11, 11, 11, 11, 11, 11, 11,
11, 12, 13, 15, 16, 16, 16, 16, 0, 0, 0, 0, 0, 0, 0, 0};
 
static unsigned char text_regs[MAX_REGS]; /* VGA registers for saved text mode */
 
char *__svgalib_TextProg_argv[16]; /* should be enough */
char *__svgalib_TextProg;
 
/* saved text mode palette values */
static unsigned char text_red[256];
static unsigned char text_green[256];
static unsigned char text_blue[256];
 
/* saved graphics mode palette values */
static unsigned char graph_red[256];
static unsigned char graph_green[256];
static unsigned char graph_blue[256];
 
static int prv_mode = TEXT; /* previous video mode */
static int flip_mode = TEXT; /* flipped video mode */
 
int CM = TEXT; /* current video mode */
struct info CI; /* current video parameters */
int COL; /* current color */
 
static int initialized = 0; /* flag: initialize() called ? */
static int flip = 0; /* flag: executing vga_flip() ? */
static int background_fd = -1;
 
/* svgalib additions: */
int __svgalib_chipset = UNDEFINED;
int __svgalib_driver_report = 1;
/* report driver used after chipset detection */
int __svgalib_videomemoryused = -1;
int __svgalib_modeX = 0; /* true after vga_setmodeX() */
int __svgalib_modeflags = 0; /* copy of flags for current mode */
int __svgalib_critical = 0; /* indicates blitter is busy */
int __svgalib_screenon = 1; /* screen visible if != 0 */
int __svgalib_vgacolormode = 1; /* assume color for now. needs to be
config file option */
 
static int __svgalib_savemem=0;
 
RefreshRange __svgalib_horizsync =
{31500U, 60000U}; /* horz. refresh (Hz) min, max */
RefreshRange __svgalib_vertrefresh =
{50U, 70U}; /* vert. refresh (Hz) min, max */
int __svgalib_bandwidth=50000; /* monitor maximum bandwidth (kHz) */
int __svgalib_grayscale = 0; /* grayscale vs. color mode */
int __svgalib_modeinfo_linearset = 0; /* IS_LINEAR handled via extended vga_modeinfo */
const int __svgalib_max_modes = MAX_MODES; /* Needed for dynamical allocated tables in mach32.c */
 
static unsigned __svgalib_maxhsync[] =
{
31500, 35100, 35500, 37900, 48300, 56000, 60000
};
 
static int lastmodenumber = __GLASTMODE; /* Last defined mode */
static int my_pid = 0; /* process PID, used with atexit() */
static int __svgalib_currentpage;
static int vga_page_offset; /* offset to add to all vga_set*page() calls */
static int currentlogicalwidth;
static int currentdisplaystart;
static int mouse_support = 0;
int mouse_open = 0;
static int mouse_mode = 0;
static int mouse_type = -1;
static int mouse_modem_ctl = 0;
char *__svgalib_mouse_device = "/dev/mouse";
int __svgalib_mouse_flag;
static char *mem_device = "/dev/svga";
static int __svgalib_oktowrite = 1;
static int modeinfo_mask = ~0;
 
int __svgalib_mem_fd = -1; /* /dev/svga file descriptor */
int __svgalib_tty_fd = -1; /* /dev/tty file descriptor */
int __svgalib_nosigint = 0; /* Don't generate SIGINT in graphics mode */
int __svgalib_runinbackground = 0;
int __svgalib_startup_vc = -1;
static int __svgalib_security_revokeallprivs = 1;
static unsigned fontbufsize = 8192; /* compatibility */
 
/* Dummy buffer for mmapping grahics memory; points to 64K VGA framebuffer. */
unsigned char *GM;
/* Exported variable (read-only) is shadowed from internal variable, for */
/* better shared library performance. */
unsigned char *graph_mem;
 
void *__svgalib_physaddr;
int __svgalib_linear_memory_size;
 
static unsigned long graph_buf_size = 0;
static unsigned char *graph_buf = NULL; /* saves graphics data during flip */
static int inbackground=0;
 
static unsigned char *font_buf1; /* saved font data - plane 2 */
static unsigned char *font_buf2; /* saved font data - plane 3 */
static unsigned char *text_buf1=NULL; /* saved text data - plane 0 */
static unsigned char *text_buf2; /* saved text data - plane 1 */
 
int __svgalib_flipchar = '\x1b'; /* flip character - initially ESCAPE */
 
/* Chipset specific functions */
 
DriverSpecs *__svgalib_driverspecs = &__svgalib_vga_driverspecs;
 
static void (*__svgalib_setpage) (int); /* gives little faster vga_setpage() */
static void (*__svgalib_setrdpage) (int);
static void (*__svgalib_setwrpage) (int);
 
int (*__svgalib_inmisc)(void);
void (*__svgalib_outmisc)(int);
int (*__svgalib_incrtc)(int);
void (*__svgalib_outcrtc)(int,int);
int (*__svgalib_inseq)(int);
void (*__svgalib_outseq)(int,int);
int (*__svgalib_ingra)(int);
void (*__svgalib_outgra)(int,int);
int (*__svgalib_inatt)(int);
void (*__svgalib_outatt)(int,int);
void (*__svgalib_attscreen)(int);
void (*__svgalib_inpal)(int,int*,int*,int*);
void (*__svgalib_outpal)(int,int,int,int);
int (*__svgalib_inis1)(void);
 
void map_banked(void);
void map_banked_fix(void);
inline void vga_setpage(int p);
 
DriverSpecs *__svgalib_driverspecslist[] =
{
NULL, /* chipset undefined */
&__svgalib_vga_driverspecs,
#ifdef INCLUDE_ET4000_DRIVER
&__svgalib_et4000_driverspecs,
#else
NULL,
#endif
#ifdef INCLUDE_CIRRUS_DRIVER
&__svgalib_cirrus_driverspecs,
#else
NULL,
#endif
#ifdef INCLUDE_TVGA_DRIVER
&__svgalib_tvga8900_driverspecs,
#else
NULL,
#endif
#ifdef INCLUDE_OAK_DRIVER
&__svgalib_oak_driverspecs,
#else
NULL,
#endif
#ifdef INCLUDE_EGA_DRIVER
&__svgalib_ega_driverspecs,
#else
NULL,
#endif
#ifdef INCLUDE_S3_DRIVER
&__svgalib_s3_driverspecs,
#else
NULL,
#endif
#ifdef INCLUDE_ET3000_DRIVER
&__svgalib_et3000_driverspecs,
#else
NULL,
#endif
#ifdef INCLUDE_MACH32_DRIVER
&__svgalib_mach32_driverspecs,
#else
NULL,
#endif
#ifdef INCLUDE_GVGA6400_DRIVER
&__svgalib_gvga6400_driverspecs,
#else
NULL,
#endif
#ifdef INCLUDE_ARK_DRIVER
&__svgalib_ark_driverspecs,
#else
NULL,
#endif
#ifdef INCLUDE_ATI_DRIVER
&__svgalib_ati_driverspecs,
#else
NULL,
#endif
#ifdef INCLUDE_ALI_DRIVER
&__svgalib_ali_driverspecs,
#else
NULL,
#endif
#ifdef INCLUDE_MACH64_DRIVER
&__svgalib_mach64_driverspecs,
#else
NULL,
#endif
#ifdef INCLUDE_CHIPS_DRIVER
&__svgalib_chips_driverspecs,
#else
NULL,
#endif
#ifdef INCLUDE_APM_DRIVER
&__svgalib_apm_driverspecs,
#else
NULL,
#endif
#ifdef INCLUDE_NV3_DRIVER
&__svgalib_nv3_driverspecs,
#else
NULL,
#endif
#ifdef INCLUDE_ET6000_DRIVER
&__svgalib_et6000_driverspecs,
#else
NULL,
#endif
#ifdef INCLUDE_VESA_DRIVER
&__svgalib_vesa_driverspecs,
#else
NULL,
#endif
#ifdef INCLUDE_MX_DRIVER
&__svgalib_mx_driverspecs,
#else
NULL,
#endif
#ifdef INCLUDE_PARADISE_DRIVER
&__svgalib_paradise_driverspecs,
#else
NULL,
#endif
#ifdef INCLUDE_RAGE_DRIVER
&__svgalib_rage_driverspecs,
#else
NULL,
#endif
#ifdef INCLUDE_BANSHEE_DRIVER
&__svgalib_banshee_driverspecs,
#else
NULL,
#endif
#ifdef INCLUDE_SIS_DRIVER
&__svgalib_sis_driverspecs,
#else
NULL,
#endif
#ifdef INCLUDE_I740_DRIVER
&__svgalib_i740_driverspecs,
#else
NULL,
#endif
#ifdef INCLUDE_NEO_DRIVER
&__svgalib_neo_driverspecs,
#else
NULL,
#endif
#ifdef INCLUDE_LAGUNA_DRIVER
&__svgalib_laguna_driverspecs,
#else
NULL,
#endif
#ifdef INCLUDE_FBDEV_DRIVER
&__svgalib_fbdev_driverspecs,
#else
NULL,
#endif
#ifdef INCLUDE_G400_DRIVER
&__svgalib_g400_driverspecs,
#else
NULL,
#endif
#ifdef INCLUDE_R128_DRIVER
&__svgalib_r128_driverspecs,
#else
NULL,
#endif
#ifdef INCLUDE_SAVAGE_DRIVER
&__svgalib_savage_driverspecs,
#else
NULL,
#endif
#ifdef INCLUDE_MILLENNIUM_DRIVER
&__svgalib_mil_driverspecs,
#else
NULL,
#endif
#ifdef INCLUDE_I810_DRIVER
&__svgalib_i810_driverspecs,
#else
NULL,
#endif
#ifdef INCLUDE_TRIDENT_DRIVER
&__svgalib_trident_driverspecs,
#else
NULL,
#endif
#ifdef INCLUDE_RENDITION_DRIVER
&__svgalib_rendition_driverspecs,
#else
NULL,
#endif
#ifdef INCLUDE_G450C2_DRIVER
&__svgalib_g450c2_driverspecs,
#else
NULL,
#endif
#ifdef INCLUDE_PM2_DRIVER
&__svgalib_pm2_driverspecs,
#else
NULL,
#endif
};
 
static char *driver_names[] =
{
"",
"VGA",
"ET4000",
"Cirrus",
"TVGA",
"Oak",
"EGA",
"S3",
"ET3000",
"Mach32",
"GVGA6400",
"ARK",
"ATI",
"ALI",
"Mach64",
"C&T",
"APM",
"NV3",
"ET6000",
"VESA",
"MX",
"PARADISE",
"RAGE",
"BANSHEE",
"SIS",
"I740",
"NEOMAGIC",
"LAGUNA",
"FBDev",
"G400",
"R128",
"SAVAGE",
"MILLENNIUM",
"I810",
"TRIDENT",
"RENDITION",
"G450C2",
"PM2",
NULL};
 
/* Chipset drivers */
 
/* vgadrv Standard VGA (also used by drivers below) */
/* et4000 Tseng ET4000 (from original vgalib) */
/* cirrus Cirrus Logic GD542x */
/* tvga8900 Trident TVGA 8900/9000 (derived from tvgalib) */
/* oak Oak Technologies 037/067/077 */
/* egadrv IBM EGA (subset of VGA) */
/* s3 S3 911 */
/* mach32 ATI MACH32 */
/* ark ARK Logic */
/* gvga6400 Genoa 6400 (old SVGA) */
/* ati ATI */
/* ali ALI2301 */
/* mach64 ATI MACH64 */
/* chips chips & technologies*/
/* et6000 Tseng ET6000 */ /* DS */
 
inline void vga_setpage(int p)
{
p += vga_page_offset;
if (p == __svgalib_currentpage)
return;
 
__svgalib_currentpage = p;
}
 
int __svgalib_setregs(const unsigned char *regs)
{
int i;
 
if(__svgalib_novga) return 1;
 
if (__svgalib_chipset == EGA) {
/* Enable graphics register modification */
port_out(0x00, GRA_E0);
port_out(0x01, GRA_E1);
}
/* update misc output register */
__svgalib_outmisc(regs[MIS]);
 
/* synchronous reset on */
__svgalib_outseq(0x00,0x01);
 
/* write sequencer registers */
__svgalib_outseq(0x01,regs[SEQ + 1] | 0x20);
for (i = 2; i < SEQ_C; i++) {
__svgalib_outseq(i,regs[SEQ + i]);
}
 
/* synchronous reset off */
__svgalib_outseq(0x00,0x03);
 
if (__svgalib_chipset != EGA) {
/* deprotect CRT registers 0-7 */
__svgalib_outcrtc(0x11,__svgalib_incrtc(0x11)&0x7f);
}
/* write CRT registers */
for (i = 0; i < CRT_C; i++) {
__svgalib_outcrtc(i,regs[CRT + i]);
}
 
/* write graphics controller registers */
for (i = 0; i < GRA_C; i++) {
__svgalib_outgra(i,regs[GRA+i]);
}
 
/* write attribute controller registers */
for (i = 0; i < ATT_C; i++) {
__svgalib_outatt(i,regs[ATT+i]);
}
 
return 0;
}
 
int vga_screenon(void)
{
int tmp = 0;
 
SCREENON = 1;
if(__svgalib_novga) return 0;
if (__svgalib_driverspecs->emul && __svgalib_driverspecs->emul->screenon) {
tmp = __svgalib_driverspecs->emul->screenon();
} else {
/* turn screen back on */
if ((CHIPSET != EGA) && !__svgalib_novga) {
__svgalib_outseq(0x01,__svgalib_inseq(0x01) & 0xdf);
}
/* #ifdef DISABLE_VIDEO_OUTPUT */
/* enable video output */
__svgalib_attscreen(0x20);
/* #endif */
}
 
return 0;
}
 
int vga_claimvideomemory(int m)
{
vga_modeinfo *modeinfo;
int cardmemory;
 
modeinfo = vga_getmodeinfo(CM);
if (m < VMEM)
return 0;
if (modeinfo->colors == 16)
cardmemory = modeinfo->maxpixels / 2;
else
cardmemory = (modeinfo->maxpixels * modeinfo->bytesperpixel
+ 2) & 0xffff0000;
/* maxpixels * bytesperpixel can be 2 less than video memory in */
/* 3 byte-per-pixel modes; assume memory is multiple of 64K */
if (m > cardmemory)
return -1;
VMEM = m;
return 0;
}
 
void map_banked() {
if(__svgalib_emulatepage){
BANKED_POINTER=(void *)__svgalib_linear_mem_base;
} else {
BANKED_POINTER=(void *)__svgalib_banked_mem_base;
}
 
}
 
void map_mmio() {
 
if(mmio_mapped) return;
 
if(__svgalib_mmio_size) {
mmio_mapped=1;
MMIO_POINTER=(void *)__svgalib_mmio_base;
} else {
MMIO_POINTER=NULL;
SPARSE_MMIO=NULL;
}
}
 
void map_mem() {
if(mem_mapped) return;
if(__svgalib_banked_mem_size==0) __svgalib_banked_mem_size = 0x10000;
 
map_banked();
if(__svgalib_linear_mem_size) {
map_linear(__svgalib_linear_mem_base, __svgalib_linear_mem_size);
};
 
B8000_POINTER = (void *)0xb8000;
 
mem_mapped = 1;
 
}
 
static void __vga_map(void)
{
GM = (unsigned char *) BANKED_POINTER;
graph_mem = GM; /* Exported variable. */
}
 
void __svgalib_emul_setpage(int page)
{
static int oldpage = -2;
 
if (page != oldpage)
{
oldpage = page;
}
}
 
static void map_vgaio(void)
{
__svgalib_inmisc=__svgalib_vga_inmisc;
__svgalib_outmisc=__svgalib_vga_outmisc;
__svgalib_incrtc=__svgalib_vga_incrtc;
__svgalib_outcrtc=__svgalib_vga_outcrtc;
__svgalib_inseq=__svgalib_vga_inseq;
__svgalib_outseq=__svgalib_vga_outseq;
__svgalib_ingra=__svgalib_vga_ingra;
__svgalib_outgra=__svgalib_vga_outgra;
__svgalib_inatt=__svgalib_vga_inatt;
__svgalib_outatt=__svgalib_vga_outatt;
__svgalib_attscreen=__svgalib_vga_attscreen;
__svgalib_inpal=__svgalib_vga_inpal;
__svgalib_outpal=__svgalib_vga_outpal;
__svgalib_inis1=__svgalib_vga_inis1;
}
 
int __svgalib_saveregs(unsigned char *regs)
{
int i;
 
if (__svgalib_chipset == EGA || __svgalib_novga) {
/* Special case: Don't save standard VGA registers. */
return chipset_saveregs(regs);
}
/* save VGA registers */
for (i = 0; i < CRT_C; i++) {
regs[CRT + i] = __svgalib_incrtc(i);
}
for (i = 0; i < ATT_C; i++) {
regs[ATT + i] = __svgalib_inatt(i);
}
for (i = 0; i < GRA_C; i++) {
regs[GRA + i] = __svgalib_ingra(i);
}
for (i = 0; i < SEQ_C; i++) {
regs[SEQ + i] = __svgalib_inseq(i);
}
regs[MIS] = __svgalib_inmisc();
 
i = chipset_saveregs(regs); /* save chipset-specific registers */
/* i : additional registers */
if (!SCREENON) { /* We turned off the screen */
__svgalib_attscreen(0x20);
}
return CRT_C + ATT_C + GRA_C + SEQ_C + 1 + i;
}
 
int vga_setcolor(int color)
{
switch (CI.colors) {
case 2:
if (color != 0)
color = 15;
case 16: /* update set/reset register */
__svgalib_outgra(0x00,color&0x0f);
break;
default:
COL = color;
break;
}
return 0;
}
 
vga_modeinfo *vga_getmodeinfo(int mode)
{
static vga_modeinfo modeinfo;
int is_modeX = (CM == mode) && MODEX;
 
printk(KERN_INFO "getmodeinfo %i\n",mode);
 
modeinfo.linewidth = infotable[mode].xbytes;
__svgalib_getchipset(CHIPSET);
if (mode > vga_lastmodenumber())
return NULL;
modeinfo.width = infotable[mode].xdim;
modeinfo.height = infotable[mode].ydim;
modeinfo.bytesperpixel = infotable[mode].bytesperpixel;
modeinfo.colors = infotable[mode].colors;
if (is_modeX) {
modeinfo.linewidth = modeinfo.width / 4;
modeinfo.bytesperpixel = 0;
}
if (mode == TEXT) {
modeinfo.flags = HAVE_EXT_SET;
return &modeinfo;
}
modeinfo.flags = 0;
if ((STDVGAMODE(mode) && mode != G320x200x256) || is_modeX)
__svgalib_vga_driverspecs.getmodeinfo(mode, &modeinfo);
else
/* Get chipset specific info for SVGA modes and */
/* 320x200x256 (chipsets may support more pages) */
chipset_getmodeinfo(mode, &modeinfo);
 
if (modeinfo.colors == 256 && modeinfo.bytesperpixel == 0)
modeinfo.flags |= IS_MODEX;
if (mode > __GLASTMODE)
modeinfo.flags |= IS_DYNAMICMODE;
 
/* Maskout CAPABLE_LINEAR if requested by config file */
modeinfo.flags &= modeinfo_mask;
 
/* Many cards have problems with linear 320x200x256 mode */
if(mode==G320x200x256)modeinfo.flags &= (~CAPABLE_LINEAR) & (~IS_LINEAR) ;
 
/* If all needed info is here, signal if linear support has been enabled */
if ((modeinfo.flags & (CAPABLE_LINEAR | EXT_INFO_AVAILABLE)) ==
(CAPABLE_LINEAR | EXT_INFO_AVAILABLE)) {
modeinfo.flags |= __svgalib_modeinfo_linearset;
}
 
return &modeinfo;
}
 
char *__svgalib_token(char **ptr)
{
char *p;
p=*ptr;
while(*p==' ')p++;
if(*p != '\0' ) {
char *t;
t=p;
while((*t != '\0') && (*t != ' '))t++;
if(*t==' ') {
*t='\0';
t++;
}
*ptr=t;
return p;
} else {
*ptr=NULL;
return NULL;
}
}
 
int vga_lastmodenumber(void)
{
__svgalib_getchipset(CHIPSET);
return lastmodenumber;
}
 
int __svgalib_getchipset(int set_chipset)
{
 
/* SHARK: Supported Graphics Drivers
*
* NV3 (NVIDIA: GEFORCE/TNT/TNT2)
* SAVAGE (S3: VIRGE/SAVAGE
* R128 (ATI: RAGE 128/RADEON)
*
*/
CHIPSET = set_chipset;
 
if(!initialized) {
map_vgaio();
init_vgapci();
switch(CHIPSET) {
case NV3:
nv3_test();
break;
case SAVAGE:
savage_test();
break;
case R128:
r128_test();
break;
}
}
 
return CHIPSET;
 
}
 
int vga_getxdim(void)
{
return CI.xdim;
}
 
 
int vga_getydim(void)
{
return CI.ydim;
}
 
 
int vga_getcolors(void)
{
return CI.colors;
}
 
int vga_white(void)
{
switch (CI.colors) {
case 2:
case 16:
case 256:
return 15;
case 1 << 15:
return 32767;
case 1 << 16:
return 65535;
case 1 << 24:
return (1 << 24) - 1;
}
return CI.colors - 1;
}
 
void __svgalib_delay(void)
{
int i;
for (i = 0; i < 10; i++);
}
 
int vga_screenoff(void)
{
int tmp = 0;
 
SCREENON = 0;
 
if(__svgalib_novga) return 0;
 
if (__svgalib_driverspecs->emul && __svgalib_driverspecs->emul->screenoff) {
tmp = __svgalib_driverspecs->emul->screenoff();
} else {
/* turn off screen for faster VGA memory acces */
if ((CHIPSET != EGA) && !__svgalib_novga) {
__svgalib_outseq(0x01,__svgalib_inseq(0x01) | 0x20);
}
/* Disable video output */
#ifdef DISABLE_VIDEO_OUTPUT
__svgalib_attscreen(0);
#endif
}
 
return tmp;
}
 
static void setcoloremulation(void)
{
/* shift to color emulation */
__svgalib_CRT_I = CRT_IC;
__svgalib_CRT_D = CRT_DC;
__svgalib_IS1_R = IS1_RC;
__svgalib_vgacolormode=1;
if (CHIPSET != EGA && !__svgalib_novga)
__svgalib_outmisc(__svgalib_inmisc()|0x01);
}
 
void map_linear(unsigned long base, unsigned long size) {
LINEAR_POINTER= (void *)base;
 
}
 
static void savepalette(unsigned char *red, unsigned char *green,
unsigned char *blue)
{
int i;
 
if (__svgalib_driverspecs->emul && __svgalib_driverspecs->emul->savepalette)
return (__svgalib_driverspecs->emul->savepalette(red, green, blue));
 
if (CHIPSET == EGA || __svgalib_novga)
return;
 
/* save graphics mode palette */
 
for (i = 0; i < 256; i++) {
int r,g,b;
__svgalib_inpal(i,&r,&g,&b);
*(red++) = r;
*(green++) = g;
*(blue++) = b;
}
}
 
static void restorepalette(const unsigned char *red,
const unsigned char *green, const unsigned char *blue)
{
int i;
 
if (__svgalib_driverspecs->emul && __svgalib_driverspecs->emul->restorepalette)
return (__svgalib_driverspecs->emul->restorepalette(red, green, blue));
 
if (CHIPSET == EGA || __svgalib_novga)
return;
 
/* restore saved palette */
/* read RGB components - index is autoincremented */
for (i = 0; i < 256; i++) {
__svgalib_outpal(i,*(red++),*(green++),*(blue++));
}
}
 
int vga_getcurrentmode(void)
{
return CM;
}
 
 
static void initialize(int set_chipset)
{
int i;
 
printk(KERN_INFO "Initialize\n");
 
// __svgalib_disable_interrupt(); /* Is reenabled later by set_texttermio */
 
__svgalib_getchipset(set_chipset);
chipset_unlock();
 
/* mmap graphics memory */
map_mem();
map_mmio();
 
__vga_map();
 
/* disable video */
vga_screenoff();
 
/* Sanity check: (from painful experience) */
i = __svgalib_saveregs(text_regs);
if (i > MAX_REGS) {
printk(KERN_INFO "svgalib: FATAL internal error:\n");
printk(KERN_INFO "Set MAX_REGS at least to %d in src/driver.h and recompile everything.\n",
i);
}
 
/* save text mode palette */
savepalette(text_red, text_green, text_blue);
 
/* shift to color emulation */
setcoloremulation();
 
initialized = 1;
/* vga_unlockvc(); */
 
}
 
void vga_gettextfont(void *font)
{
unsigned int getsize;
 
getsize = fontbufsize;
if (getsize > FONT_SIZE)
getsize = FONT_SIZE;
memcpy(font, font_buf1, getsize);
if (fontbufsize > getsize)
memset(((char *)font) + getsize, 0, (size_t)(fontbufsize - getsize));
}
 
void vga_puttextfont(void *font)
{
unsigned int putsize;
 
putsize = fontbufsize;
if (putsize > FONT_SIZE)
putsize = FONT_SIZE;
memcpy(font_buf1, font, putsize);
memcpy(font_buf2, font, putsize);
if (putsize < FONT_SIZE) {
memset(font_buf1 + putsize, 0, (size_t)(FONT_SIZE - putsize));
memset(font_buf2 + putsize, 0, (size_t)(FONT_SIZE - putsize));
}
 
}
 
int vga_setmode(int mode,int set_chipset)
{
int modeflags=mode&0xfffff000;
#ifndef VM86
BYTE p1,p2;
#endif
printk(KERN_INFO "Setmode %i from %i\n", mode, CM);
 
if(mode==-1)return vga_version;
mode&=0xfff;
if (!initialized) {
if (mode == TEXT) return 0;
initialize(set_chipset);
}
 
if (mode != TEXT && !chipset_modeavailable(mode)) {
return -1;
}
// __svgalib_disable_interrupt();
 
prv_mode = CM;
CM = mode;
 
/* disable video */
vga_screenoff();
 
if (mode == TEXT) {
/* Returning to textmode. */
 
X_REGS16 inregs, outregs;
X_SREGS16 sregs;
 
inregs.x.ax = 0x03;
#ifndef VM86
p1 = inp(0x21);
p2 = inp(0xA1);
outp(0x21,0xFF);
outp(0xA1,0xFF);
X_callBIOS(0x10, &inregs, &outregs, &sregs);
outp(0x21,p1);
outp(0xA1,p2);
#else
vm86_callBIOS(0x10, &inregs, &outregs, &sregs);
#endif
if (SVGAMODE(prv_mode)) vga_setpage(0);
 
} else {
/* Setting a graphics mode. */
 
if (SVGAMODE(prv_mode)) {
/* The current mode is an SVGA mode, and we now want to */
/* set a standard VGA mode. Make sure the extended regs */
/* are restored. */
/* Also used when setting another SVGA mode to hopefully */
/* eliminate lock-ups. */
vga_setpage(0);
chipset_setregs(text_regs, mode);
/* restore old extended regs */
}
/* shift to color emulation */
setcoloremulation();
 
CI.xdim = infotable[mode].xdim;
CI.ydim = infotable[mode].ydim;
CI.colors = infotable[mode].colors;
CI.xbytes = infotable[mode].xbytes;
CI.bytesperpixel = infotable[mode].bytesperpixel;
 
chipset_setmode(mode, prv_mode);
MODEX = 0;
 
/* Set default claimed memory (moved here from initialize - Michael.) */
if (mode == G320x200x256)
VMEM = 65536;
else if (STDVGAMODE(mode))
VMEM = 256 * 1024; /* Why always 256K ??? - Michael */
else {
vga_modeinfo *modeinfo;
 
modeinfo = vga_getmodeinfo(mode);
VMEM = modeinfo->linewidth * modeinfo->height;
CI.xbytes = modeinfo->linewidth;
}
 
if (!flip) {
/* set default palette */
if (CI.colors <= 256)
restorepalette(default_red, default_green, default_blue);
 
/* clear screen (sets current color to 15) */
__svgalib_currentpage = -1;
if(!(modeflags&0x8000))vga_clear();
 
if (SVGAMODE(CM))
vga_setpage(0);
}
__svgalib_currentpage = -1;
currentlogicalwidth = CI.xbytes;
currentdisplaystart = 0;
 
/* enable video */
if (!flip)
vga_screenon();
 
{
vga_modeinfo *modeinfo;
modeinfo = vga_getmodeinfo(mode);
MODEX = ((MODEFLAGS = modeinfo->flags) & IS_MODEX);
}
 
// __svgalib_enable_interrupt();
}
 
return 0;
 
}
 
inline void copy_videomem_32to16(void *src, void *dst, unsigned long int memdiv2)
{
__asm__ __volatile__("push %%esi
push %%edi
movl %1, %%esi
movl %2, %%edi
1:
movl (%%esi), %%edx
xorl %%ebx, %%ebx
xorw %%ax, %%ax
movb %%dl, %%al
shrl $0x8, %%edx
shrw $0x3, %%ax
orw %%ax, %%bx
shll $0x6, %%ebx
xorw %%ax, %%ax
movb %%dl, %%al
shrl $0x8, %%edx
shrw $0x2, %%ax
orw %%ax, %%bx
shll $0x5, %%ebx
xorw %%ax, %%ax
movb %%dl, %%al
shrw $0x3, %%ax
orw %%ax, %%bx
shll $0x5, %%ebx
incl %%esi
incl %%esi
incl %%esi
incl %%esi
movl (%%esi), %%edx
xorw %%ax, %%ax
movb %%dl, %%al
shrl $0x8,%%edx
shrw $0x3, %%ax
orw %%ax, %%bx
shll $0x6, %%ebx
xorw %%ax, %%ax
movb %%dl, %%al
shrl $0x8, %%edx
shrw $0x2, %%ax
orw %%ax, %%bx
shll $0x5, %%ebx
xorw %%ax, %%ax
movb %%dl, %%al
shrw $0x3, %%ax
orw %%ax, %%bx
rorl $0x10, %%ebx
movl %%ebx, (%%edi)
incl %%esi
incl %%esi
incl %%esi
incl %%esi
incl %%edi
incl %%edi
incl %%edi
incl %%edi
loop 1b
pop %%edi
pop %%esi"
:
: "c" (memdiv2), "a" (src), "b" (dst));
 
}
 
inline void copy_videomem_16to16(void *src, void *dst, unsigned long int memdiv4)
{
__asm__ __volatile__("push %%esi
push %%edi
movl %1, %%esi
movl %2, %%edi
cld
rep
movsl
pop %%edi
pop %%esi"
:
: "c" (memdiv4), "a" (src), "b" (dst));
 
}
/shark/tags/rel_0_5/drivers/svga/vgaregs.c
0,0 → 1,122
 
#include "timing.h"
#include "vgaregs.h"
 
 
/*
* Setup VGA registers for SVGA mode timing. Adapted from XFree86,
* vga256/vga/vgaHW.c vgaHWInit().
*
* Note that VGA registers are set up in a way that is common for
* SVGA modes. This is not particularly useful for standard VGA
* modes, since VGA does not have a clean packed-pixel mode.
*/
 
void __svgalib_setup_VGA_registers(unsigned char *moderegs, ModeTiming * modetiming,
ModeInfo * modeinfo)
{
int i;
/* Sync Polarities */
if ((modetiming->flags & (PHSYNC | NHSYNC)) &&
(modetiming->flags & (PVSYNC | NVSYNC))) {
/*
* If both horizontal and vertical polarity are specified,
* set them as specified.
*/
moderegs[VGA_MISCOUTPUT] = 0x23;
if (modetiming->flags & NHSYNC)
moderegs[VGA_MISCOUTPUT] |= 0x40;
if (modetiming->flags & NVSYNC)
moderegs[VGA_MISCOUTPUT] |= 0x80;
} else {
/*
* Otherwise, calculate the polarities according to
* monitor standards.
*/
if (modetiming->VDisplay < 400)
moderegs[VGA_MISCOUTPUT] = 0xA3;
else if (modetiming->VDisplay < 480)
moderegs[VGA_MISCOUTPUT] = 0x63;
else if (modetiming->VDisplay < 768)
moderegs[VGA_MISCOUTPUT] = 0xE3;
else
moderegs[VGA_MISCOUTPUT] = 0x23;
}
 
/* Sequencer */
moderegs[VGA_SR0] = 0x00;
if (modeinfo->bitsPerPixel == 4)
moderegs[VGA_SR0] = 0x02;
moderegs[VGA_SR1] = 0x01;
moderegs[VGA_SR2] = 0x0F; /* Bitplanes. */
moderegs[VGA_SR3] = 0x00;
moderegs[VGA_SR4] = 0x0E;
if (modeinfo->bitsPerPixel == 4)
moderegs[VGA_SR4] = 0x06;
 
/* CRTC Timing */
moderegs[VGA_CR0] = (modetiming->CrtcHTotal / 8) - 5;
moderegs[VGA_CR1] = (modetiming->CrtcHDisplay / 8) - 1;
moderegs[VGA_CR2] = (modetiming->CrtcHSyncStart / 8) - 1;
moderegs[VGA_CR3] = ((modetiming->CrtcHSyncEnd / 8) & 0x1F) | 0x80;
moderegs[VGA_CR4] = (modetiming->CrtcHSyncStart / 8);
moderegs[VGA_CR5] = (((modetiming->CrtcHSyncEnd / 8) & 0x20) << 2)
| ((modetiming->CrtcHSyncEnd / 8) & 0x1F);
moderegs[VGA_CR6] = (modetiming->CrtcVTotal - 2) & 0xFF;
moderegs[VGA_CR7] = (((modetiming->CrtcVTotal - 2) & 0x100) >> 8)
| (((modetiming->CrtcVDisplay - 1) & 0x100) >> 7)
| ((modetiming->CrtcVSyncStart & 0x100) >> 6)
| (((modetiming->CrtcVSyncStart) & 0x100) >> 5)
| 0x10
| (((modetiming->CrtcVTotal - 2) & 0x200) >> 4)
| (((modetiming->CrtcVDisplay - 1) & 0x200) >> 3)
| ((modetiming->CrtcVSyncStart & 0x200) >> 2);
moderegs[VGA_CR8] = 0x00;
moderegs[VGA_CR9] = ((modetiming->CrtcVSyncStart & 0x200) >> 4) | 0x40;
if (modetiming->flags & DOUBLESCAN)
moderegs[VGA_CR9] |= 0x80;
moderegs[VGA_CRA] = 0x00;
moderegs[VGA_CRB] = 0x00;
moderegs[VGA_CRC] = 0x00;
moderegs[VGA_CRD] = 0x00;
moderegs[VGA_CRE] = 0x00;
moderegs[VGA_CRF] = 0x00;
moderegs[VGA_CR10] = modetiming->CrtcVSyncStart & 0xFF;
moderegs[VGA_CR11] = (modetiming->CrtcVSyncEnd & 0x0F) | 0x20;
moderegs[VGA_CR12] = (modetiming->CrtcVDisplay - 1) & 0xFF;
moderegs[VGA_CR13] = modeinfo->lineWidth >> 4; /* Just a guess. */
moderegs[VGA_CR14] = 0x00;
moderegs[VGA_CR15] = modetiming->CrtcVSyncStart & 0xFF;
moderegs[VGA_CR16] = (modetiming->CrtcVSyncStart + 1) & 0xFF;
moderegs[VGA_CR17] = 0xC3;
if (modeinfo->bitsPerPixel == 4)
moderegs[VGA_CR17] = 0xE3;
moderegs[VGA_CR18] = 0xFF;
 
/* Graphics Controller */
moderegs[VGA_GR0] = 0x00;
moderegs[VGA_GR1] = 0x00;
moderegs[VGA_GR2] = 0x00;
moderegs[VGA_GR3] = 0x00;
moderegs[VGA_GR4] = 0x00;
moderegs[VGA_GR5] = 0x40;
if (modeinfo->bitsPerPixel == 4)
moderegs[VGA_GR5] = 0x02;
moderegs[VGA_GR6] = 0x05;
moderegs[VGA_GR7] = 0x0F;
moderegs[VGA_GR8] = 0xFF;
 
/* Attribute Controller */
for (i = 0; i < 16; i++)
moderegs[VGA_AR0 + i] = i;
moderegs[VGA_AR10] = 0x41;
if (modeinfo->bitsPerPixel == 4)
moderegs[VGA_AR10] = 0x01; /* was 0x81 */
/* Attribute register 0x11 is the overscan color.
Should have no affect in svga modes. */
moderegs[VGA_AR11] = 0x00;
moderegs[VGA_AR12] = 0x0F;
moderegs[VGA_AR13] = 0x00;
moderegs[VGA_AR14] = 0x00;
}
 
/shark/tags/rel_0_5/drivers/svga/interface.c
0,0 → 1,98
 
#include <stdlib.h>
#include <string.h>
 
#include "timing.h"
#include "libvga.h" /* for __svgalib_infotable and ramdac inlines */
#include "ramdac.h" //SHARK
#include "accel.h"
 
 
/*
* This is a temporary function that allocates and fills in a ModeInfo
* structure based on a svgalib mode number.
*/
 
ModeInfo *
__svgalib_createModeInfoStructureForSvgalibMode(int mode)
{
ModeInfo *modeinfo;
/* Create the new ModeInfo structure. */
modeinfo = malloc(sizeof(ModeInfo));
modeinfo->width = __svgalib_infotable[mode].xdim;
modeinfo->height = __svgalib_infotable[mode].ydim;
modeinfo->bytesPerPixel = __svgalib_infotable[mode].bytesperpixel;
switch (__svgalib_infotable[mode].colors) {
case 16:
modeinfo->colorBits = 4;
break;
case 256:
modeinfo->colorBits = 8;
break;
case 32768:
modeinfo->colorBits = 15;
modeinfo->blueOffset = 0;
modeinfo->greenOffset = 5;
modeinfo->redOffset = 10;
modeinfo->blueWeight = 5;
modeinfo->greenWeight = 5;
modeinfo->redWeight = 5;
break;
case 65536:
modeinfo->colorBits = 16;
modeinfo->blueOffset = 0;
modeinfo->greenOffset = 5;
modeinfo->redOffset = 11;
modeinfo->blueWeight = 5;
modeinfo->greenWeight = 6;
modeinfo->redWeight = 5;
break;
case 256 * 65536:
modeinfo->colorBits = 24;
modeinfo->blueOffset = 0;
modeinfo->greenOffset = 8;
modeinfo->redOffset = 16;
modeinfo->blueWeight = 8;
modeinfo->greenWeight = 8;
modeinfo->redWeight = 8;
break;
}
modeinfo->bitsPerPixel = modeinfo->bytesPerPixel * 8;
if (__svgalib_infotable[mode].colors == 16)
modeinfo->bitsPerPixel = 4;
modeinfo->lineWidth = __svgalib_infotable[mode].xbytes;
return modeinfo;
}
 
 
/*
* This function converts a number of significant color bits to a matching
* DAC mode type as defined in the RAMDAC interface.
*/
 
int __svgalib_colorbits_to_colormode(int bpp, int colorbits)
{
if (colorbits == 8)
return CLUT8_6;
if (colorbits == 15)
return RGB16_555;
if (colorbits == 16)
return RGB16_565;
if (colorbits == 24) {
if (bpp == 24)
return RGB24_888_B;
else
return RGB32_888_B;
}
return CLUT8_6;
}
 
 
/*
* Clear the accelspecs structure (disable acceleration).
*/
 
void __svgalib_clear_accelspecs(AccelSpecs * accelspecs)
{
memset(accelspecs, 0, sizeof(AccelSpecs));
}
/shark/tags/rel_0_5/drivers/svga/vgarelvgaio.c
0,0 → 1,166
#include "libvga.h"
 
int __svgalib_io_reloc;
 
int __svgalib_rel_inmisc(void)
{
return port_in(MIS_R+__svgalib_io_reloc);
}
 
void __svgalib_rel_outmisc(int i)
{
outb(MIS_W+__svgalib_io_reloc,i);
}
 
int __svgalib_rel_incrtc(int i)
{
outb(__svgalib_CRT_I+__svgalib_io_reloc,i);
return port_in(__svgalib_CRT_D+__svgalib_io_reloc);
}
 
void __svgalib_rel_outcrtc(int i, int d)
{
outb(__svgalib_CRT_I+__svgalib_io_reloc, i);
outb(__svgalib_CRT_D+__svgalib_io_reloc, d);
}
 
int __svgalib_rel_inseq(int index)
{
outb(SEQ_I+__svgalib_io_reloc, index);
return port_in(SEQ_D+__svgalib_io_reloc);
}
 
void __svgalib_rel_outseq(int index, int val)
{
outb(SEQ_I+__svgalib_io_reloc, index);
outb(SEQ_D+__svgalib_io_reloc, val);
}
 
int __svgalib_rel_ingra(int index)
{
outb(GRA_I+__svgalib_io_reloc, index);
return port_in(GRA_D+__svgalib_io_reloc);
}
 
void __svgalib_rel_outgra(int index, int val)
{
outb(GRA_I+__svgalib_io_reloc, index);
outb(GRA_D+__svgalib_io_reloc, val);
}
 
int __svgalib_rel_inis1(void)
{
return port_in(__svgalib_IS1_R+__svgalib_io_reloc);
}
 
#ifdef NO_DELAY
 
int __svgalib_rel_inatt(int index)
{
__svgalib_rel_inis1();
outb(ATT_IW+__svgalib_io_reloc, index);
return port_in(ATT_R+__svgalib_io_reloc);
}
 
void __svgalib_rel_outatt(int index, int val)
{
__svgalib_rel_inis1();
outb(ATT_IW+__svgalib_io_reloc, index);
outb(ATT_IW+__svgalib_io_reloc, val);
}
 
void __svgalib_rel_attscreen(int i)
{
__svgalib_rel_inis1();
outb(ATT_IW+__svgalib_io_reloc, i);
}
 
void __svgalib_rel_inpal(int i, int *r, int *g, int *b)
{
outb(PEL_IR+__svgalib_io_reloc,i);
*r=port_in(PEL_D+__svgalib_io_reloc);
*g=port_in(PEL_D+__svgalib_io_reloc);
*b=port_in(PEL_D+__svgalib_io_reloc);
}
 
void __svgalib_rel_outpal(int i, int r, int g, int b)
{
 
outb(PEL_IW+__svgalib_io_reloc,i);
outb(PEL_D+__svgalib_io_reloc,r);
outb(PEL_D+__svgalib_io_reloc,g);
outb(PEL_D+__svgalib_io_reloc,b);
}
 
#else /* NO_DELAY */
 
int __svgalib_rel_inatt(int index)
{
__svgalib_delay();
__svgalib_rel_inis1();
__svgalib_delay();
outb(ATT_IW+__svgalib_io_reloc, index);
__svgalib_delay();
return port_in(ATT_R+__svgalib_io_reloc);
}
 
void __svgalib_rel_outatt(int index, int val)
{
__svgalib_delay();
__svgalib_rel_inis1();
__svgalib_delay();
outb(ATT_IW+__svgalib_io_reloc, index);
__svgalib_delay();
outb(ATT_IW+__svgalib_io_reloc, val);
}
 
void __svgalib_rel_attscreen(int i)
{
__svgalib_delay();
__svgalib_rel_inis1();
__svgalib_delay();
outb(ATT_IW+__svgalib_io_reloc, i);
}
 
void __svgalib_rel_inpal(int i, int *r, int *g, int *b)
{
outb(PEL_IR+__svgalib_io_reloc,i);
__svgalib_delay();
*r=port_in(PEL_D+__svgalib_io_reloc);
__svgalib_delay();
*g=port_in(PEL_D+__svgalib_io_reloc);
__svgalib_delay();
*b=port_in(PEL_D+__svgalib_io_reloc);
}
 
void __svgalib_rel_outpal(int i, int r, int g, int b)
{
 
outb(PEL_D+__svgalib_io_reloc,i);
__svgalib_delay();
outb(PEL_D+__svgalib_io_reloc,r);
__svgalib_delay();
outb(PEL_D+__svgalib_io_reloc,g);
__svgalib_delay();
outb(PEL_D+__svgalib_io_reloc,b);
}
 
#endif /* NO_DELAY */
 
void __svgalib_rel_io_mapio(void)
{
__svgalib_inmisc=__svgalib_rel_inmisc;
__svgalib_outmisc=__svgalib_rel_outmisc;
__svgalib_incrtc=__svgalib_rel_incrtc;
__svgalib_outcrtc=__svgalib_rel_outcrtc;
__svgalib_inseq=__svgalib_rel_inseq;
__svgalib_outseq=__svgalib_rel_outseq;
__svgalib_ingra=__svgalib_rel_ingra;
__svgalib_outgra=__svgalib_rel_outgra;
__svgalib_inatt=__svgalib_rel_inatt;
__svgalib_outatt=__svgalib_rel_outatt;
__svgalib_attscreen=__svgalib_rel_attscreen;
__svgalib_inis1=__svgalib_rel_inis1;
__svgalib_inpal=__svgalib_rel_inpal;
__svgalib_outpal=__svgalib_rel_outpal;
}
/shark/tags/rel_0_5/drivers/svga/accel.c
0,0 → 1,20
 
#include "vga.h"
#include "timing.h"
#include "accel.h"
 
 
int __svgalib_accel_screenpitch;
int __svgalib_accel_bytesperpixel;
int __svgalib_accel_screenpitchinbytes;
int __svgalib_accel_mode;
int __svgalib_accel_bitmaptransparency;
 
void __svgalib_InitializeAcceleratorInterface(ModeInfo * modeinfo)
{
__svgalib_accel_screenpitch = modeinfo->lineWidth / modeinfo->bytesPerPixel;
__svgalib_accel_bytesperpixel = modeinfo->bytesPerPixel;
__svgalib_accel_screenpitchinbytes = modeinfo->lineWidth;
__svgalib_accel_mode = BLITS_SYNC;
__svgalib_accel_bitmaptransparency = 0;
}
/shark/tags/rel_0_5/drivers/svga/vgapci.c
0,0 → 1,168
#include <stdlib.h>
#include <linux/pci.h>
 
#include <asm/types.h>
#include <asm/io.h>
 
#include "endianess.h"
#include "libvga.h"
#include "svgalib_helper.h"
#include "interrupt.h"
 
static struct sh_pci_device graph_dev;
static struct pci_dev dev;
 
DWORD __svgalib_pci_read_config_dword(int pos, int address);
 
int init_vgapci(void)
{
int i;
DWORD result;
BYTE bus,dv;
 
printk(KERN_DEBUG "Initializing PCI BUS...\n");
memset(&graph_dev,0,sizeof(struct pci_dev));
 
/* Scan the devices connected to the PCI bus */
if (pci_init() == 1) {
clear();
pci_show();
} else {
return -1;
}
 
if(pci_present()) {
pci_class(PCI_CLASS_DISPLAY_VGA<<8,0,&bus,&dv);
dev.bus->number = bus;
dev.devfn = dv;
memcpy(&(graph_dev.dev),&dev,sizeof(struct pci_dev));
pci_read_config_word(&dev,0,&(graph_dev.vendor));
pci_read_config_word(&dev,2,&(graph_dev.id));
pci_read_config_byte(&dev,8,&(graph_dev.revision));
printk(KERN_INFO "VGA Vendor:%.4x id:%.4x bus:%d dev:%d\n",\
graph_dev.vendor,graph_dev.id,bus,dv);
for(i=0;i<6;i++){
DWORD t;
int len;
pci_read_config_dword(&dev,16+4*i,&result);
if(result) {
pci_write_config_dword(&dev,16+4*i,0xffffffff);
pci_read_config_dword(&dev,16+4*i,&t);
pci_write_config_dword(&dev,16+4*i,result);
len = ~(t&~0xf)+1;
if (len){
graph_dev.mem[i]=result&~0xf;
graph_dev.flags[i]=0x80 | (result&0xf);
graph_dev.len[i]=len;
graph_dev.mask[i]=t&~0xf;
printk(KERN_INFO "region%d, base=%.8x len=%d type=%d\n",\
i, result&(~0xf), len, result&0xf);
}
}
}
vga_init_vsync(&graph_dev);
}
return 0;
 
}
 
static int proc_pci_read_config(DWORD *buf, int size)
{
int i;
 
for(i=0;i<size;i++) {
buf[i]=__svgalib_pci_read_config_dword(0,i*4);
}
return 0;
};
 
/*
find a vga device of the specified vendor, and return
its configuration (64 dwords) in conf
return zero if device found.
*/
 
int __svgalib_pci_find_vendor_vga(unsigned int vendor, unsigned long *conf, int cont)
{
DWORD buf[64];
 
proc_pci_read_config(buf,64);
if(((buf[0]&0xffff)==vendor)&&
(((buf[2]>>16)&0xffff)==0x0300)) { /* VGA Class */
memcpy(conf,buf,256);
return 0;
}
return 1;
 
}
 
unsigned char __svgalib_pci_read_config_byte(int pos, int address)
{
u8 t;
 
pci_read_config_byte(&dev, (BYTE)address, &t);
 
return t;
 
};
 
unsigned int __svgalib_pci_read_config_word(int pos, int address)
{
u16 t;
pci_read_config_word(&dev, (BYTE)address, &t);
return t;
};
 
DWORD __svgalib_pci_read_config_dword(int pos, int address)
{
DWORD t;
pci_read_config_dword(&dev, (BYTE)address, &t);
return t;
};
 
int __svgalib_pci_read_aperture_len(int pos, int address)
{
 
return graph_dev.len[address];
};
 
void __svgalib_pci_write_config_byte(int pos, int address, unsigned char data)
{
 
pci_write_config_byte(&dev, (BYTE)address, data);
 
};
 
void __svgalib_pci_write_config_word(int pos, int address, unsigned int data)
{
pci_write_config_word(&dev, (BYTE)address, data);
 
};
 
void __svgalib_pci_write_config_dword(int pos, int address, DWORD data)
{
 
pci_write_config_dword(&dev, (BYTE)address, data);
};
 
/shark/tags/rel_0_5/drivers/svga/modetab.c
0,0 → 1,27
/*
** modetab.c - part of svgalib
** (C) 1993 by Hartmut Schirmer
**
** A modetable holds a pair of values
** for each mode :
**
** <mode number> <pointer to registers>
**
** the last entry is marked by
**
** <any number> <NULL>
*/
 
#include <stdlib.h>
#include "driver.h"
 
const unsigned char *
__svgalib_mode_in_table(const ModeTable * modes, int mode)
{
while (modes->regs != NULL) {
if (modes->mode_number == mode)
return modes->regs;
modes++;
}
return NULL;
}
/shark/tags/rel_0_5/drivers/svga/vgaclear.c
0,0 → 1,68
/* VGAlib version 1.2 - (c) 1993 Tommy Frandsen */
/* */
/* This library is free software; you can redistribute it and/or */
/* modify it without any restrictions. This library is distributed */
/* in the hope that it will be useful, but without any warranty. */
 
/* Multi-chipset support Copyright 1993 Harm Hanemaayer */
/* partially copyrighted (C) 1993 by Hartmut Schirmer */
 
#include <stdio.h>
#include <string.h>
#include "vga.h"
#include "libvga.h"
#include "driver.h"
 
int vga_clear(void)
{
vga_screenoff();
if (MODEX)
goto modeX;
switch (CM) {
case G320x200x256:
case G320x240x256:
case G320x400x256:
case G360x480x256:
case G400x300x256X:
modeX:
/* write to all planes */
__svgalib_outseq(0x02,0x0f);
/* clear video memory */
memset(GM, 0, 65536);
break;
 
default:
switch (CI.colors) {
case 2:
case 16:
vga_setcolor(0);
 
/* write to all bits */
__svgalib_outseq(0x08,0xff);
 
default:
{
int i;
int pages = (CI.ydim * CI.xbytes + 65535) >> 16;
if (__svgalib_modeinfo_linearset & IS_LINEAR ) {
memset(LINEAR_POINTER, 0, pages<<16);
} else {
for (i = 0; i < pages; ++i) {
vga_setpage(i);
/* clear video memory */
memset(GM, 0, 65536);
}
}
}
break;
}
break;
}
 
vga_setcolor(15);
vga_screenon();
 
return 0;
}
/shark/tags/rel_0_5/drivers/svga/vgaline.c
0,0 → 1,57
/* VGAlib version 1.2 - (c) 1993 Tommy Frandsen */
/* */
/* This library is free software; you can redistribute it and/or */
/* modify it without any restrictions. This library is distributed */
/* in the hope that it will be useful, but without any warranty. */
 
/* Multi-chipset support Copyright 1993 Harm Hanemaayer */
/* partially copyrighted (C) 1993 by Hartmut Schirmer */
 
#include <stdio.h>
#include "vga.h"
#include "libvga.h"
 
#define ABS(a) (((a)<0) ? -(a) : (a))
 
int vga_drawline(int x1, int y1, int x2, int y2)
{
int dx = x2 - x1;
int dy = y2 - y1;
int ax = ABS(dx) << 1;
int ay = ABS(dy) << 1;
int sx = (dx >= 0) ? 1 : -1;
int sy = (dy >= 0) ? 1 : -1;
 
int x = x1;
int y = y1;
 
if (ax > ay) {
int d = ay - (ax >> 1);
while (x != x2) {
vga_drawpixel(x, y);
 
if (d > 0 || (d == 0 && sx == 1)) {
y += sy;
d -= ax;
}
x += sx;
d += ay;
}
} else {
int d = ax - (ay >> 1);
while (y != y2) {
vga_drawpixel(x, y);
 
if (d > 0 || (d == 0 && sy == 1)) {
x += sx;
d -= ay;
}
y += sy;
d += ax;
}
}
vga_drawpixel(x, y);
 
return 0;
}
 
/shark/tags/rel_0_5/drivers/svga/interrupt.c
0,0 → 1,272
#include <linux/pci.h>
#include <asm/io.h>
#include <stdint.h>
#include "svgalib_helper.h"
 
#define ioremap(a,b) \
(((a)<0x100000) ? (void *)((u_long)(a)) : vremap(a,b))
#define iounmap(v) \
do { if ((u_long)(v) > 0x100000) vfree(v); } while (0)
 
int vga_test_vsync(struct sh_pci_device *dev) {
return inb(0x3c2)&0x80;
}
 
void vga_ack_vsync(struct sh_pci_device *dev) {
int pb;
/* disable interrupt, clear pending */
outb(0x11, 0x3d4);
pb = inb(0x3d5);
outb(0x11, 0x3d4);
outb((pb&0xef) | 0x20, 0x3d5);
}
 
void vga_enable_vsync(struct sh_pci_device *dev) {
int pb;
 
/* enable interrupt, clear pending */
outb(0x11, 0x3d4);
pb = inb(0x3d5);
outb(0x11, 0x3d4);
outb((pb&0xcf) , 0x3d5);
 
/* Allow interrupts */
outb(0x11, 0x3d4);
pb = inb(0x3d5);
outb(0x11, 0x3d4);
outb(pb | 0x10 , 0x3d5);
}
 
int io_test_vsync(struct sh_pci_device *dev) {
return inb(dev->iobase+0x3c2)&0x80;
}
 
void io_ack_vsync(struct sh_pci_device *dev) {
int pb;
/* disable interrupt, clear pending */
outb(0x11, dev->iobase+0x3d4);
pb = inb(dev->iobase+0x3d5);
outb(0x11, dev->iobase+0x3d4);
outb((pb&0xef) | 0x20, dev->iobase+0x3d5);
}
 
void io_enable_vsync(struct sh_pci_device *dev) {
int pb;
 
/* enable interrupt, clear pending */
outb(0x11, dev->iobase+0x3d4);
pb = inb(dev->iobase+0x3d5);
outb(0x11, dev->iobase+0x3d4);
outb((pb&0xcf) , dev->iobase+0x3d5);
 
/* Allow interrupts */
outb(0x11, dev->iobase+0x3d4);
pb = inb(dev->iobase+0x3d5);
outb(0x11, dev->iobase+0x3d4);
outb(pb | 0x10 , dev->iobase+0x3d5);
}
 
int mm_test_vsync(struct sh_pci_device *dev) {
return readb(dev->iobase+0x3c2)&0x80;
}
 
void mm_ack_vsync(struct sh_pci_device *dev) {
int pb;
/* disable interrupt, clear pending */
writeb(0x11, dev->iobase+0x3d4);
pb = readb(dev->iobase+0x3d5);
writeb(0x11, dev->iobase+0x3d4);
writeb((pb&0xef) | 0x20, dev->iobase+0x3d5);
}
 
void mm_enable_vsync(struct sh_pci_device *dev) {
int pb;
 
/* enable interrupt, clear pending */
writeb(0x11, dev->iobase+0x3d4);
pb = readb(dev->iobase+0x3d5);
writeb(0x11, dev->iobase+0x3d4);
writeb((pb&0xcf) , dev->iobase+0x3d5);
 
/* Allow interrupts */
writeb(0x11, dev->iobase+0x3d4);
pb = readb(dev->iobase+0x3d5);
writeb(0x11, dev->iobase+0x3d4);
writeb(pb | 0x10 , dev->iobase+0x3d5);
}
 
static uint32_t saved_pmc;
 
int nv3_test_vsync(struct sh_pci_device *dev) {
return readl(dev->iobase+0x400100)&0x100;
}
 
void nv3_ack_vsync(struct sh_pci_device *dev) {
 
/* disable interrupt, clear pending */
writel(0xffffffff, dev->iobase + 0x000100);
writel(0x100, dev->iobase + 0x400100);
writel(0, dev->iobase + 0x000140);
writel(0, dev->iobase + 0x400140);
writel(saved_pmc, dev->iobase + 0x000200);
 
}
 
void nv3_enable_vsync(struct sh_pci_device *dev) {
saved_pmc = inl(dev->iobase + 0x200);
writel(saved_pmc|0x1000, dev->iobase+0x200);
writel(0x1, dev->iobase + 0x000140);
writel(0x100, dev->iobase + 0x400140);
writel(0xffffffff, dev->iobase + 0x000100);
writel(0xffffffff, dev->iobase + 0x400100);
}
 
int nv4_test_vsync(struct sh_pci_device *dev) {
return readl(dev->iobase+0x600100)&0x1;
}
 
void nv4_ack_vsync(struct sh_pci_device *dev) {
 
/* disable interrupt, clear pending */
writel(0xffffffff, dev->iobase + 0x000100);
writel(0x1, dev->iobase + 0x600100);
writel(0, dev->iobase + 0x000140);
writel(0, dev->iobase + 0x600140);
writel(saved_pmc, dev->iobase + 0x000200);
}
 
void nv4_enable_vsync(struct sh_pci_device *dev) {
saved_pmc = inl(dev->iobase + 0x200);
writel(saved_pmc|(1<<24),dev->iobase+0x200);
writel(0x1, dev->iobase + 0x000140);
writel(0x1, dev->iobase + 0x600140);
writel(0xffffffff, dev->iobase + 0x000100);
writel(0xffffffff, dev->iobase + 0x600100);
}
 
int r128_test_vsync(struct sh_pci_device *dev) {
return readl(dev->iobase + 0x44) &1;
}
 
void r128_ack_vsync(struct sh_pci_device *dev) {
writel(1, dev->iobase + 0x44);
writel(readl(dev->iobase + 0x40) & 0xfffffffe, dev->iobase + 0x40);
}
 
void r128_enable_vsync(struct sh_pci_device *dev) {
writel(1, dev->iobase + 0x44);
writel(readl(dev->iobase + 0x40) | 1, dev->iobase + 0x40);
}
 
int rage_test_vsync(struct sh_pci_device *dev) {
return inl(dev->iobase + 0x18) &4;
}
 
void rage_ack_vsync(struct sh_pci_device *dev) {
outl((inl(dev->iobase + 0x18) & 0xfffffff8) | 4, dev->iobase + 0x18);
}
 
void rage_enable_vsync(struct sh_pci_device *dev) {
outl((inl(dev->iobase + 0x18) & 0xfffffff8) | 6, dev->iobase + 0x18);
}
 
int rendition_test_vsync(struct sh_pci_device *dev) {
return inw(dev->iobase + 0x44) & 1;
}
 
void rendition_ack_vsync(struct sh_pci_device *dev) {
outw(1, dev->iobase + 0x44);
outw(0, dev->iobase + 0x46);
}
 
void rendition_enable_vsync(struct sh_pci_device *dev) {
outw(1, dev->iobase + 0x44);
outw(1, dev->iobase + 0x46);
}
 
void vga_init_vsync(struct sh_pci_device *dev) {
int i, id;
switch(dev->vendor) {
case PCI_VENDOR_ID_MATROX:
i=0;
if(dev->len[0]>=1048576)i=1;
dev->iobase = (unsigned long)ioremap(dev->mem[i],0x2000) + 0x1c00;
dev->test_vsync = mm_test_vsync;
dev->ack_vsync = mm_ack_vsync;
dev->enable_vsync = mm_enable_vsync;
break;
case PCI_VENDOR_ID_SI: /* SiS */
dev->iobase = dev->mem[2]-0x380;
dev->test_vsync = io_test_vsync;
dev->ack_vsync = io_ack_vsync;
dev->enable_vsync = io_enable_vsync;
break;
case PCI_VENDOR_ID_NVIDIA_SGS:
dev->iobase = (unsigned long)ioremap(dev->mem[0],0x800000);
if(dev->id<0x20) {
dev->test_vsync = nv3_test_vsync;
dev->ack_vsync = nv3_ack_vsync;
dev->enable_vsync = nv3_enable_vsync;
} else {
dev->test_vsync = nv4_test_vsync;
dev->ack_vsync = nv4_ack_vsync;
dev->enable_vsync = nv4_enable_vsync;
}
break;
case PCI_VENDOR_ID_NVIDIA:
dev->iobase = (unsigned long)ioremap(dev->mem[0],0x800000);
dev->test_vsync = nv4_test_vsync;
dev->ack_vsync = nv4_ack_vsync;
dev->enable_vsync = nv4_enable_vsync;
break;
case PCI_VENDOR_ID_ATI:
id=dev->id;
if( (id==0x4c45) ||
(id==0x4c56) ||
(id==0x4d46) ||
(id==0x4d4c) ||
((id>>8)==0x50) ||
((id>>8)==0x52) ||
((id>>8)==0x53) ||
((id>>8)==0x54)) {
dev->iobase = (unsigned long)ioremap(dev->mem[2], 16384);
dev->test_vsync = r128_test_vsync;
dev->ack_vsync = r128_ack_vsync;
dev->enable_vsync = r128_enable_vsync;
} else
if( (id==0x4242) ||
(id==0x4c57) ||
(id==0x4c59) ||
(id==0x4c5a) ||
((id>>8)==0x51)) {
dev->iobase = (unsigned long)ioremap(dev->mem[2], 16384);
dev->test_vsync = r128_test_vsync;
dev->ack_vsync = r128_ack_vsync;
dev->enable_vsync = r128_enable_vsync;
} else {
dev->iobase = dev->mem[1];
dev->test_vsync = rage_test_vsync;
dev->ack_vsync = rage_ack_vsync;
dev->enable_vsync = rage_enable_vsync;
 
}
break;
case PCI_VENDOR_ID_RENDITION:
dev->iobase = dev->mem[1];
dev->test_vsync = rendition_test_vsync;
dev->ack_vsync = rendition_ack_vsync;
dev->enable_vsync = rendition_enable_vsync;
break;
default:
dev->test_vsync = vga_test_vsync;
dev->ack_vsync = vga_ack_vsync;
dev->enable_vsync = vga_enable_vsync;
dev->iobase = 0;
}
}
 
/shark/tags/rel_0_5/drivers/svga/nv3io.c
0,0 → 1,105
static int __svgalib_nv3_inmisc(void)
{
return v_readb(NV_PVGA0+MIS_R);
}
 
static void __svgalib_nv3_outmisc(int i)
{
v_writeb(i, NV_PVGA0+MIS_W);
}
 
static int __svgalib_nv3_incrtc(int i)
{
v_writeb(i, NV_PVGA1+__svgalib_CRT_I);
return v_readb(NV_PVGA1+__svgalib_CRT_D);
}
 
static void __svgalib_nv3_outcrtc(int i, int d)
{
v_writeb(i, NV_PVGA1+__svgalib_CRT_I);
v_writeb(d, NV_PVGA1+__svgalib_CRT_D);
}
 
static int __svgalib_nv3_inseq(int index)
{
v_writeb(index, NV_PVGA0+SEQ_I);
return v_readb(NV_PVGA0+SEQ_D);
}
 
static void __svgalib_nv3_outseq(int index, int val)
{
v_writeb(index, NV_PVGA0+SEQ_I);
v_writeb(val, NV_PVGA0+SEQ_D);
}
 
static int __svgalib_nv3_ingra(int index)
{
v_writeb(index, NV_PVGA0+GRA_I);
return v_readb(NV_PVGA0+GRA_D);
}
 
static void __svgalib_nv3_outgra(int index, int val)
{
v_writeb(index, NV_PVGA0+GRA_I);
v_writeb(val, NV_PVGA0+GRA_D);
}
 
static int __svgalib_nv3_inis1(void)
{
return v_readb(NV_PVGA1+__svgalib_IS1_R);
}
 
static int __svgalib_nv3_inatt(int index)
{
__svgalib_nv3_inis1();
v_writeb(index, NV_PVGA1+ATT_IW);
return v_readb(NV_PVGA1+ATT_R);
}
 
static void __svgalib_nv3_outatt(int index, int val)
{
__svgalib_nv3_inis1();
v_writeb(index, NV_PVGA1+ATT_IW);
v_writeb(val, NV_PVGA1+ATT_IW);
}
 
static void __svgalib_nv3_attscreen(int i)
{
__svgalib_nv3_inis1();
v_writeb(i, NV_PVGA1+ATT_IW);
}
 
static void __svgalib_nv3_inpal(int i, int *r, int *g, int *b)
{
v_writeb(i, NV_PVGA2+PEL_IR);
*r=v_readb(NV_PVGA2+PEL_D);
*g=v_readb(NV_PVGA2+PEL_D);
*b=v_readb(NV_PVGA2+PEL_D);
}
 
static void __svgalib_nv3_outpal(int i, int r, int g, int b)
{
v_writeb(i, NV_PVGA2+PEL_IW);
v_writeb(r, NV_PVGA2+PEL_D);
v_writeb(g, NV_PVGA2+PEL_D);
v_writeb(b, NV_PVGA2+PEL_D);
}
 
static void nv3_mapio(void)
{
__svgalib_inmisc=__svgalib_nv3_inmisc;
__svgalib_outmisc=__svgalib_nv3_outmisc;
__svgalib_incrtc=__svgalib_nv3_incrtc;
__svgalib_outcrtc=__svgalib_nv3_outcrtc;
__svgalib_inseq=__svgalib_nv3_inseq;
__svgalib_outseq=__svgalib_nv3_outseq;
__svgalib_ingra=__svgalib_nv3_ingra;
__svgalib_outgra=__svgalib_nv3_outgra;
__svgalib_inatt=__svgalib_nv3_inatt;
__svgalib_outatt=__svgalib_nv3_outatt;
__svgalib_attscreen=__svgalib_nv3_attscreen;
__svgalib_inis1=__svgalib_nv3_inis1;
__svgalib_inpal=__svgalib_nv3_inpal;
__svgalib_outpal=__svgalib_nv3_outpal;
}
 
/shark/tags/rel_0_5/drivers/svga/vgaaccel.c
0,0 → 1,173
/* Written by Michael Weller and Harm Hanemaayer. */
 
 
#include <stdarg.h>
#include "vga.h"
#include "driver.h"
#include "timing.h"
#include "accel.h"
 
 
/*
* This calls one of the acceleration interface functions.
*/
 
int vga_accel(unsigned operation,...)
{
va_list params;
 
va_start(params, operation);
/* This is the fast interface which I thought of first: */
if (__svgalib_driverspecs->accel) {
int retval;
 
retval = (*(__svgalib_driverspecs->accel))(operation, params);
va_end(params);
return retval;
}
 
/* Do a quick availability check to avoid disasters. */
if (__svgalib_driverspecs->accelspecs == 0)
return -1;
/* Check for operation availability flag. */
if (!(__svgalib_driverspecs->accelspecs->operations & (1 << (operation - 1))))
return -1;
 
vga_lockvc();
 
/*
* gcc doesn't produce glorious code here, it's much better with
* only one va_arg traversal in a function.
*/
 
switch (operation) {
case ACCEL_FILLBOX:
{
int x, y, w, h;
x = va_arg(params, int);
y = va_arg(params, int);
w = va_arg(params, int);
h = va_arg(params, int);
(*__svgalib_driverspecs->accelspecs->FillBox) (x, y, w, h);
break;
}
case ACCEL_SCREENCOPY:
{
int x1, y1, x2, y2, w, h;
x1 = va_arg(params, int);
y1 = va_arg(params, int);
x2 = va_arg(params, int);
y2 = va_arg(params, int);
w = va_arg(params, int);
h = va_arg(params, int);
(*__svgalib_driverspecs->accelspecs->ScreenCopy) (x1, y1, x2, y2, w, h);
break;
}
case ACCEL_PUTIMAGE:
{
int x, y, w, h;
void *p;
x = va_arg(params, int);
y = va_arg(params, int);
w = va_arg(params, int);
h = va_arg(params, int);
p = va_arg(params, void *);
(*__svgalib_driverspecs->accelspecs->PutImage) (x, y, w, h, p);
break;
}
case ACCEL_DRAWLINE:
{
int x1, x2, y1, y2;
x1 = va_arg(params, int);
y1 = va_arg(params, int);
x2 = va_arg(params, int);
y2 = va_arg(params, int);
(*__svgalib_driverspecs->accelspecs->DrawLine) (x1, y1, x2, y2);
break;
}
case ACCEL_SETFGCOLOR:
{
int c;
c = va_arg(params, int);
(*__svgalib_driverspecs->accelspecs->SetFGColor) (c);
break;
}
case ACCEL_SETBGCOLOR:
{
int c;
c = va_arg(params, int);
(__svgalib_driverspecs->accelspecs->SetBGColor) (c);
break;
}
case ACCEL_SETTRANSPARENCY:
{
int m, c;
m = va_arg(params, int);
c = va_arg(params, int);
(*__svgalib_driverspecs->accelspecs->SetTransparency) (m, c);
break;
}
case ACCEL_SETRASTEROP:
{
int r;
r = va_arg(params, int);
(*__svgalib_driverspecs->accelspecs->SetRasterOp) (r);
break;
}
case ACCEL_PUTBITMAP:
{
int x, y, w, h;
void *p;
x = va_arg(params, int);
y = va_arg(params, int);
w = va_arg(params, int);
h = va_arg(params, int);
p = va_arg(params, void *);
(*__svgalib_driverspecs->accelspecs->PutBitmap) (x, y, w, h, p);
break;
}
case ACCEL_SCREENCOPYBITMAP:
{
int x1, y1, x2, y2, w, h;
x1 = va_arg(params, int);
y1 = va_arg(params, int);
x2 = va_arg(params, int);
y2 = va_arg(params, int);
w = va_arg(params, int);
h = va_arg(params, int);
(*__svgalib_driverspecs->accelspecs->ScreenCopyBitmap) (x1, y1, x2, y2, w, h);
break;
}
case ACCEL_DRAWHLINELIST:
{
int y, n, *x1, *x2;
y = va_arg(params, int);
n = va_arg(params, int);
x1 = va_arg(params, int *);
x2 = va_arg(params, int *);
(*__svgalib_driverspecs->accelspecs->DrawHLineList) (y, n, x1, x2);
break;
}
case ACCEL_SETMODE:
{
int m;
/* This isn't sent to the chipset-specific driver. */
m = va_arg(params, int);
if ((__svgalib_accel_mode & BLITS_IN_BACKGROUND)
&& !(m & BLITS_IN_BACKGROUND))
/* Make sure background blits are finished. */
(*__svgalib_driverspecs->accelspecs->Sync) ();
__svgalib_accel_mode = m;
break;
}
case ACCEL_SYNC:
(*__svgalib_driverspecs->accelspecs->Sync) ();
break;
} /* switch */
 
va_end(params);
 
vga_unlockvc();
 
return 0;
}
/shark/tags/rel_0_5/drivers/svga/vgaio.c
0,0 → 1,147
#include "libvga.h"
#include <stdio.h>
 
int __svgalib_vga_inmisc(void)
{
return port_in(MIS_R);
}
 
void __svgalib_vga_outmisc(int i)
{
outb(MIS_W,i);
}
 
int __svgalib_vga_incrtc(int i)
{
outb(__svgalib_CRT_I,i);
return port_in(__svgalib_CRT_D);
}
 
void __svgalib_vga_outcrtc(int i, int d)
{
outb(__svgalib_CRT_I, i);
outb(__svgalib_CRT_D, d);
}
 
int __svgalib_vga_inseq(int index)
{
outb(SEQ_I, index);
return port_in(SEQ_D);
}
 
void __svgalib_vga_outseq(int index, int val)
{
outb(SEQ_I, index);
outb(SEQ_D, val);
}
 
int __svgalib_vga_ingra(int index)
{
outb(GRA_I, index);
return port_in(GRA_D);
}
 
void __svgalib_vga_outgra(int index, int val)
{
outb(GRA_I, index);
outb(GRA_D, val);
}
 
int __svgalib_vga_inis1(void)
{
return port_in(__svgalib_IS1_R);
}
 
#ifdef NO_DELAY
 
int __svgalib_vga_inatt(int index)
{
__svgalib_vga_inis1();
outb(ATT_IW, index);
return port_in(ATT_R);
}
 
void __svgalib_vga_outatt(int index, int val)
{
__svgalib_vga_inis1();
outb(ATT_IW, index);
outb(ATT_IW, val);
}
 
void __svgalib_vga_attscreen(int i)
{
__svgalib_vga_inis1();
outb(ATT_IW, i);
}
 
void __svgalib_vga_inpal(int i, int *r, int *g, int *b)
{
outb(PEL_IR,i);
*r=port_in(PEL_D);
*g=port_in(PEL_D);
*b=port_in(PEL_D);
}
 
void __svgalib_vga_outpal(int i, int r, int g, int b)
{
 
outb(PEL_IW,i);
outb(PEL_D,r);
outb(PEL_D,g);
outb(PEL_D,b);
}
 
#else /* NO_DELAY */
 
int __svgalib_vga_inatt(int index)
{
__svgalib_delay();
__svgalib_vga_inis1();
__svgalib_delay();
outb(ATT_IW, index);
__svgalib_delay();
return port_in(ATT_R);
}
 
void __svgalib_vga_outatt(int index, int val)
{
__svgalib_delay();
__svgalib_vga_inis1();
__svgalib_delay();
outb(ATT_IW, index);
__svgalib_delay();
outb(ATT_IW, val);
}
 
void __svgalib_vga_attscreen(int i)
{
__svgalib_delay();
__svgalib_vga_inis1();
__svgalib_delay();
outb(ATT_IW, i);
}
 
void __svgalib_vga_inpal(int i, int *r, int *g, int *b)
{
outb(PEL_IR,i);
__svgalib_delay();
*r=port_in(PEL_D);
__svgalib_delay();
*g=port_in(PEL_D);
__svgalib_delay();
*b=port_in(PEL_D);
}
 
void __svgalib_vga_outpal(int i, int r, int g, int b)
{
 
outb(PEL_IW,i);
__svgalib_delay();
outb(PEL_D,r);
__svgalib_delay();
outb(PEL_D,g);
__svgalib_delay();
outb(PEL_D,b);
}
 
#endif /* NO_DELAY */
/shark/tags/rel_0_5/drivers/svga/nv3.c
0,0 → 1,845
/*
Riva 128 driver - Matan Ziv-Av matan@svgalib.org
please report problems to me,
 
This driver is based on the XFREE86 nv3 driver, developed by
David J. Mckay.
 
I used the file cirrus.c in this directory as a skeleton.
 
there are still the following problems:
* no 24bit modes. (maybe the hardware does not support)
* pageflipping (in threeDKit) does not work.
* no acceleration (is there a program that uses it anyway?).
*/
 
#include <stdlib.h>
#include <stdio.h> /* for printf */
#include <string.h> /* for memset */
//#include <sys/mman.h> //SHARK
#include <fcntl.h>
#include <math.h>
#include <unistd.h>
#include "vga.h"
#include "libvga.h"
#include "driver.h"
 
/* New style driver interface. */
#include "timing.h"
#include "vgaregs.h"
#include "interface.h"
#include "nv3ref.h"
#include "nvreg.h"
#include "vgapci.h"
 
#define REG(i) (VGA_TOTAL_REGS+i)
#define NV3_TOTAL_REGS (VGA_TOTAL_REGS + 24 + 40 )
 
#define P_MIN 0
 
#define SetBitField(value,from,to) SetBF(to,GetBF(value,from))
#define SetBit(n) (1<<(n))
#define Set8Bits(value) ((value)&0xff)
 
#define GET15BITCOLOR(r,g,b) ((((r)&0xf8)<<7)|(((g)&0xf8)<<2)|((b)>>3))
 
#include "nv3io.c"
 
static int nv3_init(int, int, int);
static void nv3_unlock(void);
 
static int memory, chip, nvnum;
static int nv3_is_linear;
static CardSpecs *cardspecs;
static int PLL_INPUT_FREQ, MAXVCLOCK, M_MIN, M_MAX, P_MAX;
 
static unsigned long MMIOBASE, LINEARBASE;
 
enum {
Riva128 = 0, RivaTNT, GEFORCE
};
 
static void nv3_setpage(int page)
{
__svgalib_outcrtc(0x1d,page << 1);
__svgalib_outcrtc(0x1e,page << 1);
}
 
static int __svgalib_nv3_inlinearmode(void)
{
return nv3_is_linear;
}
 
/* Fill in chipset specific mode information */
 
static void nv3_getmodeinfo(int mode, vga_modeinfo *modeinfo)
{
if(modeinfo->colors==16)return;
 
modeinfo->maxpixels = memory*1024/modeinfo->bytesperpixel;
modeinfo->maxlogicalwidth = 4088;
modeinfo->startaddressrange = memory * 1024 - 1;
modeinfo->haveblit = 0;
modeinfo->flags &= ~HAVE_RWPAGE;
 
if (modeinfo->bytesperpixel >= 1) {
modeinfo->flags |= CAPABLE_LINEAR;
if (__svgalib_nv3_inlinearmode())
modeinfo->flags |= IS_LINEAR | LINEAR_MODE;
}
}
 
/* Read and save chipset-specific registers */
 
static int nv3_saveregs(unsigned char regs[])
{
int i;
nv3_unlock(); /* May be locked again by other programs (e.g. X) */
 
regs[REG(0)] = __svgalib_incrtc(NV_PCRTC_REPAINT0);
regs[REG(1)] = __svgalib_incrtc(NV_PCRTC_REPAINT1);
regs[REG(2)] = __svgalib_incrtc(NV_PCRTC_EXTRA);
regs[REG(3)] = __svgalib_incrtc(NV_PCRTC_PIXEL);
regs[REG(4)] = __svgalib_incrtc(NV_PCRTC_HORIZ_EXTRA);
regs[REG(5)] = __svgalib_incrtc(NV_PCRTC_FIFO_CONTROL);
regs[REG(6)] = __svgalib_incrtc(NV_PCRTC_FIFO);
regs[REG(7)] = __svgalib_incrtc(NV_PCRTC_SCREEN);
 
*(uint32_t *)(regs+REG(8)) = v_readl(NV_PFB_CONFIG_0);
*(uint32_t *)(regs+REG(12)) = v_readl(NV_PRAMDAC_VPLL_COEFF);
*(uint32_t *)(regs+REG(16)) = v_readl(NV_PRAMDAC_PLL_COEFF_SELECT);
*(uint32_t *)(regs+REG(20)) = v_readl(NV_PRAMDAC_GENERAL_CONTROL);
*(uint32_t *)(regs+REG(56)) = v_readl(NV_PRAMDAC_GRCURSOR_START_POS);
for(i=0x18;i<0x3A;i++)regs[84+i-0x18]=__svgalib_incrtc(i);
return NV3_TOTAL_REGS - VGA_TOTAL_REGS;
}
 
/* Set chipset-specific registers */
 
static void nv3_setregs(const unsigned char regs[], int mode)
{
nv3_unlock(); /* May be locked again by other programs (eg. X) */
 
__svgalib_outcrtc(NV_PCRTC_REPAINT0,regs[REG(0)]);
__svgalib_outcrtc(NV_PCRTC_REPAINT1,regs[REG(1)]);
__svgalib_outcrtc(NV_PCRTC_EXTRA,regs[REG(2)]);
__svgalib_outcrtc(NV_PCRTC_PIXEL,regs[REG(3)]);
__svgalib_outcrtc(NV_PCRTC_HORIZ_EXTRA,regs[REG(4)]);
__svgalib_outcrtc(NV_PCRTC_FIFO_CONTROL,regs[REG(5)]);
__svgalib_outcrtc(NV_PCRTC_FIFO,regs[REG(6)]);
if(chip>= GEFORCE)
__svgalib_outcrtc(NV_PCRTC_SCREEN,regs[REG(7)]);
 
__svgalib_outcrtc(0x1c,regs[88]); /* this enables banking at 0xa0000 */
__svgalib_outcrtc(0x1d,regs[89]);
__svgalib_outcrtc(0x1e,regs[90]);
__svgalib_outcrtc(0x30,regs[108]);
__svgalib_outcrtc(0x31,regs[109]);
__svgalib_outcrtc(0x39,regs[117]);
 
v_writel(*(uint32_t *)(regs+REG(8)), NV_PFB_CONFIG_0);
 
v_writel(*(uint32_t *)(regs+REG(12)), NV_PRAMDAC_VPLL_COEFF);
v_writel(*(uint32_t *)(regs+REG(16)), NV_PRAMDAC_PLL_COEFF_SELECT);
v_writel(*(uint32_t *)(regs+REG(20)), NV_PRAMDAC_GENERAL_CONTROL);
v_writel(*(uint32_t *)(regs+REG(56)), NV_PRAMDAC_GRCURSOR_START_POS);
}
 
 
/* Return nonzero if mode is available */
 
static int nv3_modeavailable(int mode)
{
struct info *info;
ModeTiming *modetiming;
ModeInfo *modeinfo;
 
printk(KERN_INFO "Test Mode...\n");
if (IS_IN_STANDARD_VGA_DRIVER(mode))
return __svgalib_vga_driverspecs.modeavailable(mode);
 
info = &__svgalib_infotable[mode];
if (memory * 1024 < info->ydim * info->xbytes)
return 0;
modeinfo = __svgalib_createModeInfoStructureForSvgalibMode(mode);
 
if(modeinfo->bitsPerPixel==24) {
free(modeinfo);
return 0;
}
 
printk(KERN_INFO "Test Timing...\n");
modetiming = malloc(sizeof(ModeTiming));
if (__svgalib_getmodetiming(modetiming, modeinfo, cardspecs)) {
printk(KERN_INFO "Test Mode Failed !\n");
free(modetiming);
free(modeinfo);
return 0;
}
 
free(modetiming);
free(modeinfo);
return SVGADRV;
}
 
static int CalcVClock(int clockIn,int *clockOut,int *mOut,
int *nOut,int *pOut);
 
static int CalculateCRTC(ModeTiming *mode, ModeInfo *modeinfo, unsigned char *moderegs)
{
int bpp=modeinfo->bitsPerPixel/8,
horizDisplay = (mode->CrtcHDisplay/8) - 1,
horizStart = (mode->CrtcHSyncStart/8) - 0,
horizEnd = (mode->CrtcHSyncEnd/8) - 0,
horizTotal = (mode->CrtcHTotal/8) - 5,
horizBlankStart = (mode->CrtcHDisplay/8) - 1,
horizBlankEnd = (mode->CrtcHTotal/8) - 1,
vertDisplay = mode->CrtcVDisplay - 1,
vertStart = mode->CrtcVSyncStart - 1,
vertEnd = mode->CrtcVSyncEnd - 1,
vertTotal = mode->CrtcVTotal - 2,
vertBlankStart = mode->CrtcVDisplay - 1,
vertBlankEnd = mode->CrtcVTotal - 1;
 
if(mode->flags & INTERLACED) vertTotal |= 1;
 
/* Calculate correct value for offset register */
moderegs[0x13]=((modeinfo->width/8)*bpp)&0xff;
 
/* Extra bits for CRTC offset register */
moderegs[REG(0)]=
SetBitField((modeinfo->width/8)*bpp,10:8,7:5);
 
/* The NV3 manuals states that for native modes, there should be no
* borders. This code should also be tidied up to use symbolic names
*/
moderegs[0x0]=Set8Bits(horizTotal);
moderegs[0x1]=Set8Bits(horizDisplay);
moderegs[0x2]=Set8Bits(horizBlankStart);
moderegs[0x3]=SetBitField(horizBlankEnd,4:0,4:0) | SetBit(7);
moderegs[0x4]=Set8Bits(horizStart);
moderegs[0x5]=SetBitField(horizBlankEnd,5:5,7:7)|
SetBitField(horizEnd,4:0,4:0);
moderegs[0x6]=SetBitField(vertTotal,7:0,7:0);
 
moderegs[0x7]=SetBitField(vertTotal,8:8,0:0)|
SetBitField(vertDisplay,8:8,1:1)|
SetBitField(vertStart,8:8,2:2)|
SetBitField(vertBlankStart,8:8,3:3)|
SetBit(4)|
SetBitField(vertTotal,9:9,5:5)|
SetBitField(vertDisplay,9:9,6:6)|
SetBitField(vertStart,9:9,7:7);
 
moderegs[0x9]= SetBitField(vertBlankStart,9:9,5:5) | SetBit(6);
moderegs[0x10]= Set8Bits(vertStart);
moderegs[0x11]= SetBitField(vertEnd,3:0,3:0) | SetBit(5);
moderegs[0x12]= Set8Bits(vertDisplay);
moderegs[0x15]= Set8Bits(vertBlankStart);
moderegs[0x16]= Set8Bits(vertBlankEnd);
 
moderegs[REG(2)] = SetBitField(horizBlankEnd,6:6,4:4)
| SetBitField(vertBlankStart,10:10,3:3)
| SetBitField(vertStart,10:10,2:2)
| SetBitField(vertDisplay,10:10,1:1)
| SetBitField(vertTotal,10:10,0:0);
 
moderegs[REG(4)] = SetBitField(horizTotal,8:8,0:0)
| SetBitField(horizDisplay,8:8,1:1)
| SetBitField(horizBlankStart,8:8,2:2)
| SetBitField(horizStart,8:8,3:3);
 
moderegs[REG(7)] = SetBitField(vertTotal,11:11,0:0)
| SetBitField(vertDisplay,11:11,2:2)
| SetBitField(vertStart,11:11,4:4)
| SetBitField(vertBlankStart,11:11,6:6);
 
if(mode->flags & DOUBLESCAN) moderegs[0x9]|=0x80;
/* I think this should be SetBitField(horizTotal,8:8,0:0), but this
* doesn't work apparently. Why 260 ? 256 would make sense.
*/
if(mode->flags & INTERLACED) {
horizTotal=(horizTotal>>1)& ~1;
moderegs[117]=horizTotal & 0xff;
moderegs[REG(4)] |= SetBitField(horizTotal,8:8,4:4);
} else {
moderegs[117]=255;
}
 
return 1;
}
 
/* Set a mode */
 
/* Local, called by nv3_setmode(). */
 
static void nv3_initializemode(unsigned char *moderegs,
ModeTiming * modetiming, ModeInfo * modeinfo, int mode)
{
long k;
unsigned int config0=0;
int m,n,p;
int clockIn=modetiming->pixelClock;
int clockOut;
int pixelDepth;
nv3_saveregs(moderegs);
 
__svgalib_setup_VGA_registers(moderegs, modetiming, modeinfo);
 
CalcVClock(clockIn,&clockOut,&m,&n,&p);
 
*(unsigned int *)(moderegs+REG(12)) = PRAMDAC_Val(VPLL_COEFF_NDIV,n) |
PRAMDAC_Val(VPLL_COEFF_MDIV,m) |
PRAMDAC_Val(VPLL_COEFF_PDIV,p);
 
CalculateCRTC(modetiming,modeinfo,moderegs);
 
moderegs[REG(1)] = PCRTC_Val(REPAINT1_LARGE_SCREEN,modetiming->CrtcHDisplay<1280);
 
/* The new xfree driver (from nVidia) calculates those in some
twisted way, but I leave it for now */
moderegs[REG(5)]=0x83;
if(modetiming->pixelClock*modeinfo->bytesPerPixel>720000) {
moderegs[REG(6)]=0x2f;
}
 
/* PixelFormat controls how many bits per pixel.
* There is another register in the
* DAC which controls if mode is 5:5:5 or 5:6:5
*/
pixelDepth=(modeinfo->bitsPerPixel+1)/8;
if(pixelDepth>3) pixelDepth=3;
moderegs[REG(3)]=pixelDepth;
if(modetiming->flags & TVMODE) {
moderegs[REG(3)]|=0x80;
if(modetiming->flags & TVPAL) moderegs[REG(3)]|=0x40;
};
 
*(unsigned int *)(moderegs+REG(20))=
PRAMDAC_Def(GENERAL_CONTROL_IDC_MODE,GAMMA)|
PRAMDAC_Val(GENERAL_CONTROL_565_MODE,modeinfo->greenWeight==6)|
PRAMDAC_Def(GENERAL_CONTROL_TERMINATION,37OHM)|
((modeinfo->bitsPerPixel>8) ?
PRAMDAC_Def(GENERAL_CONTROL_BPC,8BITS) :
PRAMDAC_Def(GENERAL_CONTROL_BPC,6BITS)) | PRAMDAC_Def(GENERAL_CONTROL_VGA_STATE,SEL);
/* Not sure about this */
 
switch(chip){
case Riva128:
config0=PFB_Val(CONFIG_0_RESOLUTION,((modeinfo->lineWidth+31)/32))|
PFB_Val(CONFIG_0_PIXEL_DEPTH,pixelDepth)|
PFB_Def(CONFIG_0_TILING,DISABLED);
k=PRAMDAC_Def(PLL_COEFF_SELECT_MPLL_SOURCE,PROG)|
PRAMDAC_Def(PLL_COEFF_SELECT_VPLL_SOURCE,PROG)|
PRAMDAC_Def(PLL_COEFF_SELECT_VCLK_RATIO,DB2);
moderegs[REG(1)] |= PCRTC_Def(REPAINT1_PALETTE_WIDTH,6BITS);
break;
case RivaTNT:
config0=0x1114;
k=0x10000700;
break;
case GEFORCE:
default:
config0=*(unsigned int *)(moderegs+REG(8));
k=0x10000700;
break;
};
 
*(unsigned int *)(moderegs+REG(16))=k;
*(unsigned int *)(moderegs+REG(8))=config0;
 
moderegs[88]=28;
moderegs[109]&=0xfe; /* hide cursor */
 
nv3_is_linear=0;
 
return ;
}
 
 
int nv3_setmode(int mode, int prv_mode)
{
unsigned char *moderegs;
ModeTiming *modetiming;
ModeInfo *modeinfo;
int i;
 
if (IS_IN_STANDARD_VGA_DRIVER(mode)) {
unsigned int k;
printk(KERN_INFO "Standard VGA Mode\n");
 
if(chip==Riva128)
v_writel(0x00000100, NV_PRAMDAC_PLL_COEFF_SELECT);
else v_writel(0x00000500, NV_PRAMDAC_PLL_COEFF_SELECT);
__svgalib_outcrtc(NV_PCRTC_REPAINT0,0);
__svgalib_outcrtc(NV_PCRTC_REPAINT1,0x3d);
__svgalib_outcrtc(NV_PCRTC_EXTRA,0);
__svgalib_outcrtc(NV_PCRTC_PIXEL,0);
__svgalib_outcrtc(NV_PCRTC_HORIZ_EXTRA,0);
__svgalib_outcrtc(NV_PCRTC_FIFO_CONTROL,0x83);
__svgalib_outcrtc(0x1c,0x18);
__svgalib_outcrtc(0x1d,0);
__svgalib_outcrtc(0x1e,0);
__svgalib_outcrtc(0x30,0);
__svgalib_outcrtc(0x31,0);
k = v_readl(NV_PRAMDAC_GENERAL_CONTROL);
k &= ~0x00100000;
v_writel(k, NV_PRAMDAC_GENERAL_CONTROL);
 
return __svgalib_vga_driverspecs.setmode(mode, prv_mode);
}
 
if (!nv3_modeavailable(mode))
return 1;
 
printk(KERN_INFO "Mode Available !\nStart Set Mode...\n");
modeinfo = __svgalib_createModeInfoStructureForSvgalibMode(mode);
 
modetiming = malloc(sizeof(ModeTiming));
if (__svgalib_getmodetiming(modetiming, modeinfo, cardspecs)) {
free(modetiming);
free(modeinfo);
return 1;
}
 
moderegs = malloc(NV3_TOTAL_REGS);
 
printk(KERN_INFO "Start Init Mode...\n");
nv3_initializemode(moderegs, modetiming, modeinfo, mode);
free(modetiming);
 
__svgalib_setregs(moderegs); /* Set standard regs. */
nv3_setregs(moderegs, mode); /* Set extended regs. */
free(moderegs);
 
__svgalib_InitializeAcceleratorInterface(modeinfo);
 
for(i=0;i<256;i++)vga_setpalette(i,i,i,i);
free(modeinfo);
return 0;
}
 
/* Unlock chipset-specific registers */
 
static void nv3_unlock(void)
{
if(chip!=Riva128) {
__svgalib_nv3_outcrtc(0x11,__svgalib_incrtc(0x11)&0x7f);
__svgalib_nv3_outcrtc(0x1f, UNLOCK_EXT_MAGIC);
} else {
// __svgalib_outcrtc(0x11,__svgalib_incrtc(0x11)&0x7f);
__svgalib_outseq(LOCK_EXT_INDEX,UNLOCK_EXT_MAGIC);
}
}
 
/* Relock chipset-specific registers */
/* (currently not used) */
 
static void nv3_lock(void)
{
__svgalib_outseq(LOCK_EXT_INDEX,UNLOCK_EXT_MAGIC+1);
 
}
 
/* Indentify chipset, initialize and return non-zero if detected */
 
int nv3_test(void)
{ unsigned long buf[64];
int found=0;
 
MMIOBASE=0; /* let nv3_init() find those */
LINEARBASE=0;
nv3_init(0,0,0);
return 1;
}
 
/* No r/w paging - I guess it's possible, but is it useful? */
static void nv3_setrdpage(int page)
{
}
static void nv3_setwrpage(int page)
{
}
 
/* Set display start address (not for 16 color modes) */
 
static void nv3_setdisplaystart(int address)
{ unsigned char byte;
int pan;
 
pan=(address&3)<<1;
address=address >> 2;
__svgalib_outcrtc(0x0d,address&0xff);
__svgalib_outcrtc(0x0c,(address>>8)&0xff);
byte=__svgalib_incrtc(NV_PCRTC_REPAINT0) & 0xe0;
__svgalib_outcrtc(NV_PCRTC_REPAINT0,((address>>16)&0x1f)|byte);
byte=__svgalib_incrtc(0x2D) & ~0x60;
__svgalib_outcrtc(0x2D,((address>>16)&0x60)|byte);
 
byte = __svgalib_inis1();
__svgalib_outatt(0x13, pan);
}
 
/* Set logical scanline length (usually multiple of 8) */
 
static void nv3_setlogicalwidth(int width)
{ int byte ;
 
__svgalib_outcrtc(0x13,(width >> 3)&0xff);
byte=__svgalib_incrtc(NV_PCRTC_REPAINT0) & 0x1f;
__svgalib_outcrtc(NV_PCRTC_REPAINT0,SetBitField(width,13:11,7:5)|byte);
 
}
 
static int nv3_linear(int op, int param)
{
if (op==LINEAR_ENABLE){ nv3_is_linear=1; return 0;}
if (op==LINEAR_DISABLE){ nv3_is_linear=0; return 0;}
if (op==LINEAR_QUERY_BASE) { return LINEARBASE ;}
if (op == LINEAR_QUERY_RANGE || op == LINEAR_QUERY_GRANULARITY) return 0; /* No granularity or range. */
else return -1; /* Unknown function. */
}
 
static int nv3_cursor( int cmd, int p1, int p2, int p3, int p4, void *p5) {
unsigned char *b1, *b2;
unsigned short *b3;
unsigned int i, j, k, l, c0, c1;
switch(cmd){
case CURSOR_INIT:
return 1;
case CURSOR_HIDE:
__svgalib_outcrtc(0x31,__svgalib_incrtc(0x31)&0xfe); /* disable cursor */
break;
case CURSOR_SHOW:
__svgalib_outcrtc(0x31,__svgalib_incrtc(0x31)|1); /* enable cursor */
break;
case CURSOR_POSITION:
v_writel(p1+(p2<<16), NV_PRAMDAC_GRCURSOR_START_POS);
break;
case CURSOR_SELECT:
i=memory/2-(p1+1);
if (chip==Riva128) {
__svgalib_outcrtc(0x31,(__svgalib_incrtc(0x31)&7)|(((~i)&0x1f)<<3));
} else {
__svgalib_outcrtc(0x31,(__svgalib_incrtc(0x31)&3)|(((~i)&0x3f)<<2));
}
#if 0
__svgalib_outcrtc(0x30,((~i)&0x3fc0)>>6);
#else
__svgalib_outcrtc(0x30,0);
#endif
break;
case CURSOR_IMAGE:
i=memory/2-(p1+1);
i=i*2048;
switch(p2) {
case 0: /* X11 format, 32x32 */
b3=malloc(2048);
b1=(unsigned char *)p5;
b2=b1+128;
c0=0x8000|GET15BITCOLOR((p3>>16)&0xff,(p3>>8)&0xff,p3&0xff);
c1=0x8000|GET15BITCOLOR((p4>>16)&0xff,(p4>>8)&0xff,p4&0xff);
l=992;
for(k=0;k<128;k++) {
int cc1=*(b1+k);
int cc2=*(b2+k);
for(j=0;j<8;j++) {
if(!(cc2&0x80)) *(b3+l)=0; else if (cc1&0x80)
*(b3+l)=c1; else *(b3+l)=c0;
l++;
if((l&0x1f)==0)l-=64;
cc2<<=1;
cc1<<=1;
}
}
memcpy(LINEAR_POINTER+i,b3,2048);
free(b3);
break;
case 1: /* nvidia 1555 format 32x32 */
memcpy(LINEAR_POINTER+i,p5,2048);
break;
}
break;
}
return 0;
}
 
static int nv3_match_programmable_clock(int clock)
{
return clock ;
}
static int nv3_map_clock(int bpp, int clock)
{
return clock ;
}
static int nv3_map_horizontal_crtc(int bpp, int pixelclock, int htiming)
{
return htiming;
}
/* Function table (exported) */
 
DriverSpecs __svgalib_nv3_driverspecs =
{
nv3_saveregs,
nv3_setregs,
nv3_unlock,
nv3_lock,
nv3_test,
nv3_init,
nv3_setpage,
nv3_setrdpage,
nv3_setwrpage,
nv3_setmode,
nv3_modeavailable,
nv3_setdisplaystart,
nv3_setlogicalwidth,
nv3_getmodeinfo,
0, /* old blit funcs */
0,
0,
0,
0,
0, /* ext_set */
0, /* accel */
nv3_linear,
0, /* accelspecs, filled in during init. */
0,
nv3_cursor
};
 
/* Initialize chipset (called after detection) */
 
static int nv3_init(int force, int par1, int par2) //SHARK
{
char *archs[3]={"Riva128",
"RivaTNT",
"GeForce"};
int flags;
flags=0;
if(MMIOBASE==0) {
unsigned long buf[64];
int found;
printk(KERN_INFO "Init NVidia card: scan pci bus\n");
found=__svgalib_pci_find_vendor_vga(0x12d2,buf,0);
if (found) {
found=__svgalib_pci_find_vendor_vga(0x10de,buf,0);
if(found) {
printk(KERN_INFO "Error: NVidia card not found\n");
return 0;
}
}
switch((buf[0]>>20)&0xff){
case 0x1:
chip=Riva128;
nvnum=3;
break;
case 0x2:
case 0xA:
chip=RivaTNT;
switch((buf[0]>>16)&0xff){
case 0x20:
nvnum=4;
break;
case 0x2c:
case 0x2d:
case 0x2e:
case 0x2f:
nvnum=6;
break;
default:
nvnum=5;
}
break;
case 0x10:
case 0x15:
chip=GEFORCE;
nvnum=(buf[0]>>20)&0xff;
break;
case 0x11:
case 0x17:
case 0x1A:
case 0x20:
case 0x25:
default:
flags = NO_INTERLACE;
chip=GEFORCE;
nvnum=(buf[0]>>20)&0xff;
break;
};
MMIOBASE=buf[4]&0xffffff00;
LINEARBASE=buf[5]&0xffffff00;
};
printk(KERN_INFO "NVidia card found ! BASE_ADDR: %.8x TYPE: %s (NV%.8x)\n",MMIOBASE,archs[chip],nvnum);
if (force) {
memory = par1;
chip = par2;
};
 
__svgalib_modeinfo_linearset |= IS_LINEAR;
 
__svgalib_mmio_base=MMIOBASE;
__svgalib_mmio_size=8*1024*1024;
 
map_mmio();
if(!force){
int boot0;
boot0=v_readl(NV_PFB_BOOT_0);
switch(chip){
case Riva128:
if(boot0&0x20)memory=8192; else memory=1024<<(boot0&3);
if(memory==1024)memory=8192;
break;
case RivaTNT:
memory=2048<<(boot0&3);
if(memory==2048)memory=32768;
break;
case GEFORCE:
memory=(v_readl(NV_PFB_BOOT_10)>>10) & 0x3fc00;
if(memory<8192)memory=8192; // do this later
break;
}
}
 
nv3_mapio();
nv3_unlock();
 
{
int temp;
temp=v_readl(NV_PEXTDEV_0);
switch(chip){
case Riva128:
PLL_INPUT_FREQ= (temp&0x20) ? 14318 : 13500;
MAXVCLOCK=256000;
P_MAX=4;// XFree say 3, but 4 works on my Riva128
if(PLL_INPUT_FREQ==13500)M_MAX=12; else M_MAX=13;
M_MIN=M_MAX-5;
break;
case RivaTNT:
PLL_INPUT_FREQ= (temp&0x40) ? 14318 : 13500;
MAXVCLOCK=350000;
P_MAX=4;
if(PLL_INPUT_FREQ==13500)M_MAX=13; else M_MAX=14;
M_MIN=M_MAX-6;
break;
case GEFORCE:
default:
PLL_INPUT_FREQ= (temp&0x40 ) ? 14318 : 13500;
if(nvnum==0x17 || nvnum==0x25) {
if(temp&0x400000) PLL_INPUT_FREQ=27000;
}
MAXVCLOCK=350000;
P_MAX=4;
if(PLL_INPUT_FREQ==13500)M_MAX=13; else M_MAX=14;
M_MIN=M_MAX-6;
break;
};
};
 
cardspecs = malloc(sizeof(CardSpecs));
cardspecs->videoMemory = memory;
if(chip==Riva128) {
cardspecs->maxPixelClock4bpp = 75000;
cardspecs->maxPixelClock8bpp = 230000;
cardspecs->maxPixelClock16bpp = 230000;
cardspecs->maxPixelClock24bpp = 0;
cardspecs->maxPixelClock32bpp = 230000;
} else {
cardspecs->maxPixelClock4bpp = 75000;
cardspecs->maxPixelClock8bpp = 350000;
cardspecs->maxPixelClock16bpp = 350000;
cardspecs->maxPixelClock24bpp = 0;
cardspecs->maxPixelClock32bpp = 350000;
}
cardspecs->flags = flags | CLOCK_PROGRAMMABLE ;
cardspecs->maxHorizontalCrtc = 4080;
cardspecs->maxPixelClock4bpp = 0;
cardspecs->nClocks =0;
cardspecs->clocks = NULL;
cardspecs->mapClock = nv3_map_clock;
cardspecs->mapHorizontalCrtc = nv3_map_horizontal_crtc;
cardspecs->matchProgrammableClock=nv3_match_programmable_clock;
__svgalib_driverspecs = &__svgalib_nv3_driverspecs;
__svgalib_banked_mem_base=0xa0000;
__svgalib_banked_mem_size=0x10000;
__svgalib_linear_mem_base=LINEARBASE;
__svgalib_linear_mem_size=memory*0x400;
printk(KERN_INFO "NVidia Card Initialized ! LIN_ADDR:%.8x LIN_SIZE:%d\n",__svgalib_linear_mem_base,__svgalib_linear_mem_size);
sleep(4);
return 0;
}
 
/*
* Calculate the Video Clock parameters for the PLL.
*/
static int CalcVClock
(
int clockIn,
int *clockOut,
int *mOut,
int *nOut,
int *pOut
)
{
unsigned DeltaNew, DeltaOld;
unsigned VClk, Freq;
unsigned M, N, P;
DeltaOld = 0xFFFFFFFF;
 
VClk = (unsigned)clockIn;
for (P = 0; P <= P_MAX; P ++)
{
Freq = VClk << P;
if ((Freq >= 128000) && (Freq <= MAXVCLOCK))
{
for (M = M_MIN; M <= M_MAX; M++)
{
N = ((VClk<<P) * M + PLL_INPUT_FREQ/2) / PLL_INPUT_FREQ;
Freq = (PLL_INPUT_FREQ * N / M) >> P;
if (Freq > VClk)
DeltaNew = Freq - VClk;
else
DeltaNew = VClk - Freq;
if ((DeltaNew < DeltaOld) && (N<256))
{
*mOut = M;
*nOut = N;
*pOut = P;
*clockOut = Freq;
DeltaOld = DeltaNew;
}
}
}
}
return (DeltaOld != 0xFFFFFFFF);
}
 
/shark/tags/rel_0_5/drivers/svga/IBMRGB52x.h
0,0 → 1,78
/*
* Taken from XFree86. XFree86 copyrights apply.
*/
 
/* $XFree86: xc/programs/Xserver/hw/xfree86/common_hw/IBMRGB.h,v 3.0 1995/06/29 13:32:11 dawes Exp $ */
 
#define IBMRGB_REF_FREQ_1 14.31818
#define IBMRGB_REF_FREQ_2 50.00000
 
/* #ifdef S3_SERVER */
/* Direct standard VGA registers, special index and data registers */
 
#define IBMRGB_WRITE_ADDR 0x3C8 /* CR55 low bit == 0 */
#define IBMRGB_RAMDAC_DATA 0x3C9 /* CR55 low bit == 0 */
#define IBMRGB_PIXEL_MASK 0x3C6 /* CR55 low bit == 0 */
#define IBMRGB_READ_ADDR 0x3C7 /* CR55 low bit == 0 */
#define IBMRGB_INDEX_LOW 0x3C8 /* CR55 low bit == 1 */
#define IBMRGB_INDEX_HIGH 0x3C9 /* CR55 low bit == 1 */
#define IBMRGB_INDEX_DATA 0x3C6 /* CR55 low bit == 1 */
#define IBMRGB_INDEX_CONTROL 0x3C7 /* CR55 low bit == 1 */
/* #endif */
 
#define IBMRGB_rev 0x00
#define IBMRGB_id 0x01
#define IBMRGB_misc_clock 0x02
#define IBMRGB_sync 0x03
#define IBMRGB_hsync_pos 0x04
#define IBMRGB_pwr_mgmt 0x05
#define IBMRGB_dac_op 0x06
#define IBMRGB_pal_ctrl 0x07
#define IBMRGB_sysclk 0x08 /* not RGB525 */
#define IBMRGB_pix_fmt 0x0a
#define IBMRGB_8bpp 0x0b
#define IBMRGB_16bpp 0x0c
#define IBMRGB_24bpp 0x0d
#define IBMRGB_32bpp 0x0e
#define IBMRGB_pll_ctrl1 0x10
#define IBMRGB_pll_ctrl2 0x11
#define IBMRGB_pll_ref_div_fix 0x14
#define IBMRGB_sysclk_ref_div 0x15 /* not RGB525 */
#define IBMRGB_sysclk_vco_div 0x16 /* not RGB525 */
#define IBMRGB_f0 0x20
#define IBMRGB_m0 0x20
#define IBMRGB_n0 0x21
#define IBMRGB_curs 0x30
#define IBMRGB_curs_xl 0x31
#define IBMRGB_curs_xh 0x32
#define IBMRGB_curs_yl 0x33
#define IBMRGB_curs_yh 0x34
#define IBMRGB_curs_hot_x 0x35
#define IBMRGB_curs_hot_y 0x36
#define IBMRGB_curs_col1_r 0x40
#define IBMRGB_curs_col1_g 0x41
#define IBMRGB_curs_col1_b 0x42
#define IBMRGB_curs_col2_r 0x43
#define IBMRGB_curs_col2_g 0x44
#define IBMRGB_curs_col2_b 0x45
#define IBMRGB_curs_col3_r 0x46
#define IBMRGB_curs_col3_g 0x47
#define IBMRGB_curs_col3_b 0x48
#define IBMRGB_border_col_r 0x60
#define IBMRGB_border_col_g 0x61
#define IBMRGB_botder_col_b 0x62
#define IBMRGB_misc1 0x70
#define IBMRGB_misc2 0x71
#define IBMRGB_misc3 0x72
#define IBMRGB_misc4 0x73 /* not RGB525 */
#define IBMRGB_dac_sense 0x82
#define IBMRGB_misr_r 0x84
#define IBMRGB_misr_g 0x86
#define IBMRGB_misr_b 0x88
#define IBMRGB_pll_vco_div_in 0x8e
#define IBMRGB_pll_ref_div_in 0x8f
#define IBMRGB_vram_mask_0 0x90
#define IBMRGB_vram_mask_1 0x91
#define IBMRGB_vram_mask_2 0x92
#define IBMRGB_vram_mask_3 0x93
#define IBMRGB_curs_array 0x100
/shark/tags/rel_0_5/drivers/svga/nv3ref.h
0,0 → 1,646
/***************************************************************************\
|* *|
|* Copyright (c) 1996-1998 NVIDIA, Corp. All rights reserved. *|
|* *|
|* NOTICE TO USER: The source code is copyrighted under U.S. and *|
|* international laws. NVIDIA, Corp. of Sunnyvale, California owns *|
|* the copyright and as design patents pending on the design and *|
|* interface of the NV chips. Users and possessors of this source *|
|* code are hereby granted a nonexclusive, royalty-free copyright *|
|* and design patent license to use this code in individual and *|
|* commercial software. *|
|* *|
|* Any use of this source code must include, in the user documenta- *|
|* tion and internal comments to the code, notices to the end user *|
|* as follows: *|
|* *|
|* Copyright (c) 1996-1998 NVIDIA, Corp. NVIDIA design patents *|
|* pending in the U.S. and foreign countries. *|
|* *|
|* NVIDIA, CORP. MAKES NO REPRESENTATION ABOUT THE SUITABILITY OF *|
|* THIS SOURCE CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" WITHOUT *|
|* EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORP. DISCLAIMS *|
|* ALL WARRANTIES WITH REGARD TO THIS SOURCE CODE, INCLUDING ALL *|
|* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *|
|* PARTICULAR PURPOSE. IN NO EVENT SHALL NVIDIA, CORP. BE LIABLE *|
|* FOR ANY SPECIAL, INDIRECT, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, *|
|* OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR *|
|* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER *|
|* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR *|
|* PERFORMANCE OF THIS SOURCE CODE. *|
|* *|
\***************************************************************************/
 
/* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/nv/nv3ref.h,v 1.1.2.3 1998/01/24 00:04:39 robin Exp $ */
 
#ifndef __NV3REF_H__
#define __NV3REF_H__
 
 
/* Magic values to lock/unlock extended regs */
#define UNLOCK_EXT_MAGIC 0x57
#define LOCK_EXT_MAGIC 0x99 /* Any value other than 0x57 will do */
 
#define LOCK_EXT_INDEX 0x6
 
/* Extended offset and start address */
#define NV_PCRTC_REPAINT0 0x19
#define NV_PCRTC_REPAINT0_OFFSET_10_8 7:5
#define NV_PCRTC_REPAINT0_START_ADDR_20_16 4:0
 
/* Horizonal extended bits */
#define NV_PCRTC_HORIZ_EXTRA 0x2d
#define NV_PCRTC_HORIZ_EXTRA_INTER_HALF_START_8 4:4
#define NV_PCRTC_HORIZ_EXTRA_HORIZ_RETRACE_START_8 3:3
#define NV_PCRTC_HORIZ_EXTRA_HORIZ_BLANK_START_8 2:2
#define NV_PCRTC_HORIZ_EXTRA_DISPLAY_END_8 1:1
#define NV_PCRTC_HORIZ_EXTRA_DISPLAY_TOTAL_8 0:0
 
/* Assorted extra bits */
#define NV_PCRTC_EXTRA 0x25
#define NV_PCRTC_EXTRA_OFFSET_11 5:5
#define NV_PCRTC_EXTRA_HORIZ_BLANK_END_6 4:4
#define NV_PCRTC_EXTRA_VERT_BLANK_START_10 3:3
#define NV_PCRTC_EXTRA_VERT_RETRACE_START_10 2:2
#define NV_PCRTC_EXTRA_VERT_DISPLAY_END_10 1:1
#define NV_PCRTC_EXTRA_VERT_TOTAL_10 0:0
 
 
/* Controls how much data the refresh fifo requests */
#define NV_PCRTC_FIFO_CONTROL 0x1b
#define NV_PCRTC_FIFO_CONTROL_UNDERFLOW_WARN 7:7
#define NV_PCRTC_FIFO_CONTROL_BURST_LENGTH 2:0
#define NV_PCRTC_FIFO_CONTROL_BURST_LENGTH_8 0x0
#define NV_PCRTC_FIFO_CONTROL_BURST_LENGTH_32 0x1
#define NV_PCRTC_FIFO_CONTROL_BURST_LENGTH_64 0x2
#define NV_PCRTC_FIFO_CONTROL_BURST_LENGTH_128 0x3
#define NV_PCRTC_FIFO_CONTROL_BURST_LENGTH_256 0x4
 
/* When the fifo occupancy falls below *twice* the watermark,
* the refresh fifo will start to be refilled. If this value is
* too low, you will get junk on the screen. Too high, and performance
* will suffer. Watermark in units of 8 bytes
*/
#define NV_PCRTC_FIFO 0x20
#define NV_PCRTC_FIFO_RESET 7:7
#define NV_PCRTC_FIFO_WATERMARK 5:0
 
 
/* Various flags */
#define NV_PCRTC_REPAINT1 0x1a
#define NV_PCRTC_REPAINT1_HSYNC 7:7
#define NV_PCRTC_REPAINT1_HYSNC_DISABLE 0x01
#define NV_PCRTC_REPAINT1_HYSNC_ENABLE 0x00
#define NV_PCRTC_REPAINT1_VSYNC 6:6
#define NV_PCRTC_REPAINT1_VYSNC_DISABLE 0x01
#define NV_PCRTC_REPAINT1_VYSNC_ENABLE 0x00
#define NV_PCRTC_REPAINT1_COMPATIBLE_TEXT 4:4
#define NV_PCRTC_REPAINT1_COMPATIBLE_TEXT_ENABLE 0x01
#define NV_PCRTC_REPAINT1_COMPATIBLE_TEXT_DISABLE 0x00
#define NV_PCRTC_REPAINT1_LARGE_SCREEN 2:2
#define NV_PCRTC_REPAINT1_LARGE_SCREEN_DISABLE 0x01
#define NV_PCRTC_REPAINT1_LARGE_SCREEN_ENABLE 0x00 /* >=1280 */
#define NV_PCRTC_REPAINT1_PALETTE_WIDTH 1:1
#define NV_PCRTC_REPAINT1_PALETTE_WIDTH_8BITS 0x00
#define NV_PCRTC_REPAINT1_PALETTE_WIDTH_6BITS 0x01
 
 
#define NV_PCRTC_GRCURSOR0 0x30
#define NV_PCRTC_GRCURSOR0_START_ADDR_21_16 5:0
 
#define NV_PCRTC_GRCURSOR1 0x31
#define NV_PCRTC_GRCURSOR1_START_ADDR_15_11 7:3
#define NV_PCRTC_GRCURSOR1_SCAN_DBL 1:1
#define NV_PCRTC_GRCURSOR1_SCAN_DBL_DISABLE 0
#define NV_PCRTC_GRCURSOR1_SCAN_DBL_ENABLE 1
#define NV_PCRTC_GRCURSOR1_CURSOR 0:0
#define NV_PCRTC_GRCURSOR1_CURSOR_DISABLE 0
#define NV_PCRTC_GRCURSOR1_CURSOR_ENABLE 1
 
#define NV_PCRTC_SCREEN 0x41
 
 
/* Controls what the format of the framebuffer is */
#define NV_PCRTC_PIXEL 0x28
#define NV_PCRTC_PIXEL_MODE 7:7
#define NV_PCRTC_PIXEL_MODE_TV 0x01
#define NV_PCRTC_PIXEL_MODE_VGA 0x00
#define NV_PCRTC_PIXEL_TV_MODE 6:6
#define NV_PCRTC_PIXEL_TV_MODE_NTSC 0x00
#define NV_PCRTC_PIXEL_TV_MODE_PAL 0x01
#define NV_PCRTC_PIXEL_TV_HORIZ_ADJUST 5:3
#define NV_PCRTC_PIXEL_FORMAT 1:0
#define NV_PCRTC_PIXEL_FORMAT_VGA 0x00
#define NV_PCRTC_PIXEL_FORMAT_8BPP 0x01
#define NV_PCRTC_PIXEL_FORMAT_16BPP 0x02
#define NV_PCRTC_PIXEL_FORMAT_32BPP 0x03
 
#define NV_PEXTDEV 0x00101fff:0x00101000
#define NV_PEXTDEV_0 0x00101000
 
#define NV_PRAMDAC 0x00680FFF:0x00680000 /* RW--D */
 
#define NV_PRAMDAC_VPLL_COEFF 0x00680508 /* RW-4R */
#define NV_PRAMDAC_VPLL_COEFF_MDIV 7:0 /* RWIUF */
#define NV_PRAMDAC_VPLL_COEFF_NDIV 15:8 /* RWIUF */
#define NV_PRAMDAC_VPLL_COEFF_PDIV 18:16 /* RWIVF */
 
 
#define NV_PRAMDAC_PLL_COEFF_SELECT 0x0068050C /* RW-4R */
#define NV_PRAMDAC_PLL_COEFF_SELECT_DLL_BYPASS 4:4 /* RWIVF */
#define NV_PRAMDAC_PLL_COEFF_SELECT_DLL_BYPASS_FALSE 0x00000000 /* RWI-V */
#define NV_PRAMDAC_PLL_COEFF_SELECT_DLL_BYPASS_TRUE 0x00000001 /* RW--V */
#define NV_PRAMDAC_PLL_COEFF_SELECT_MPLL_SOURCE 8:8 /* RWIVF */
#define NV_PRAMDAC_PLL_COEFF_SELECT_MPLL_SOURCE_DEFAULT 0x00000000 /* RWI-V */
#define NV_PRAMDAC_PLL_COEFF_SELECT_MPLL_SOURCE_PROG 0x00000001 /* RW--V */
#define NV_PRAMDAC_PLL_COEFF_SELECT_MPLL_BYPASS 12:12 /* RWIVF */
#define NV_PRAMDAC_PLL_COEFF_SELECT_MPLL_BYPASS_FALSE 0x00000000 /* RWI-V */
#define NV_PRAMDAC_PLL_COEFF_SELECT_MPLL_BYPASS_TRUE 0x00000001 /* RW--V */
#define NV_PRAMDAC_PLL_COEFF_SELECT_VPLL_SOURCE 16:16 /* RWIVF */
#define NV_PRAMDAC_PLL_COEFF_SELECT_VPLL_SOURCE_DEFAULT 0x00000000 /* RWI-V */
#define NV_PRAMDAC_PLL_COEFF_SELECT_VPLL_SOURCE_PROG 0x00000001 /* RW--V */
#define NV_PRAMDAC_PLL_COEFF_SELECT_VPLL_BYPASS 20:20 /* RWIVF */
#define NV_PRAMDAC_PLL_COEFF_SELECT_VPLL_BYPASS_FALSE 0x00000000 /* RWI-V */
#define NV_PRAMDAC_PLL_COEFF_SELECT_VPLL_BYPASS_TRUE 0x00000001 /* RW--V */
#define NV_PRAMDAC_PLL_COEFF_SELECT_PCLK_SOURCE 25:24 /* RWIVF */
#define NV_PRAMDAC_PLL_COEFF_SELECT_PCLK_SOURCE_VPLL 0x00000000 /* RWI-V */
#define NV_PRAMDAC_PLL_COEFF_SELECT_PCLK_SOURCE_VIP 0x00000001 /* RW--V */
#define NV_PRAMDAC_PLL_COEFF_SELECT_PCLK_SOURCE_XTALOSC 0x00000002 /* RW--V */
#define NV_PRAMDAC_PLL_COEFF_SELECT_VCLK_RATIO 28:28 /* RWIVF */
#define NV_PRAMDAC_PLL_COEFF_SELECT_VCLK_RATIO_DB1 0x00000000 /* RWI-V */
#define NV_PRAMDAC_PLL_COEFF_SELECT_VCLK_RATIO_DB2 0x00000001 /* RW--V */
 
 
/* Various flags for DAC. BPC controls the width of the palette */
 
#define NV_PRAMDAC_GENERAL_CONTROL 0x00680600 /* RW-4R */
#define NV_PRAMDAC_GENERAL_CONTROL_FF_COEFF 1:0 /* RWIVF */
#define NV_PRAMDAC_GENERAL_CONTROL_FF_COEFF_DEF 0x00000000 /* RWI-V */
#define NV_PRAMDAC_GENERAL_CONTROL_IDC_MODE 4:4 /* RWIVF */
#define NV_PRAMDAC_GENERAL_CONTROL_IDC_MODE_GAMMA 0x00000000 /* RWI-V */
#define NV_PRAMDAC_GENERAL_CONTROL_IDC_MODE_INDEX 0x00000001 /* RW--V */
#define NV_PRAMDAC_GENERAL_CONTROL_VGA_STATE 8:8 /* RWIVF */
#define NV_PRAMDAC_GENERAL_CONTROL_VGA_STATE_NOTSE 0x00000000 /* RWI-V */
#define NV_PRAMDAC_GENERAL_CONTROL_VGA_STATE_SEL 0x00000001 /* RW--V */
#define NV_PRAMDAC_GENERAL_CONTROL_565_MODE 12:12 /* RWIVF */
#define NV_PRAMDAC_GENERAL_CONTROL_565_MODE_NOTSEL 0x00000000 /* RWI-V */
#define NV_PRAMDAC_GENERAL_CONTROL_565_MODE_SEL 0x00000001 /* RW--V */
#define NV_PRAMDAC_GENERAL_CONTROL_BLK_PEDSTL 16:16 /* RWIVF */
#define NV_PRAMDAC_GENERAL_CONTROL_BLK_PEDSTL_OFF 0x00000000 /* RWI-V */
#define NV_PRAMDAC_GENERAL_CONTROL_BLK_PEDSTL_ON 0x00000001 /* RW--V */
#define NV_PRAMDAC_GENERAL_CONTROL_TERMINATION 17:17 /* RWIVF */
#define NV_PRAMDAC_GENERAL_CONTROL_TERMINATION_37OHM 0x00000000 /* RWI-V */
#define NV_PRAMDAC_GENERAL_CONTROL_TERMINATION_75OHM 0x00000001 /* RW--V */
#define NV_PRAMDAC_GENERAL_CONTROL_BPC 20:20 /* RWIVF */
#define NV_PRAMDAC_GENERAL_CONTROL_BPC_6BITS 0x00000000 /* RWI-V */
#define NV_PRAMDAC_GENERAL_CONTROL_BPC_8BITS 0x00000001 /* RW--V */
#define NV_PRAMDAC_GENERAL_CONTROL_DAC_SLEEP 24:24 /* RWIVF */
#define NV_PRAMDAC_GENERAL_CONTROL_DAC_SLEEP_DIS 0x00000000 /* RWI-V */
#define NV_PRAMDAC_GENERAL_CONTROL_DAC_SLEEP_EN 0x00000001 /* RW--V */
#define NV_PRAMDAC_GENERAL_CONTROL_PALETTE_CLK 28:28 /* RWIVF */
#define NV_PRAMDAC_GENERAL_CONTROL_PALETTE_CLK_EN 0x00000000 /* RWI-V */
#define NV_PRAMDAC_GENERAL_CONTROL_PALETTE_CLK_DIS 0x00000001 /* RW--V */
 
 
#define NV_PRAMDAC_GRCURSOR_START_POS 0x00680300 /* RW-4R */
#define NV_PRAMDAC_GRCURSOR_START_POS_X 11:0 /* RWXSF */
#define NV_PRAMDAC_GRCURSOR_START_POS_Y 27:16 /* RWXSF */
 
#define NV_PMC 0x00000FFF:0x00000000 /* RW--D */
#define NV_PMC_INTR_0 0x00000100 /* RW-4R */
#define NV_PMC_INTR_0_PAUDIO 0:0 /* R--VF */
#define NV_PMC_INTR_0_PAUDIO_NOT_PENDING 0x00000000 /* R---V */
#define NV_PMC_INTR_0_PAUDIO_PENDING 0x00000001 /* R---V */
#define NV_PMC_INTR_0_PMEDIA 4:4 /* R--VF */
#define NV_PMC_INTR_0_PMEDIA_NOT_PENDING 0x00000000 /* R---V */
#define NV_PMC_INTR_0_PMEDIA_PENDING 0x00000001 /* R---V */
#define NV_PMC_INTR_0_PFIFO 8:8 /* R--VF */
#define NV_PMC_INTR_0_PFIFO_NOT_PENDING 0x00000000 /* R---V */
#define NV_PMC_INTR_0_PFIFO_PENDING 0x00000001 /* R---V */
#define NV_PMC_INTR_0_PGRAPH0 12:12 /* R--VF */
#define NV_PMC_INTR_0_PGRAPH0_NOT_PENDING 0x00000000 /* R---V */
#define NV_PMC_INTR_0_PGRAPH0_PENDING 0x00000001 /* R---V */
#define NV_PMC_INTR_0_PGRAPH1 13:13 /* R--VF */
#define NV_PMC_INTR_0_PGRAPH1_NOT_PENDING 0x00000000 /* R---V */
#define NV_PMC_INTR_0_PGRAPH1_PENDING 0x00000001 /* R---V */
#define NV_PMC_INTR_0_PVIDEO 16:16 /* R--VF */
#define NV_PMC_INTR_0_PVIDEO_NOT_PENDING 0x00000000 /* R---V */
#define NV_PMC_INTR_0_PVIDEO_PENDING 0x00000001 /* R---V */
#define NV_PMC_INTR_0_PTIMER 20:20 /* R--VF */
#define NV_PMC_INTR_0_PTIMER_NOT_PENDING 0x00000000 /* R---V */
#define NV_PMC_INTR_0_PTIMER_PENDING 0x00000001 /* R---V */
#define NV_PMC_INTR_0_PFB 24:24 /* R--VF */
#define NV_PMC_INTR_0_PFB_NOT_PENDING 0x00000000 /* R---V */
#define NV_PMC_INTR_0_PFB_PENDING 0x00000001 /* R---V */
#define NV_PMC_INTR_0_PBUS 28:28 /* R--VF */
#define NV_PMC_INTR_0_PBUS_NOT_PENDING 0x00000000 /* R---V */
#define NV_PMC_INTR_0_PBUS_PENDING 0x00000001 /* R---V */
#define NV_PMC_INTR_0_SOFTWARE 31:31 /* RWIVF */
#define NV_PMC_INTR_0_SOFTWARE_NOT_PENDING 0x00000000 /* RWI-V */
#define NV_PMC_INTR_0_SOFTWARE_PENDING 0x00000001 /* RW--V */
 
#define NV_PMC_INTR_EN_0 0x00000140 /* RW-4R */
#define NV_PMC_INTR_EN_0_INTA 1:0 /* RWIVF */
#define NV_PMC_INTR_EN_0_INTA_DISABLED 0x00000000 /* RWI-V */
#define NV_PMC_INTR_EN_0_INTA_HARDWARE 0x00000001 /* RW--V */
#define NV_PMC_INTR_EN_0_INTA_SOFTWARE 0x00000002 /* RW--V */
 
#define NV_PMC_ENABLE 0x00000200 /* RW-4R */
 
#define NV_PFIFO 0x00003FFF:0x00002000 /* RW--D */
#define NV_PFIFO_INTR_0 0x00002100 /* RW-4R */
#define NV_PFIFO_INTR_0_CACHE_ERROR 0:0 /* RWXVF */
#define NV_PFIFO_INTR_0_CACHE_ERROR_NOT_PENDING 0x00000000 /* R---V */
#define NV_PFIFO_INTR_0_CACHE_ERROR_PENDING 0x00000001 /* R---V */
#define NV_PFIFO_INTR_0_CACHE_ERROR_RESET 0x00000001 /* -W--V */
#define NV_PFIFO_INTR_0_RUNOUT 4:4 /* RWXVF */
#define NV_PFIFO_INTR_0_RUNOUT_NOT_PENDING 0x00000000 /* R---V */
#define NV_PFIFO_INTR_0_RUNOUT_PENDING 0x00000001 /* R---V */
#define NV_PFIFO_INTR_0_RUNOUT_RESET 0x00000001 /* -W--V */
#define NV_PFIFO_INTR_0_RUNOUT_OVERFLOW 8:8 /* RWXVF */
#define NV_PFIFO_INTR_0_RUNOUT_OVERFLOW_NOT_PENDING 0x00000000 /* R---V */
#define NV_PFIFO_INTR_0_RUNOUT_OVERFLOW_PENDING 0x00000001 /* R---V */
#define NV_PFIFO_INTR_0_RUNOUT_OVERFLOW_RESET 0x00000001 /* -W--V */
#define NV_PFIFO_INTR_0_DMA_PUSHER 12:12 /* RWXVF */
#define NV_PFIFO_INTR_0_DMA_PUSHER_NOT_PENDING 0x00000000 /* R---V */
#define NV_PFIFO_INTR_0_DMA_PUSHER_PENDING 0x00000001 /* R---V */
#define NV_PFIFO_INTR_0_DMA_PUSHER_RESET 0x00000001 /* -W--V */
#define NV_PFIFO_INTR_0_DMA_PTE 16:16 /* RWXVF */
#define NV_PFIFO_INTR_0_DMA_PTE_NOT_PENDING 0x00000000 /* R---V */
#define NV_PFIFO_INTR_0_DMA_PTE_PENDING 0x00000001 /* R---V */
#define NV_PFIFO_INTR_0_DMA_PTE_RESET 0x00000001 /* -W--V */
#define NV_PFIFO_INTR_EN_0 0x00002140 /* RW-4R */
#define NV_PFIFO_INTR_EN_0_CACHE_ERROR 0:0 /* RWIVF */
#define NV_PFIFO_INTR_EN_0_CACHE_ERROR_DISABLED 0x00000000 /* RWI-V */
#define NV_PFIFO_INTR_EN_0_CACHE_ERROR_ENABLED 0x00000001 /* RW--V */
#define NV_PFIFO_INTR_EN_0_RUNOUT 4:4 /* RWIVF */
#define NV_PFIFO_INTR_EN_0_RUNOUT_DISABLED 0x00000000 /* RWI-V */
#define NV_PFIFO_INTR_EN_0_RUNOUT_ENABLED 0x00000001 /* RW--V */
#define NV_PFIFO_INTR_EN_0_RUNOUT_OVERFLOW 8:8 /* RWIVF */
#define NV_PFIFO_INTR_EN_0_RUNOUT_OVERFLOW_DISABLED 0x00000000 /* RWI-V */
#define NV_PFIFO_INTR_EN_0_RUNOUT_OVERFLOW_ENABLED 0x00000001 /* RW--V */
#define NV_PFIFO_CONFIG_0 0x00002200 /* RW-4R */
#define NV_PFIFO_RAMHT 0x00002210 /* RW-4R */
#define NV_PFIFO_RAMHT_BASE_ADDRESS 15:12 /* RWXVF */
#define NV_PFIFO_RAMHT_SIZE 17:16 /* RWXVF */
#define NV_PFIFO_RAMHT_SIZE_4K 0x00000000 /* RWI-V */
#define NV_PFIFO_RAMHT_SIZE_8K 0x00000001 /* RW--V */
#define NV_PFIFO_RAMHT_SIZE_16K 0x00000002 /* RW--V */
#define NV_PFIFO_RAMHT_SIZE_32K 0x00000003 /* RW--V */
#define NV_PFIFO_RAMFC 0x00002214 /* RW-4R */
#define NV_PFIFO_RAMFC_BASE_ADDRESS 15:9 /* RWXVF */
#define NV_PFIFO_RAMRO 0x00002218 /* RW-4R */
#define NV_PFIFO_RAMRO_BASE_ADDRESS 15:9 /* RWXVF */
#define NV_PFIFO_RAMRO_SIZE 16:16 /* RWXVF */
#define NV_PFIFO_RAMRO_SIZE_512 0x00000000 /* RWI-V */
#define NV_PFIFO_RAMRO_SIZE_8K 0x00000001 /* RW--V */
#define NV_PFIFO_CACHES 0x00002500 /* RW-4R */
#define NV_PFIFO_CACHES_REASSIGN 0:0 /* RWIVF */
#define NV_PFIFO_CACHES_REASSIGN_DISABLED 0x00000000 /* RWI-V */
#define NV_PFIFO_CACHES_REASSIGN_ENABLED 0x00000001 /* RW--V */
#define NV_PFIFO_CACHE0_PUSH0 0x00003000 /* RW-4R */
#define NV_PFIFO_CACHE0_PUSH0_ACCESS 0:0 /* RWIVF */
#define NV_PFIFO_CACHE0_PUSH0_ACCESS_DISABLED 0x00000000 /* RWI-V */
#define NV_PFIFO_CACHE0_PUSH0_ACCESS_ENABLED 0x00000001 /* RW--V */
#define NV_PFIFO_CACHE1_PUSH0 0x00003200 /* RW-4R */
#define NV_PFIFO_CACHE1_PUSH0_ACCESS 0:0 /* RWIVF */
#define NV_PFIFO_CACHE1_PUSH0_ACCESS_DISABLED 0x00000000 /* RWI-V */
#define NV_PFIFO_CACHE1_PUSH0_ACCESS_ENABLED 0x00000001 /* RW--V */
#define NV_PFIFO_CACHE0_PUSH1 0x00003004 /* RW-4R */
#define NV_PFIFO_CACHE0_PUSH1_CHID 6:0 /* RWXUF */
#define NV_PFIFO_CACHE1_PUSH1 0x00003204 /* RW-4R */
#define NV_PFIFO_CACHE1_PUSH1_CHID 6:0 /* RWXUF */
#define NV_PFIFO_CACHE1_DMA0 0x00003220 /* RW-4R */
#define NV_PFIFO_CACHE1_DMA1 0x00003224 /* RW-4R */
#define NV_PFIFO_CACHE1_DMA2 0x00003228 /* RW-4R */
#define NV_PFIFO_CACHE0_PULL0 0x00003040 /* RW-4R */
#define NV_PFIFO_CACHE0_PULL0_ACCESS 0:0 /* RWIVF */
#define NV_PFIFO_CACHE0_PULL0_ACCESS_DISABLED 0x00000000 /* RWI-V */
#define NV_PFIFO_CACHE0_PULL0_ACCESS_ENABLED 0x00000001 /* RW--V */
#define NV_PFIFO_CACHE1_PULL0 0x00003240 /* RW-4R */
#define NV_PFIFO_CACHE1_PULL0_ACCESS 0:0 /* RWIVF */
#define NV_PFIFO_CACHE1_PULL0_ACCESS_DISABLED 0x00000000 /* RWI-V */
#define NV_PFIFO_CACHE1_PULL0_ACCESS_ENABLED 0x00000001 /* RW--V */
#define NV_PFIFO_CACHE1_PULL1 0x00003250 /* RW-4R */
#define NV_PFIFO_CACHE1_PULL1_CTX 4:4 /* RWXVF */
#define NV_PFIFO_CACHE1_PULL1_CTX_CLEAN 0x00000000 /* RW--V */
#define NV_PFIFO_CACHE1_PULL1_CTX_DIRTY 0x00000001 /* RW--V */
#define NV_PFIFO_CACHE1_PUT 0x00003210 /* RW-4R */
#define NV_PFIFO_CACHE1_PUT_ADDRESS 6:2 /* RWXUF */
#define NV_PFIFO_CACHE1_GET 0x00003270 /* RW-4R */
#define NV_PFIFO_CACHE1_GET_ADDRESS 6:2 /* RWXUF */
#define NV_PFIFO_CACHE1_CTX(i) (0x00003280+(i)*16) /* RW-4A */
#define NV_PFIFO_CACHE1_CTX__SIZE_1 8 /* */
#define NV_PFIFO_RUNOUT_PUT 0x00002410 /* RW-4R */
#define NV_PFIFO_RUNOUT_GET 0x00002420 /* RW-4R */
#define NV_PFIFO_RUNOUT_STATUS 0x00002400 /* R--4R */
 
#define NV_PGRAPH 0x00401FFF:0x00400000 /* RW--D */
#define NV_PGRAPH_DEBUG_0 0x00400080 /* RW-4R */
#define NV_PGRAPH_DEBUG_0_STATE 0:0 /* CW-VF */
#define NV_PGRAPH_DEBUG_0_STATE_NORMAL 0x00000000 /* CW--V */
#define NV_PGRAPH_DEBUG_0_STATE_RESET 0x00000001 /* -W--V */
#define NV_PGRAPH_DEBUG_0_BULK_READS 4:4 /* RWIVF */
#define NV_PGRAPH_DEBUG_0_BULK_READS_DISABLED 0x00000000 /* RWI-V */
#define NV_PGRAPH_DEBUG_0_BULK_READS_ENABLED 0x00000001 /* RW--V */
#define NV_PGRAPH_DEBUG_0_WRITE_ONLY_ROPS_2D 20:20 /* RWIVF */
#define NV_PGRAPH_DEBUG_0_WRITE_ONLY_ROPS_2D_DISABLED 0x00000000 /* RWI-V */
#define NV_PGRAPH_DEBUG_0_WRITE_ONLY_ROPS_2D_ENABLED 0x00000001 /* RW--V */
#define NV_PGRAPH_DEBUG_0_DRAWDIR_AUTO 24:24 /* RWIVF */
#define NV_PGRAPH_DEBUG_0_DRAWDIR_AUTO_DISABLED 0x00000000 /* RWI-V */
#define NV_PGRAPH_DEBUG_0_DRAWDIR_AUTO_ENABLED 0x00000001 /* RW--V */
#define NV_PGRAPH_DEBUG_1 0x00400084 /* RW-4R */
#define NV_PGRAPH_DEBUG_1_VOLATILE_RESET 0:0 /* RWIVF */
#define NV_PGRAPH_DEBUG_1_VOLATILE_RESET_NOT_LAST 0x00000000 /* RWI-V */
#define NV_PGRAPH_DEBUG_1_VOLATILE_RESET_LAST 0x00000001 /* RW--V */
#define NV_PGRAPH_DEBUG_1_INSTANCE 16:16 /* RWIVF */
#define NV_PGRAPH_DEBUG_1_INSTANCE_DISABLED 0x00000000 /* RWI-V */
#define NV_PGRAPH_DEBUG_1_INSTANCE_ENABLED 0x00000001 /* RW--V */
#define NV_PGRAPH_DEBUG_1_CTX 20:20 /* RWIVF */
#define NV_PGRAPH_DEBUG_1_CTX_DISABLED 0x00000000 /* RWI-V */
#define NV_PGRAPH_DEBUG_1_CTX_ENABLED 0x00000001 /* RW--V */
#define NV_PGRAPH_DEBUG_2 0x00400088 /* RW-4R */
#define NV_PGRAPH_DEBUG_2_AVOID_RMW_BLEND 0:0 /* RWIVF */
#define NV_PGRAPH_DEBUG_2_AVOID_RMW_BLEND_DISABLED 0x00000000 /* RWI-V */
#define NV_PGRAPH_DEBUG_2_AVOID_RMW_BLEND_ENABLED 0x00000001 /* RW--V */
#define NV_PGRAPH_DEBUG_2_DPWR_FIFO 8:8 /* RWIVF */
#define NV_PGRAPH_DEBUG_2_DPWR_FIFO_DISABLED 0x00000000 /* RWI-V */
#define NV_PGRAPH_DEBUG_2_DPWR_FIFO_ENABLED 0x00000001 /* RW--V */
#define NV_PGRAPH_DEBUG_2_VOLATILE_RESET 28:28 /* RWIVF */
#define NV_PGRAPH_DEBUG_2_VOLATILE_RESET_DISABLED 0x00000000 /* RWI-V */
#define NV_PGRAPH_DEBUG_2_VOLATILE_RESET_ENABLED 0x00000001 /* RW--V */
#define NV_PGRAPH_DEBUG_3 0x0040008C /* RW-4R */
#define NV_PGRAPH_DEBUG_3_HONOR_ALPHA 24:24 /* RWIVF */
#define NV_PGRAPH_DEBUG_3_HONOR_ALPHA_DISABLED 0x00000000 /* RWI-V */
#define NV_PGRAPH_DEBUG_3_HONOR_ALPHA_ENABLED 0x00000001 /* RW--V */
 
#define NV_PGRAPH_INTR_0 0x00400100 /* RW-4R */
#define NV_PGRAPH_INTR_0_RESERVED 0:0 /* RW-VF */
#define NV_PGRAPH_INTR_0_RESERVED_NOT_PENDING 0x00000000 /* R---V */
#define NV_PGRAPH_INTR_0_RESERVED_PENDING 0x00000001 /* R---V */
#define NV_PGRAPH_INTR_0_RESERVED_RESET 0x00000001 /* -W--V */
#define NV_PGRAPH_INTR_0_CONTEXT_SWITCH 4:4 /* RWIVF */
#define NV_PGRAPH_INTR_0_CONTEXT_SWITCH_NOT_PENDING 0x00000000 /* R-I-V */
#define NV_PGRAPH_INTR_0_CONTEXT_SWITCH_PENDING 0x00000001 /* R---V */
#define NV_PGRAPH_INTR_0_CONTEXT_SWITCH_RESET 0x00000001 /* -W--V */
#define NV_PGRAPH_INTR_0_VBLANK 8:8 /* RWIVF */
#define NV_PGRAPH_INTR_0_VBLANK_NOT_PENDING 0x00000000 /* R-I-V */
#define NV_PGRAPH_INTR_0_VBLANK_PENDING 0x00000001 /* R---V */
#define NV_PGRAPH_INTR_0_VBLANK_RESET 0x00000001 /* -W--V */
#define NV_PGRAPH_INTR_0_RANGE 12:12 /* RWIVF */
#define NV_PGRAPH_INTR_0_RANGE_NOT_PENDING 0x00000000 /* R-I-V */
#define NV_PGRAPH_INTR_0_RANGE_PENDING 0x00000001 /* R---V */
#define NV_PGRAPH_INTR_0_RANGE_RESET 0x00000001 /* -W--V */
#define NV_PGRAPH_INTR_0_METHOD_COUNT 16:16 /* RWIVF */
#define NV_PGRAPH_INTR_0_METHOD_COUNT_NOT_PENDING 0x00000000 /* R-I-V */
#define NV_PGRAPH_INTR_0_METHOD_COUNT_PENDING 0x00000001 /* R---V */
#define NV_PGRAPH_INTR_0_METHOD_COUNT_RESET 0x00000001 /* -W--V */
#define NV_PGRAPH_INTR_0_FORMAT 20:20 /* RWIVF */
#define NV_PGRAPH_INTR_0_FORMAT_NOT_PENDING 0x00000000 /* R-I-V */
#define NV_PGRAPH_INTR_0_FORMAT_PENDING 0x00000001 /* R---V */
#define NV_PGRAPH_INTR_0_FORMAT_RESET 0x00000001 /* -W--V */
#define NV_PGRAPH_INTR_0_COMPLEX_CLIP 24:24 /* RWIVF */
#define NV_PGRAPH_INTR_0_COMPLEX_CLIP_NOT_PENDING 0x00000000 /* R-I-V */
#define NV_PGRAPH_INTR_0_COMPLEX_CLIP_PENDING 0x00000001 /* R---V */
#define NV_PGRAPH_INTR_0_COMPLEX_CLIP_RESET 0x00000001 /* -W--V */
#define NV_PGRAPH_INTR_0_NOTIFY 28:28 /* RWIVF */
#define NV_PGRAPH_INTR_0_NOTIFY_NOT_PENDING 0x00000000 /* R-I-V */
#define NV_PGRAPH_INTR_0_NOTIFY_PENDING 0x00000001 /* R---V */
#define NV_PGRAPH_INTR_0_NOTIFY_RESET 0x00000001 /* -W--V */
 
#define NV_PGRAPH_INTR_1 0x00400104 /* RW-4R */
#define NV_PGRAPH_INTR_1_METHOD 0:0 /* RWIVF */
#define NV_PGRAPH_INTR_1_METHOD_NOT_PENDING 0x00000000 /* R-I-V */
#define NV_PGRAPH_INTR_1_METHOD_PENDING 0x00000001 /* R---V */
#define NV_PGRAPH_INTR_1_METHOD_RESET 0x00000001 /* -W--V */
#define NV_PGRAPH_INTR_1_DATA 4:4 /* RWIVF */
#define NV_PGRAPH_INTR_1_DATA_NOT_PENDING 0x00000000 /* R-I-V */
#define NV_PGRAPH_INTR_1_DATA_PENDING 0x00000001 /* R---V */
#define NV_PGRAPH_INTR_1_DATA_RESET 0x00000001 /* -W--V */
#define NV_PGRAPH_INTR_1_DOUBLE_NOTIFY 12:12 /* RWIVF */
#define NV_PGRAPH_INTR_1_DOUBLE_NOTIFY_NOT_PENDING 0x00000000 /* R-I-V */
#define NV_PGRAPH_INTR_1_DOUBLE_NOTIFY_PENDING 0x00000001 /* R---V */
#define NV_PGRAPH_INTR_1_DOUBLE_NOTIFY_RESET 0x00000001 /* -W--V */
#define NV_PGRAPH_INTR_1_CTXSW_NOTIFY 16:16 /* RWIVF */
#define NV_PGRAPH_INTR_1_CTXSW_NOTIFY_NOT_PENDING 0x00000000 /* R-I-V */
#define NV_PGRAPH_INTR_1_CTXSW_NOTIFY_PENDING 0x00000001 /* R---V */
#define NV_PGRAPH_INTR_1_CTXSW_NOTIFY_RESET 0x00000001 /* -W--V */
 
#define NV_PGRAPH_INTR_EN_0 0x00400140 /* RW-4R */
 
#define NV_PGRAPH_INTR_EN_1 0x00400144 /* RW-4R */
 
#define NV_PGRAPH_CTX_CACHE(i) (0x004001a0+(i)*4) /* RW-4A */
#define NV_PGRAPH_CTX_CACHE__SIZE_1 8 /* */
 
#define NV_PGRAPH_CTX_SWITCH 0x00400180 /* RW-4R */
 
#define NV_PGRAPH_CTX_CONTROL 0x00400190 /* RW-4R */
#define NV_PGRAPH_CTX_CONTROL_MINIMUM_TIME 1:0 /* RWIVF */
#define NV_PGRAPH_CTX_CONTROL_MINIMUM_TIME_33US 0x00000000 /* RWI-V */
#define NV_PGRAPH_CTX_CONTROL_MINIMUM_TIME_262US 0x00000001 /* RW--V */
#define NV_PGRAPH_CTX_CONTROL_MINIMUM_TIME_2MS 0x00000002 /* RW--V */
#define NV_PGRAPH_CTX_CONTROL_MINIMUM_TIME_17MS 0x00000003 /* RW--V */
#define NV_PGRAPH_CTX_CONTROL_TIME 8:8 /* RWIVF */
#define NV_PGRAPH_CTX_CONTROL_TIME_EXPIRED 0x00000000 /* RWI-V */
#define NV_PGRAPH_CTX_CONTROL_TIME_NOT_EXPIRED 0x00000001 /* RW--V */
#define NV_PGRAPH_CTX_CONTROL_CHID 16:16 /* RWIVF */
#define NV_PGRAPH_CTX_CONTROL_CHID_INVALID 0x00000000 /* RWI-V */
#define NV_PGRAPH_CTX_CONTROL_CHID_VALID 0x00000001 /* RW--V */
#define NV_PGRAPH_CTX_CONTROL_SWITCH 20:20 /* R--VF */
#define NV_PGRAPH_CTX_CONTROL_SWITCH_UNAVAILABLE 0x00000000 /* R---V */
#define NV_PGRAPH_CTX_CONTROL_SWITCH_AVAILABLE 0x00000001 /* R---V */
#define NV_PGRAPH_CTX_CONTROL_SWITCHING 24:24 /* RWIVF */
#define NV_PGRAPH_CTX_CONTROL_SWITCHING_IDLE 0x00000000 /* RWI-V */
#define NV_PGRAPH_CTX_CONTROL_SWITCHING_BUSY 0x00000001 /* RW--V */
#define NV_PGRAPH_CTX_CONTROL_DEVICE 28:28 /* RWIVF */
#define NV_PGRAPH_CTX_CONTROL_DEVICE_DISABLED 0x00000000 /* RWI-V */
#define NV_PGRAPH_CTX_CONTROL_DEVICE_ENABLED 0x00000001 /* RW--V */
 
#define NV_PGRAPH_CTX_USER 0x00400194 /* RW-4R */
 
#define NV_PGRAPH_FIFO 0x004006A4 /* RW-4R */
#define NV_PGRAPH_FIFO_ACCESS 0:0 /* RWIVF */
#define NV_PGRAPH_FIFO_ACCESS_DISABLED 0x00000000 /* RW--V */
#define NV_PGRAPH_FIFO_ACCESS_ENABLED 0x00000001 /* RWI-V */
 
#define NV_PGRAPH_STATUS 0x004006B0 /* R--4R */
 
#define NV_PGRAPH_CLIP_MISC 0x004006A0 /* RW-4R */
#define NV_PGRAPH_SRC_CANVAS_MIN 0x00400550 /* RW-4R */
#define NV_PGRAPH_DST_CANVAS_MIN 0x00400558 /* RW-4R */
#define NV_PGRAPH_SRC_CANVAS_MAX 0x00400554 /* RW-4R */
#define NV_PGRAPH_DST_CANVAS_MAX 0x0040055C /* RW-4R */
#define NV_PGRAPH_CLIP0_MIN 0x00400690 /* RW-4R */
#define NV_PGRAPH_CLIP1_MIN 0x00400698 /* RW-4R */
#define NV_PGRAPH_CLIP0_MAX 0x00400694 /* RW-4R */
#define NV_PGRAPH_CLIP1_MAX 0x0040069C /* RW-4R */
#define NV_PGRAPH_DMA 0x00400680 /* RW-4R */
#define NV_PGRAPH_NOTIFY 0x00400684 /* RW-4R */
#define NV_PGRAPH_INSTANCE 0x00400688 /* RW-4R */
#define NV_PGRAPH_MEMFMT 0x0040068C /* RW-4R */
#define NV_PGRAPH_BOFFSET0 0x00400630 /* RW-4R */
#define NV_PGRAPH_BOFFSET1 0x00400634 /* RW-4R */
#define NV_PGRAPH_BOFFSET2 0x00400638 /* RW-4R */
#define NV_PGRAPH_BOFFSET3 0x0040063C /* RW-4R */
#define NV_PGRAPH_BPITCH0 0x00400650 /* RW-4R */
#define NV_PGRAPH_BPITCH1 0x00400654 /* RW-4R */
#define NV_PGRAPH_BPITCH2 0x00400658 /* RW-4R */
#define NV_PGRAPH_BPITCH3 0x0040065C /* RW-4R */
 
#define NV_PGRAPH_BPIXEL 0x004006a8 /* RW-4R */
#define NV_PGRAPH_BPIXEL_DEPTH0_FMT 1:0 /* RWXVF */
#define NV_PGRAPH_BPIXEL_DEPTH0_FMT_Y16_BITS 0x00000000 /* RW--V */
#define NV_PGRAPH_BPIXEL_DEPTH0_FMT_BITS_8 0x00000001 /* RW--V */
#define NV_PGRAPH_BPIXEL_DEPTH0_FMT_BITS_16 0x00000002 /* RW--V */
#define NV_PGRAPH_BPIXEL_DEPTH0_FMT_BITS_32 0x00000003 /* RW--V */
#define NV_PGRAPH_BPIXEL_DEPTH0 2:2 /* RWXVF */
#define NV_PGRAPH_BPIXEL_DEPTH0_NOT_VALID 0x00000000 /* RW--V */
#define NV_PGRAPH_BPIXEL_DEPTH0_VALID 0x00000001 /* RW--V */
#define NV_PGRAPH_BPIXEL_DEPTH1_FMT 5:4 /* RWXVF */
#define NV_PGRAPH_BPIXEL_DEPTH1_FMT_Y16_BITS 0x00000000 /* RW--V */
#define NV_PGRAPH_BPIXEL_DEPTH1_FMT_BITS_8 0x00000001 /* RW--V */
#define NV_PGRAPH_BPIXEL_DEPTH1_FMT_BITS_16 0x00000002 /* RW--V */
#define NV_PGRAPH_BPIXEL_DEPTH1_FMT_BITS_32 0x00000003 /* RW--V */
#define NV_PGRAPH_BPIXEL_DEPTH1 6:6 /* RWXVF */
#define NV_PGRAPH_BPIXEL_DEPTH1_NOT_VALID 0x00000000 /* RW--V */
#define NV_PGRAPH_BPIXEL_DEPTH1_VALID 0x00000001 /* RW--V */
#define NV_PGRAPH_BPIXEL_DEPTH2_FMT 9:8 /* RWXVF */
#define NV_PGRAPH_BPIXEL_DEPTH2_FMT_Y16_BITS 0x00000000 /* RW--V */
#define NV_PGRAPH_BPIXEL_DEPTH2_FMT_BITS_8 0x00000001 /* RW--V */
#define NV_PGRAPH_BPIXEL_DEPTH2_FMT_BITS_16 0x00000002 /* RW--V */
#define NV_PGRAPH_BPIXEL_DEPTH2_FMT_BITS_32 0x00000003 /* RW--V */
#define NV_PGRAPH_BPIXEL_DEPTH2 10:10 /* RWXVF */
#define NV_PGRAPH_BPIXEL_DEPTH2_NOT_VALID 0x00000000 /* RW--V */
#define NV_PGRAPH_BPIXEL_DEPTH2_VALID 0x00000001 /* RW--V */
#define NV_PGRAPH_BPIXEL_DEPTH3_FMT 13:12 /* RWXVF */
#define NV_PGRAPH_BPIXEL_DEPTH3_FMT_Y16_BITS 0x00000000 /* RW--V */
#define NV_PGRAPH_BPIXEL_DEPTH3_FMT_BITS_8 0x00000001 /* RW--V */
#define NV_PGRAPH_BPIXEL_DEPTH3_FMT_BITS_16 0x00000002 /* RW--V */
#define NV_PGRAPH_BPIXEL_DEPTH3_FMT_BITS_32 0x00000003 /* RW--V */
#define NV_PGRAPH_BPIXEL_DEPTH3 14:14 /* RWXVF */
#define NV_PGRAPH_BPIXEL_DEPTH3_NOT_VALID 0x00000000 /* RW--V */
#define NV_PGRAPH_BPIXEL_DEPTH3_VALID 0x00000001 /* RW--V */
 
#define NV_PGRAPH_PATT_COLOR0_0 0x00400600 /* RW-4R */
#define NV_PGRAPH_PATT_COLOR0_1 0x00400604 /* RW-4R */
#define NV_PGRAPH_PATT_COLOR1_0 0x00400608 /* RW-4R */
#define NV_PGRAPH_PATT_COLOR1_1 0x0040060C /* RW-4R */
#define NV_PGRAPH_PATTERN(i) (0x00400610+(i)*4) /* RW-4A */
#define NV_PGRAPH_PATTERN_SHAPE 0x00400618 /* RW-4R */
#define NV_PGRAPH_PATTERN_SHAPE_VALUE 1:0 /* RWXVF */
#define NV_PGRAPH_PATTERN_SHAPE_VALUE_8X8 0x00000000 /* RW--V */
#define NV_PGRAPH_PATTERN_SHAPE_VALUE_64X1 0x00000001 /* RW--V */
#define NV_PGRAPH_PATTERN_SHAPE_VALUE_1X64 0x00000002 /* RW--V */
#define NV_PGRAPH_MONO_COLOR0 0x0040061C /* RW-4R */
#define NV_PGRAPH_ROP3 0x00400624 /* RW-4R */
#define NV_PGRAPH_PLANE_MASK 0x00400628 /* RW-4R */
#define NV_PGRAPH_CHROMA 0x0040062C /* RW-4R */
#define NV_PGRAPH_BETA 0x00400640 /* RW-4R */
#define NV_PGRAPH_CONTROL_OUT 0x00400644 /* RW-4R */
#define NV_PGRAPH_ABS_X_RAM(i) (0x00400400+(i)*4) /* RW-4A */
#define NV_PGRAPH_ABS_X_RAM__SIZE_1 32 /* */
#define NV_PGRAPH_ABS_Y_RAM(i) (0x00400480+(i)*4) /* RW-4A */
#define NV_PGRAPH_ABS_Y_RAM__SIZE_1 32 /* */
 
#define NV_PGRAPH_XY_LOGIC_MISC0 0x00400514 /* RW-4R */
#define NV_PGRAPH_XY_LOGIC_MISC1 0x00400518 /* RW-4R */
#define NV_PGRAPH_XY_LOGIC_MISC2 0x0040051C /* RW-4R */
#define NV_PGRAPH_XY_LOGIC_MISC1_DVDY_VALUE 0x00000000 /* RWI-V */
#define NV_PGRAPH_XY_LOGIC_MISC3 0x00400520 /* RW-4R */
#define NV_PGRAPH_X_MISC 0x00400500 /* RW-4R */
#define NV_PGRAPH_Y_MISC 0x00400504 /* RW-4R */
#define NV_PGRAPH_ABS_UCLIP_XMIN 0x0040053C /* RW-4R */
#define NV_PGRAPH_ABS_UCLIP_XMAX 0x00400544 /* RW-4R */
#define NV_PGRAPH_ABS_UCLIP_YMIN 0x00400540 /* RW-4R */
#define NV_PGRAPH_ABS_UCLIP_YMAX 0x00400548 /* RW-4R */
#define NV_PGRAPH_ABS_UCLIPA_XMIN 0x00400560 /* RW-4R */
#define NV_PGRAPH_ABS_UCLIPA_XMAX 0x00400568 /* RW-4R */
#define NV_PGRAPH_ABS_UCLIPA_YMIN 0x00400564 /* RW-4R */
#define NV_PGRAPH_ABS_UCLIPA_YMAX 0x0040056C /* RW-4R */
#define NV_PGRAPH_SOURCE_COLOR 0x0040050C /* RW-4R */
#define NV_PGRAPH_EXCEPTIONS 0x00400508 /* RW-4R */
#define NV_PGRAPH_ABS_ICLIP_XMAX 0x00400534 /* RW-4R */
#define NV_PGRAPH_ABS_ICLIP_YMAX 0x00400538 /* RW-4R */
#define NV_PGRAPH_CLIPX_0 0x00400524 /* RW-4R */
#define NV_PGRAPH_CLIPX_1 0x00400528 /* RW-4R */
#define NV_PGRAPH_CLIPY_0 0x0040052c /* RW-4R */
#define NV_PGRAPH_CLIPY_1 0x00400530 /* RW-4R */
#define NV_PGRAPH_DMA_INTR_0 0x00401100 /* RW-4R */
#define NV_PGRAPH_DMA_INTR_0_INSTANCE 0:0 /* RWXVF */
#define NV_PGRAPH_DMA_INTR_0_INSTANCE_NOT_PENDING 0x00000000 /* R---V */
#define NV_PGRAPH_DMA_INTR_0_INSTANCE_PENDING 0x00000001 /* R---V */
#define NV_PGRAPH_DMA_INTR_0_INSTANCE_RESET 0x00000001 /* -W--V */
#define NV_PGRAPH_DMA_INTR_0_PRESENT 4:4 /* RWXVF */
#define NV_PGRAPH_DMA_INTR_0_PRESENT_NOT_PENDING 0x00000000 /* R---V */
#define NV_PGRAPH_DMA_INTR_0_PRESENT_PENDING 0x00000001 /* R---V */
#define NV_PGRAPH_DMA_INTR_0_PRESENT_RESET 0x00000001 /* -W--V */
#define NV_PGRAPH_DMA_INTR_0_PROTECTION 8:8 /* RWXVF */
#define NV_PGRAPH_DMA_INTR_0_PROTECTION_NOT_PENDING 0x00000000 /* R---V */
#define NV_PGRAPH_DMA_INTR_0_PROTECTION_PENDING 0x00000001 /* R---V */
#define NV_PGRAPH_DMA_INTR_0_PROTECTION_RESET 0x00000001 /* -W--V */
#define NV_PGRAPH_DMA_INTR_0_LINEAR 12:12 /* RWXVF */
#define NV_PGRAPH_DMA_INTR_0_LINEAR_NOT_PENDING 0x00000000 /* R---V */
#define NV_PGRAPH_DMA_INTR_0_LINEAR_PENDING 0x00000001 /* R---V */
#define NV_PGRAPH_DMA_INTR_0_LINEAR_RESET 0x00000001 /* -W--V */
#define NV_PGRAPH_DMA_INTR_0_NOTIFY 16:16 /* RWXVF */
#define NV_PGRAPH_DMA_INTR_0_NOTIFY_NOT_PENDING 0x00000000 /* R---V */
#define NV_PGRAPH_DMA_INTR_0_NOTIFY_PENDING 0x00000001 /* R---V */
#define NV_PGRAPH_DMA_INTR_0_NOTIFY_RESET 0x00000001 /* -W--V */
#define NV_PGRAPH_DMA_INTR_EN_0 0x00401140 /* RW-4R */
#define NV_PGRAPH_DMA_CONTROL 0x00401210 /* RW-4R */
 
#define NV_PFB 0x00100FFF:0x00100000 /* RW--D */
#define NV_PFB_BOOT_0 0x00100000 /* RW-4R */
#define NV_PFB_BOOT_0_RAM_AMOUNT 1:0 /* RWIVF */
#define NV_PFB_BOOT_0_RAM_AMOUNT_1MB 0x00000000 /* RW--V */
#define NV_PFB_BOOT_0_RAM_AMOUNT_2MB 0x00000001 /* RW--V */
#define NV_PFB_BOOT_0_RAM_AMOUNT_4MB 0x00000002 /* RW--V */
 
#define NV_PFB_CONFIG_0 0x00100200 /* RW-4R */
#define NV_PFB_CONFIG_0_RESOLUTION 5:0 /* RWIVF */
#define NV_PFB_CONFIG_0_RESOLUTION_320_PIXELS 0x0000000a /* RW--V */
#define NV_PFB_CONFIG_0_RESOLUTION_400_PIXELS 0x0000000d /* RW--V */
#define NV_PFB_CONFIG_0_RESOLUTION_480_PIXELS 0x0000000f /* RW--V */
#define NV_PFB_CONFIG_0_RESOLUTION_512_PIXELS 0x00000010 /* RW--V */
#define NV_PFB_CONFIG_0_RESOLUTION_640_PIXELS 0x00000014 /* RW--V */
#define NV_PFB_CONFIG_0_RESOLUTION_800_PIXELS 0x00000019 /* RW--V */
#define NV_PFB_CONFIG_0_RESOLUTION_960_PIXELS 0x0000001e /* RW--V */
#define NV_PFB_CONFIG_0_RESOLUTION_1024_PIXELS 0x00000020 /* RW--V */
#define NV_PFB_CONFIG_0_RESOLUTION_1152_PIXELS 0x00000024 /* RW--V */
#define NV_PFB_CONFIG_0_RESOLUTION_1280_PIXELS 0x00000028 /* RW--V */
#define NV_PFB_CONFIG_0_RESOLUTION_1600_PIXELS 0x00000032 /* RW--V */
#define NV_PFB_CONFIG_0_RESOLUTION_DEFAULT 0x00000014 /* RWI-V */
#define NV_PFB_CONFIG_0_PIXEL_DEPTH 9:8 /* RWIVF */
#define NV_PFB_CONFIG_0_PIXEL_DEPTH_8_BITS 0x00000001 /* RW--V */
#define NV_PFB_CONFIG_0_PIXEL_DEPTH_16_BITS 0x00000002 /* RW--V */
#define NV_PFB_CONFIG_0_PIXEL_DEPTH_32_BITS 0x00000003 /* RW--V */
#define NV_PFB_CONFIG_0_PIXEL_DEPTH_DEFAULT 0x00000001 /* RWI-V */
#define NV_PFB_CONFIG_0_TILING 12:12 /* RWIVF */
#define NV_PFB_CONFIG_0_TILING_ENABLED 0x00000000 /* RW--V */
#define NV_PFB_CONFIG_0_TILING_DISABLED 0x00000001 /* RWI-V */
 
#define NV_PFB_BOOT_10 0x0010020C /* RW-4R */
 
 
#define NV_PRAMIN 0x00FFFFFF:0x00C00000
#define NV_PNVM 0x00BFFFFF:0x00800000
#define NV_CHAN0 0x0080ffff:0x00800000
 
#define NV_UROP 0x00421FFF:0x00420000 /* -W--D */
#define NV_UCHROMA 0x00431FFF:0x00430000 /* -W--D */
#define NV_UPLANE 0x00441FFF:0x00440000 /* -W--D */
#define NV_UCLIP 0x00451FFF:0x00450000 /* -W--D */
#define NV_UPATT 0x00461FFF:0x00460000 /* -W--D */
#define NV_ULINE 0x00491FFF:0x00490000 /* -W--D */
#define NV_ULIN 0x004A1FFF:0x004A0000 /* -W--D */
#define NV_UTRI 0x004B1FFF:0x004B0000 /* -W--D */
#define NV_URECT 0x00471FFF:0x00470000 /* -W--D */
#define NV_UBLIT 0x00501FFF:0x00500000 /* -W--D */
#define NV_UBITMAP 0x00521FFF:0x00520000 /* -W--D */
 
#define NV_PVGA0 0x000C0000
#define NV_PVGA1 0x00601000
#define NV_PVGA2 0x00681000
 
#endif
/shark/tags/rel_0_5/drivers/svga/vga_helper.c
0,0 → 1,40
#include <kernel/log.h>
#include <ll/i386/hw-instr.h>
#include <ll/i386/hw-io.h>
#include <ll/sys/types.h>
 
void port_rep_outb(unsigned char* string, int length, int port)
{
printk(KERN_INFO "port_rep_outb: NOT SUPPORTED !!\n");
}
 
void port_out(int value, int port)
{
outp(port,(BYTE)value);
}
 
void port_outw(int value, int port)
{
outpw(port,(WORD)value);
}
 
void port_outl(int value, int port)
{
outpd(port,(DWORD)value);
}
 
int port_in(int port)
{
return (WORD)inp(port);
}
 
int port_inw(int port)
{
return (WORD)inpw(port);
}
 
int port_inl(int port)
{
return (WORD)inpd(port);
}
 
/shark/tags/rel_0_5/drivers/svga/ramdac.c
0,0 → 1,122
/*
* ramdac.c:
*
* This file contains RAMDAC definitions of type DacMethods for
* various DACs.
*
* Note that the restoreState function is the only function that
* should program the DAC registers; the initializeState function
* should merely define the values that will be written in a
* subsequent call of the restore funtion.
*/
 
#include <stdlib.h>
//#include <stdio.h>
#include "libvga.h"
 
#include "timing.h"
#include "vgaregs.h"
#include "driver.h" /* for __svgalib_driver_report */
#include "ramdac.h"
 
/*
* The following function probes the DACs in daclist, which must be
* terminated by NULL. It returns the detected DAC if successful, NULL
* otherwise. The detected DAC is also initialized.
*/
 
DacMethods *__svgalib_probeDacs(DacMethods ** dacs_to_probe)
{
/* Probe for a RAMDAC. */
for (;;) {
DacMethods *dac;
dac = *dacs_to_probe;
if (dac == NULL)
/* None found. */
return NULL;
if (dac->probe()) {
dac->initialize();
return dac;
}
dacs_to_probe++;
}
}
 
int __svgalib_setDacSpeed(int dacspeed, int defspeed)
{
if (!dacspeed) {
if (__svgalib_driver_report)
printk(KERN_INFO "svgalib: Assuming %dMHz DAC.\n", defspeed / 1000);
dacspeed = defspeed;
} else {
if (__svgalib_driver_report)
printk(KERN_INFO "svgalib: DAC speed set to %dMHz.\n", dacspeed / 1000);
}
return dacspeed;
}
 
#ifndef __OPTIMIZE__ /* otherwise inlined from ramdac.h */
void _ramdac_dactocomm(void)
{
inb(PEL_IW);
inb(PEL_MSK);
inb(PEL_MSK);
inb(PEL_MSK);
inb(PEL_MSK);
}
 
void _ramdac_dactopel(void)
{
inb(PEL_IW);
}
 
unsigned char _ramdac_setcomm(unsigned char data)
{
_ramdac_dactocomm();
outb(PEL_MSK, data);
_ramdac_dactocomm();
return inb(PEL_MSK);
}
#endif
 
/*
* List of all DACs.
*/
 
DacMethods *__svgalib_all_dacs[] =
{
#ifdef INCLUDE_NORMAL_DAC
&__svgalib_normal_dac_methods,
#endif
#ifdef INCLUDE_S3_SDAC_DAC
&__svgalib_S3_SDAC_methods,
#endif
#ifdef INCLUDE_S3_GENDAC_DAC
&__svgalib_S3_GENDAC_methods,
#endif
#ifdef INCLUDE_S3_TRIO64_DAC
&__svgalib_Trio64_methods,
#endif
#ifdef INCLUDE_SIERRA_DAC
&__svgalib_Sierra_32K_methods,
#endif
#ifdef INCLUDE_SC15025_DAC
&__svgalib_SC15025_methods,
#endif
#ifdef INCLUDE_ATT20C490_DAC
&__svgalib_ATT20C490_methods,
#endif
#ifdef INCLUDE_ATT20C498_DAC
&__svgalib_ATT20C498_methods,
#endif
#ifdef INCLUDE_ICW_DAC
&__svgalib_ICW_methods,
#endif
#ifdef INCLUDE_SC1148X_DAC
&__svgalib_SC1148X_methods,
#endif
#ifdef INCLUDE_ICS_GENDAC_DAC
&__svgalib_ICS_GENDAC_methods,
#endif
NULL
};
/shark/tags/rel_0_5/drivers/svga/timing.c
0,0 → 1,898
/*
* Generic mode timing module.
*/
#include <stdlib.h>
 
#include "timing.h" /* Types. */
 
#include "driver.h" /* for __svgalib_monitortype (remove me) */
 
/* Standard mode timings. */
 
MonitorModeTiming __svgalib_standard_timings[] =
{
#define S __svgalib_standard_timings
/* 320x200 @ 70 Hz, 31.5 kHz hsync */
{12588, 320, 336, 384, 400, 200, 204, 206, 225, DOUBLESCAN, S + 1},
/* 320x200 @ 83 Hz, 37.5 kHz hsync */
{13333, 320, 336, 384, 400, 200, 204, 206, 225, DOUBLESCAN, S + 2},
/* 320x240 @ 60 Hz, 31.5 kHz hsync */
{12588, 320, 336, 384, 400, 240, 245, 247, 263, DOUBLESCAN, S + 3},
/* 320x240 @ 72Hz, 38.5 kHz hsync */
{15000, 320, 336, 384, 400, 240, 244, 246, 261, DOUBLESCAN, S + 4},
/* 320x400 @ 70 Hz, 31.5 kHz hsync */
{12588, 320, 336, 384, 400, 400, 408, 412, 450, 0, S + 5},
/* 320x400 @ 83 Hz, 37.5 kHz hsync */
{13333, 320, 336, 384, 400, 400, 408, 412, 450, 0, S + 6},
/* 320x480 @ 60 Hz, 31.5 kHz hsync */
{12588, 320, 336, 384, 400, 480, 490, 494, 526, 0, S + 7},
/* 320x480 @ 72Hz, 38.5 kHz hsync */
{15000, 320, 336, 384, 400, 480, 488, 492, 522, 0, S + 8},
/* 400x300 @ 56 Hz, 35.2 kHz hsync, 4:3 aspect ratio */
{18000, 400, 416, 448, 512, 300, 301, 302, 312, DOUBLESCAN, S+9},
/* 400x300 @ 60 Hz, 37.8 kHz hsync */
{20000, 400, 416, 480, 528, 300, 301, 303, 314, DOUBLESCAN, S+10},
/* 400x300 @ 72 Hz, 48.0 kHz hsync*/
{25000, 400, 424, 488, 520, 300, 319, 322, 333, DOUBLESCAN, S+11},
/* 400x600 @ 56 Hz, 35.2 kHz hsync, 4:3 aspect ratio */
{18000, 400, 416, 448, 512, 600, 602, 604, 624, 0, S+12},
/* 400x600 @ 60 Hz, 37.8 kHz hsync */
{20000, 400, 416, 480, 528, 600, 602, 606, 628, 0, S+13},
/* 400x600 @ 72 Hz, 48.0 kHz hsync*/
{25000, 400, 424, 488, 520, 600, 639, 644, 666, 0, S+14},
/* 512x384 @ 67Hz */
{19600, 512, 522, 598, 646, 384, 418, 426, 454, 0, S+15 },
/* 512x384 @ 86Hz */
{25175, 512, 522, 598, 646, 384, 418, 426, 454,0, S+16},
/* 512x480 @ 55Hz */
{19600, 512, 522, 598, 646, 480, 500, 510, 550, 0, S+17},
/* 512x480 @ 71Hz */
{25175, 512, 522, 598, 646, 480, 500, 510, 550,0, S+18},
/* 640x400 at 70 Hz, 31.5 kHz hsync */
{25175, 640, 664, 760, 800, 400, 409, 411, 450, 0, S + 19},
/* 640x480 at 60 Hz, 31.5 kHz hsync */
{25175, 640, 664, 760, 800, 480, 491, 493, 525, 0, S + 20},
/* 640x480 at 72 Hz, 36.5 kHz hsync */
{31500, 640, 680, 720, 864, 480, 488, 491, 521, 0, S + 21},
/* 800x600 at 56 Hz, 35.15 kHz hsync */
{36000, 800, 824, 896, 1024, 600, 601, 603, 625, 0, S + 22},
/* 800x600 at 60 Hz, 37.8 kHz hsync */
{40000, 800, 840, 968, 1056, 600, 601, 605, 628, PHSYNC | PVSYNC, S + 23},
/* 800x600 at 72 Hz, 48.0 kHz hsync */
{50000, 800, 856, 976, 1040, 600, 637, 643, 666, PHSYNC | PVSYNC, S + 24},
/* 960x720 @ 70Hz */
{66000, 960, 984, 1112, 1248, 720, 723, 729, 756, NHSYNC | NVSYNC, S+25},
/* 960x720* interlaced, 35.5 kHz hsync */
{40000, 960, 984, 1192, 1216, 720, 728, 784, 817, INTERLACED, S + 26},
/* 1024x768 at 87 Hz interlaced, 35.5 kHz hsync */
{44900, 1024, 1048, 1208, 1264, 768, 776, 784, 817, INTERLACED, S + 27},
/* 1024x768 at 100 Hz, 40.9 kHz hsync */
{55000, 1024, 1048, 1208, 1264, 768, 776, 784, 817, INTERLACED, S + 28},
/* 1024x768 at 60 Hz, 48.4 kHz hsync */
{65000, 1024, 1032, 1176, 1344, 768, 771, 777, 806, NHSYNC | NVSYNC, S + 29},
/* 1024x768 at 70 Hz, 56.6 kHz hsync */
{75000, 1024, 1048, 1184, 1328, 768, 771, 777, 806, NHSYNC | NVSYNC, S + 30},
/* 1152x864 at 59.3Hz */
{85000, 1152, 1214, 1326, 1600, 864, 870, 885, 895, 0, S+31},
/* 1280x1024 at 87 Hz interlaced, 51 kHz hsync */
{80000, 1280, 1296, 1512, 1568, 1024, 1025, 1037, 1165, INTERLACED, S + 32},
/* 1024x768 at 76 Hz, 62.5 kHz hsync */
{85000, 1024, 1032, 1152, 1360, 768, 784, 787, 823, 0, S + 33},
/* 1280x1024 at 60 Hz, 64.3 kHz hsync */
{110000, 1280, 1328, 1512, 1712, 1024, 1025, 1028, 1054, 0, S + 34},
/* 1280x1024 at 74 Hz, 78.9 kHz hsync */
{135000, 1280, 1312, 1456, 1712, 1024, 1027, 1030, 1064, 0, S + 35},
/* 1600x1200 at 68Hz */
{188500, 1600, 1792, 1856, 2208, 1200, 1202, 1205, 1256, 0, S + 36},
/* 1600x1200 at 75 Hz */
{198000, 1600, 1616, 1776, 2112, 1200, 1201, 1204, 1250, 0, S + 37},
/* 720x540 at 56 Hz, 35.15 kHz hsync */
{32400, 720, 744, 808, 920, 540, 541, 543, 563, 0, S + 38},
/* 720x540 at 60 Hz, 37.8 kHz hsync */
{36000, 720, 760, 872, 952, 540, 541, 545, 565, 0, S + 39},
/* 720x540 at 72 Hz, 48.0 kHz hsync */
{45000, 720, 768, 880, 936, 540, 552, 558, 599, 0, S + 40},
/* 1072x600 at 57 Hz interlaced, 35.5 kHz hsync */
{44900, 1072, 1096, 1208, 1264, 600, 602, 604, 625, 0, S + 41},
/* 1072x600 at 65 Hz, 40.9 kHz hsync */
{55000, 1072, 1096, 1208, 1264, 600, 602, 604, 625, 0, S + 42},
/* 1072x600 at 78 Hz, 48.4 kHz hsync */
{65000, 1072, 1088, 1184, 1344, 600, 603, 607, 625, NHSYNC | NVSYNC, S + 43},
/* 1072x600 at 90 Hz, 56.6 kHz hsync */
{75000, 1072, 1096, 1200, 1328, 768, 603, 607, 625, NHSYNC | NVSYNC, S + 44},
/* 1072x600 at 100 Hz, 62.5 kHz hsync */
{85000, 1072, 1088, 1160, 1360, 768, 603, 607, 625, 0, NULL},
#undef S
};
 
#define NUMBER_OF_STANDARD_MODES \
(sizeof(__svgalib_standard_timings) / sizeof(__svgalib_standard_timings[0]))
 
static MonitorModeTiming *user_timings = NULL;
static MonitorModeTiming *current_timing, *force_timing = NULL, new_timing;
static void GTF_calcTimings(double hPixels,double vLines,double freq,
int type,int wantMargins,int wantInterlace, int wantDblscan,
MonitorModeTiming *mmt);
/*
* SYNC_ALLOWANCE is in percent
* 1% corresponds to a 315 Hz deviation at 31.5 kHz, 1 Hz at 100 Hz
*/
#define SYNC_ALLOWANCE 1
 
#define INRANGE(x,y) \
((x) > __svgalib_##y.min * (1.0f - SYNC_ALLOWANCE / 100.0f) && \
(x) < __svgalib_##y.max * (1.0f + SYNC_ALLOWANCE / 100.0f))
 
/*
* Check monitor spec.
*/
static int timing_within_monitor_spec(MonitorModeTiming * mmtp)
{
float hsf; /* Horz. sync freq in Hz */
float vsf; /* Vert. sync freq in Hz */
 
printk(KERN_INFO "Check Timing Within Monitor Spec...\n");
hsf = mmtp->pixelClock * 1000.0f / mmtp->HTotal;
vsf = hsf / mmtp->VTotal;
if ((mmtp->flags & INTERLACED))
vsf *= 2.0f;
if ((mmtp->flags & DOUBLESCAN))
vsf /= 2.0f;
 
printk(KERN_INFO "hsf = %f (in:%d), vsf = %f (in:%d)\n",
hsf / 1000, (int) INRANGE(hsf, horizsync),
vsf, (int) INRANGE(vsf, vertrefresh));
 
return INRANGE(hsf, horizsync) && INRANGE(vsf, vertrefresh);
}
 
void __svgalib_addusertiming(MonitorModeTiming * mmtp)
{
MonitorModeTiming *newmmt;
 
if (!(newmmt = malloc(sizeof(*newmmt))))
return;
*newmmt = *mmtp;
if(newmmt->VSyncStart<newmmt->VDisplay+1)newmmt->VSyncStart=newmmt->VDisplay+1;
if(newmmt->VSyncEnd<newmmt->VSyncStart+1)newmmt->VSyncEnd=newmmt->VSyncStart+1;
newmmt->next = user_timings;
user_timings = newmmt;
}
 
/*
* The __svgalib_getmodetiming function looks up a mode in the standard mode
* timings, choosing the mode with the highest dot clock that matches
* the requested svgalib mode, and is supported by the hardware
* (card limits, and monitor type). cardlimits points to a structure
* of type CardSpecs that describes the dot clocks the card supports
* at different depths. Returns non-zero if no mode is found.
*/
 
/*
* findclock is an auxilliary function that checks if a close enough
* pixel clock is provided by the card. Returns clock number if
* succesful (a special number if a programmable clock must be used), -1
* otherwise.
*/
 
/*
* Clock allowance in 1/1000ths. 10 (1%) corresponds to a 250 kHz
* deviation at 25 MHz, 1 MHz at 100 MHz
*/
#define CLOCK_ALLOWANCE 10
 
#define PROGRAMMABLE_CLOCK_MAGIC_NUMBER 0x1234
 
static int findclock(int clock, CardSpecs * cardspecs)
{
int i;
 
/* Find a clock that is close enough. */
for (i = 0; i < cardspecs->nClocks; i++) {
int diff;
diff = cardspecs->clocks[i] - clock;
if (diff < 0)
diff = -diff;
if (diff * 1000 / clock < CLOCK_ALLOWANCE)
return i;
}
/* Try programmable clocks if available. */
if (cardspecs->flags & CLOCK_PROGRAMMABLE) {
int diff;
diff = cardspecs->matchProgrammableClock(clock) - clock;
if (diff < 0)
diff = -diff;
if (diff * 1000 / clock < CLOCK_ALLOWANCE) {
return PROGRAMMABLE_CLOCK_MAGIC_NUMBER;
}
}
/* No close enough clock found. */
return -1;
}
 
static MonitorModeTiming *search_mode(MonitorModeTiming * timings,
int maxclock,
ModeInfo * modeinfo,
CardSpecs * cardspecs)
{
int bestclock = 0;
MonitorModeTiming *besttiming = NULL, *t;
 
/*
* bestclock is the highest pixel clock found for the resolution
* in the mode timings, within the spec of the card and
* monitor.
* besttiming holds a pointer to timing with this clock.
*/
 
/* Search the timings for the best matching mode. */
for (t = timings; t; t = t->next)
if (t->HDisplay == modeinfo->width
&& t->VDisplay == modeinfo->height
&& ( (!(t->flags&INTERLACED)) || (!(cardspecs->flags&NO_INTERLACE)) )
&& timing_within_monitor_spec(t)
&& t->pixelClock <= maxclock
&& t->pixelClock > bestclock
&& cardspecs->mapHorizontalCrtc(modeinfo->bitsPerPixel,
t->pixelClock,
t->HTotal)
<= cardspecs->maxHorizontalCrtc
/* Find the clock (possibly scaled by mapClock). */
&& findclock(cardspecs->mapClock(modeinfo->bitsPerPixel,
t->pixelClock), cardspecs) != -1
) {
bestclock = t->pixelClock;
besttiming = t;
}
return besttiming;
}
 
int __svgalib_getmodetiming(ModeTiming * modetiming, ModeInfo * modeinfo,
CardSpecs * cardspecs)
{
int maxclock, desiredclock;
MonitorModeTiming *besttiming=NULL;
 
if(force_timing){
if(timing_within_monitor_spec(force_timing) &&
force_timing->HDisplay == modeinfo->width &&
force_timing->VDisplay == modeinfo->height)
{
besttiming=force_timing;
};
};
 
/* Get the maximum pixel clock for the depth of the requested mode. */
if (modeinfo->bitsPerPixel == 4)
maxclock = cardspecs->maxPixelClock4bpp;
else if (modeinfo->bitsPerPixel == 8)
maxclock = cardspecs->maxPixelClock8bpp;
else if (modeinfo->bitsPerPixel == 16) {
if ((cardspecs->flags & NO_RGB16_565)
&& modeinfo->greenWeight == 6)
return 1; /* No 5-6-5 RGB. */
maxclock = cardspecs->maxPixelClock16bpp;
} else if (modeinfo->bitsPerPixel == 24)
maxclock = cardspecs->maxPixelClock24bpp;
else if (modeinfo->bitsPerPixel == 32)
maxclock = cardspecs->maxPixelClock32bpp;
else
maxclock = 0;
 
/*
* Check user defined timings first.
* If there is no match within these, check the standard timings.
*/
if(!besttiming)
besttiming = search_mode(user_timings, maxclock, modeinfo, cardspecs);
if (!besttiming) {
besttiming = search_mode(__svgalib_standard_timings, maxclock, modeinfo, cardspecs);
if (!besttiming) return 1;
}
/*
* Copy the selected timings into the result, which may
* be adjusted for the chipset.
*/
 
modetiming->flags = besttiming->flags;
modetiming->pixelClock = besttiming->pixelClock; /* Formal clock. */
 
/*
* We know a close enough clock is available; the following is the
* exact clock that fits the mode. This is probably different
* from the best matching clock that will be programmed.
*/
desiredclock = cardspecs->mapClock(modeinfo->bitsPerPixel,
besttiming->pixelClock);
 
/* Fill in the best-matching clock that will be programmed. */
modetiming->selectedClockNo = findclock(desiredclock, cardspecs);
if (modetiming->selectedClockNo == PROGRAMMABLE_CLOCK_MAGIC_NUMBER) {
modetiming->programmedClock =
cardspecs->matchProgrammableClock(desiredclock);
modetiming->flags |= USEPROGRCLOCK;
} else
modetiming->programmedClock = cardspecs->clocks[
modetiming->selectedClockNo];
modetiming->HDisplay = besttiming->HDisplay;
modetiming->HSyncStart = besttiming->HSyncStart;
modetiming->HSyncEnd = besttiming->HSyncEnd;
modetiming->HTotal = besttiming->HTotal;
if (cardspecs->mapHorizontalCrtc(modeinfo->bitsPerPixel,
modetiming->programmedClock,
besttiming->HTotal)
!= besttiming->HTotal) {
/* Horizontal CRTC timings are scaled in some way. */
modetiming->CrtcHDisplay =
cardspecs->mapHorizontalCrtc(modeinfo->bitsPerPixel,
modetiming->programmedClock,
besttiming->HDisplay);
modetiming->CrtcHSyncStart =
cardspecs->mapHorizontalCrtc(modeinfo->bitsPerPixel,
modetiming->programmedClock,
besttiming->HSyncStart);
modetiming->CrtcHSyncEnd =
cardspecs->mapHorizontalCrtc(modeinfo->bitsPerPixel,
modetiming->programmedClock,
besttiming->HSyncEnd);
modetiming->CrtcHTotal =
cardspecs->mapHorizontalCrtc(modeinfo->bitsPerPixel,
modetiming->programmedClock,
besttiming->HTotal);
modetiming->flags |= HADJUSTED;
} else {
modetiming->CrtcHDisplay = besttiming->HDisplay;
modetiming->CrtcHSyncStart = besttiming->HSyncStart;
modetiming->CrtcHSyncEnd = besttiming->HSyncEnd;
modetiming->CrtcHTotal = besttiming->HTotal;
}
modetiming->VDisplay = besttiming->VDisplay;
modetiming->VSyncStart = besttiming->VSyncStart;
modetiming->VSyncEnd = besttiming->VSyncEnd;
modetiming->VTotal = besttiming->VTotal;
if (modetiming->flags & DOUBLESCAN){
modetiming->VDisplay <<= 1;
modetiming->VSyncStart <<= 1;
modetiming->VSyncEnd <<= 1;
modetiming->VTotal <<= 1;
}
modetiming->CrtcVDisplay = modetiming->VDisplay;
modetiming->CrtcVSyncStart = modetiming->VSyncStart;
modetiming->CrtcVSyncEnd = modetiming->VSyncEnd;
modetiming->CrtcVTotal = modetiming->VTotal;
if (((modetiming->flags & INTERLACED)
&& (cardspecs->flags & INTERLACE_DIVIDE_VERT))
|| (modetiming->VTotal >= 1024
&& (cardspecs->flags & GREATER_1024_DIVIDE_VERT))) {
/*
* Card requires vertical CRTC timing to be halved for
* interlaced modes, or for all modes with vertical
* timing >= 1024.
*/
modetiming->CrtcVDisplay /= 2;
modetiming->CrtcVSyncStart /= 2;
modetiming->CrtcVSyncEnd /= 2;
modetiming->CrtcVTotal /= 2;
modetiming->flags |= VADJUSTED;
}
current_timing=besttiming;
printk(KERN_INFO "Found Valid Timing.\n");
return 0; /* Succesful. */
}
 
int vga_getcurrenttiming(int *pixelClock,
int *HDisplay,
int *HSyncStart,
int *HSyncEnd,
int *HTotal,
int *VDisplay,
int *VSyncStart,
int *VSyncEnd,
int *VTotal,
int *flags)
{
if(current_timing){
*pixelClock=current_timing->pixelClock;
*HDisplay=current_timing->HDisplay;
*HSyncStart=current_timing->HSyncStart;
*HSyncEnd=current_timing->HSyncEnd;
*HTotal=current_timing->HTotal;
*VDisplay=current_timing->VDisplay;
*VSyncStart=current_timing->VSyncStart;
*VSyncEnd=current_timing->VSyncEnd;
*VTotal=current_timing->VTotal;
*flags=current_timing->flags;
return 0;
}
return 1;
};
 
int vga_changetiming(int pixelClock,
int HDisplay,
int HSyncStart,
int HSyncEnd,
int HTotal,
int VDisplay,
int VSyncStart,
int VSyncEnd,
int VTotal,
int flags) {
if(current_timing){
new_timing=*current_timing;
new_timing.pixelClock+=pixelClock;
new_timing.HDisplay+=HDisplay;
new_timing.HSyncStart+=HSyncStart;
new_timing.HSyncEnd+=HSyncEnd;
new_timing.HTotal+=HTotal;
new_timing.VDisplay+=VDisplay;
new_timing.VSyncStart+=VSyncStart;
new_timing.VSyncEnd+=VSyncEnd;
new_timing.VTotal+=VTotal;
force_timing=&new_timing;
vga_setmode(CM|0x8000,CHIPSET);
force_timing=NULL;
};
return 1;
};
 
static int find_up_timing(int x, int y, int *bestx, int *besty, MonitorModeTiming **bestmodetiming)
{
MonitorModeTiming *t;
int bestclock=0;
int mode_ar;
 
*bestmodetiming=NULL;
*bestx=*besty=4096;
for (t = user_timings; t; t = t->next) {
if ((mode_ar=1000*t->VDisplay/t->HDisplay)<=765
&& mode_ar>=735
&& t->HDisplay >= x
&& t->VDisplay >= y
&& timing_within_monitor_spec(t)
&& t->HDisplay <= *bestx
&& t->VDisplay <= *besty
&& t->pixelClock>=bestclock
) {
bestclock = t->pixelClock;
*bestx=t->HDisplay;
*besty=t->VDisplay;
*bestmodetiming = t;
};
};
for (t = __svgalib_standard_timings; t; t = t->next) {
if (t->HDisplay >= x
&& t->VDisplay >= y
&& timing_within_monitor_spec(t)
&& t->HDisplay <= *bestx
&& t->VDisplay <= *besty
&& t->pixelClock>=bestclock
) {
bestclock = t->pixelClock;
*bestx=t->HDisplay;
*besty=t->VDisplay;
*bestmodetiming = t;
};
};
return *bestmodetiming!=NULL;
};
 
static int find_down_timing(int x, int y, int *bestx, int *besty, MonitorModeTiming **bestmodetiming)
{
MonitorModeTiming *t;
int bestclock=0;
int mode_ar;
 
*bestmodetiming=NULL;
*bestx=*besty=0;
for (t = user_timings; t; t = t->next) {
if ((mode_ar=1000*t->VDisplay/t->HDisplay)<=765
&& mode_ar>=735
&& t->HDisplay <= x
&& t->VDisplay <= y
&& timing_within_monitor_spec(t)
&& t->HDisplay >= *bestx
&& t->VDisplay >= *besty
&& t->pixelClock>=bestclock
) {
bestclock = t->pixelClock;
*bestx=t->HDisplay;
*besty=t->VDisplay;
*bestmodetiming = t;
};
};
for (t = __svgalib_standard_timings; t; t = t->next) {
if (t->HDisplay <= x
&& t->VDisplay <= y
&& timing_within_monitor_spec(t)
&& t->HDisplay >= *bestx
&& t->VDisplay >= *besty
&& t->pixelClock>=bestclock
) {
bestclock = t->pixelClock;
*bestx=t->HDisplay;
*besty=t->VDisplay;
*bestmodetiming = t;
};
};
return *bestmodetiming!=NULL;
};
 
int vga_guesstiming(int x, int y, int clue, int arg)
{
/* This functions tries to add timings that fit a specific mode,
by changing the timings of a similar mode
currently only works for x:y = 4:3, clue means:
0- scale down timing of a higher res mode
1- scale up timings of a lower res mode
*/
 
MonitorModeTiming mmt, *bestmodetiming = NULL ;
int bestx, besty, flag, mx, my /*, bestclock */ ;
 
int aspect_ratio=1000*y/x;
switch(clue) {
case 0: /* 0,1 only 4:3 ratio, find close mode, and up/down scale timing */
case 1:
if((aspect_ratio>765)||(aspect_ratio<735))return 0;
if(clue==0)find_up_timing(x,y,&bestx,&besty,&bestmodetiming);
if(clue==1)find_down_timing(x,y,&bestx,&besty,&bestmodetiming);
if(bestmodetiming){
mmt=*bestmodetiming;
mmt.pixelClock=(mmt.pixelClock*x)/bestx;
mmt.HDisplay=x;
mmt.VDisplay=y;
mmt.HSyncStart=(mmt.HSyncStart*x)/bestx;
mmt.HSyncEnd=(mmt.HSyncEnd*x)/bestx;
mmt.HTotal=(mmt.HTotal*x)/bestx;
mmt.VSyncStart=(mmt.VSyncStart*x)/bestx;
mmt.VSyncEnd=(mmt.VSyncEnd*x)/bestx;
mmt.VTotal=(mmt.VTotal*x)/bestx;
__svgalib_addusertiming(&mmt);
return 1;
};
break;
case 2: /* Use GTF, caller provides all parameters. */
flag = arg>>16;
GTF_calcTimings(x , y, arg&0xffff, flag&3, flag&4, flag&8, flag&16, &mmt);
__svgalib_addusertiming(&mmt);
return 1;
case 256: /* 256,257: find a 4:3 mode with y close to requested, and */
case 257: /* up/down scale timing */
mx=y*4/3;
if((clue&1)==0)find_up_timing(mx,y,&bestx,&besty,&bestmodetiming);
if((clue&1)==1)find_down_timing(mx,y,&bestx,&besty,&bestmodetiming);
if(bestmodetiming){
mmt=*bestmodetiming;
mmt.pixelClock=(mmt.pixelClock*x)/bestx;
mmt.HDisplay=x;
mmt.HSyncStart=(mmt.HSyncStart*x)/bestx;
mmt.HSyncEnd=(mmt.HSyncEnd*x)/bestx;
mmt.HTotal=(mmt.HTotal*x)/bestx;
mmt.VDisplay=y;
mmt.VSyncStart=(mmt.VSyncStart*mx)/bestx;
mmt.VSyncEnd=(mmt.VSyncEnd*mx)/bestx;
mmt.VTotal=(mmt.VTotal*mx)/bestx;
__svgalib_addusertiming(&mmt);
return 1;
};
break;
case 258: /* 258,259: find a 4:3 mode with x close to requested, and */
case 259: /* up/down scale timing */
my=(x*3)>>2;
if((clue&1)==0)find_up_timing(x,my,&bestx,&besty,&bestmodetiming);
if((clue&1)==1)find_down_timing(x,my,&bestx,&besty,&bestmodetiming);
if(bestmodetiming){
mmt=*bestmodetiming;
mmt.pixelClock=(mmt.pixelClock*x)/bestx;
mmt.HDisplay=x;
mmt.HSyncStart=(mmt.HSyncStart*x)/bestx;
mmt.HSyncEnd=(mmt.HSyncEnd*x)/bestx;
mmt.HTotal=(mmt.HTotal*x)/bestx;
mmt.VDisplay=y;
mmt.VSyncStart=(mmt.VSyncStart*y)/besty;
mmt.VSyncEnd=(mmt.VSyncEnd*y)/besty;
mmt.VTotal=(mmt.VTotal*y)/besty;
__svgalib_addusertiming(&mmt);
return 1;
};
break;
};
return 0;
};
 
/* Everything from here to the end of the file is copyright by
scitechsoft. See their original program in utils/gtf subdirectory */
typedef struct {
double margin; /* Margin size as percentage of display */
double cellGran; /* Character cell granularity */
double minPorch; /* Minimum front porch in lines/chars */
double vSyncRqd; /* Width of V sync in lines */
double hSync; /* Width of H sync as percent of total */
double minVSyncBP; /* Minimum vertical sync + back porch (us) */
double m; /* Blanking formula gradient */
double c; /* Blanking formula offset */
double k; /* Blanking formula scaling factor */
double j; /* Blanking formula scaling factor weight */
} GTF_constants;
 
static GTF_constants GC = {
1.8, /* Margin size as percentage of display */
8, /* Character cell granularity */
1, /* Minimum front porch in lines/chars */
3, /* Width of V sync in lines */
8, /* Width of H sync as percent of total */
550, /* Minimum vertical sync + back porch (us) */
600, /* Blanking formula gradient */
40, /* Blanking formula offset */
128, /* Blanking formula scaling factor */
20, /* Blanking formula scaling factor weight */
};
 
static double round(double v)
{
double u=v;
int j;
if(u<0) u=-u;
u=u+0.5;
j=u;
if(v<0) j=-j;
 
return j;
}
 
static double sqrt(double u)
{
double v,w;
int i;
v=0;
if(u==0) return 0;
if(u<0) u=-u;
w=u;
if(u<1) w=1;
for(i=0;i<50;i++){
w=w/2;
if(v*v==u)break;
if(v*v<u)v=v+w;
if(v*v>u)v=v-w;
};
return v;
}
static void GetInternalConstants(GTF_constants *c)
{
c->margin = GC.margin;
c->cellGran = round(GC.cellGran);
c->minPorch = round(GC.minPorch);
c->vSyncRqd = round(GC.vSyncRqd);
c->hSync = GC.hSync;
c->minVSyncBP = GC.minVSyncBP;
if (GC.k == 0)
c->k = 0.001;
else
c->k = GC.k;
c->m = (c->k / 256) * GC.m;
c->c = (GC.c - GC.j) * (c->k / 256) + GC.j;
c->j = GC.j;
}
 
static void GTF_calcTimings(double hPixels,double vLines,double freq,
int type,int wantMargins,int wantInterlace, int wantDblscan,
MonitorModeTiming *mmt)
{
double interlace,vFieldRate,hPeriod=0;
double topMarginLines,botMarginLines;
double leftMarginPixels,rightMarginPixels;
double hPeriodEst=0,vSyncBP=0,vBackPorch=0;
double vTotalLines=0,vFieldRateEst;
double hTotalPixels,hTotalActivePixels,hBlankPixels;
double idealDutyCycle=0,hSyncWidth,hSyncBP,hBackPorch;
double idealHPeriod;
double vFreq,hFreq,dotClock;
GTF_constants c;
 
/* Get rounded GTF constants used for internal calculations */
GetInternalConstants(&c);
 
/* Move input parameters into appropriate variables */
vFreq = hFreq = dotClock = freq;
 
/* Round pixels to character cell granularity */
hPixels = round(hPixels / c.cellGran) * c.cellGran;
 
/* For interlaced mode halve the vertical parameters, and double
* the required field refresh rate.
*/
if(wantDblscan) vLines = vLines * 2;
if (wantInterlace) {
vLines = round(vLines / 2);
vFieldRate = vFreq * 2;
dotClock = dotClock * 2;
interlace = 0.5;
}
else {
vFieldRate = vFreq;
interlace = 0;
}
 
/* Determine the lines for margins */
if (wantMargins) {
topMarginLines = round(c.margin / 100 * vLines);
botMarginLines = round(c.margin / 100 * vLines);
}
else {
topMarginLines = 0;
botMarginLines = 0;
}
 
if (type != GTF_lockPF) {
if (type == GTF_lockVF) {
/* Estimate the horizontal period */
hPeriodEst = ((1/vFieldRate) - (c.minVSyncBP/1000000)) /
(vLines + (2*topMarginLines) + c.minPorch + interlace) * 1000000;
 
/* Find the number of lines in vSync + back porch */
vSyncBP = round(c.minVSyncBP / hPeriodEst);
}
else if (type == GTF_lockHF) {
/* Find the number of lines in vSync + back porch */
vSyncBP = round((c.minVSyncBP * hFreq) / 1000);
}
 
/* Find the number of lines in the V back porch alone */
vBackPorch = vSyncBP - c.vSyncRqd;
 
/* Find the total number of lines in the vertical period */
vTotalLines = vLines + topMarginLines + botMarginLines + vSyncBP
+ interlace + c.minPorch;
 
if (type == GTF_lockVF) {
/* Estimate the vertical frequency */
vFieldRateEst = 1000000 / (hPeriodEst * vTotalLines);
 
/* Find the actual horizontal period */
hPeriod = (hPeriodEst * vFieldRateEst) / vFieldRate;
 
/* Find the actual vertical field frequency */
vFieldRate = 1000000 / (hPeriod * vTotalLines);
}
else if (type == GTF_lockHF) {
/* Find the actual vertical field frequency */
vFieldRate = (hFreq / vTotalLines) * 1000;
}
}
 
/* Find the number of pixels in the left and right margins */
if (wantMargins) {
leftMarginPixels = round(hPixels * c.margin) / (100 * c.cellGran);
rightMarginPixels = round(hPixels * c.margin) / (100 * c.cellGran);
}
else {
leftMarginPixels = 0;
rightMarginPixels = 0;
}
 
/* Find the total number of active pixels in image + margins */
hTotalActivePixels = hPixels + leftMarginPixels + rightMarginPixels;
 
if (type == GTF_lockVF) {
/* Find the ideal blanking duty cycle */
idealDutyCycle = c.c - ((c.m * hPeriod) / 1000);
}
else if (type == GTF_lockHF) {
/* Find the ideal blanking duty cycle */
idealDutyCycle = c.c - (c.m / hFreq);
}
else if (type == GTF_lockPF) {
/* Find ideal horizontal period from blanking duty cycle formula */
idealHPeriod = (((c.c - 100) + (sqrt(((100-c.c)*(100-c.c)) +
(0.4 * c.m * (hTotalActivePixels + rightMarginPixels +
leftMarginPixels) / dotClock)))) / (2 * c.m)) * 1000;
 
/* Find the ideal blanking duty cycle */
idealDutyCycle = c.c - ((c.m * idealHPeriod) / 1000);
}
 
/* Find the number of pixels in blanking time */
hBlankPixels = round((hTotalActivePixels * idealDutyCycle) /
((100 - idealDutyCycle) * 2 * c.cellGran)) * (2 * c.cellGran);
 
/* Find the total number of pixels */
hTotalPixels = hTotalActivePixels + hBlankPixels;
 
/* Find the horizontal back porch */
hBackPorch = round((hBlankPixels / 2) / c.cellGran) * c.cellGran;
 
/* Find the horizontal sync width */
hSyncWidth = round(((c.hSync/100) * hTotalPixels) / c.cellGran) * c.cellGran;
 
/* Find the horizontal sync + back porch */
hSyncBP = hBackPorch + hSyncWidth;
 
if (type == GTF_lockPF) {
/* Find the horizontal frequency */
hFreq = (dotClock / hTotalPixels) * 1000;
 
/* Find the horizontal period */
hPeriod = 1000 / hFreq;
 
/* Find the number of lines in vSync + back porch */
vSyncBP = round((c.minVSyncBP * hFreq) / 1000);
 
/* Find the number of lines in the V back porch alone */
vBackPorch = vSyncBP - c.vSyncRqd;
 
/* Find the total number of lines in the vertical period */
vTotalLines = vLines + topMarginLines + botMarginLines + vSyncBP
+ interlace + c.minPorch;
 
/* Find the actual vertical field frequency */
vFieldRate = (hFreq / vTotalLines) * 1000;
}
else {
if (type == GTF_lockVF) {
/* Find the horizontal frequency */
hFreq = 1000 / hPeriod;
}
else if (type == GTF_lockHF) {
/* Find the horizontal frequency */
hPeriod = 1000 / hFreq;
}
 
/* Find the pixel clock frequency */
dotClock = hTotalPixels / hPeriod;
}
 
/* Find the vertical frame frequency */
if (wantInterlace) {
vFreq = vFieldRate / 2;
}
else
vFreq = vFieldRate;
 
mmt->pixelClock = dotClock;
 
/* Determine the vertical timing parameters */
mmt->HTotal = hTotalPixels;
mmt->HDisplay = hTotalActivePixels;
mmt->HSyncStart = mmt->HTotal - hSyncBP;
mmt->HSyncEnd = mmt->HTotal - hBackPorch;
 
/* Determine the vertical timing parameters */
mmt->VTotal = vTotalLines;
mmt->VDisplay = vLines;
mmt->VSyncStart = mmt->VTotal - vSyncBP;
mmt->VSyncEnd = mmt->VTotal - vBackPorch;
 
if(wantDblscan) {
mmt->VTotal >>= 1;
mmt->VDisplay >>= 1 ;
mmt->VSyncStart >>= 1 ;
mmt->VSyncEnd >>= 1 ;
};
 
if(wantInterlace) {
mmt->VTotal <<= 1;
mmt->VDisplay <<= 1 ;
mmt->VSyncStart <<= 1 ;
mmt->VSyncEnd <<= 1 ;
};
 
mmt->flags = NHSYNC | PVSYNC | ((wantInterlace) ? INTERLACED : 0)
| ((wantDblscan) ? DOUBLESCAN : 0);
}
 
/shark/tags/rel_0_5/drivers/svga/normal.c
0,0 → 1,82
/*
* normal.c:
*
* RAMDAC definition for normal VGA DAC.
* Max dot clock is set at 80 MHz.
*/
 
#include <stdlib.h>
//#include <stdio.h>
#include "libvga.h"
 
#include "timing.h"
#include "vgaregs.h"
#include "driver.h" /* for __svgalib_driver_report */
#include "ramdac.h"
 
#ifdef INCLUDE_NORMAL_DAC_TEST
static int normal_dac_probe(void)
{
return 1;
}
#else
#define normal_dac_probe 0
#endif
 
#ifdef INCLUDE_NORMAL_DAC
static void normal_dac_init(void)
{
if (__svgalib_driver_report)
printk(KERN_INFO "svgalib: Using Normal VGA RAMDAC.\n");
}
 
static int normal_dac_map_clock(int bpp, int pixelclock)
{
return pixelclock;
}
 
static int normal_dac_map_horizontal_crtc(int bpp, int pixelclock, int htiming)
{
return htiming;
}
 
static void normal_dac_savestate(unsigned char *regs)
{
}
 
static void normal_dac_restorestate(const unsigned char *regs)
{
}
 
static void normal_dac_initializestate(unsigned char *regs, int bpp, int colormode,
int pixelclock)
{
/* Nothing to do. */
}
 
static void normal_dac_qualify_cardspecs(CardSpecs * cardspecs, int dacspeed)
{
dacspeed = __svgalib_setDacSpeed(dacspeed, 80000);
cardspecs->maxPixelClock4bpp = dacspeed;
cardspecs->maxPixelClock8bpp = dacspeed;
cardspecs->maxPixelClock16bpp = 0;
cardspecs->maxPixelClock24bpp = 0;
cardspecs->maxPixelClock32bpp = 0;
cardspecs->mapClock = normal_dac_map_clock;
cardspecs->mapHorizontalCrtc = normal_dac_map_horizontal_crtc;
}
 
DacMethods __svgalib_normal_dac_methods =
{
NORMAL_DAC,
"Normal VGA DAC",
0,
normal_dac_probe,
normal_dac_init,
normal_dac_qualify_cardspecs,
normal_dac_savestate,
normal_dac_restorestate,
normal_dac_initializestate,
0 /* State size. */
};
#endif
/shark/tags/rel_0_5/drivers/svga/vgadraw.c
0,0 → 1,590
/* VGAlib version 1.2 - (c) 1993 Tommy Frandsen */
/* */
/* This library is free software; you can redistribute it and/or */
/* modify it without any restrictions. This library is distributed */
/* in the hope that it will be useful, but without any warranty. */
 
/* Multi-chipset support Copyright 1993 Harm Hanemaayer */
/* partially copyrighted (C) 1993 by Hartmut Schirmer */
 
/* 21 January 1995 - added vga_readscanline(), added support for */
/* non 8-pixel aligned scanlines in 16 color mode. billr@rastergr.com */
#include <stdio.h>
#include "vga.h"
#include "libvga.h"
#include "driver.h"
 
/* used to decompose color value into bits (for fast scanline drawing) */
union bits {
struct {
unsigned char bit3;
unsigned char bit2;
unsigned char bit1;
unsigned char bit0;
} b;
unsigned int i;
};
 
/* color decompositions */
static union bits color16[16] =
{
{
{0, 0, 0, 0}},
{
{0, 0, 0, 1}},
{
{0, 0, 1, 0}},
{
{0, 0, 1, 1}},
{
{0, 1, 0, 0}},
{
{0, 1, 0, 1}},
{
{0, 1, 1, 0}},
{
{0, 1, 1, 1}},
{
{1, 0, 0, 0}},
{
{1, 0, 0, 1}},
{
{1, 0, 1, 0}},
{
{1, 0, 1, 1}},
{
{1, 1, 0, 0}},
{
{1, 1, 0, 1}},
{
{1, 1, 1, 0}},
{
{1, 1, 1, 1}}};
 
/* mask for end points in plane buffer mode */
static unsigned char mask[8] =
{
0xff, 0x7f, 0x3f, 0x1f, 0x0f, 0x07, 0x03, 0x01};
/* display plane buffers (for fast scanline drawing) */
/* 256 bytes -> max 2048 pixel per line (2/16 colors) */
static unsigned char plane0[256];
static unsigned char plane1[256];
static unsigned char plane2[256];
static unsigned char plane3[256];
 
static inline void shifted_memcpy(void *dest_in, void *source_in, int len)
{
int *dest = dest_in;
int *source = source_in;
 
len >>= 2;
 
while (len--)
*dest++ = (*source++ << 8);
}
 
/* RGB_swapped_memcopy returns the amount of bytes unhandled */
static inline int RGB_swapped_memcpy(char *dest, char *source, int len)
{
int rest, tmp;
 
tmp = len / 3;
rest = len - 3 * tmp;
len = tmp;
 
while (len--) {
*dest++ = source[2];
*dest++ = source[1];
*dest++ = source[0];
source += 3;
}
 
return rest;
}
 
int vga_drawscanline(int line, unsigned char *colors)
{
if ((CI.colors == 2) || (CI.colors > 256))
return vga_drawscansegment(colors, 0, line, CI.xbytes);
else
return vga_drawscansegment(colors, 0, line, CI.xdim);
}
 
#ifdef LIBC_MEMCPY
#define MEMCPY memcpy
#else
void MEMCPY(unsigned char *dst, unsigned char *src, size_t n) {
unsigned char *e;
e=src+n;
while(src<e) *(dst++)=*(src++);
}
#endif
 
int vga_drawscansegment(unsigned char *colors, int x, int y, int length)
{
/* both length and x must divide with 8 */
/* no longer true (at least for 16 & 256 colors) */
 
if (MODEX)
goto modeX;
switch (CI.colors) {
case 16:
{
int i, j, k, first, last, page, l1, l2;
int offset, eoffs, soffs, ioffs;
union bits bytes;
unsigned char *address;
 
k = 0;
soffs = ioffs = (x & 0x7); /* starting offset into first byte */
eoffs = (x + length) & 0x7; /* ending offset into last byte */
for (i = 0; i < length;) {
bytes.i = 0;
first = i;
last = i + 8 - ioffs;
if (last > length)
last = length;
for (j = first; j < last; j++, i++)
bytes.i = (bytes.i << 1) | color16[colors[j]].i;
plane0[k] = bytes.b.bit0;
plane1[k] = bytes.b.bit1;
plane2[k] = bytes.b.bit2;
plane3[k++] = bytes.b.bit3;
ioffs = 0;
}
if (eoffs) {
/* fixup last byte */
k--;
bytes.i <<= (8 - eoffs);
plane0[k] = bytes.b.bit0;
plane1[k] = bytes.b.bit1;
plane2[k] = bytes.b.bit2;
plane3[k++] = bytes.b.bit3;
}
offset = (y * CI.xdim + x) / 8;
vga_setpage((page = offset >> 16));
l1 = 0x10000 - (offset &= 0xffff);
/* k currently contains number of bytes to write */
if (l1 > k)
l1 = k;
l2 = k - l1;
/* make k the index of the last byte to write */
k--;
 
address = GM + offset;
 
/* disable Set/Reset Register */
__svgalib_outgra(0x01,0x00);
 
/* write to all bits */
__svgalib_outgra(0x08,0xff);
 
/* select write map mask register */
__svgalib_outseq(0x02,0x01);
 
/* select read map mask register */
__svgalib_outgra(0x04,0x00);
if (soffs)
plane0[0] |= *address & ~mask[soffs];
if (eoffs && l2 == 0)
plane0[k] |= *(address + l1 - 1) & mask[eoffs];
MEMCPY(address, plane0, l1);
 
/* write plane 1 */
__svgalib_outseq(0x02,0x02);
/* read plane 1 */
__svgalib_outgra(0x04,0x01);
if (soffs)
plane1[0] |= *address & ~mask[soffs];
if (eoffs && l2 == 0)
plane1[k] |= *(address + l1 - 1) & mask[eoffs];
MEMCPY(address, plane1, l1);
 
/* write plane 2 */
__svgalib_outseq(0x02,0x04);
/* read plane 2 */
__svgalib_outgra(0x04,0x02);
if (soffs)
plane2[0] |= *address & ~mask[soffs];
if (eoffs && l2 == 0)
plane2[k] |= *(address + l1 - 1) & mask[eoffs];
MEMCPY(address, plane2, l1);
 
/* write plane 3 */
__svgalib_outseq(0x02,0x08);
/* read plane 3 */
__svgalib_outgra(0x04,0x03);
if (soffs)
plane3[0] |= *address & ~mask[soffs];
if (eoffs && l2 == 0)
plane3[k] |= *(address + l1 - 1) & mask[eoffs];
MEMCPY(address, plane3, l1);
 
if (l2 > 0) {
vga_setpage(page + 1);
 
/* write plane 0 */
__svgalib_outseq(0x02,0x01);
if (eoffs) {
/* read plane 0 */
__svgalib_outgra(0x04,0x00);
plane0[k] |= *(GM + l2 - 1) & mask[eoffs];
}
MEMCPY(GM, &plane0[l1], l2);
 
/* write plane 1 */
__svgalib_outseq(0x02,0x02);
if (eoffs) {
/* read plane 1 */
__svgalib_outgra(0x04,0x01);
plane1[k] |= *(GM + l2 - 1) & mask[eoffs];
}
MEMCPY(GM, &plane1[l1], l2);
 
/* write plane 2 */
__svgalib_outseq(0x02,0x04);
if (eoffs) {
/* read plane 2 */
__svgalib_outgra(0x04,0x02);
plane2[k] |= *(GM + l2 - 1) & mask[eoffs];
}
MEMCPY(GM, &plane2[l1], l2);
 
/* write plane 3 */
__svgalib_outseq(0x02,0x08);
if (eoffs) {
/* read plane 3 */
__svgalib_outgra(0x04,0x03);
plane3[k] |= *(GM + l2 - 1) & mask[eoffs];
}
MEMCPY(GM, &plane3[l1], l2);
}
/* restore map mask register */
__svgalib_outseq(0x02,0x0f);
 
/* enable Set/Reset Register */
__svgalib_outgra(0x01,0x0f);
}
break;
case 2:
{
/* disable Set/Reset Register */
__svgalib_outgra(0x01,0x00);
 
/* write to all bits */
__svgalib_outgra(0x08,0xff);
 
/* write to all planes */
__svgalib_outseq(0x02,0x0f);
 
MEMCPY(GM + (y * CI.xdim + x) / 8, colors, length);
 
/* restore map mask register */
__svgalib_outseq(0x02,0x0f);
 
/* enable Set/Reset Register */
__svgalib_outgra(0x01,0x0f);
}
break;
case 256:
{
switch (CM) {
case G320x200x256: /* linear addressing - easy and fast */
MEMCPY(GM + (y * CI.xdim + x), colors, length);
return 0;
case G320x240x256:
case G320x400x256:
case G360x480x256:
case G400x300x256X:
modeX:
{
int first, offset, pixel, plane;
 
for (plane = 0; plane < 4; plane++) {
/* select plane */
__svgalib_outseq(0x02,1 << plane );
 
pixel = ((4 - (x & 3) + plane) & 3);
first = (y * CI.xdim + x) / 4;
if((x & 3) + pixel > 3)
first++;
for (offset = first; pixel < length; offset++) {
*(GM+offset) = colors[pixel];
pixel += 4;
}
}
}
return 0;
}
{
unsigned long offset;
int segment, free;
 
SegmentedCopy:
offset = y * CI.xbytes + x;
if (__svgalib_modeinfo_linearset & IS_LINEAR ) {
MEMCPY(LINEAR_POINTER+offset, colors, length);
} else {
segment = offset >> 16;
free = ((segment + 1) << 16) - offset;
offset &= 0xFFFF;
if (free < length) {
vga_setpage(segment);
MEMCPY(GM + offset, colors, free);
vga_setpage(segment + 1);
MEMCPY(GM, colors + free, length - free);
} else {
vga_setpage(segment);
MEMCPY(GM + offset, colors, length);
}
}
}
}
break;
case 32768:
case 65536:
x *= 2;
goto SegmentedCopy;
case 1 << 24:
if (__svgalib_cur_info.bytesperpixel == 4) {
x <<= 2;
if (MODEFLAGS & RGB_MISORDERED) {
unsigned long offset;
int segment, free;
 
offset = y * CI.xbytes + x;
if (__svgalib_modeinfo_linearset & IS_LINEAR ) {
shifted_memcpy(LINEAR_POINTER+offset, colors, length);
} else {
segment = offset >> 16;
free = ((segment + 1) << 16) - offset;
offset &= 0xFFFF;
if (free < length) {
vga_setpage(segment);
shifted_memcpy(GM + offset, colors, free);
vga_setpage(segment + 1);
shifted_memcpy(GM, colors + free, length - free);
} else {
vga_setpage(segment);
shifted_memcpy(GM + offset, colors, length);
}
}
} else {
goto SegmentedCopy;
}
break;
}
x *= 3;
if (MODEFLAGS & RGB_MISORDERED) {
unsigned long offset;
int segment, free;
 
offset = y * CI.xbytes + x;
if (__svgalib_modeinfo_linearset & IS_LINEAR ) {
RGB_swapped_memcpy(LINEAR_POINTER+offset, colors, length);
} else {
segment = offset >> 16;
free = ((segment + 1) << 16) - offset;
offset &= 0xFFFF;
if (free < length) {
int i;
vga_setpage(segment);
i = RGB_swapped_memcpy(GM + offset, colors, free);
colors += (free - i);
switch (i) {
case 2:
*(GM+0xfffe) = colors[2];
*(GM+0xffff) = colors[1];
break;
case 1:
*(GM+0xffff) = colors[2];
break;
}
vga_setpage(segment + 1);
switch (i) {
case 1:
*(GM+1) = colors[0];
*(GM) = colors[1];
i = 3 - i;
free += i;
colors += 3;
break;
case 2:
*(GM) = colors[0];
i = 3 - i;
free += i;
colors += 3;
break;
}
RGB_swapped_memcpy(GM + i, colors, length - free);
} else {
vga_setpage(segment);
RGB_swapped_memcpy(GM + offset, colors, length);
}
}
} else {
goto SegmentedCopy;
}
}
 
return 0;
}
 
int vga_getscansegment(unsigned char *colors, int x, int y, int length)
{
 
if (MODEX)
goto modeX2;
switch (CI.colors) {
case 16:
{
int i, k, page, l1, l2;
int offset, eoffs, soffs, nbytes, bit;
unsigned char *address;
unsigned char color;
k = 0;
soffs = (x & 0x7); /* starting offset into first byte */
eoffs = (x + length) & 0x7; /* ending offset into last byte */
offset = (y * CI.xdim + x) / 8;
vga_setpage((page = offset >> 16));
l1 = 0x10000 - (offset &= 0xffff);
if (soffs)
nbytes = (length - (8 - soffs)) / 8 + 1;
else
nbytes = length / 8;
if (eoffs)
nbytes++;
if (l1 > nbytes)
l1 = nbytes;
l2 = nbytes - l1;
address = GM + offset;
/* disable Set/Reset Register */
__svgalib_outgra(0x01,0x00);
/* read plane 0 */
__svgalib_outgra(0x04,0x00);
memcpy(plane0, address, l1);
/* read plane 1 */
__svgalib_outgra(0x04,0x01);
memcpy(plane1, address, l1);
/* read plane 2 */
__svgalib_outgra(0x04,0x02);
memcpy(plane2, address, l1);
/* read plane 3 */
__svgalib_outgra(0x04,0x03);
memcpy(plane3, address, l1);
if (l2 > 0) {
vga_setpage(page + 1);
/* read plane 0 */
__svgalib_outgra(0x04,0x00);
memcpy(&plane0[l1], GM, l2);
/* read plane 1 */
__svgalib_outgra(0x04,0x01);
memcpy(&plane1[l1], GM, l2);
/* read plane 2 */
__svgalib_outgra(0x04,0x02);
memcpy(&plane2[l1], GM, l2);
/* read plane 3 */
__svgalib_outgra(0x04,0x03);
memcpy(&plane3[l1], GM, l2);
}
/* enable Set/Reset Register */
__svgalib_outgra(0x01,0x0f);
k = 0;
for (i = 0; i < length;) {
for (bit = 7 - soffs; bit >= 0 && i < length; bit--, i++) {
color = (plane0[k] & (1 << bit) ? 1 : 0);
color |= (plane1[k] & (1 << bit) ? 1 : 0) << 1;
color |= (plane2[k] & (1 << bit) ? 1 : 0) << 2;
color |= (plane3[k] & (1 << bit) ? 1 : 0) << 3;
colors[i] = color;
}
k++;
soffs = 0;
}
}
break;
case 2:
{
/* disable Set/Reset Register */
__svgalib_outgra(0x01,0x00);
/* read from plane 0 */
__svgalib_outseq(0x04,0x00);
memcpy(colors, GM + (y * CI.xdim + x) / 8, length);
/* enable Set/Reset Register */
__svgalib_outgra(0x01,0x0f);
}
break;
case 256:
{
switch (CM) {
case G320x200x256: /* linear addressing - easy and fast */
memcpy(colors, GM + y * CI.xdim + x, length);
return 0;
case G320x240x256:
case G320x400x256:
case G360x480x256:
case G400x300x256X:
modeX2:
{
int first, offset, pixel, plane;
for (plane = 0; plane < 4; plane++) {
/* select plane */
__svgalib_outgra(0x04, plane);
pixel = ((4 - (x & 3) + plane) & 3);
first = (y * CI.xdim + x) / 4;
if((x & 3) + pixel > 3)
first++;
for (offset = first; pixel < length; offset++) {
colors[pixel] = gr_readb(offset);
pixel += 4;
}
}
}
return 0;
}
{
unsigned long offset;
int segment, free;
SegmentedCopy2:
offset = y * CI.xbytes + x;
if (__svgalib_modeinfo_linearset & IS_LINEAR ) {
memcpy(colors, LINEAR_POINTER+offset, length);
} else {
segment = offset >> 16;
free = ((segment + 1) << 16) - offset;
offset &= 0xFFFF;
if (free < length) {
vga_setpage(segment);
memcpy(colors, GM + offset, free);
vga_setpage(segment + 1);
memcpy(colors + free, GM, length - free);
} else {
vga_setpage(segment);
memcpy(colors, GM + offset, length);
}
}
}
}
break;
case 32768:
case 65536:
x *= 2;
goto SegmentedCopy2;
case 1 << 24:
if (__svgalib_cur_info.bytesperpixel == 4) {
x<<=2;
} else {
x *= 3;
}
goto SegmentedCopy2;
}
return 0;
}
/shark/tags/rel_0_5/drivers/svga/vgammvgaio.c
0,0 → 1,109
#include "libvga.h"
#include "io.h"
 
unsigned long __svgalib_vgammbase;
 
int __svgalib_mm_inmisc(void)
{
return v_readb(__svgalib_vgammbase+MIS_R);
}
 
void __svgalib_mm_outmisc(int i)
{
v_writeb(i, __svgalib_vgammbase+MIS_W);
}
 
int __svgalib_mm_incrtc(int i)
{
v_writeb(i, __svgalib_vgammbase+__svgalib_CRT_I);
return v_readb(__svgalib_vgammbase+__svgalib_CRT_D);
}
 
void __svgalib_mm_outcrtc(int i, int d)
{
v_writeb(i, __svgalib_vgammbase+__svgalib_CRT_I);
v_writeb(d, __svgalib_vgammbase+__svgalib_CRT_D);
}
 
int __svgalib_mm_inseq(int i)
{
v_writeb(i, __svgalib_vgammbase+SEQ_I);
return v_readb(__svgalib_vgammbase+SEQ_D);
}
 
void __svgalib_mm_outseq(int i, int val)
{
v_writeb(i, __svgalib_vgammbase+SEQ_I);
v_writeb(val, __svgalib_vgammbase+SEQ_D);
}
 
int __svgalib_mm_ingra(int index)
{
v_writeb(index, __svgalib_vgammbase+GRA_I);
return v_readb(__svgalib_vgammbase+GRA_D);
}
 
void __svgalib_mm_outgra(int index, int val)
{
v_writeb(index, __svgalib_vgammbase+GRA_I);
v_writeb(val, __svgalib_vgammbase+GRA_D);
}
 
int __svgalib_mm_inis1(void)
{
return v_readb(__svgalib_vgammbase+__svgalib_IS1_R);
}
 
int __svgalib_mm_inatt(int index)
{
__svgalib_mm_inis1();
v_writeb(index, __svgalib_vgammbase+ATT_IW);
return v_readb(__svgalib_vgammbase+ATT_R);
}
 
void __svgalib_mm_outatt(int index, int val)
{
__svgalib_mm_inis1();
v_writeb(index, __svgalib_vgammbase+ATT_IW);
v_writeb(val, __svgalib_vgammbase+ATT_IW);
}
 
void __svgalib_mm_attscreen(int i)
{
__svgalib_mm_inis1();
v_writeb(i, __svgalib_vgammbase+ATT_IW);
}
 
void __svgalib_mm_inpal(int i, int *r, int *g, int *b)
{
v_writeb(i, __svgalib_vgammbase+PEL_IR);
*r=v_readb(__svgalib_vgammbase+PEL_D);
*g=v_readb(__svgalib_vgammbase+PEL_D);
*b=v_readb(__svgalib_vgammbase+PEL_D);
}
 
void __svgalib_mm_outpal(int i, int r, int g, int b)
{
v_writeb(i, __svgalib_vgammbase+PEL_IW);
v_writeb(r, __svgalib_vgammbase+PEL_D);
v_writeb(g, __svgalib_vgammbase+PEL_D);
v_writeb(b, __svgalib_vgammbase+PEL_D);
}
 
void __svgalib_mm_io_mapio(void)
{
__svgalib_inmisc=__svgalib_mm_inmisc;
__svgalib_outmisc=__svgalib_mm_outmisc;
__svgalib_incrtc=__svgalib_mm_incrtc;
__svgalib_outcrtc=__svgalib_mm_outcrtc;
__svgalib_inseq=__svgalib_mm_inseq;
__svgalib_outseq=__svgalib_mm_outseq;
__svgalib_ingra=__svgalib_mm_ingra;
__svgalib_outgra=__svgalib_mm_outgra;
__svgalib_inatt=__svgalib_mm_inatt;
__svgalib_outatt=__svgalib_mm_outatt;
__svgalib_attscreen=__svgalib_mm_attscreen;
__svgalib_inis1=__svgalib_mm_inis1;
__svgalib_inpal=__svgalib_mm_inpal;
__svgalib_outpal=__svgalib_mm_outpal;
}
/shark/tags/rel_0_5/drivers/linuxc24/include/linux/compatib.h
0,0 → 1,129
#include <kernel/kern.h>
#include "ll/sys/cdefs.h"
 
__BEGIN_DECLS
 
#ifndef __UNIXCOMP__
#define __UNIXCOMP__
 
#define LINUX_VERSION_CODE 0x22000
 
#define SA_NOCLDSTOP 1
#define SA_SHIRQ 0x04000000
#define SA_STACK 0x08000000
#define SA_RESTART 0x10000000
#define SA_INTERRUPT 0x20000000
#define SA_NOMASK 0x40000000
#define SA_ONESHOT 0x80000000
 
#define PAGE_SIZE 0x400
 
/* #define USE_SHARED_IRQ */
 
struct pt_regs {
}; /* This have to be checked... */
 
#define atomic_t int
 
#ifndef NULL
#define NULL 0
#endif
 
#define jiffies 0 /* Has to be controlled... */
#define HZ 100 /* Has to be controlled... */
extern long unsigned int loops_per_sec; /* ... */
#define EISA_bus 0 /* We do not support EISA buses... */
 
#define NET_BH 1 /* ???? */
 
/* Linux Module stub emulation... */
#define MOD_INC_USE_COUNT /* Do nothing... */
#define MOD_DEC_USE_COUNT /* Do nothing... */
#define MOD_IN_USE 0 /* No module => never in use... */
 
#define GFP_KERNEL 0x03 /* Don't know what it is... */
#define GFP_ATOMIC 0x01 /* Don't know what it is... */
 
 
/* Linux kernel call emulation */
#define kmalloc(a,b) malloc(a)
//#define printk cprintf I would like to use the kernel printk if possible...
#define check_region(a,b) 0
#define request_region(a,b,c)
 
/* Linux funcs emulation... */
#define outb_p(v,p) outp(p,v)
#define outb(v,p) outp(p,v)
#define outw(v,p) outpw(p,v)
#define outl(v,p) outpd(p,v)
#define inb_p(p) inp(p)
#define inb(p) inp(p)
#define inw(p) inpw(p)
#define inl(p) inpd(p)
#define malloc(a) kern_alloc(a)
 
#define mark_bh(NET_BH) /* Don't use soft int emulation... */
 
 
#define cli() kern_cli()
#define sti() kern_sti()
#define save_flags(f) f = kern_fsave()
#define restore_flags(f) kern_frestore(f)
 
 
/* URKA Stubs */
 
extern void panic_stub(void);
/* #define eth_header panic_stub */
#define eth_rebuild_header panic_stub
#define eth_header_cache_bind panic_stub
#define eth_header_cache_update panic_stub
 
 
#define atomic_sub(a,b)
 
 
#define vremap(a,b) 0
 
 
extern __inline__ int suser(void)
{
return 1;
}
 
 
// spinlocks
#define spinlock_t DWORD
#define spin_lock(x) (void)(x)
#define spin_unlock(x) (void)(x)
 
#define spin_lock_irqsave(x,y) y = kern_fsave()
#define spin_unlock_irqrestore(x,y) kern_frestore(y)
#define spin_lock_init(x)
#define SPIN_LOCK_UNLOCKED (spinlock_t) 0
 
 
extern __inline__ void panic(const char *c)
{
cputs((char *)c);
sys_end();
}
 
/* below tuff added for rtl8139 net driver
at some point this stuff should moved in a more conevenient place.
*/
 
/* *** from linux-2.2.17/include/linux/compatmac.h */
#define capable(x) suser()
 
/* *** from linux-2.2.17/include/linux/capability.h */
#define CAP_NET_ADMIN 12
 
/* *** from linux-2.2.17/include/linux/byteorder/little_endian.h */
#define __le16_to_cpu(x) ((__u16)(x))
 
/* *** from linux-2.2.17/include/linux/byteorder/generic.h */
#define le16_to_cpu __le16_to_cpu
 
__END_DECLS
#endif
/shark/tags/rel_0_5/drivers/linuxc24/include/linux/pci.h
0,0 → 1,23
/* OIO!!! I just have PCI!!! */
 
#ifndef __PCI__
#define __PCI__
 
#include <kernel/kern.h>
#include <drivers/pci.h>
#include <drivers/../../drivers/pci/linuxpci.h>
#include <linux/compatib.h>
 
#if 0
#define PCI_COMMAND 0x04 /* 16 bits */
#define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */
 
#define PCI_LATENCY_TIMER 0x0d /* 8 bits */
 
#define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */
 
#define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
#endif
 
#endif /* PCI_H */
 
/shark/tags/rel_0_5/drivers/linuxc24/include/linux/config.h
0,0 → 1,5
#ifndef _LINUX_CONFIG_H
#define _LINUX_CONFIG_H
 
 
#endif
/shark/tags/rel_0_5/drivers/linuxc24/include/asm/io.h
0,0 → 1,78
#ifndef __IO__
#define __IO__
 
#include <linux/compatib.h>
#include "ll/sys/cdefs.h"
 
__BEGIN_DECLS
 
/*
* Thanks to James van Artsdalen for a better timing-fix than
* the two short jumps: using outb's to a nonexistent port seems
* to guarantee better timings even on fast machines.
*
* On the other hand, I'd like to be sure of a non-existent port:
* I feel a bit unsafe about using 0x80 (should be safe, though)
*
* Linus
*/
 
#ifdef SLOW_IO_BY_JUMPING
#define __SLOW_DOWN_IO __asm__ __volatile__("jmp 1f\n1:\tjmp 1f\n1:")
#else
#define __SLOW_DOWN_IO __asm__ __volatile__("outb %al,$0x80")
#endif
 
#ifdef REALLY_SLOW_IO
#define SLOW_DOWN_IO { __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; }
#else
#define SLOW_DOWN_IO __SLOW_DOWN_IO
#endif
 
 
#define __INS(s) \
extern inline void ins##s(unsigned short port, void * addr, unsigned long count) \
{ __asm__ __volatile__ ("cld ; rep ; ins" #s \
: "=D" (addr), "=c" (count) : "d" (port),"0" (addr),"1" (count)); }
__INS(b)
__INS(w)
__INS(l)
 
#define __OUTS(s) \
extern inline void outs##s(unsigned short port, const void * addr, unsigned long count) \
{ __asm__ __volatile__ ("cld ; rep ; outs" #s \
: "=S" (addr), "=c" (count) : "d" (port),"0" (addr),"1" (count)); }
__OUTS(b)
__OUTS(w)
__OUTS(l)
 
/* Traslation from virtual to phisical address...*/
/* from asm/io.h */
 
#define __io_virt(x) ((void *)(x))
 
extern inline void * phys_to_virt(unsigned long address)
{
return __io_virt(address);
}
 
 
extern __inline__ DWORD virt_to_phys(volatile void * address)
{
return (DWORD)address;
}
 
#define bus_to_virt phys_to_virt
#define virt_to_bus virt_to_phys
 
 
#define readb(addr) (*(volatile unsigned char *) __io_virt(addr))
#define readw(addr) (*(volatile unsigned short *) __io_virt(addr))
#define readl(addr) (*(volatile unsigned int *) __io_virt(addr))
 
#define writeb(b,addr) (*(volatile unsigned char *) __io_virt(addr) = (b))
#define writew(b,addr) (*(volatile unsigned short *) __io_virt(addr) = (b))
#define writel(b,addr) (*(volatile unsigned int *) __io_virt(addr) = (b))
 
__END_DECLS
#endif
/shark/tags/rel_0_5/drivers/linuxc24/include/asm/ioctl.h
0,0 → 1,75
/* $Id: ioctl.h,v 1.1 2003-02-28 12:10:00 pj Exp $
*
* linux/ioctl.h for Linux by H.H. Bergman.
*/
 
#ifndef _ASMI386_IOCTL_H
#define _ASMI386_IOCTL_H
 
/* ioctl command encoding: 32 bits total, command in lower 16 bits,
* size of the parameter structure in the lower 14 bits of the
* upper 16 bits.
* Encoding the size of the parameter structure in the ioctl request
* is useful for catching programs compiled with old versions
* and to avoid overwriting user space outside the user buffer area.
* The highest 2 bits are reserved for indicating the ``access mode''.
* NOTE: This limits the max parameter size to 16kB -1 !
*/
 
/*
* The following is for compatibility across the various Linux
* platforms. The i386 ioctl numbering scheme doesn't really enforce
* a type field. De facto, however, the top 8 bits of the lower 16
* bits are indeed used as a type field, so we might just as well make
* this explicit here. Please be sure to use the decoding macros
* below from now on.
*/
#define _IOC_NRBITS 8
#define _IOC_TYPEBITS 8
#define _IOC_SIZEBITS 14
#define _IOC_DIRBITS 2
 
#define _IOC_NRMASK ((1 << _IOC_NRBITS)-1)
#define _IOC_TYPEMASK ((1 << _IOC_TYPEBITS)-1)
#define _IOC_SIZEMASK ((1 << _IOC_SIZEBITS)-1)
#define _IOC_DIRMASK ((1 << _IOC_DIRBITS)-1)
 
#define _IOC_NRSHIFT 0
#define _IOC_TYPESHIFT (_IOC_NRSHIFT+_IOC_NRBITS)
#define _IOC_SIZESHIFT (_IOC_TYPESHIFT+_IOC_TYPEBITS)
#define _IOC_DIRSHIFT (_IOC_SIZESHIFT+_IOC_SIZEBITS)
 
/*
* Direction bits.
*/
#define _IOC_NONE 0U
#define _IOC_WRITE 1U
#define _IOC_READ 2U
 
#define _IOC(dir,type,nr,size) \
(((dir) << _IOC_DIRSHIFT) | \
((type) << _IOC_TYPESHIFT) | \
((nr) << _IOC_NRSHIFT) | \
((size) << _IOC_SIZESHIFT))
 
/* used to create numbers */
#define _IO(type,nr) _IOC(_IOC_NONE,(type),(nr),0)
#define _IOR(type,nr,size) _IOC(_IOC_READ,(type),(nr),sizeof(size))
#define _IOW(type,nr,size) _IOC(_IOC_WRITE,(type),(nr),sizeof(size))
#define _IOWR(type,nr,size) _IOC(_IOC_READ|_IOC_WRITE,(type),(nr),sizeof(size))
 
/* used to decode ioctl numbers.. */
#define _IOC_DIR(nr) (((nr) >> _IOC_DIRSHIFT) & _IOC_DIRMASK)
#define _IOC_TYPE(nr) (((nr) >> _IOC_TYPESHIFT) & _IOC_TYPEMASK)
#define _IOC_NR(nr) (((nr) >> _IOC_NRSHIFT) & _IOC_NRMASK)
#define _IOC_SIZE(nr) (((nr) >> _IOC_SIZESHIFT) & _IOC_SIZEMASK)
 
/* ...and for the drivers/sound files... */
 
#define IOC_IN (_IOC_WRITE << _IOC_DIRSHIFT)
#define IOC_OUT (_IOC_READ << _IOC_DIRSHIFT)
#define IOC_INOUT ((_IOC_WRITE|_IOC_READ) << _IOC_DIRSHIFT)
#define IOCSIZE_MASK (_IOC_SIZEMASK << _IOC_SIZESHIFT)
#define IOCSIZE_SHIFT (_IOC_SIZESHIFT)
 
#endif /* _ASMI386_IOCTL_H */
/shark/tags/rel_0_5/drivers/linuxc24/include/asm/ioctls.h
0,0 → 1,83
#ifndef __ARCH_I386_IOCTLS_H__
#define __ARCH_I386_IOCTLS_H__
 
#include <asm/ioctl.h>
 
/* 0x54 is just a magic number to make these relatively unique ('T') */
 
#define TCGETS 0x5401
#define TCSETS 0x5402
#define TCSETSW 0x5403
#define TCSETSF 0x5404
#define TCGETA 0x5405
#define TCSETA 0x5406
#define TCSETAW 0x5407
#define TCSETAF 0x5408
#define TCSBRK 0x5409
#define TCXONC 0x540A
#define TCFLSH 0x540B
#define TIOCEXCL 0x540C
#define TIOCNXCL 0x540D
#define TIOCSCTTY 0x540E
#define TIOCGPGRP 0x540F
#define TIOCSPGRP 0x5410
#define TIOCOUTQ 0x5411
#define TIOCSTI 0x5412
#define TIOCGWINSZ 0x5413
#define TIOCSWINSZ 0x5414
#define TIOCMGET 0x5415
#define TIOCMBIS 0x5416
#define TIOCMBIC 0x5417
#define TIOCMSET 0x5418
#define TIOCGSOFTCAR 0x5419
#define TIOCSSOFTCAR 0x541A
#define FIONREAD 0x541B
#define TIOCINQ FIONREAD
#define TIOCLINUX 0x541C
#define TIOCCONS 0x541D
#define TIOCGSERIAL 0x541E
#define TIOCSSERIAL 0x541F
#define TIOCPKT 0x5420
#define FIONBIO 0x5421
#define TIOCNOTTY 0x5422
#define TIOCSETD 0x5423
#define TIOCGETD 0x5424
#define TCSBRKP 0x5425 /* Needed for POSIX tcsendbreak() */
#define TIOCTTYGSTRUCT 0x5426 /* For debugging only */
#define TIOCSBRK 0x5427 /* BSD compatibility */
#define TIOCCBRK 0x5428 /* BSD compatibility */
#define TIOCGSID 0x5429 /* Return the session ID of FD */
#define TIOCGPTN _IOR('T',0x30, unsigned int) /* Get Pty Number (of pty-mux device) */
#define TIOCSPTLCK _IOW('T',0x31, int) /* Lock/unlock Pty */
 
#define FIONCLEX 0x5450 /* these numbers need to be adjusted. */
#define FIOCLEX 0x5451
#define FIOASYNC 0x5452
#define TIOCSERCONFIG 0x5453
#define TIOCSERGWILD 0x5454
#define TIOCSERSWILD 0x5455
#define TIOCGLCKTRMIOS 0x5456
#define TIOCSLCKTRMIOS 0x5457
#define TIOCSERGSTRUCT 0x5458 /* For debugging only */
#define TIOCSERGETLSR 0x5459 /* Get line status register */
#define TIOCSERGETMULTI 0x545A /* Get multiport config */
#define TIOCSERSETMULTI 0x545B /* Set multiport config */
 
#define TIOCMIWAIT 0x545C /* wait for a change on serial input line(s) */
#define TIOCGICOUNT 0x545D /* read serial port inline interrupt counts */
#define TIOCGHAYESESP 0x545E /* Get Hayes ESP configuration */
#define TIOCSHAYESESP 0x545F /* Set Hayes ESP configuration */
#define FIOQSIZE 0x5460
 
/* Used for packet mode */
#define TIOCPKT_DATA 0
#define TIOCPKT_FLUSHREAD 1
#define TIOCPKT_FLUSHWRITE 2
#define TIOCPKT_STOP 4
#define TIOCPKT_START 8
#define TIOCPKT_NOSTOP 16
#define TIOCPKT_DOSTOP 32
 
#define TIOCSER_TEMT 0x01 /* Transmitter physically empty */
 
#endif
/shark/tags/rel_0_5/drivers/linuxc24/include/asm/types.h
0,0 → 1,59
#ifndef _I386_TYPES_H
#define _I386_TYPES_H
 
#define __signed__ signed
 
typedef unsigned short umode_t;
 
/*
* __xx is ok: it doesn't pollute the POSIX namespace. Use these in the
* header files exported to user space
*/
 
typedef __signed__ char __s8;
typedef unsigned char __u8;
 
typedef __signed__ short __s16;
typedef unsigned short __u16;
 
typedef __signed__ int __s32;
typedef unsigned int __u32;
 
#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
typedef __signed__ long long __s64;
typedef unsigned long long __u64;
#endif
 
/*
* These aren't exported outside the kernel to avoid name space clashes
*/
#ifdef __KERNEL__
 
#include <linux/config.h>
 
typedef signed char s8;
typedef unsigned char u8;
 
typedef signed short s16;
typedef unsigned short u16;
 
typedef signed int s32;
typedef unsigned int u32;
 
typedef signed long long s64;
typedef unsigned long long u64;
 
#define BITS_PER_LONG 32
 
/* DMA addresses come in generic and 64-bit flavours. */
 
#ifdef CONFIG_HIGHMEM
typedef u64 dma_addr_t;
#else
typedef u32 dma_addr_t;
#endif
typedef u64 dma64_addr_t;
 
#endif /* __KERNEL__ */
 
#endif
/shark/tags/rel_0_5/drivers/linuxc24/include/fpu_control.h
0,0 → 1,103
/* FPU control word bits. i387 version.
Copyright (C) 1993,1995,1996,1997,1998,2000,2001 Free Software Foundation, Inc.
This file is part of the GNU C Library.
Contributed by Olaf Flebbe.
 
The GNU C Library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option) any later version.
 
The GNU C Library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
 
You should have received a copy of the GNU Lesser General Public
License along with the GNU C Library; if not, write to the Free
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
02111-1307 USA. */
 
#ifndef _FPU_CONTROL_H
#define _FPU_CONTROL_H 1
 
#include "ll/sys/cdefs.h"
 
__BEGIN_DECLS
 
/* Here is the dirty part. Set up your 387 through the control word
* (cw) register.
*
* 15-13 12 11-10 9-8 7-6 5 4 3 2 1 0
* | reserved | IC | RC | PC | reserved | PM | UM | OM | ZM | DM | IM
*
* IM: Invalid operation mask
* DM: Denormalized operand mask
* ZM: Zero-divide mask
* OM: Overflow mask
* UM: Underflow mask
* PM: Precision (inexact result) mask
*
* Mask bit is 1 means no interrupt.
*
* PC: Precision control
* 11 - round to extended precision
* 10 - round to double precision
* 00 - round to single precision
*
* RC: Rounding control
* 00 - rounding to nearest
* 01 - rounding down (toward - infinity)
* 10 - rounding up (toward + infinity)
* 11 - rounding toward zero
*
* IC: Infinity control
* That is for 8087 and 80287 only.
*
* The hardware default is 0x037f which we use.
*/
 
#include <features.h>
 
/* masking of interrupts */
#define _FPU_MASK_IM 0x01
#define _FPU_MASK_DM 0x02
#define _FPU_MASK_ZM 0x04
#define _FPU_MASK_OM 0x08
#define _FPU_MASK_UM 0x10
#define _FPU_MASK_PM 0x20
 
/* precision control */
#define _FPU_EXTENDED 0x300 /* libm requires double extended precision. */
#define _FPU_DOUBLE 0x200
#define _FPU_SINGLE 0x0
 
/* rounding control */
#define _FPU_RC_NEAREST 0x0 /* RECOMMENDED */
#define _FPU_RC_DOWN 0x400
#define _FPU_RC_UP 0x800
#define _FPU_RC_ZERO 0xC00
 
#define _FPU_RESERVED 0xF0C0 /* Reserved bits in cw */
 
 
/* The fdlibm code requires strict IEEE double precision arithmetic,
and no interrupts for exceptions, rounding to nearest. */
 
#define _FPU_DEFAULT 0x037f
 
/* IEEE: same as above. */
#define _FPU_IEEE 0x037f
 
/* Type of the control word. */
typedef unsigned int fpu_control_t __attribute__ ((__mode__ (__HI__)));
 
/* Macros for accessing the hardware control word. */
#define _FPU_GETCW(cw) __asm__ ("fnstcw %0" : "=m" (*&cw))
#define _FPU_SETCW(cw) __asm__ ("fldcw %0" : : "m" (*&cw))
 
/* Default control word set at startup. */
extern fpu_control_t __fpu_control;
 
__END_DECLS
#endif /* fpu_control.h */
/shark/tags/rel_0_5/drivers/linuxc24/include/byteswap.h
0,0 → 1,44
/* Copyright (C) 1997 Free Software Foundation, Inc.
This file is part of the GNU C Library.
 
The GNU C Library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option) any later version.
 
The GNU C Library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
 
You should have received a copy of the GNU Lesser General Public
License along with the GNU C Library; if not, write to the Free
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
02111-1307 USA. */
 
#ifndef _BYTESWAP_H
#define _BYTESWAP_H 1
 
/* Get the machine specific, optimized definitions. */
#include <bits/byteswap.h>
#include "ll/sys/cdefs.h"
 
__BEGIN_DECLS
 
 
/* The following definitions must all be macros since otherwise some
of the possible optimizations are not possible. */
 
/* Return a value with all bytes in the 16 bit argument swapped. */
#define bswap_16(x) __bswap_16 (x)
 
/* Return a value with all bytes in the 32 bit argument swapped. */
#define bswap_32(x) __bswap_32 (x)
 
#if defined __GNUC__ && __GNUC__ >= 2
/* Return a value with all bytes in the 64 bit argument swapped. */
# define bswap_64(x) __bswap_64 (x)
#endif
 
__END_DECLS
#endif /* byteswap.h */
/shark/tags/rel_0_5/drivers/linuxc24/include/stdint.h
0,0 → 1,324
/* Copyright (C) 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
This file is part of the GNU C Library.
 
The GNU C Library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option) any later version.
 
The GNU C Library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
 
You should have received a copy of the GNU Lesser General Public
License along with the GNU C Library; if not, write to the Free
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
02111-1307 USA. */
 
/*
* ISO C99: 7.18 Integer types <stdint.h>
*/
 
#ifndef _STDINT_H
#define _STDINT_H 1
 
#include <features.h>
#include <bits/wchar.h>
#include <bits/wordsize.h>
#include "ll/sys/cdefs.h"
 
__BEGIN_DECLS
 
/* Exact integral types. */
 
/* Signed. */
 
/* There is some amount of overlap with <sys/types.h> as known by inet code */
#ifndef __int8_t_defined
# define __int8_t_defined
//typedef signed char int8_t; //SHARK
//typedef short int int16_t; //SHARK
//typedef int int32_t; //SHARK
# if __WORDSIZE == 64
//typedef long int int64_t; //SHARK
# else
__extension__
//typedef long long int int64_t; //SHARK
# endif
#endif
 
/* Unsigned. */
typedef unsigned char uint8_t;
typedef unsigned short int uint16_t;
#ifndef __uint32_t_defined
typedef unsigned int uint32_t;
# define __uint32_t_defined
#endif
#if __WORDSIZE == 64
typedef unsigned long int uint64_t;
#else
__extension__
typedef unsigned long long int uint64_t;
#endif
 
 
/* Small types. */
 
/* Signed. */
typedef signed char int_least8_t;
typedef short int int_least16_t;
typedef int int_least32_t;
#if __WORDSIZE == 64
typedef long int int_least64_t;
#else
__extension__
typedef long long int int_least64_t;
#endif
 
/* Unsigned. */
typedef unsigned char uint_least8_t;
typedef unsigned short int uint_least16_t;
typedef unsigned int uint_least32_t;
#if __WORDSIZE == 64
typedef unsigned long int uint_least64_t;
#else
__extension__
typedef unsigned long long int uint_least64_t;
#endif
 
 
/* Fast types. */
 
/* Signed. */
typedef signed char int_fast8_t;
#if __WORDSIZE == 64
typedef long int int_fast16_t;
typedef long int int_fast32_t;
typedef long int int_fast64_t;
#else
typedef int int_fast16_t;
typedef int int_fast32_t;
__extension__
typedef long long int int_fast64_t;
#endif
 
/* Unsigned. */
typedef unsigned char uint_fast8_t;
#if __WORDSIZE == 64
typedef unsigned long int uint_fast16_t;
typedef unsigned long int uint_fast32_t;
typedef unsigned long int uint_fast64_t;
#else
typedef unsigned int uint_fast16_t;
typedef unsigned int uint_fast32_t;
__extension__
typedef unsigned long long int uint_fast64_t;
#endif
 
 
/* Types for `void *' pointers. */
#if __WORDSIZE == 64
# ifndef __intptr_t_defined
typedef long int intptr_t;
# define __intptr_t_defined
# endif
typedef unsigned long int uintptr_t;
#else
# ifndef __intptr_t_defined
typedef int intptr_t;
# define __intptr_t_defined
# endif
typedef unsigned int uintptr_t;
#endif
 
 
/* Largest integral types. */
#if __WORDSIZE == 64
typedef long int intmax_t;
typedef unsigned long int uintmax_t;
#else
__extension__
typedef long long int intmax_t;
__extension__
typedef unsigned long long int uintmax_t;
#endif
 
 
/* The ISO C99 standard specifies that in C++ implementations these
macros should only be defined if explicitly requested. */
#if !defined __cplusplus || defined __STDC_LIMIT_MACROS
 
# if __WORDSIZE == 64
# define __INT64_C(c) c ## L
# define __UINT64_C(c) c ## UL
# else
# define __INT64_C(c) c ## LL
# define __UINT64_C(c) c ## ULL
# endif
 
/* Limits of integral types. */
 
/* Minimum of signed integral types. */
# define INT8_MIN (-128)
# define INT16_MIN (-32767-1)
# define INT32_MIN (-2147483647-1)
# define INT64_MIN (-__INT64_C(9223372036854775807)-1)
/* Maximum of signed integral types. */
# define INT8_MAX (127)
# define INT16_MAX (32767)
# define INT32_MAX (2147483647)
# define INT64_MAX (__INT64_C(9223372036854775807))
 
/* Maximum of unsigned integral types. */
# define UINT8_MAX (255)
# define UINT16_MAX (65535)
# define UINT32_MAX (4294967295U)
# define UINT64_MAX (__UINT64_C(18446744073709551615))
 
 
/* Minimum of signed integral types having a minimum size. */
# define INT_LEAST8_MIN (-128)
# define INT_LEAST16_MIN (-32767-1)
# define INT_LEAST32_MIN (-2147483647-1)
# define INT_LEAST64_MIN (-__INT64_C(9223372036854775807)-1)
/* Maximum of signed integral types having a minimum size. */
# define INT_LEAST8_MAX (127)
# define INT_LEAST16_MAX (32767)
# define INT_LEAST32_MAX (2147483647)
# define INT_LEAST64_MAX (__INT64_C(9223372036854775807))
 
/* Maximum of unsigned integral types having a minimum size. */
# define UINT_LEAST8_MAX (255)
# define UINT_LEAST16_MAX (65535)
# define UINT_LEAST32_MAX (4294967295U)
# define UINT_LEAST64_MAX (__UINT64_C(18446744073709551615))
 
 
/* Minimum of fast signed integral types having a minimum size. */
# define INT_FAST8_MIN (-128)
# if __WORDSIZE == 64
# define INT_FAST16_MIN (-9223372036854775807L-1)
# define INT_FAST32_MIN (-9223372036854775807L-1)
# else
# define INT_FAST16_MIN (-2147483647-1)
# define INT_FAST32_MIN (-2147483647-1)
# endif
# define INT_FAST64_MIN (-__INT64_C(9223372036854775807)-1)
/* Maximum of fast signed integral types having a minimum size. */
# define INT_FAST8_MAX (127)
# if __WORDSIZE == 64
# define INT_FAST16_MAX (9223372036854775807L)
# define INT_FAST32_MAX (9223372036854775807L)
# else
# define INT_FAST16_MAX (2147483647)
# define INT_FAST32_MAX (2147483647)
# endif
# define INT_FAST64_MAX (__INT64_C(9223372036854775807))
 
/* Maximum of fast unsigned integral types having a minimum size. */
# define UINT_FAST8_MAX (255)
# if __WORDSIZE == 64
# define UINT_FAST16_MAX (18446744073709551615UL)
# define UINT_FAST32_MAX (18446744073709551615UL)
# else
# define UINT_FAST16_MAX (4294967295U)
# define UINT_FAST32_MAX (4294967295U)
# endif
# define UINT_FAST64_MAX (__UINT64_C(18446744073709551615))
 
 
/* Values to test for integral types holding `void *' pointer. */
# if __WORDSIZE == 64
# define INTPTR_MIN (-9223372036854775807L-1)
# define INTPTR_MAX (9223372036854775807L)
# define UINTPTR_MAX (18446744073709551615UL)
# else
# define INTPTR_MIN (-2147483647-1)
# define INTPTR_MAX (2147483647)
# define UINTPTR_MAX (4294967295U)
# endif
 
 
/* Minimum for largest signed integral type. */
# define INTMAX_MIN (-__INT64_C(9223372036854775807)-1)
/* Maximum for largest signed integral type. */
# define INTMAX_MAX (__INT64_C(9223372036854775807))
 
/* Maximum for largest unsigned integral type. */
# define UINTMAX_MAX (__UINT64_C(18446744073709551615))
 
 
/* Limits of other integer types. */
 
/* Limits of `ptrdiff_t' type. */
# if __WORDSIZE == 64
# define PTRDIFF_MIN (-9223372036854775807L-1)
# define PTRDIFF_MAX (9223372036854775807L)
# else
# define PTRDIFF_MIN (-2147483647-1)
# define PTRDIFF_MAX (2147483647)
# endif
 
/* Limits of `sig_atomic_t'. */
# define SIG_ATOMIC_MIN (-2147483647-1)
# define SIG_ATOMIC_MAX (2147483647)
 
/* Limit of `size_t' type. */
# if __WORDSIZE == 64
# define SIZE_MAX (18446744073709551615UL)
# else
# define SIZE_MAX (4294967295U)
# endif
 
/* Limits of `wchar_t'. */
# ifndef WCHAR_MIN
/* These constants might also be defined in <wchar.h>. */
# define WCHAR_MIN __WCHAR_MIN
# define WCHAR_MAX __WCHAR_MAX
# endif
 
/* Limits of `wint_t'. */
# define WINT_MIN (0u)
# define WINT_MAX (4294967295u)
 
#endif /* C++ && limit macros */
 
 
/* The ISO C99 standard specifies that in C++ implementations these
should only be defined if explicitly requested. */
#if !defined __cplusplus || defined __STDC_CONSTANT_MACROS
 
/* Signed. */
# define INT8_C(c) c
# define INT16_C(c) c
# define INT32_C(c) c
# if __WORDSIZE == 64
# define INT64_C(c) c ## L
# else
# define INT64_C(c) c ## LL
# endif
 
/* Unsigned. */
# define UINT8_C(c) c ## U
# define UINT16_C(c) c ## U
# define UINT32_C(c) c ## U
# if __WORDSIZE == 64
# define UINT64_C(c) c ## UL
# else
# define UINT64_C(c) c ## ULL
# endif
 
/* Maximal type. */
# if __WORDSIZE == 64
# define INTMAX_C(c) c ## L
# define UINTMAX_C(c) c ## UL
# else
# define INTMAX_C(c) c ## LL
# define UINTMAX_C(c) c ## ULL
# endif
 
#endif /* C++ && constant macros */
 
__END_DECLS
#endif /* stdint.h */
/shark/tags/rel_0_5/drivers/linuxc24/include/sys/ttydefaults.h
0,0 → 1,106
/*-
* Copyright (c) 1982, 1986, 1993
* The Regents of the University of California. All rights reserved.
* (c) UNIX System Laboratories, Inc.
* All or some portions of this file are derived from material licensed
* to the University of California by American Telephone and Telegraph
* Co. or Unix System Laboratories, Inc. and are reproduced herein with
* the permission of UNIX System Laboratories, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 4. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* @(#)ttydefaults.h 8.4 (Berkeley) 1/21/94
*/
 
/*
* System wide defaults for terminal state. Linux version.
*/
#ifndef _SYS_TTYDEFAULTS_H_
#define _SYS_TTYDEFAULTS_H_
 
#include "ll/sys/cdefs.h"
 
__BEGIN_DECLS
 
/*
* Defaults on "first" open.
*/
#define TTYDEF_IFLAG (BRKINT | ISTRIP | ICRNL | IMAXBEL | IXON | IXANY)
#define TTYDEF_OFLAG (OPOST | ONLCR | XTABS)
#define TTYDEF_LFLAG (ECHO | ICANON | ISIG | IEXTEN | ECHOE|ECHOKE|ECHOCTL)
#define TTYDEF_CFLAG (CREAD | CS7 | PARENB | HUPCL)
#define TTYDEF_SPEED (B9600)
 
/*
* Control Character Defaults
*/
#define CTRL(x) (x&037)
#define CEOF CTRL('d')
#ifdef _POSIX_VDISABLE
# define CEOL _POSIX_VDISABLE
#else
# define CEOL '\0' /* XXX avoid _POSIX_VDISABLE */
#endif
#define CERASE 0177
#define CINTR CTRL('c')
#ifdef _POSIX_VDISABLE
# define CSTATUS _POSIX_VDISABLE
#else
# define CSTATUS '\0' /* XXX avoid _POSIX_VDISABLE */
#endif
#define CKILL CTRL('u')
#define CMIN 1
#define CQUIT 034 /* FS, ^\ */
#define CSUSP CTRL('z')
#define CTIME 0
#define CDSUSP CTRL('y')
#define CSTART CTRL('q')
#define CSTOP CTRL('s')
#define CLNEXT CTRL('v')
#define CDISCARD CTRL('o')
#define CWERASE CTRL('w')
#define CREPRINT CTRL('r')
#define CEOT CEOF
/* compat */
#define CBRK CEOL
#define CRPRNT CREPRINT
#define CFLUSH CDISCARD
 
/* PROTECTED INCLUSION ENDS HERE */
#endif /* !_SYS_TTYDEFAULTS_H_ */
 
/*
* #define TTYDEFCHARS to include an array of default control characters.
*/
#ifdef TTYDEFCHARS
cc_t ttydefchars[NCCS] = {
CEOF, CEOL, CEOL, CERASE, CWERASE, CKILL, CREPRINT,
_POSIX_VDISABLE, CINTR, CQUIT, CSUSP, CDSUSP, CSTART, CSTOP, CLNEXT,
CDISCARD, CMIN, CTIME, CSTATUS, _POSIX_VDISABLE
};
#undef TTYDEFCHARS
 
__END_DECLS
#endif
/shark/tags/rel_0_5/drivers/linuxc24/include/bits/ioctl-types.h
0,0 → 1,78
/* Structure types for pre-termios terminal ioctls. Linux version.
Copyright (C) 1996, 1997, 1999, 2001 Free Software Foundation, Inc.
This file is part of the GNU C Library.
 
The GNU C Library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option) any later version.
 
The GNU C Library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
 
You should have received a copy of the GNU Lesser General Public
License along with the GNU C Library; if not, write to the Free
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
02111-1307 USA. */
 
#ifndef _SYS_IOCTL_H
# error "Never use <bits/ioctl-types.h> directly; include <sys/ioctl.h> instead."
#endif
 
/* Get definition of constants for use with `ioctl'. */
#include <asm/ioctls.h>
 
 
struct winsize
{
unsigned short int ws_row;
unsigned short int ws_col;
unsigned short int ws_xpixel;
unsigned short int ws_ypixel;
};
 
#define NCC 8
struct termio
{
unsigned short int c_iflag; /* input mode flags */
unsigned short int c_oflag; /* output mode flags */
unsigned short int c_cflag; /* control mode flags */
unsigned short int c_lflag; /* local mode flags */
unsigned char c_line; /* line discipline */
unsigned char c_cc[NCC]; /* control characters */
};
 
/* modem lines */
#define TIOCM_LE 0x001
#define TIOCM_DTR 0x002
#define TIOCM_RTS 0x004
#define TIOCM_ST 0x008
#define TIOCM_SR 0x010
#define TIOCM_CTS 0x020
#define TIOCM_CAR 0x040
#define TIOCM_RNG 0x080
#define TIOCM_DSR 0x100
#define TIOCM_CD TIOCM_CAR
#define TIOCM_RI TIOCM_RNG
 
/* ioctl (fd, TIOCSERGETLSR, &result) where result may be as below */
 
/* line disciplines */
#define N_TTY 0
#define N_SLIP 1
#define N_MOUSE 2
#define N_PPP 3
#define N_STRIP 4
#define N_AX25 5
#define N_X25 6 /* X.25 async */
#define N_6PACK 7
#define N_MASC 8 /* Mobitex module */
#define N_R3964 9 /* Simatic R3964 module */
#define N_PROFIBUS_FDL 10 /* Profibus */
#define N_IRDA 11 /* Linux IR */
#define N_SMSBLOCK 12 /* SMS block mode */
#define N_HDLC 13 /* synchronous HDLC */
#define N_SYNC_PPP 14 /* synchronous PPP */
#define N_HCI 15 /* Bluetooth HCI UART */
/shark/tags/rel_0_5/drivers/linuxc24/include/bits/byteswap.h
0,0 → 1,115
/* Macros to swap the order of bytes in integer values.
Copyright (C) 1997, 1998, 2000, 2002 Free Software Foundation, Inc.
This file is part of the GNU C Library.
 
The GNU C Library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option) any later version.
 
The GNU C Library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
 
You should have received a copy of the GNU Lesser General Public
License along with the GNU C Library; if not, write to the Free
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
02111-1307 USA. */
 
#if !defined _BYTESWAP_H && !defined _NETINET_IN_H
# error "Never use <bits/byteswap.h> directly; include <byteswap.h> instead."
#endif
 
#ifndef _BITS_BYTESWAP_H
#define _BITS_BYTESWAP_H 1
 
/* Swap bytes in 16 bit value. */
#define __bswap_constant_16(x) \
((((x) >> 8) & 0xff) | (((x) & 0xff) << 8))
 
#if defined __GNUC__ && __GNUC__ >= 2
# define __bswap_16(x) \
(__extension__ \
({ register unsigned short int __v; \
if (__builtin_constant_p (x)) \
__v = __bswap_constant_16 (x); \
else \
__asm__ __volatile__ ("rorw $8, %w0" \
: "=r" (__v) \
: "0" ((unsigned short int) (x)) \
: "cc"); \
__v; }))
#else
/* This is better than nothing. */
# define __bswap_16(x) __bswap_constant_16 (x)
#endif
 
 
/* Swap bytes in 32 bit value. */
#define __bswap_constant_32(x) \
((((x) & 0xff000000) >> 24) | (((x) & 0x00ff0000) >> 8) | \
(((x) & 0x0000ff00) << 8) | (((x) & 0x000000ff) << 24))
 
#if defined __GNUC__ && __GNUC__ >= 2
/* To swap the bytes in a word the i486 processors and up provide the
`bswap' opcode. On i386 we have to use three instructions. */
# if !defined __i486__ && !defined __pentium__ && !defined __pentiumpro__
# define __bswap_32(x) \
(__extension__ \
({ register unsigned int __v; \
if (__builtin_constant_p (x)) \
__v = __bswap_constant_32 (x); \
else \
__asm__ __volatile__ ("rorw $8, %w0;" \
"rorl $16, %0;" \
"rorw $8, %w0" \
: "=r" (__v) \
: "0" ((unsigned int) (x)) \
: "cc"); \
__v; }))
# else
# define __bswap_32(x) \
(__extension__ \
({ register unsigned int __v; \
if (__builtin_constant_p (x)) \
__v = __bswap_constant_32 (x); \
else \
__asm__ __volatile__ ("bswap %0" \
: "=r" (__v) \
: "0" ((unsigned int) (x))); \
__v; }))
# endif
#else
# define __bswap_32(x) __bswap_constant_32 (x)
#endif
 
 
#if defined __GNUC__ && __GNUC__ >= 2
/* Swap bytes in 64 bit value. */
#define __bswap_constant_64(x) \
((((x) & 0xff00000000000000ull) >> 56) \
| (((x) & 0x00ff000000000000ull) >> 40) \
| (((x) & 0x0000ff0000000000ull) >> 24) \
| (((x) & 0x000000ff00000000ull) >> 8) \
| (((x) & 0x00000000ff000000ull) << 8) \
| (((x) & 0x0000000000ff0000ull) << 24) \
| (((x) & 0x000000000000ff00ull) << 40) \
| (((x) & 0x00000000000000ffull) << 56))
 
# define __bswap_64(x) \
(__extension__ \
({ union { __extension__ unsigned long long int __ll; \
unsigned long int __l[2]; } __w, __r; \
if (__builtin_constant_p (x)) \
__r.__ll = __bswap_constant_64 (x); \
else \
{ \
__w.__ll = (x); \
__r.__l[0] = __bswap_32 (__w.__l[1]); \
__r.__l[1] = __bswap_32 (__w.__l[0]); \
} \
__r.__ll; }))
#endif
 
#endif /* _BITS_BYTESWAP_H */
/shark/tags/rel_0_5/drivers/linuxc24/include/bits/wchar.h
0,0 → 1,26
/* wchar_t type related definitions.
Copyright (C) 2000 Free Software Foundation, Inc.
This file is part of the GNU C Library.
 
The GNU C Library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option) any later version.
 
The GNU C Library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
 
You should have received a copy of the GNU Lesser General Public
License along with the GNU C Library; if not, write to the Free
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
02111-1307 USA. */
 
#ifndef _BITS_WCHAR_H
#define _BITS_WCHAR_H 1
 
#define __WCHAR_MIN (-2147483647l - 1l)
#define __WCHAR_MAX (2147483647l)
 
#endif /* bits/wchar.h */
/shark/tags/rel_0_5/drivers/pcl812/pclab.h
0,0 → 1,17
/*--------------------------------------------------------------*/
/* File header da includere nel main quando si usano */
/* le funzioni di aquisizione contenute in PCLAB.C */
/*--------------------------------------------------------------*/
 
#include "ll/sys/cdefs.h"
 
__BEGIN_DECLS
 
float ad_conv(int ); /* conversione A/D */
int da_conv(float, int ); /* conversione D/A */
int par_in(void); /* ingresso digitale */
void par_out(int n); /* uscita digitale */
 
__END_DECLS
 
/*--------------------------------------------------------------*/
/shark/tags/rel_0_5/drivers/pcl812/makefile
0,0 → 1,16
# The PCI library
 
ifndef BASE
BASE=../..
endif
 
include $(BASE)/config/config.mk
 
LIBRARY = pcl812
 
OBJS_PATH = $(BASE)/drivers/pcl812
 
OBJS = pclab.o
 
include $(BASE)/config/lib.mk
 
/shark/tags/rel_0_5/drivers/pcl812/pclab.c
0,0 → 1,131
/*==============================================================*/
/* LIBRERIA DI GESTIONE DELLA SCHEDA PCL-812 */
/* Marco Caccamo, 6-2-2000 */
/*==============================================================*/
 
/*--------------------------------------------------------------*/
/* Register bit: 7 6 5 4 3 2 1 0 */
/*--------------------------------------------------------------*/
/* ABUFL D7 D6 D5 D4 D3 D2 D1 D0 */
/* ABUFH 0 0 0 DRDY D3 D2 D1 D0 */
/*--------------------------------------------------------------*/
/* SELEC X X X X C3 C2 C1 C0 */
/*--------------------------------------------------------------*/
/* CTRLB X X X X X S2 S1 S0 */
/*--------------------------------------------------------------*/
/* TRIGG X X X X X X X TR */
 
 
 
#include <kernel/kern.h>
#define BASE 0x220 /* indirizzo base BIT */
#define ABUFL (BASE + 4) /* low byte for AD/DA (0 - 7) */
#define ABUFH (BASE + 5) /* high byte for AD/DA (8 -13) */
#define IBUFL (BASE + 6) /* low byte for DIN (0 - 7) */
#define IBUFH (BASE + 7) /* high byte for DIN (8 -15) */
#define SELEC (BASE + 10) /* select AD channel (0 - 3) */
#define CTRLB (BASE + 11) /* control register (0 - 2) */
#define TRIGG (BASE + 12) /* A/D trigger control (0) */
#define OBUFL (BASE + 13) /* low byte for DOUT (0 - 7) */
#define OBUFH (BASE + 14) /* high byte for DOUT (8 -15) */
 
/*--------------------------------------------------------------*/
/* AD_CONV(ch) ritorna il valore (in volt) convertito */
/* dal canale ch dell'ingresso analogico. */
/* Volt range: [-10,10], Resolution: 2.4 mV */
/*--------------------------------------------------------------*/
 
float ad_conv(int ch) /* AD channel [0-15] */
{
int lb, hb; /* low byte, high byte [0,255] */
int n; /* converted value [-8192,8191] */
float v; /* value in volt [-10,10] */
 
outp(SELEC, ch); /* set AD channel */
outp(CTRLB, 1); /* enable software trigger */
outp(TRIGG, 1); /* trigger AD converter */
 
do { /* wait conversion */
hb = 0xff & inp(ABUFH); /* read high byte */
} while ((hb & 0x10) == 16); /* loop if (bit 4 == 1) */
 
lb = 0xff & inp(ABUFL); /* read low byte */
 
n = (hb * 256 + lb); // -4096; //- 2048; /* compose number */
//cprintf();
v = (20. * (float)n ) / 4096 - 10.; //2048.; /* convert n in volt */
return(v);
}
 
/*--------------------------------------------------------------*/
/* DA_CONV(float v,int ch) converte in analogico il valore in volt */
/* passato come parametro sul canale ch. */
/* Volt range: [0,5], Resolution: 1.2 mV */
/* return(-1) se non viene eseguita la conversione */
/* altrimenti return(0) */
/*--------------------------------------------------------------*/
 
int da_conv(float v, int ch) /* value (in volt) to convert */
{
int lb, hb; /* low byte, high byte */
float x; /* value to convert */
 
 
 
if (v > 5 || v < 0)
return(-1);
else{
x = ((v / 5.) * 4095.); /* compose number */
hb = (int) x / 256; /* compute high byte */
lb = (int) x % 256; /* compute low byte */
if(ch == 2) {
outp(IBUFL, lb); /* write lb in IBUFL */
outp(IBUFH, hb); /* write hb in IBUFL */
}
else if(ch == 1) {
outp(ABUFL, lb); /* write lb in ABUFL */
outp(ABUFH, hb); /* write hb in ABUFH */
}
else return(-1);
return(0);
}
}
 
/*--------------------------------------------------------------*/
/* PAR_IN() ritorna il valore letto sui 16 bit */
/* della porta parallela di ingresso. */
/*--------------------------------------------------------------*/
 
int par_in()
{
int lb, hb; /* low byte, high byte */
int n; /* value on 16 bit */
 
lb = 0xff & inp(IBUFL); /* read low byte */
hb = 0xff & inp(IBUFH); /* read high byte */
 
n = hb * 256 + lb; /* compose number */
return(n);
}
 
/*--------------------------------------------------------------*/
/* PAR_OUT(n) scrive il valore n sui 16 bit */
/* della porta parallela di uscita. */
/*--------------------------------------------------------------*/
 
void par_out(n)
int n; /* value to write */
{
int lb, hb; /* low byte, high byte */
 
hb = n / 256; /* extract high byte */
lb = n % 256; /* extract low byte */
 
outp(OBUFL,lb); /* write low byte */
outp(OBUFH,hb); /* write high byte */
}
 
/*--------------------------------------------------------------*/
/shark/tags/rel_0_5/drivers/cons/makefile
0,0 → 1,17
# The console Devices (console)
 
ifndef BASE
BASE=../..
endif
 
include $(BASE)/config/config.mk
 
 
LIBRARY = cons
 
OBJS_PATH = $(BASE)/drivers/cons
 
OBJS = cons1.o cons2.o message.o cprintf.o
 
include $(BASE)/config/lib.mk
 
/shark/tags/rel_0_5/drivers/cons/cons1.c
0,0 → 1,198
/* Project: OSLib
* Description: The OS Construction Kit
* Date: 1.6.2000
* Idea by: Luca Abeni & Gerardo Lamastra
*
* OSLib is an SO project aimed at developing a common, easy-to-use
* low-level infrastructure for developing OS kernels and Embedded
* Applications; it partially derives from the HARTIK project but it
* currently is independently developed.
*
* OSLib is distributed under GPL License, and some of its code has
* been derived from the Linux kernel source; also some important
* ideas come from studying the DJGPP go32 extender.
*
* We acknowledge the Linux Community, Free Software Foundation,
* D.J. Delorie and all the other developers who believe in the
* freedom of software and ideas.
*
* For legalese, check out the included GPL license.
*/
 
/* Console output functions */
 
#include <ll/i386/hw-data.h>
#include <ll/i386/hw-instr.h>
#include <ll/i386/cons.h>
/* #include <xsys.h>*/
#include <ll/i386/string.h>
#include <ll/i386/stdlib.h>
#include <ll/i386/stdio.h>
#include <ll/stdarg.h>
 
FILE(Cons1);
/* CGA compatible registers value */
 
#define CURSOR_POS_MSB 0x0E
#define CURSOR_POS_LSB 0x0F
#define CURSOR_START 0x0A
#define CURSOR_END 0x0B
 
/* CGA compatible registers */
 
#define CGA_INDEX_REG 0x3D4
#define CGA_DATA_REG 0x3D5
 
/* Standard tab size */
 
#define TAB_SIZE 8
 
/* Store bios settings */
 
static unsigned char bios_start,bios_end;
BYTE bios_x, bios_y, bios_attr;
 
/* MG */
extern int cons_columns; /* number of screen columns */
extern int cons_rows; /* number of screen rows */
 
/* Access directly to video & BIOS memory through linear addressing */
 
/* Active video page-buffer */
#define PAGE_SIZE 2048
 
int active_page = 0;
int visual_page = 0;
 
void bios_save(void)
{
/* This function must be called to init CONSole output */
#if 1
/* MG */
cons_columns=lmempeekw((LIN_ADDR)0x0044a);
cons_rows=lmempeekb((LIN_ADDR)0x00484)+1;
 
bios_attr = lmempeekb((LIN_ADDR)0xB8000 + cons_columns * 2 -1);
bios_x = lmempeekb((LIN_ADDR)0x00450);
bios_y = lmempeekb((LIN_ADDR)0x00451);
bios_end = lmempeekb((LIN_ADDR)0x00460);
bios_start = lmempeekb((LIN_ADDR)0x00461);
active_page = visual_page = 0;
#else
LIN_ADDR p;
 
p = (LIN_ADDR)(0xB8000 + 159);
bios_attr = *p;
p = (LIN_ADDR)0x00450;
bios_x = *p;
p = (LIN_ADDR)0x00451;
bios_y = *p;
p = (LIN_ADDR)0x00460;
bios_end = *p;
p = (LIN_ADDR)0x00461;
bios_start = *p;
active_page = visual_page = 0;
#endif
}
 
void cursor(int start,int end)
{
/* Same thing as above; Set cursor scan line */
outp(CGA_INDEX_REG, CURSOR_START);
outp(CGA_DATA_REG, start);
outp(CGA_INDEX_REG, CURSOR_END);
outp(CGA_DATA_REG, end);
}
 
void bios_restore(void)
{
lmempokeb((LIN_ADDR)0x00450,bios_x);
lmempokeb((LIN_ADDR)0x00451,bios_y);
place(bios_x,bios_y);
cursor(bios_start, bios_end);
}
 
void place(int x,int y)
{
unsigned short cursor_word = x + y*cons_columns + active_page*PAGE_SIZE;
/* Set cursor position */
/* CGA is programmed writing first the Index register */
/* to specify what internal register we are accessing */
/* Then we load the Data register with the wanted val */
outp(CGA_INDEX_REG,CURSOR_POS_LSB);
outp(CGA_DATA_REG,cursor_word & 0xFF);
outp(CGA_INDEX_REG,CURSOR_POS_MSB);
outp(CGA_DATA_REG,(cursor_word >> 8) & 0xFF);
/* Adjust temporary cursor bios position */
bios_x = x;
bios_y = y;
}
 
 
void _scroll(char attr,int x1,int y1,int x2,int y2)
{
register int x,y;
WORD xattr = attr << 8,w;
LIN_ADDR v = (LIN_ADDR)(0xB8000 + active_page*(2*PAGE_SIZE));
for (y = y1+1; y <= y2; y++)
for (x = x1; x <= x2; x++) {
w = lmempeekw((LIN_ADDR)(v + 2*(y*cons_columns+x)));
lmempokew((LIN_ADDR)(v + 2*((y-1)*cons_columns+x)),w);
}
for (x = x1; x <= x2; x++)
lmempokew((LIN_ADDR)(v + 2*((y-1)*cons_columns+x)),xattr);
}
 
void scroll(void)
{
_scroll(bios_attr,0,0,(cons_columns-1),(cons_rows-1));
}
 
void cputc(char c)
{
static unsigned short scan_x,x,y;
LIN_ADDR v = (LIN_ADDR)(0xB8000 + active_page*(2*PAGE_SIZE));
x = bios_x;
y = bios_y;
switch (c) {
case '\t' : x += 8;
if (x >= cons_columns) {
x = 0;
if (y == (cons_rows-1)) scroll();
else y++;
} else {
scan_x = 0;
while ((scan_x+8) < x) scan_x += 8;
x = scan_x;
}
break;
case '\n' : x = 0;
if (y == (cons_rows-1)) scroll();
else y++;
break;
case '\b' : x--;
lmempokeb((LIN_ADDR)(v + 2*(x + y*cons_columns)),' ');
x++;
break;
default : lmempokeb((LIN_ADDR)(v + 2*(x + y*cons_columns)),c);
x++;
if (x > cons_columns) {
x = 0;
if (y == (cons_rows-1)) scroll();
else y++;
}
}
place(x,y);
}
 
void cputs(char *s)
{
char c;
while (*s != '\0') {
c = *s++;
cputc(c);
}
}
 
 
/shark/tags/rel_0_5/drivers/cons/cons2.c
0,0 → 1,134
/* Project: OSLib
* Description: The OS Construction Kit
* Date: 1.6.2000
* Idea by: Luca Abeni & Gerardo Lamastra
*
* OSLib is an SO project aimed at developing a common, easy-to-use
* low-level infrastructure for developing OS kernels and Embedded
* Applications; it partially derives from the HARTIK project but it
* currently is independently developed.
*
* OSLib is distributed under GPL License, and some of its code has
* been derived from the Linux kernel source; also some important
* ideas come from studying the DJGPP go32 extender.
*
* We acknowledge the Linux Community, Free Software Foundation,
* D.J. Delorie and all the other developers who believe in the
* freedom of software and ideas.
*
* For legalese, check out the included GPL license.
*/
 
/* Console output functions - part 2 */
 
#include <ll/i386/hw-data.h>
#include <ll/i386/hw-instr.h>
#include <ll/i386/cons.h>
/* #include <xsys.h>*/
#include <ll/i386/string.h>
#include <ll/i386/stdlib.h>
#include <ll/i386/stdio.h>
#include <ll/stdarg.h>
 
FILE(Cons2);
 
#define PAGE_SIZE 2048
#define PAGE_MAX 8
 
/* CGA compatible registers */
 
#define CGA_INDEX_REG 0x3D4
#define CGA_DATA_REG 0x3D5
 
#define VIDEO_ADDRESS_MSB 0x0C
#define VIDEO_ADDRESS_LSB 0x0D
 
 
extern int active_page;
extern int visual_page;
static int curs_x[PAGE_MAX];
static int curs_y[PAGE_MAX];
extern BYTE bios_x, bios_y, bios_attr;
 
/* MG */
int cons_columns; /* number of screen columns */
int cons_rows; /* number of screen rows */
 
void set_visual_page(int page)
{
unsigned short page_offset;
page_offset = page * PAGE_SIZE;
visual_page = page;
outp(CGA_INDEX_REG, VIDEO_ADDRESS_LSB);
outp(CGA_DATA_REG, page_offset & 0xFF);
outp(CGA_INDEX_REG, VIDEO_ADDRESS_MSB);
outp(CGA_DATA_REG, (page_offset >> 8) & 0xFF);
}
 
void set_active_page(int page)
{
curs_x[active_page] = bios_x;
curs_y[active_page] = bios_y;
bios_x = curs_x[page];
bios_y = curs_y[page];
active_page = page;
}
 
int get_visual_page(void)
{
return(visual_page);
}
 
int get_active_page(void)
{
return(active_page);
}
 
void _clear(char c,char attr,int x1,int y1,int x2,int y2)
{
register int i,j;
WORD w = attr;
w <<= 8; w |= c;
for (i = x1; i <= x2; i++)
for (j = y1; j <= y2; j++)
lmempokew((LIN_ADDR)(0xB8000 + 2*i+cons_columns*2*j + 2*active_page*PAGE_SIZE),w);
place(x1,y1);
bios_y = y1;
bios_x = x1;
}
 
void clear()
{
_clear(' ',bios_attr,0,0,(cons_columns-1),(cons_rows-1));
}
 
void puts_xy(int x,int y,char attr,char *s)
{
LIN_ADDR v = (LIN_ADDR)(0xB8000 + (cons_columns*y+x)*2 + active_page*(2*PAGE_SIZE));
while (*s != 0) {
/* REMEMBER! This is a macro! v++ is out to prevent side-effects */
lmempokeb(v,*s); s++; v++;
lmempokeb(v,attr); v++;
}
}
 
void putc_xy(int x,int y,char attr,char c)
{
LIN_ADDR v = (LIN_ADDR)(0xB8000 + (cons_columns*y+x)*2 + active_page*(2*PAGE_SIZE));
/* REMEMBER! This is a macro! v++ is out to prevent side-effects */
lmempokeb(v,c); v++;
lmempokeb(v,attr);
}
 
char getc_xy(int x,int y,char *attr,char *c)
{
LIN_ADDR v = (LIN_ADDR)(0xB8000 + (cons_columns*y+x)*2 + active_page*(2*PAGE_SIZE));
char r;
r = lmempeekb(v); v++;
if (c != NULL) *c = r;
r = lmempeekb(v);
if (attr != NULL) *attr = r;
return(r);
}
/shark/tags/rel_0_5/drivers/cons/message.c
0,0 → 1,45
/* Project: OSLib
* Description: The OS Construction Kit
* Date: 1.6.2000
* Idea by: Luca Abeni & Gerardo Lamastra
*
* OSLib is an SO project aimed at developing a common, easy-to-use
* low-level infrastructure for developing OS kernels and Embedded
* Applications; it partially derives from the HARTIK project but it
* currently is independently developed.
*
* OSLib is distributed under GPL License, and some of its code has
* been derived from the Linux kernel source; also some important
* ideas come from studying the DJGPP go32 extender.
*
* We acknowledge the Linux Community, Free Software Foundation,
* D.J. Delorie and all the other developers who believe in the
* freedom of software and ideas.
*
* For legalese, check out the included GPL license.
*/
 
/* Console output functions */
 
#include <ll/i386/hw-data.h>
#include <ll/i386/hw-instr.h>
#include <ll/i386/cons.h>
#include <ll/i386/string.h>
#include <ll/i386/stdlib.h>
#include <ll/i386/stdio.h>
#include <ll/stdarg.h>
 
FILE(message);
 
int message(const char *fmt,...)
{
static char cbuf[500];
va_list parms;
int result;
 
va_start(parms,fmt);
result = vksprintf(cbuf,(char *)fmt,parms);
va_end(parms);
cputs(cbuf);
return(result);
}
/shark/tags/rel_0_5/drivers/cons/cprintf.c
0,0 → 1,57
/* Project: OSLib
* Description: The OS Construction Kit
* Date: 1.6.2000
* Idea by: Luca Abeni & Gerardo Lamastra
*
* OSLib is an SO project aimed at developing a common, easy-to-use
* low-level infrastructure for developing OS kernels and Embedded
* Applications; it partially derives from the HARTIK project but it
* currently is independently developed.
*
* OSLib is distributed under GPL License, and some of its code has
* been derived from the Linux kernel source; also some important
* ideas come from studying the DJGPP go32 extender.
*
* We acknowledge the Linux Community, Free Software Foundation,
* D.J. Delorie and all the other developers who believe in the
* freedom of software and ideas.
*
* For legalese, check out the included GPL license.
*/
 
/* Console output functions */
 
#include <ll/i386/hw-data.h>
#include <ll/i386/hw-instr.h>
#include <ll/i386/cons.h>
#include <ll/i386/string.h>
#include <ll/i386/stdlib.h>
#include <ll/i386/stdio.h>
#include <ll/stdarg.h>
 
FILE(cprintf);
 
int cprintf(char *fmt,...)
{
static char cbuf[500];
va_list parms;
int result;
va_start(parms,fmt);
result = vsprintf(cbuf,fmt,parms);
va_end(parms);
cputs(cbuf);
return(result);
}
 
int printf_xy(int x,int y,char attr,char *fmt,...)
{
char cbuf[200];
va_list parms;
int result;
 
va_start(parms,fmt);
result = vsprintf(cbuf,fmt,parms);
va_end(parms);
puts_xy(x,y,attr,cbuf);
return(result);
}
/shark/tags/rel_0_5/drivers/parport/makefile
0,0 → 1,16
# The Parallel Port Library, by Andrea Battistotti & Armando Leggio
 
ifndef BASE
BASE=../..
endif
 
include $(BASE)/config/config.mk
 
LIBRARY = pport
 
OBJS_PATH = $(BASE)/drivers/parport
 
OBJS = ppdrv.o ppnrtdrv.o pppindrv.o
 
include $(BASE)/config/lib.mk
 
/shark/tags/rel_0_5/drivers/parport/ppnrtdrv.c
0,0 → 1,295
/*
*
* Project:
* Parallel Port S.Ha.R.K. Project
*
* Module:
* ppNRTDrv.c
*
* Description:
* file contents description
*
* Coordinators:
* Giorgio Buttazzo <giorgio@sssup.it>
* Paolo Gai <pj@gandalf.sssup.it>
*
* Authors:
* Andrea Battistotti <btandrea@libero.it>
* Armando Leggio <a_leggio@hotmail.com>
*
*
* http://www.sssup.it
* http://retis.sssup.it
* http://shark.sssup.it
*
*/
/*************************************************************************
* Module : ppNRTDrv.c
* Author : Andrea Battistotti , Armando Leggio
* Description: Set On/Off single pin of LPT1...
* 2002 @ Pavia - GNU Copyrights
*******************************************************************************************/
 
/*
* Copyright (C) 2002 Andrea Battistotti , Armando Leggio
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
* CVS : $Id: ppnrtdrv.c,v 1.1 2002-10-28 08:03:54 pj Exp $
*/
 
 
/*******************************************************************************************
* A standard PC provides for three printer ports, at the following base addresses:
*
* LPT1 = 0x0378 or 0x03BC
* LPT2 = 0x0278 or 0x0378
* LPT3 = 0x0278
*
* This module assumes that LPT1 is at 0x0378.
*
* The printer port has three 8-bit registers:
*
* Data Register (base + 0) ........ outputs
*
* 7 6 5 4 3 2 1 0
* . . . . . . . * D0 ........... (pin 2), 1=High, 0=Low (true)
* . . . . . . * . D1 ........... (pin 3), 1=High, 0=Low (true)
* . . . . . * . . D2 ........... (pin 4), 1=High, 0=Low (true)
* . . . . * . . . D3 ........... (pin 5), 1=High, 0=Low (true)
* . . . * . . . . D4 ........... (pin 6), 1=High, 0=Low (true)
* . . * . . . . . D5 ........... (pin 7), 1=High, 0=Low (true)
* . * . . . . . . D6 ........... (pin 8), 1=High, 0=Low (true)
* * . . . . . . . D7 ........... (pin 9), 1=High, 0=Low (true)
*
* Status Register (base + 1) ...... inputs
*
* 7 6 5 4 3 2 1 0
* . . . . . * * * Undefined
* . . . . * . . . Error ........ (pin 15), high=1, low=0 (true)
* . . . * . . . . Selected ..... (pin 13), high=1, low=0 (true)
* . . * . . . . . No paper ..... (pin 12), high=1, low=0 (true)
* . * . . . . . . Ack .......... (pin 10), high=1, low=0 (true)
* * . . . . . . . Busy ......... (pin 11), high=0, low=1 (inverted)
*
* Control Register (base + 2) ..... outputs
*
* 7 6 5 4 3 2 1 0
* . . . . . . . * Strobe ....... (pin 1), 1=low, 0=high (inverted)
* . . . . . . * . Auto Feed .... (pin 14), 1=low, 0=high (inverted)
* . . . . . * . . Initialize ... (pin 16), 1=high, 0=low (true)
* . . . . * . . . Select ....... (pin 17), 1=low, 0=high (inverted)
* * * * * . . . . Unused
*
* Pins 18-25 are ground.
********************************************************************************************/
 
#include <drivers/parport.h>
 
 
/*************************************************************************/
BOOL ppNRTWaitRTS(void)
{
BYTE port;
TIME start = clock();
do
{
port = ~inp(RX_PORT); /* port status */
port = port & RX_CTR; /* test cntr read bit*/
if(clock() > start + CLK_TIMEOUT) return TIMEOUT;
} while(port == 0);
return TRUE;
}
 
/*************************************************************************/
BOOL ppNRTWaitDR(void)
{
BYTE port;
TIME start = clock(); /* start */
do {
port = (~inp(RX_PORT)) | (~RX_CTR); /* test cntr read bit*/
if(clock() > start + CLK_TIMEOUT) return TIMEOUT;
} while(port != 0x7F); /* 0111 1111 */
 
return TRUE;
}
 
/*************************************************************************/
BOOL ppNRTWaitOTS(void)
{
BYTE port;
TIME start = clock(); /* start time */
do
{
port = ~inp(RX_PORT); /* read port status */
port = port & RX_CTR; /* test cntr read bit*/
if(clock() > start + CLK_TIMEOUT) return TIMEOUT;
} while(port == 0);
return TRUE;
}
 
/*************************************************************************/
BOOL ppNRTWaitER(void)
{
BYTE port;
TIME start = clock(); /* start */
do
{
port = ~inp(RX_PORT); /* read port status */
port = port | (~RX_CTR); /* test cntr read bit*/
if(clock() > start + CLK_TIMEOUT) return TIMEOUT;
} while(port != 0x7F); /* 0111 1111 */
return TRUE;
}
 
 
/**************************************************************************/
BOOL ppNRTTxOneByte(BYTE c)
{
BYTE port;
/*------------------------- Least Significative Nibble */
ppSendRTS(); /* Request To Send */
 
port = inp(TX_PORT); /* read port status */
port = port & (~TX_DATA); /* set tx bits == 0 */
port = port | (c & LSN); /* set bit 0..3 with LSN */
 
#if PP_DEBUG == 1
kern_printf("ppNRTTxOneByte: SendRTS, before WaitOTS\n");
#endif
 
if(ppNRTWaitOTS()!=TRUE) return TIMEOUT;
outp(TX_PORT,port);
ppSendDR(); /* Data Ready */
 
#if PP_DEBUG == 1
kern_printf("ppNRTTxOneByte: SendDR, before WaitER\n");
#endif
 
 
if(ppNRTWaitER() !=TRUE) return TIMEOUT;
 
/*------------------------- More Significative Nibble */
ppSendRTS(); /* Request To Send */
 
port = inp(TX_PORT); /* read port status */
port = port & (~TX_DATA); /* set off trasmission bits... */
port = port | (c >> 4); /* set bit 0..3 with MSN */
 
#if PP_DEBUG == 1
kern_printf("ppNRTTxOneByte: SendRTS, before WaitOTS\n");
#endif
 
if(ppNRTWaitOTS()!=TRUE) return TIMEOUT;
outp(TX_PORT,port); /* send data nibble... */
ppSendDR(); /* Data Ready */
 
#if PP_DEBUG == 1
kern_printf("ppNRTTxOneByte: SendDR, before WaitER\n");
#endif
 
if(ppNRTWaitER() !=TRUE) return TIMEOUT;
 
return TRUE;
}
 
/**************************************************************************/
BOOL ppNRTRxOneByte(BYTE *c)
{
BYTE port;
 
if(ppIsRTS() == FALSE) return FALSE;
 
 
ppSendOTS(); /* Ok To Send */
 
#if PP_DEBUG == 1
kern_printf("ppNRTRxOneByte: IsRTS, SendOTS, before WaitDR\n");
#endif
 
if(ppNRTWaitDR() != TRUE) return TIMEOUT;
port = inp(RX_PORT); /* read nibble */
ppSendER(); /* End Read */
*c = (port >> 3); /* read LSN */
 
#if PP_DEBUG == 1
kern_printf("ppNRTRxOneByte: SendER, before WaitRTS\n");
#endif
 
if(ppNRTWaitRTS() != TRUE) return TIMEOUT;
ppSendOTS();
 
#if PP_DEBUG == 1
kern_printf("ppNRTRxOneByte: SendOTS, before WaitDR\n");
#endif
 
if(ppNRTWaitDR() != TRUE) return TIMEOUT;
 
#if PP_DEBUG == 1
kern_printf("ppNRTRxOneByte: DR received, send ER\n");
#endif
 
port = inp(RX_PORT); /* read nibble */
ppSendER(); /* End Read */
*c = (*c & ~MSN); /* set 0 c MSN nibble... */
*c = (*c | ((port >> 3) << 4)); /* read MSN */
 
return TRUE;
}
 
 
/*************************************************************************
------------------------------------------------------------------------*/
BOOL ppNRTOpenComm(void)
{
BYTE c,port,rx,tx;
TIME start = clock();
 
outp(TX_PORT,0);
outp(TX_CTR,0);
 
do
{
port = inp(RX_PORT); /* read nibble */
/* x4321x xx */
c = (port >> 3); /* xxxx 4321 */
c = c & 0xF; /* 0000 4321 */
if(clock() > start + CLK_TIMEOUT*20) return TIMEOUT;
} while (c != 0); /* test nibble 4321 == 0000 */
 
/* the other also is laying down his TX_PORT (==my RX_PORT...) */
 
rx = FALSE; tx = FALSE; start = clock();
do /* try if it also on line... */
{
 
if((rx == FALSE) && (ppNRTRxOneByte(&c)==TRUE) && (c == BYTE_CTR)) rx = TRUE;
if((tx == FALSE) && (ppNRTTxOneByte(BYTE_CTR) == TRUE)) tx = TRUE;
 
if(clock() > start + CLK_TIMEOUT*20) return TIMEOUT;
 
} while(tx==FALSE || rx==FALSE);
 
ppSendER();
ppNRTWaitER();
 
return TRUE;
 
}
 
/shark/tags/rel_0_5/drivers/parport/pppindrv.c
0,0 → 1,127
/*
*
* Project:
* Parallel Port S.Ha.R.K. Project
*
* Module:
* ppPinDrv.c
*
* Description:
* file contents description
*
* Coordinators:
* Giorgio Buttazzo <giorgio@sssup.it>
* Paolo Gai <pj@gandalf.sssup.it>
*
* Authors:
* Andrea Battistotti <btandrea@libero.it>
* Armando Leggio <a_leggio@hotmail.com>
*
*
* http://www.sssup.it
* http://retis.sssup.it
* http://shark.sssup.it
*
*/
/*******************************************************************************************
* Module : ppPinDrv.c
* Author : Andrea Battistotti , Armando Leggio
* Description: Set On/Off single pin of LPT1...
* 2002 @ Pavia - GNU Copyrights
*******************************************************************************************/
 
/*
* Copyright (C) 2002 Andrea Battistotti , Armando Leggio
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
* CVS : $Id: pppindrv.c,v 1.1 2002-10-28 08:03:55 pj Exp $
*/
 
 
/*******************************************************************************************
* A standard PC provides for three printer ports, at the following base addresses:
*
* LPT1 = 0x0378 or 0x03BC
* LPT2 = 0x0278 or 0x0378
* LPT3 = 0x0278
*
* This module assumes that LPT1 is at 0x0378.
*
* The printer port has three 8-bit registers:
*
* Data Register (base + 0) ........ outputs
*
* 7 6 5 4 3 2 1 0
* . . . . . . . * D0 ........... (pin 2), 1=High, 0=Low (true)
* . . . . . . * . D1 ........... (pin 3), 1=High, 0=Low (true)
* . . . . . * . . D2 ........... (pin 4), 1=High, 0=Low (true)
* . . . . * . . . D3 ........... (pin 5), 1=High, 0=Low (true)
* . . . * . . . . D4 ........... (pin 6), 1=High, 0=Low (true)
* . . * . . . . . D5 ........... (pin 7), 1=High, 0=Low (true)
* . * . . . . . . D6 ........... (pin 8), 1=High, 0=Low (true)
* * . . . . . . . D7 ........... (pin 9), 1=High, 0=Low (true)
*
* Status Register (base + 1) ...... inputs
*
* 7 6 5 4 3 2 1 0
* . . . . . * * * Undefined
* . . . . * . . . Error ........ (pin 15), high=1, low=0 (true)
* . . . * . . . . Selected ..... (pin 13), high=1, low=0 (true)
* . . * . . . . . No paper ..... (pin 12), high=1, low=0 (true)
* . * . . . . . . Ack .......... (pin 10), high=1, low=0 (true)
* * . . . . . . . Busy ......... (pin 11), high=0, low=1 (inverted)
*
* Control Register (base + 2) ..... outputs
*
* 7 6 5 4 3 2 1 0
* . . . . . . . * Strobe ....... (pin 1), 1=low, 0=high (inverted)
* . . . . . . * . Auto Feed .... (pin 14), 1=low, 0=high (inverted)
* . . . . . * . . Initialize ... (pin 16), 1=high, 0=low (true)
* . . . . * . . . Select ....... (pin 17), 1=low, 0=high (inverted)
* * * * * . . . . Unused
*
* Pins 18-25 are ground.
********************************************************************************************/
 
#include <drivers/parport.h>
 
 
void ppSetDataPin(int state, PIN_MASK pin)
{
BYTE port;
port=ppReadDataByte();
switch (state)
{
case PIN_OFF: port &= ~pin;
case PIN_ON: port |= pin;
}
ppSetDataByte(port);
}
 
 
void ppSetCtrlPin(int state, PIN_MASK pin)
{
BYTE port;
port=ppReadCtrlByte();
switch (state)
{
case PIN_OFF: port &= ~pin;
case PIN_ON: port |= pin;
}
ppSetCtrlByte(port);
}
 
/shark/tags/rel_0_5/drivers/parport/ppdrv.c
0,0 → 1,543
/*
* Project:
* Parallel Port S.Ha.R.K. Project
*
* Module:
* ppDrv.c
*
* Description:
* file contents description
*
* Coordinators:
* Giorgio Buttazzo <giorgio@sssup.it>
* Paolo Gai <pj@gandalf.sssup.it>
*
* Authors:
* Andrea Battistotti <btandrea@libero.it>
* Armando Leggio <a_leggio@hotmail.com>
*
*
* http://www.sssup.it
* http://retis.sssup.it
* http://shark.sssup.it
*
*/
 
/**********************************************************************************************************
* Module : ppDrv.c Author : Andrea Battistotti , Armando Leggio
* Description: Tranfer Byte via LPT1 laplink cable... 2002 @ Pavia -
* GNU Copyrights */
 
/*
* Copyright (C) 2002 Andrea Battistotti , Armando Leggio
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
* CVS : $Id: ppdrv.c,v 1.1 2002-10-28 08:03:54 pj Exp $
*/
 
 
#include <drivers/parport.h>
 
 
/* internal */
BYTE RxBuf[PP_BUF_LEN]; /* Received bytes buffer */
BYTE TxBuf[PP_BUF_LEN]; /* To transmit bytes buffer */
 
unsigned int nextByteReadyToRx; /* pointer to first byte to read by ppOneByteRx(BYTE *c) ... */
unsigned int nextByteReadyToTx; /* when ppbTransmit had to send a byte, send this...*/
unsigned int nextByteFreeRx; /* when polling complete reading a byte, will save it in this loc...*/
unsigned int nextByteFreeTx; /* when ppbTransmit had to write a byte, write it here...*/
 
/* define inline macro */
/* these are for cicle buffer mamagement */
#define RxPointerGap (nextByteFreeRx-nextByteReadyToRx)
#define bytesReadyToRx ((RxPointerGap)>=0? (RxPointerGap):PP_BUF_LEN+(RxPointerGap))
#define TxPointerGap (nextByteFreeTx-nextByteReadyToTx)
#define bytesReadyToTx ((TxPointerGap)>=0? (TxPointerGap):PP_BUF_LEN+(TxPointerGap))
#define freeBytesInRxBuffer (PP_BUF_LEN-bytesReadyToRx)
#define freeBytesInTxBuffer (PP_BUF_LEN-bytesReadyToTx)
 
 
/* for pp sys msg */
char SysMsg[SYS_MSG_COLS+1][SYS_MSG_LINS+1]; /* space for sys msgs... */
char bufMsg[SYS_MSG_COLS+1]; /* to build msgs... */
 
unsigned int nextMsgToRead;
unsigned int nextMsgFreeToWrite;
 
/* define inline macro */
/* these are for cicle buffer mamagement */
#define msgPointerGap (nextMsgFreeToWrite-nextMsgToRead)
#define msgReadyToRead ((msgPointerGap)>=0? (msgPointerGap):SYS_MSG_LINS+(msgPointerGap))
#define freeMsgInBuffer (SYS_MSG_LINS-msgReadyToRead)
 
 
 
 
/* status ... */
enum ppReadingAvailableStates
{
ppNoAllowReading, /* writing is on...*/
ppNoReading,
ppWaitingDR_Nibble1,
ppWaitingRTS_Nibble2,
ppWaitingDR_Nibble2,
};
 
enum ppWritingAvailableStates
{
ppNoAllowWriting, /* reading is on...*/
ppNoWriting,
ppWaitingOTS_Nibble1,
ppWaitingER_Nibble1,
ppWaitingOTS_Nibble2,
ppWaitingER_Nibble2
};
 
 
int ppStatusReading;
int ppStatusWriting;
BYTE ppReceivingByte;
BYTE ppTransmittingByte;
 
 
#if PP_STATS == 1
/* for internal statistic ...if activate...*/
long statReading[ppWaitingDR_Nibble2+1];
long statWriting[ppWaitingER_Nibble2+1];
#endif
 
 
 
/*********************************************/
/* sys msg managment */
/*********************************************/
 
int ppReadSysMsg(char * buf)
{
if (!msgReadyToRead) /* there is nothing to read...*/
{
return (PP_NOSYSMSG_EXC);
}
else
{int i=0;
while (i<SYS_MSG_COLS && SysMsg[nextMsgToRead][i]) /* !='\0'...*/
*buf++=SysMsg[nextMsgToRead][i++]; /* read char */
*buf='\0';
nextMsgToRead=++nextMsgToRead%SYS_MSG_LINS; /* circular buffer increment */
return (PP_SYSMSG_OK);
}
}
 
 
 
int ppWriteSysMsg(char * buf, ...)
{
char * pbufMsg=bufMsg;
va_list args;
bufMsg[0]='\0';
va_start(args, buf);
vsprintf(bufMsg,buf,args); /* Not garatee msg len... */
va_end(args);
 
if (freeMsgInBuffer < 1)
{
return (PP_NOFREEMSG_EXC);
}
else
{int i=0;
while ((i<SYS_MSG_COLS) && (*pbufMsg) ) /* !='\0'...*/
SysMsg[nextMsgFreeToWrite][i++]=*pbufMsg++;
SysMsg[nextMsgFreeToWrite][i-1]='\n';
SysMsg[nextMsgFreeToWrite][i]='\0';
nextMsgFreeToWrite=++nextMsgFreeToWrite%SYS_MSG_LINS; /* circular buffer pointer increment */
return (PP_SYSMSG_OK);
}
}
 
 
/******************************************/
/* Inizialization: this is NRT task... */
/******************************************/
 
void ppInitDrv(void (*pf)(char *))
{
/* set to zero all pointer & buffer & status... */
 
 
while(ppNRTOpenComm()!=TRUE) // not real-time....
{
if (pf!=NULL) (*pf)("Waiting Open Communcation...\n");
ppSendER();
}
if (pf!=NULL) (*pf)("Open Communcation OK!\n");
}
 
 
/******************************************/
/* TX RX funtions... */
/******************************************/
 
int ppRxOneByte(BYTE *c)
{
if (!bytesReadyToRx) /* there is nothing to read...*/
{
return (PP_COMM_NOREADYBYTES_EXC);
}
else
{
*c=RxBuf[nextByteReadyToRx]; /* read byte */
nextByteReadyToRx=++nextByteReadyToRx%PP_BUF_LEN; /* circular buffer increment */
return (PP_COMM_OK);
}
}
 
 
int ppTxOneByte(BYTE c)
{
if (freeBytesInTxBuffer < 1)
{
return (PP_COMM_NOFREEBYTES_EXC);
}
else
{
TxBuf[nextByteFreeTx]=c;
nextByteFreeTx=++nextByteFreeTx%PP_BUF_LEN; /* circular buffer pointer increment */
 
return (PP_COMM_OK);
}
}
 
int ppTxBytes(BYTE * c, unsigned int nbyte)
{
if (freeBytesInTxBuffer<nbyte) /* if there are less than nbyte return nothing...*/
{
return (PP_COMM_NOFREEBYTES_EXC);
}
else
{ unsigned int i;
for (i=0;i<nbyte;i++)
{
TxBuf[nextByteFreeTx]=*c++;
nextByteFreeTx=++nextByteFreeTx%PP_BUF_LEN; /* circular buffer pointer increment */
}
 
return (PP_COMM_OK);
}
}
 
 
 
int ppRxBytes(BYTE * c, unsigned int nbyte)
{
if (bytesReadyToRx<nbyte) /* if there are less than nbyte return nothing...*/
{
return (PP_COMM_NOREADYBYTES_EXC);
}
else
{ unsigned int i;
 
for (i=0;i<nbyte;i++)
{
*c++=RxBuf[nextByteReadyToRx]; /* read byte */
#if PP_DEBUG == 1
ppWriteSysMsg("Received value: %i %i of %i \n",RxBuf[nextByteReadyToRx],i,nbyte);
#endif
nextByteReadyToRx=++nextByteReadyToRx%PP_BUF_LEN; /* circular buffer increment */
}
 
return (PP_COMM_OK);
}
}
 
 
 
 
/* polling server ... */
TASK ppPollingSvr(void *arg)
{
BYTE port;
nextByteReadyToRx=0;
nextByteReadyToTx=0;
nextByteFreeRx=0;
nextByteFreeTx=0;
 
nextMsgToRead=0;
nextMsgFreeToWrite=0;
 
 
ppStatusReading=ppNoReading;
ppStatusWriting=ppNoWriting;
 
ppWriteSysMsg("Polling Server started...\n");
 
task_endcycle();
 
while (1)
{
/* case ppReading: read ... */
switch (ppStatusReading)
{
case ppNoAllowReading: break;
case ppNoReading:
 
ppStatusWriting=ppNoWriting;
if(!ppIsRTS()) break;
ppSendOTS(); /* Set Ok To Send - the other one can send... */
#if PP_DEBUG == 1
ppWriteSysMsg(" %i : Received RTS...\n", ppStatusReading);
#endif
 
ppStatusWriting=ppNoAllowWriting;
ppStatusReading=ppWaitingDR_Nibble1;
case ppWaitingDR_Nibble1:
#if PP_STATS == 1 /* for internal statistic ...*/
statReading[ppStatusReading]++;
#endif
 
#if PP_DEBUG == 1
ppWriteSysMsg("Send OTS\n");
ppWriteSysMsg("Waiting DR Nibble1\n");
#endif
 
if(!ppIsDR()) break; /* data no ready: read it next period...*/
port = inp(RX_PORT); /* read nibble */
ppSendER(); /* send a End Read */
 
ppReceivingByte = (port >> 3); /* read LSN */
ppStatusReading=ppWaitingRTS_Nibble2;
case ppWaitingRTS_Nibble2:
#if PP_STATS == 1 /* for internal statistic ...*/
statReading[ppStatusReading]++;
#endif
#if PP_DEBUG == 1
 
ppWriteSysMsg("Received DR Nibble1\n");
ppWriteSysMsg("Send ER Nibble1\n");
ppWriteSysMsg("Waiting RTS Nibble2\n");
#endif
if(!ppIsRTS()) break; /* */
ppSendOTS(); /* Ok To Send - the other one can send... */
 
ppStatusReading=ppWaitingDR_Nibble2;
case ppWaitingDR_Nibble2:
#if PP_STATS == 1 /* for internal statistic ...*/
statReading[ppStatusReading]++;
#endif
#if PP_DEBUG == 1
ppWriteSysMsg("Received RTS Nibble2\n");
ppWriteSysMsg("Send OTS Nibble2\n");
ppWriteSysMsg("Waiting DR Nibble2\n");
#endif
 
if(!ppIsDR()) break;
port = inp(RX_PORT); /* read nibble */
ppSendER(); /* send a End Read */
 
 
#if PP_DEBUG == 1
ppWriteSysMsg("Received DR Nibble2\n");
ppWriteSysMsg("Read Nibble2\n");
ppWriteSysMsg("Send ER Nibble2\n");
#endif
 
 
 
ppReceivingByte = (ppReceivingByte & ~MSN); /* set to zero c MSN */
ppReceivingByte = (ppReceivingByte | ((port >> 3) << 4)); /* read MSN */
 
 
/* here is possible insert some ctrl ... */
/* byte is ok, so now make it available to ppRxOneByte() */
RxBuf[nextByteFreeRx]=ppReceivingByte;
nextByteFreeRx=++nextByteFreeRx%PP_BUF_LEN; /* circular buffer pointer increment */
#if PP_STATS == 1
ppWriteSysMsg("Trasmission :\n");
ppWriteSysMsg("W_DR_1 : %d\n",statReading[ppWaitingDR_Nibble1]);
ppWriteSysMsg("W_RTS_2 : %d\n",statReading[ppWaitingRTS_Nibble2]);
ppWriteSysMsg("W_DR_2 : %d\n",statReading[ppWaitingDR_Nibble2]);
ppWriteSysMsg("Received byte : %i\n",ppReceivingByte);
statReading[ppWaitingDR_Nibble1]=0;
statReading[ppWaitingRTS_Nibble2]=0;
statReading[ppWaitingDR_Nibble2]=0;
#endif
/* end reading so reset status... */
ppStatusReading=ppNoReading;
//ppStatusWriting=ppNoWriting;
break;
}
/* case Writing: can only if this cycle not is reading... */
switch (ppStatusWriting)
{
case ppNoAllowWriting: break;
case ppNoWriting:
 
ppStatusReading=ppNoReading;
 
if(!bytesReadyToTx)
{
break;
#if PP_DEBUG == 1
ppWriteSysMsg("Writin break\n");
#endif
}
else
{
#if PP_DEBUG == 1
ppWriteSysMsg("NO Writin break\n");
ppWriteSysMsg("TX Gap: %i \n",TxPointerGap);
ppWriteSysMsg("nextByteFreeTx: %i\n",nextByteFreeTx);
ppWriteSysMsg("nextByteReadyToTx: %i\n",nextByteReadyToTx);
#endif
}
 
ppSendRTS(); /* Set On RequestToSend bit */
 
ppTransmittingByte=TxBuf[nextByteReadyToTx];
#if PP_DEBUG == 1
ppWriteSysMsg("pllsvr: ppTransmittingByte : %i %c \n",ppTransmittingByte,ppTransmittingByte);
#endif
port = inp(TX_PORT) & (~TX_DATA); /* set to zero trasmission bits */
port = port | (ppTransmittingByte & LSN); /* set bits 0..3 with LSN */
ppStatusWriting=ppWaitingOTS_Nibble1;
ppStatusReading=ppNoAllowWriting;
case ppWaitingOTS_Nibble1:
#if PP_STATS == 1
statWriting[ppStatusWriting]++;
#endif
#if PP_DEBUG == 1
ppWriteSysMsg(" Send RTS Nibble1\n");
ppWriteSysMsg(" Waiting OTS Nibble1\n");
#endif
if(!ppIsOTS()) break;
outp(TX_PORT,port); /* send nibble 1 */
ppSendDR(); /* set on Data Ready bit */
 
 
ppStatusWriting=ppWaitingER_Nibble1;
 
 
case ppWaitingER_Nibble1:
#if PP_STATS == 1
statWriting[ppStatusWriting]++;
#endif
#if PP_DEBUG == 1
ppWriteSysMsg(" Send Nibble1\n");
ppWriteSysMsg(" Send DR Nibble1\n");
ppWriteSysMsg(" Waiting ER Nibble1\n");
#endif
 
if(!ppIsER()) break;
 
ppSendRTS(); /* send trasmission request */
 
port = inp(TX_PORT) & (~TX_DATA); /* set to zero bit trasmission bits */
port = port | (ppTransmittingByte >> 4); /* set bits 0..3 with MSN */
ppStatusWriting=ppWaitingOTS_Nibble2;
case ppWaitingOTS_Nibble2:
 
#if PP_STATS == 1
statWriting[ppStatusWriting]++;
#endif
 
#if PP_DEBUG == 1
ppWriteSysMsg(" Received ER Nibble1\n");
ppWriteSysMsg(" Send RTS Nibble2\n");
ppWriteSysMsg(" Waiting OTS Nibble2\n");
#endif
 
if(!ppIsOTS()) break;
outp(TX_PORT,port); /* send nibble 2 */
ppSendDR(); /* set on Data Ready bit */
 
ppStatusWriting=ppWaitingER_Nibble2;
 
case ppWaitingER_Nibble2:
#if PP_STATS == 1
statWriting[ppStatusWriting]++;
#endif
#if PP_DEBUG == 1
ppWriteSysMsg(" Received OTS Nibble2\n");
ppWriteSysMsg(" Write Nibble2\n");
ppWriteSysMsg(" Send DR Nibble2\n");
ppWriteSysMsg(" Waiting ER Nibble2\n");
#endif
 
if(!ppIsER()) break;
/* byte is ok, so move pointer to next byte to be send... */
nextByteReadyToTx=++nextByteReadyToTx%PP_BUF_LEN; /* circular buffer pointer increment */
#if PP_STATS == 1
ppWriteSysMsg("Reception :\n");
ppWriteSysMsg("W_OTS_1 : %ld\n",statWriting[ppWaitingOTS_Nibble1]);
ppWriteSysMsg("W_ER_2 : %ld\n",statWriting[ppWaitingER_Nibble2]);
ppWriteSysMsg("W_OTS_2 : %ld\n",statWriting[ppWaitingOTS_Nibble2]);
statWriting[ppWaitingOTS_Nibble1]=0;
statWriting[ppWaitingER_Nibble2]=0;
statWriting[ppWaitingOTS_Nibble2]=0;
#endif
 
/* end writing. so reset status... */
ppStatusReading=ppNoReading;
ppStatusWriting=ppNoWriting;
}
task_endcycle();
}
return (0);
}
 
 
 
/shark/tags/rel_0_5/drivers/pxc/makefile
3,6 → 3,7
ifndef BASE
BASE=../..
endif
 
include $(BASE)/config/config.mk
 
LIBRARY = hpxc
/shark/tags/rel_0_5/drivers/pxc/pxc.c
261,7 → 261,7
proc_table[p].frozen_activations++;
else {
l = proc_table[p].task_level;
level_table[l]->task_activate(l,p);
level_table[l]->public_activate(l,p);
event_need_reschedule();
}
 
/shark/tags/rel_0_5/drivers/makefile
1,5 → 1,5
 
dirs := $(filter-out CVS makefile, $(wildcard *))
dirs := $(filter-out CVS cvs makefile linuxc24, $(wildcard *))
p_all := $(addprefix prefixall_, $(dirs))
p_install := $(addprefix prefixinstall_, $(dirs))
p_clean := $(addprefix prefixclean_, $(dirs))
17,7 → 17,7
 
cleanall: $(p_cleanall)
 
depend: $(p_depend)
depend: $(pdepend)
 
prefixinstall_%:
make -C $* install