| 50,7 → 50,7 |
|---|
| unsigned char best_n1 = 16 + 2, best_n2 = 2, best_m = 125 + 2; |
| |
| #if DEBUG_FINDCLOCK |
| fprintf(stderr,"S3dacsFindClock: Trying to match clock of %0.3f MHz\n", freq_in / 1000.0); |
| cprintf("S3dacsFindClock: Trying to match clock of %0.3f MHz\n", freq_in / 1000.0); |
| #endif |
| |
| ffreq_in = freq_in / 1000.0 / BASE_FREQ; |
| 60,7 → 60,7 |
|---|
| /* Check if getting freq_in is possible at all */ |
| if (freq_in < freq_min / 8) { |
| #if DEBUG_FINDCLOCK |
| fprintf(stderr,"S3dacsFindClock: %0.3f MHz is too low (lowest is %0.3f MHz)\n", |
| cprintf("S3dacsFindClock: %0.3f MHz is too low (lowest is %0.3f MHz)\n", |
| freq_in / 1000.0, freq_min / 1000.0 / 8); |
| #endif |
| return 0; |
| 67,7 → 67,7 |
|---|
| } |
| if (freq_in > freq_max / (1 << min_n2)) { |
| #if DEBUG_FINDCLOCK |
| fprintf(stderr,"S3dacsFindClock: %0.3f MHz is too high (highest is %0.3f MHz)\n", |
| cprintf("S3dacsFindClock: %0.3f MHz is too high (highest is %0.3f MHz)\n", |
| freq_in / 1000.0, freq_max / 1000.0 / (1 << min_n2)); |
| #endif |
| return 0; |
| 96,7 → 96,7 |
|---|
| } |
| |
| #if DEBUG_FINDCLOCK |
| fprintf(stderr,"S3dacsFindClock: clock wanted %1.6f MHz, found %1.6f MHz (m %d, n1 %d, n2 %d)\n", |
| cprintf("S3dacsFindClock: clock wanted %1.6f MHz, found %1.6f MHz (m %d, n1 %d, n2 %d)\n", |
| freq_in / 1000.0, |
| best_m / ((double) best_n1 * (1 << best_n2)) * BASE_FREQ, |
| best_m, best_n1, best_n2); |
| 126,7 → 126,7 |
|---|
| int n, m; |
| |
| if (!S3dacsFindClock(freq, 0, 100000, 250000, &min_m, &min_n1, &n2)) { |
| fprintf(stderr,"Bad dot clock %0.3f MHz.\n", freq / 1000.0); |
| cprintf("Bad dot clock %0.3f MHz.\n", freq / 1000.0); |
| return; |
| } |
| |
| 136,7 → 136,7 |
|---|
| regs[SDAC_PLL_N1_N2] = n; |
| #if 0 |
| if (__svgalib_driver_report) |
| fprintf(stderr,"Initializing DAC PLL values; 0x%02X, 0x%02X.\n", m, n); |
| cprintf("Initializing DAC PLL values; 0x%02X, 0x%02X.\n", m, n); |
| #endif |
| } |
| |