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/shark/trunk/drivers/svga/r128_reg.h
0,0 → 1,1504
/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/r128_reg.h,v 1.6 2000/12/12 17:17:13 dawes Exp $ */
/*
* Copyright 1999, 2000 ATI Technologies Inc., Markham, Ontario,
* Precision Insight, Inc., Cedar Park, Texas, and
* VA Linux Systems Inc., Fremont, California.
*
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation on the rights to use, copy, modify, merge,
* publish, distribute, sublicense, and/or sell copies of the Software,
* and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial
* portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NON-INFRINGEMENT. IN NO EVENT SHALL ATI, PRECISION INSIGHT, VA LINUX
* SYSTEMS AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
 
/*
* Authors:
* Rickard E. Faith <faith@valinux.com>
* Kevin E. Martin <martin@valinux.com>
* Gareth Hughes <gareth@valinux.com>
*
* References:
*
* RAGE 128 VR/ RAGE 128 GL Register Reference Manual (Technical
* Reference Manual P/N RRG-G04100-C Rev. 0.04), ATI Technologies: April
* 1999.
*
* RAGE 128 Software Development Manual (Technical Reference Manual P/N
* SDK-G04000 Rev. 0.01), ATI Technologies: June 1999.
*
*/
 
#ifndef _R128_REG_H_
#define _R128_REG_H_
 
#define R128_TIMEOUT 2000000
 
#define MMIO_IN8(dummy, addr) v_readb(addr)
#define MMIO_IN16(dummy, addr) v_readw(addr)
#define MMIO_IN32(dummy, addr) LE32(v_readl(addr))
 
#define MMIO_OUT8(dummy, addr, val) v_writeb(val, addr)
#define MMIO_OUT16(dummy, addr, val) v_writew(val, addr)
#define MMIO_OUT32(dummy, addr, val) v_writel(LE32(val), addr)
 
/* Memory mapped register access macros */
#define INREG8(addr) MMIO_IN8(R128MMIO, addr)
#define INREG16(addr) MMIO_IN16(R128MMIO, addr)
#define INREG(addr) MMIO_IN32(R128MMIO, addr)
#define OUTREG8(addr, val) MMIO_OUT8(R128MMIO, addr, val)
#define OUTREG16(addr, val) MMIO_OUT16(R128MMIO, addr, val)
#define OUTREG(addr, val) MMIO_OUT32(R128MMIO, addr, val)
 
#if 0
#define R128_BIOS8(v) (VBIOS[v])
#define R128_BIOS16(v) (VBIOS[v] | \
(VBIOS[(v) + 1] << 8))
#define R128_BIOS32(v) (VBIOS[v] | \
(VBIOS[(v) + 1] << 8) | \
(VBIOS[(v) + 2] << 16) | \
(VBIOS[(v) + 3] << 24))
#endif
#define OUTREGP(addr, val, mask) \
do { \
uint32_t tmp = INREG(addr); \
tmp &= (mask); \
tmp |= (val); \
OUTREG(addr, tmp); \
} while (0)
 
#define INPLL(addr) R128INPLL(addr)
 
#define OUTPLL(addr, val) \
do { \
OUTREG8(R128_CLOCK_CNTL_INDEX, ((addr) & 0x1f) | R128_PLL_WR_EN); \
OUTREG(R128_CLOCK_CNTL_DATA, val); \
} while (0)
 
#define OUTPLLP(addr, val, mask) \
do { \
uint32_t tmp = INPLL(addr); \
tmp &= (mask); \
tmp |= (val); \
OUTPLL(addr, tmp); \
} while (0)
 
#define OUTPAL_START(idx) \
do { \
OUTREG8(R128_PALETTE_INDEX, (idx)); \
} while (0)
 
#define OUTPAL_NEXT(r, g, b) \
do { \
OUTREG(R128_PALETTE_DATA, ((r) << 16) | ((g) << 8) | (b)); \
} while (0)
 
#define OUTPAL_NEXT_uint32_t(v) \
do { \
OUTREG(R128_PALETTE_DATA, (v & 0x00ffffff)); \
} while (0)
 
#define OUTPAL(idx, r, g, b) \
do { \
OUTPAL_START((idx)); \
OUTPAL_NEXT((r), (g), (b)); \
} while (0)
 
#define INPAL_START(idx) \
do { \
OUTREG(R128_PALETTE_INDEX, (idx) << 16); \
} while (0)
 
#define INPAL_NEXT() INREG(R128_PALETTE_DATA)
 
#define PAL_SELECT(idx) \
do { \
if (idx) { \
OUTREG(R128_DAC_CNTL, INREG(R128_DAC_CNTL) | \
R128_DAC_PALETTE_ACC_CTL); \
} else { \
OUTREG(R128_DAC_CNTL, INREG(R128_DAC_CNTL) & \
~R128_DAC_PALETTE_ACC_CTL); \
} \
} while (0)
 
#define R128_ADAPTER_ID 0x0f2c /* PCI */
#define R128_AGP_APER_OFFSET 0x0178
#define R128_AGP_BASE 0x0170
#define R128_AGP_CNTL 0x0174
# define R128_AGP_APER_SIZE_256MB (0x00 << 0)
# define R128_AGP_APER_SIZE_128MB (0x20 << 0)
# define R128_AGP_APER_SIZE_64MB (0x30 << 0)
# define R128_AGP_APER_SIZE_32MB (0x38 << 0)
# define R128_AGP_APER_SIZE_16MB (0x3c << 0)
# define R128_AGP_APER_SIZE_8MB (0x3e << 0)
# define R128_AGP_APER_SIZE_4MB (0x3f << 0)
# define R128_AGP_APER_SIZE_MASK (0x3f << 0)
#define R128_AGP_CNTL_B 0x0b44
#define R128_AGP_COMMAND 0x0f58 /* PCI */
#define R128_AGP_PLL_CNTL 0x0010 /* PLL */
#define R128_AGP_STATUS 0x0f54 /* PCI */
# define R128_AGP_1X_MODE 0x01
# define R128_AGP_2X_MODE 0x02
# define R128_AGP_4X_MODE 0x04
# define R128_AGP_MODE_MASK 0x07
#define R128_AMCGPIO_A_REG 0x01a0
#define R128_AMCGPIO_EN_REG 0x01a8
#define R128_AMCGPIO_MASK 0x0194
#define R128_AMCGPIO_Y_REG 0x01a4
#define R128_ATTRDR 0x03c1 /* VGA */
#define R128_ATTRDW 0x03c0 /* VGA */
#define R128_ATTRX 0x03c0 /* VGA */
#define R128_AUX_SC_CNTL 0x1660
# define R128_AUX1_SC_EN (1 << 0)
# define R128_AUX1_SC_MODE_OR (0 << 1)
# define R128_AUX1_SC_MODE_NAND (1 << 1)
# define R128_AUX2_SC_EN (1 << 2)
# define R128_AUX2_SC_MODE_OR (0 << 3)
# define R128_AUX2_SC_MODE_NAND (1 << 3)
# define R128_AUX3_SC_EN (1 << 4)
# define R128_AUX3_SC_MODE_OR (0 << 5)
# define R128_AUX3_SC_MODE_NAND (1 << 5)
#define R128_AUX1_SC_BOTTOM 0x1670
#define R128_AUX1_SC_LEFT 0x1664
#define R128_AUX1_SC_RIGHT 0x1668
#define R128_AUX1_SC_TOP 0x166c
#define R128_AUX2_SC_BOTTOM 0x1680
#define R128_AUX2_SC_LEFT 0x1674
#define R128_AUX2_SC_RIGHT 0x1678
#define R128_AUX2_SC_TOP 0x167c
#define R128_AUX3_SC_BOTTOM 0x1690
#define R128_AUX3_SC_LEFT 0x1684
#define R128_AUX3_SC_RIGHT 0x1688
#define R128_AUX3_SC_TOP 0x168c
#define R128_AUX_WINDOW_HORZ_CNTL 0x02d8
#define R128_AUX_WINDOW_VERT_CNTL 0x02dc
 
#define R128_BASE_CODE 0x0f0b
#define R128_BIOS_0_SCRATCH 0x0010
#define R128_BIOS_1_SCRATCH 0x0014
#define R128_BIOS_2_SCRATCH 0x0018
#define R128_BIOS_3_SCRATCH 0x001c
#define R128_BIOS_ROM 0x0f30 /* PCI */
#define R128_BIST 0x0f0f /* PCI */
#define R128_BRUSH_DATA0 0x1480
#define R128_BRUSH_DATA1 0x1484
#define R128_BRUSH_DATA10 0x14a8
#define R128_BRUSH_DATA11 0x14ac
#define R128_BRUSH_DATA12 0x14b0
#define R128_BRUSH_DATA13 0x14b4
#define R128_BRUSH_DATA14 0x14b8
#define R128_BRUSH_DATA15 0x14bc
#define R128_BRUSH_DATA16 0x14c0
#define R128_BRUSH_DATA17 0x14c4
#define R128_BRUSH_DATA18 0x14c8
#define R128_BRUSH_DATA19 0x14cc
#define R128_BRUSH_DATA2 0x1488
#define R128_BRUSH_DATA20 0x14d0
#define R128_BRUSH_DATA21 0x14d4
#define R128_BRUSH_DATA22 0x14d8
#define R128_BRUSH_DATA23 0x14dc
#define R128_BRUSH_DATA24 0x14e0
#define R128_BRUSH_DATA25 0x14e4
#define R128_BRUSH_DATA26 0x14e8
#define R128_BRUSH_DATA27 0x14ec
#define R128_BRUSH_DATA28 0x14f0
#define R128_BRUSH_DATA29 0x14f4
#define R128_BRUSH_DATA3 0x148c
#define R128_BRUSH_DATA30 0x14f8
#define R128_BRUSH_DATA31 0x14fc
#define R128_BRUSH_DATA32 0x1500
#define R128_BRUSH_DATA33 0x1504
#define R128_BRUSH_DATA34 0x1508
#define R128_BRUSH_DATA35 0x150c
#define R128_BRUSH_DATA36 0x1510
#define R128_BRUSH_DATA37 0x1514
#define R128_BRUSH_DATA38 0x1518
#define R128_BRUSH_DATA39 0x151c
#define R128_BRUSH_DATA4 0x1490
#define R128_BRUSH_DATA40 0x1520
#define R128_BRUSH_DATA41 0x1524
#define R128_BRUSH_DATA42 0x1528
#define R128_BRUSH_DATA43 0x152c
#define R128_BRUSH_DATA44 0x1530
#define R128_BRUSH_DATA45 0x1534
#define R128_BRUSH_DATA46 0x1538
#define R128_BRUSH_DATA47 0x153c
#define R128_BRUSH_DATA48 0x1540
#define R128_BRUSH_DATA49 0x1544
#define R128_BRUSH_DATA5 0x1494
#define R128_BRUSH_DATA50 0x1548
#define R128_BRUSH_DATA51 0x154c
#define R128_BRUSH_DATA52 0x1550
#define R128_BRUSH_DATA53 0x1554
#define R128_BRUSH_DATA54 0x1558
#define R128_BRUSH_DATA55 0x155c
#define R128_BRUSH_DATA56 0x1560
#define R128_BRUSH_DATA57 0x1564
#define R128_BRUSH_DATA58 0x1568
#define R128_BRUSH_DATA59 0x156c
#define R128_BRUSH_DATA6 0x1498
#define R128_BRUSH_DATA60 0x1570
#define R128_BRUSH_DATA61 0x1574
#define R128_BRUSH_DATA62 0x1578
#define R128_BRUSH_DATA63 0x157c
#define R128_BRUSH_DATA7 0x149c
#define R128_BRUSH_DATA8 0x14a0
#define R128_BRUSH_DATA9 0x14a4
#define R128_BRUSH_SCALE 0x1470
#define R128_BRUSH_Y_X 0x1474
#define R128_BUS_CNTL 0x0030
# define R128_BUS_MASTER_DIS (1 << 6)
# define R128_BUS_RD_DISCARD_EN (1 << 24)
# define R128_BUS_RD_ABORT_EN (1 << 25)
# define R128_BUS_MSTR_DISCONNECT_EN (1 << 28)
# define R128_BUS_WRT_BURST (1 << 29)
# define R128_BUS_READ_BURST (1 << 30)
#define R128_BUS_CNTL1 0x0034
# define R128_BUS_WAIT_ON_LOCK_EN (1 << 4)
 
#define R128_CACHE_CNTL 0x1724
#define R128_CACHE_LINE 0x0f0c /* PCI */
#define R128_CAP0_TRIG_CNTL 0x0950 /* ? */
#define R128_CAP1_TRIG_CNTL 0x09c0 /* ? */
#define R128_CAPABILITIES_ID 0x0f50 /* PCI */
#define R128_CAPABILITIES_PTR 0x0f34 /* PCI */
#define R128_CLK_PIN_CNTL 0x0001 /* PLL */
#define R128_CLOCK_CNTL_DATA 0x000c
#define R128_CLOCK_CNTL_INDEX 0x0008
# define R128_PLL_WR_EN (1 << 7)
# define R128_PLL_DIV_SEL (3 << 8)
#define R128_CLR_CMP_CLR_3D 0x1a24
#define R128_CLR_CMP_CLR_DST 0x15c8
#define R128_CLR_CMP_CLR_SRC 0x15c4
#define R128_CLR_CMP_CNTL 0x15c0
# define R128_SRC_CMP_EQ_COLOR (4 << 0)
# define R128_SRC_CMP_NEQ_COLOR (5 << 0)
# define R128_CLR_CMP_SRC_SOURCE (1 << 24)
#define R128_CLR_CMP_MASK 0x15cc
# define R128_CLR_CMP_MSK 0xffffffff
#define R128_CLR_CMP_MASK_3D 0x1A28
#define R128_COMMAND 0x0f04 /* PCI */
#define R128_COMPOSITE_SHADOW_ID 0x1a0c
#define R128_CONFIG_APER_0_BASE 0x0100
#define R128_CONFIG_APER_1_BASE 0x0104
#define R128_CONFIG_APER_SIZE 0x0108
#define R128_CONFIG_BONDS 0x00e8
#define R128_CONFIG_CNTL 0x00e0
# define APER_0_BIG_ENDIAN_16BPP_SWAP (1 << 0)
# define APER_0_BIG_ENDIAN_32BPP_SWAP (2 << 0)
# define R128_CFG_VGA_RAM_EN (1 << 8)
#define R128_CONFIG_MEMSIZE 0x00f8
#define R128_CONFIG_MEMSIZE_EMBEDDED 0x0114
#define R128_CONFIG_REG_1_BASE 0x010c
#define R128_CONFIG_REG_APER_SIZE 0x0110
#define R128_CONFIG_XSTRAP 0x00e4
#define R128_CONSTANT_COLOR_C 0x1d34
# define R128_CONSTANT_COLOR_MASK 0x00ffffff
# define R128_CONSTANT_COLOR_ONE 0x00ffffff
# define R128_CONSTANT_COLOR_ZERO 0x00000000
#define R128_CRC_CMDFIFO_ADDR 0x0740
#define R128_CRC_CMDFIFO_DOUT 0x0744
#define R128_CRTC_CRNT_FRAME 0x0214
#define R128_CRTC_DEBUG 0x021c
#define R128_CRTC_EXT_CNTL 0x0054
# define R128_CRTC_VGA_XOVERSCAN (1 << 0)
# define R128_VGA_ATI_LINEAR (1 << 3)
# define R128_XCRT_CNT_EN (1 << 6)
# define R128_CRTC_HSYNC_DIS (1 << 8)
# define R128_CRTC_VSYNC_DIS (1 << 9)
# define R128_CRTC_DISPLAY_DIS (1 << 10)
# define R128_CRTC_CRT_ON (1 << 15)
# define R128_VGA_MEM_PS_EN (1 << 19)
#define R128_CRTC_EXT_CNTL_DPMS_BYTE 0x0055
# define R128_CRTC_HSYNC_DIS_BYTE (1 << 0)
# define R128_CRTC_VSYNC_DIS_BYTE (1 << 1)
# define R128_CRTC_DISPLAY_DIS_BYTE (1 << 2)
#define R128_CRTC_GEN_CNTL 0x0050
# define R128_CRTC_DBL_SCAN_EN (1 << 0)
# define R128_CRTC_INTERLACE_EN (1 << 1)
# define R128_CRTC_CSYNC_EN (1 << 4)
# define R128_CRTC_CUR_EN (1 << 16)
# define R128_CRTC_CUR_MODE_MASK (7 << 17)
# define R128_CRTC_ICON_EN (1 << 20)
# define R128_CRTC_EXT_DISP_EN (1 << 24)
# define R128_CRTC_EN (1 << 25)
# define R128_CRTC_DISP_REQ_EN_B (1 << 26)
#define R128_CRTC_GUI_TRIG_VLINE 0x0218
#define R128_CRTC_H_SYNC_STRT_WID 0x0204
# define R128_CRTC_H_SYNC_STRT_PIX (0x07 << 0)
# define R128_CRTC_H_SYNC_STRT_CHAR (0x1ff << 3)
# define R128_CRTC_H_SYNC_STRT_CHAR_SHIFT 3
# define R128_CRTC_H_SYNC_WID (0x3f << 16)
# define R128_CRTC_H_SYNC_WID_SHIFT 16
# define R128_CRTC_H_SYNC_POL (1 << 23)
#define R128_CRTC_H_TOTAL_DISP 0x0200
# define R128_CRTC_H_TOTAL (0x01ff << 0)
# define R128_CRTC_H_TOTAL_SHIFT 0
# define R128_CRTC_H_DISP (0x00ff << 16)
# define R128_CRTC_H_DISP_SHIFT 16
#define R128_CRTC_OFFSET 0x0224
#define R128_CRTC_OFFSET_CNTL 0x0228
#define R128_CRTC_PITCH 0x022c
#define R128_CRTC_STATUS 0x005c
# define R128_CRTC_VBLANK_SAVE (1 << 1)
#define R128_CRTC_V_SYNC_STRT_WID 0x020c
# define R128_CRTC_V_SYNC_STRT (0x7ff << 0)
# define R128_CRTC_V_SYNC_STRT_SHIFT 0
# define R128_CRTC_V_SYNC_WID (0x1f << 16)
# define R128_CRTC_V_SYNC_WID_SHIFT 16
# define R128_CRTC_V_SYNC_POL (1 << 23)
#define R128_CRTC_V_TOTAL_DISP 0x0208
# define R128_CRTC_V_TOTAL (0x07ff << 0)
# define R128_CRTC_V_TOTAL_SHIFT 0
# define R128_CRTC_V_DISP (0x07ff << 16)
# define R128_CRTC_V_DISP_SHIFT 16
#define R128_CRTC_VLINE_CRNT_VLINE 0x0210
# define R128_CRTC_CRNT_VLINE_MASK (0x7ff << 16)
#define R128_CRTC2_CRNT_FRAME 0x0314
#define R128_CRTC2_DEBUG 0x031c
#define R128_CRTC2_GEN_CNTL 0x03f8
#define R128_CRTC2_GUI_TRIG_VLINE 0x0318
#define R128_CRTC2_H_SYNC_STRT_WID 0x0304
#define R128_CRTC2_H_TOTAL_DISP 0x0300
#define R128_CRTC2_OFFSET 0x0324
#define R128_CRTC2_OFFSET_CNTL 0x0328
#define R128_CRTC2_PITCH 0x032c
#define R128_CRTC2_STATUS 0x03fc
#define R128_CRTC2_V_SYNC_STRT_WID 0x030c
#define R128_CRTC2_V_TOTAL_DISP 0x0308
#define R128_CRTC2_VLINE_CRNT_VLINE 0x0310
#define R128_CRTC8_DATA 0x03d5 /* VGA, 0x3b5 */
#define R128_CRTC8_IDX 0x03d4 /* VGA, 0x3b4 */
#define R128_CUR_CLR0 0x026c
#define R128_CUR_CLR1 0x0270
#define R128_CUR_HORZ_VERT_OFF 0x0268
#define R128_CUR_HORZ_VERT_POSN 0x0264
#define R128_CUR_OFFSET 0x0260
# define R128_CUR_LOCK (1 << 31)
 
#define R128_DAC_CNTL 0x0058
# define R128_DAC_RANGE_CNTL (3 << 0)
# define R128_DAC_BLANKING (1 << 2)
# define R128_DAC_CRT_SEL_CRTC2 (1 << 4)
# define R128_DAC_PALETTE_ACC_CTL (1 << 5)
# define R128_DAC_8BIT_EN (1 << 8)
# define R128_DAC_VGA_ADR_EN (1 << 13)
# define R128_DAC_MASK_ALL (0xff << 24)
#define R128_DAC_CRC_SIG 0x02cc
#define R128_DAC_DATA 0x03c9 /* VGA */
#define R128_DAC_MASK 0x03c6 /* VGA */
#define R128_DAC_R_INDEX 0x03c7 /* VGA */
#define R128_DAC_W_INDEX 0x03c8 /* VGA */
#define R128_DDA_CONFIG 0x02e0
#define R128_DDA_ON_OFF 0x02e4
#define R128_DEFAULT_OFFSET 0x16e0
#define R128_DEFAULT_PITCH 0x16e4
#define R128_DEFAULT_SC_BOTTOM_RIGHT 0x16e8
# define R128_DEFAULT_SC_RIGHT_MAX (0x1fff << 0)
# define R128_DEFAULT_SC_BOTTOM_MAX (0x1fff << 16)
#define R128_DESTINATION_3D_CLR_CMP_VAL 0x1820
#define R128_DESTINATION_3D_CLR_CMP_MSK 0x1824
#define R128_DEVICE_ID 0x0f02 /* PCI */
#define R128_DP_BRUSH_BKGD_CLR 0x1478
#define R128_DP_BRUSH_FRGD_CLR 0x147c
#define R128_DP_CNTL 0x16c0
# define R128_DST_X_LEFT_TO_RIGHT (1 << 0)
# define R128_DST_Y_TOP_TO_BOTTOM (1 << 1)
#define R128_DP_CNTL_XDIR_YDIR_YMAJOR 0x16d0
# define R128_DST_Y_MAJOR (1 << 2)
# define R128_DST_Y_DIR_TOP_TO_BOTTOM (1 << 15)
# define R128_DST_X_DIR_LEFT_TO_RIGHT (1 << 31)
#define R128_DP_DATATYPE 0x16c4
# define R128_HOST_BIG_ENDIAN_EN (1 << 29)
#define R128_DP_GUI_MASTER_CNTL 0x146c
# define R128_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0)
# define R128_GMC_DST_PITCH_OFFSET_CNTL (1 << 1)
# define R128_GMC_SRC_CLIPPING (1 << 2)
# define R128_GMC_DST_CLIPPING (1 << 3)
# define R128_GMC_BRUSH_DATATYPE_MASK (0x0f << 4)
# define R128_GMC_BRUSH_8X8_MONO_FG_BG (0 << 4)
# define R128_GMC_BRUSH_8X8_MONO_FG_LA (1 << 4)
# define R128_GMC_BRUSH_1X8_MONO_FG_BG (4 << 4)
# define R128_GMC_BRUSH_1X8_MONO_FG_LA (5 << 4)
# define R128_GMC_BRUSH_32x1_MONO_FG_BG (6 << 4)
# define R128_GMC_BRUSH_32x1_MONO_FG_LA (7 << 4)
# define R128_GMC_BRUSH_32x32_MONO_FG_BG (8 << 4)
# define R128_GMC_BRUSH_32x32_MONO_FG_LA (9 << 4)
# define R128_GMC_BRUSH_8x8_COLOR (10 << 4)
# define R128_GMC_BRUSH_1X8_COLOR (12 << 4)
# define R128_GMC_BRUSH_SOLID_COLOR (13 << 4)
# define R128_GMC_BRUSH_NONE (15 << 4)
# define R128_GMC_DST_8BPP_CI (2 << 8)
# define R128_GMC_DST_15BPP (3 << 8)
# define R128_GMC_DST_16BPP (4 << 8)
# define R128_GMC_DST_24BPP (5 << 8)
# define R128_GMC_DST_32BPP (6 << 8)
# define R128_GMC_DST_8BPP_RGB (7 << 8)
# define R128_GMC_DST_Y8 (8 << 8)
# define R128_GMC_DST_RGB8 (9 << 8)
# define R128_GMC_DST_VYUY (11 << 8)
# define R128_GMC_DST_YVYU (12 << 8)
# define R128_GMC_DST_AYUV444 (14 << 8)
# define R128_GMC_DST_ARGB4444 (15 << 8)
# define R128_GMC_DST_DATATYPE_MASK (0x0f << 8)
# define R128_GMC_DST_DATATYPE_SHIFT 8
# define R128_GMC_SRC_DATATYPE_MASK (3 << 12)
# define R128_GMC_SRC_DATATYPE_MONO_FG_BG (0 << 12)
# define R128_GMC_SRC_DATATYPE_MONO_FG_LA (1 << 12)
# define R128_GMC_SRC_DATATYPE_COLOR (3 << 12)
# define R128_GMC_BYTE_PIX_ORDER (1 << 14)
# define R128_GMC_BYTE_MSB_TO_LSB (0 << 14)
# define R128_GMC_BYTE_LSB_TO_MSB (1 << 14)
# define R128_GMC_CONVERSION_TEMP (1 << 15)
# define R128_GMC_CONVERSION_TEMP_6500 (0 << 15)
# define R128_GMC_CONVERSION_TEMP_9300 (1 << 15)
# define R128_GMC_ROP3_MASK (0xff << 16)
# define R128_DP_SRC_SOURCE_MASK (7 << 24)
# define R128_DP_SRC_SOURCE_MEMORY (2 << 24)
# define R128_DP_SRC_SOURCE_HOST_DATA (3 << 24)
# define R128_GMC_3D_FCN_EN (1 << 27)
# define R128_GMC_CLR_CMP_CNTL_DIS (1 << 28)
# define R128_GMC_AUX_CLIP_DIS (1 << 29)
# define R128_GMC_WR_MSK_DIS (1 << 30)
# define R128_GMC_LD_BRUSH_Y_X (1 << 31)
# define R128_ROP3_ZERO 0x00000000
# define R128_ROP3_DSa 0x00880000
# define R128_ROP3_SDna 0x00440000
# define R128_ROP3_S 0x00cc0000
# define R128_ROP3_DSna 0x00220000
# define R128_ROP3_D 0x00aa0000
# define R128_ROP3_DSx 0x00660000
# define R128_ROP3_DSo 0x00ee0000
# define R128_ROP3_DSon 0x00110000
# define R128_ROP3_DSxn 0x00990000
# define R128_ROP3_Dn 0x00550000
# define R128_ROP3_SDno 0x00dd0000
# define R128_ROP3_Sn 0x00330000
# define R128_ROP3_DSno 0x00bb0000
# define R128_ROP3_DSan 0x00770000
# define R128_ROP3_ONE 0x00ff0000
# define R128_ROP3_DPa 0x00a00000
# define R128_ROP3_PDna 0x00500000
# define R128_ROP3_P 0x00f00000
# define R128_ROP3_DPna 0x000a0000
# define R128_ROP3_D 0x00aa0000
# define R128_ROP3_DPx 0x005a0000
# define R128_ROP3_DPo 0x00fa0000
# define R128_ROP3_DPon 0x00050000
# define R128_ROP3_PDxn 0x00a50000
# define R128_ROP3_PDno 0x00f50000
# define R128_ROP3_Pn 0x000f0000
# define R128_ROP3_DPno 0x00af0000
# define R128_ROP3_DPan 0x005f0000
 
 
#define R128_DP_GUI_MASTER_CNTL_C 0x1c84
#define R128_DP_MIX 0x16c8
#define R128_DP_SRC_BKGD_CLR 0x15dc
#define R128_DP_SRC_FRGD_CLR 0x15d8
#define R128_DP_WRITE_MASK 0x16cc
#define R128_DST_BRES_DEC 0x1630
#define R128_DST_BRES_ERR 0x1628
#define R128_DST_BRES_INC 0x162c
#define R128_DST_BRES_LNTH 0x1634
#define R128_DST_BRES_LNTH_SUB 0x1638
#define R128_DST_HEIGHT 0x1410
#define R128_DST_HEIGHT_WIDTH 0x143c
#define R128_DST_HEIGHT_WIDTH_8 0x158c
#define R128_DST_HEIGHT_WIDTH_BW 0x15b4
#define R128_DST_HEIGHT_Y 0x15a0
#define R128_DST_OFFSET 0x1404
#define R128_DST_PITCH 0x1408
#define R128_DST_PITCH_OFFSET 0x142c
#define R128_DST_PITCH_OFFSET_C 0x1c80
# define R128_PITCH_SHIFT 21
# define R128_DST_TILE (1 << 31)
#define R128_DST_WIDTH 0x140c
#define R128_DST_WIDTH_HEIGHT 0x1598
#define R128_DST_WIDTH_X 0x1588
#define R128_DST_WIDTH_X_INCY 0x159c
#define R128_DST_X 0x141c
#define R128_DST_X_SUB 0x15a4
#define R128_DST_X_Y 0x1594
#define R128_DST_Y 0x1420
#define R128_DST_Y_SUB 0x15a8
#define R128_DST_Y_X 0x1438
 
#define R128_EXT_MEM_CNTL 0x0144
 
#define R128_FCP_CNTL 0x0012 /* PLL */
#define R128_FLUSH_1 0x1704
#define R128_FLUSH_2 0x1708
#define R128_FLUSH_3 0x170c
#define R128_FLUSH_4 0x1710
#define R128_FLUSH_5 0x1714
#define R128_FLUSH_6 0x1718
#define R128_FLUSH_7 0x171c
#define R128_FOG_3D_TABLE_START 0x1810
#define R128_FOG_3D_TABLE_END 0x1814
#define R128_FOG_3D_TABLE_DENSITY 0x181c
#define R128_FOG_TABLE_INDEX 0x1a14
#define R128_FOG_TABLE_DATA 0x1a18
#define R128_FP_CRTC_H_TOTAL_DISP 0x0250
#define R128_FP_CRTC_V_TOTAL_DISP 0x0254
#define R128_FP_GEN_CNTL 0x0284
# define R128_FP_FPON (1 << 0)
# define R128_FP_TDMS_EN (1 << 2)
# define R128_FP_DETECT_SENSE (1 << 8)
# define R128_FP_SEL_CRTC2 (1 << 13)
# define R128_FP_CRTC_DONT_SHADOW_VPAR (1 << 16)
# define R128_FP_CRTC_USE_SHADOW_VEND (1 << 18)
# define R128_FP_CRTC_HORZ_DIV2_EN (1 << 20)
# define R128_FP_CRTC_HOR_CRT_DIV2_DIS (1 << 21)
# define R128_FP_USE_SHADOW_EN (1 << 24)
#define R128_FP_H_SYNC_STRT_WID 0x02c4
#define R128_FP_HORZ_STRETCH 0x028c
# define R128_HORZ_STRETCH_RATIO_MASK 0xffff
# define R128_HORZ_STRETCH_RATIO_SHIFT 0
# define R128_HORZ_STRETCH_RATIO_MAX 4096
# define R128_HORZ_PANEL_SIZE (0xff << 16)
# define R128_HORZ_PANEL_SHIFT 16
# define R128_HORZ_STRETCH_PIXREP (0 << 25)
# define R128_HORZ_STRETCH_BLEND (1 << 25)
# define R128_HORZ_STRETCH_ENABLE (1 << 26)
# define R128_HORZ_FP_LOOP_STRETCH (0x7 << 27)
# define R128_HORZ_STRETCH_RESERVED (1 << 30)
# define R128_HORZ_AUTO_RATIO_FIX_EN (1 << 31)
 
#define R128_FP_PANEL_CNTL 0x0288
# define R128_FP_DIGON (1 << 0)
# define R128_FP_BLON (1 << 1)
#define R128_FP_V_SYNC_STRT_WID 0x02c8
#define R128_FP_VERT_STRETCH 0x0290
# define R128_VERT_PANEL_SIZE (0x7ff << 0)
# define R128_VERT_PANEL_SHIFT 0
# define R128_VERT_STRETCH_RATIO_MASK 0x3ff
# define R128_VERT_STRETCH_RATIO_SHIFT 11
# define R128_VERT_STRETCH_RATIO_MAX 1024
# define R128_VERT_STRETCH_ENABLE (1 << 24)
# define R128_VERT_STRETCH_LINEREP (0 << 25)
# define R128_VERT_STRETCH_BLEND (1 << 25)
# define R128_VERT_AUTO_RATIO_EN (1 << 26)
# define R128_VERT_STRETCH_RESERVED 0xf8e00000
 
#define R128_GEN_INT_CNTL 0x0040
#define R128_GEN_INT_STATUS 0x0044
# define R128_VSYNC_INT_AK (1 << 2)
# define R128_VSYNC_INT (1 << 2)
#define R128_GEN_RESET_CNTL 0x00f0
# define R128_SOFT_RESET_GUI (1 << 0)
# define R128_SOFT_RESET_VCLK (1 << 8)
# define R128_SOFT_RESET_PCLK (1 << 9)
# define R128_SOFT_RESET_DISPENG_XCLK (1 << 11)
# define R128_SOFT_RESET_MEMCTLR_XCLK (1 << 12)
#define R128_GENENB 0x03c3 /* VGA */
#define R128_GENFC_RD 0x03ca /* VGA */
#define R128_GENFC_WT 0x03da /* VGA, 0x03ba */
#define R128_GENMO_RD 0x03cc /* VGA */
#define R128_GENMO_WT 0x03c2 /* VGA */
#define R128_GENS0 0x03c2 /* VGA */
#define R128_GENS1 0x03da /* VGA, 0x03ba */
#define R128_GPIO_MONID 0x0068
# define R128_GPIO_MONID_A_0 (1 << 0)
# define R128_GPIO_MONID_A_1 (1 << 1)
# define R128_GPIO_MONID_A_2 (1 << 2)
# define R128_GPIO_MONID_A_3 (1 << 3)
# define R128_GPIO_MONID_Y_0 (1 << 8)
# define R128_GPIO_MONID_Y_1 (1 << 9)
# define R128_GPIO_MONID_Y_2 (1 << 10)
# define R128_GPIO_MONID_Y_3 (1 << 11)
# define R128_GPIO_MONID_EN_0 (1 << 16)
# define R128_GPIO_MONID_EN_1 (1 << 17)
# define R128_GPIO_MONID_EN_2 (1 << 18)
# define R128_GPIO_MONID_EN_3 (1 << 19)
# define R128_GPIO_MONID_MASK_0 (1 << 24)
# define R128_GPIO_MONID_MASK_1 (1 << 25)
# define R128_GPIO_MONID_MASK_2 (1 << 26)
# define R128_GPIO_MONID_MASK_3 (1 << 27)
#define R128_GPIO_MONIDB 0x006c
#define R128_GRPH8_DATA 0x03cf /* VGA */
#define R128_GRPH8_IDX 0x03ce /* VGA */
#define R128_GUI_DEBUG0 0x16a0
#define R128_GUI_DEBUG1 0x16a4
#define R128_GUI_DEBUG2 0x16a8
#define R128_GUI_DEBUG3 0x16ac
#define R128_GUI_DEBUG4 0x16b0
#define R128_GUI_DEBUG5 0x16b4
#define R128_GUI_DEBUG6 0x16b8
#define R128_GUI_PROBE 0x16bc
#define R128_GUI_SCRATCH_REG0 0x15e0
#define R128_GUI_SCRATCH_REG1 0x15e4
#define R128_GUI_SCRATCH_REG2 0x15e8
#define R128_GUI_SCRATCH_REG3 0x15ec
#define R128_GUI_SCRATCH_REG4 0x15f0
#define R128_GUI_SCRATCH_REG5 0x15f4
#define R128_GUI_STAT 0x1740
# define R128_GUI_FIFOCNT_MASK 0x0fff
# define R128_GUI_ACTIVE (1 << 31)
 
#define R128_HEADER 0x0f0e /* PCI */
#define R128_HOST_DATA0 0x17c0
#define R128_HOST_DATA1 0x17c4
#define R128_HOST_DATA2 0x17c8
#define R128_HOST_DATA3 0x17cc
#define R128_HOST_DATA4 0x17d0
#define R128_HOST_DATA5 0x17d4
#define R128_HOST_DATA6 0x17d8
#define R128_HOST_DATA7 0x17dc
#define R128_HOST_DATA_LAST 0x17e0
#define R128_HOST_PATH_CNTL 0x0130
#define R128_HTOTAL_CNTL 0x0009 /* PLL */
#define R128_HW_DEBUG 0x0128
#define R128_HW_DEBUG2 0x011c
 
#define R128_I2C_CNTL_1 0x0094 /* ? */
#define R128_INTERRUPT_LINE 0x0f3c /* PCI */
#define R128_INTERRUPT_PIN 0x0f3d /* PCI */
#define R128_IO_BASE 0x0f14 /* PCI */
 
#define R128_LATENCY 0x0f0d /* PCI */
#define R128_LEAD_BRES_DEC 0x1608
#define R128_LEAD_BRES_ERR 0x1600
#define R128_LEAD_BRES_INC 0x1604
#define R128_LEAD_BRES_LNTH 0x161c
#define R128_LEAD_BRES_LNTH_SUB 0x1624
#define R128_LVDS_GEN_CNTL 0x02d0
# define R128_LVDS_ON (1 << 0)
# define R128_LVDS_BLON (1 << 19)
# define R128_LVDS_SEL_CRTC2 (1 << 23)
# define R128_HSYNC_DELAY_SHIFT 28
# define R128_HSYNC_DELAY_MASK (0xf << 28)
 
#define R128_MAX_LATENCY 0x0f3f /* PCI */
#define R128_MCLK_CNTL 0x000f /* PLL */
# define R128_FORCE_GCP (1 << 16)
# define R128_FORCE_PIPE3D_CP (1 << 17)
# define R128_FORCE_RCP (1 << 18)
#define R128_MDGPIO_A_REG 0x01ac
#define R128_MDGPIO_EN_REG 0x01b0
#define R128_MDGPIO_MASK 0x0198
#define R128_MDGPIO_Y_REG 0x01b4
#define R128_MEM_ADDR_CONFIG 0x0148
#define R128_MEM_BASE 0x0f10 /* PCI */
#define R128_MEM_CNTL 0x0140
#define R128_MEM_INIT_LAT_TIMER 0x0154
#define R128_MEM_INTF_CNTL 0x014c
#define R128_MEM_SDRAM_MODE_REG 0x0158
#define R128_MEM_STR_CNTL 0x0150
#define R128_MEM_VGA_RP_SEL 0x003c
#define R128_MEM_VGA_WP_SEL 0x0038
#define R128_MIN_GRANT 0x0f3e /* PCI */
#define R128_MM_DATA 0x0004
#define R128_MM_INDEX 0x0000
#define R128_MPLL_CNTL 0x000e /* PLL */
#define R128_MPP_TB_CONFIG 0x01c0 /* ? */
#define R128_MPP_GP_CONFIG 0x01c8 /* ? */
 
#define R128_N_VIF_COUNT 0x0248
 
#define R128_OVR_CLR 0x0230
#define R128_OVR_WID_LEFT_RIGHT 0x0234
#define R128_OVR_WID_TOP_BOTTOM 0x0238
 
/* first overlay unit (there is only one) */
 
#define R128_OV0_Y_X_START 0x0400
#define R128_OV0_Y_X_END 0x0404
#define R128_OV0_EXCLUSIVE_HORZ 0x0408
# define R128_EXCL_HORZ_START_MASK 0x000000ff
# define R128_EXCL_HORZ_END_MASK 0x0000ff00
# define R128_EXCL_HORZ_BACK_PORCH_MASK 0x00ff0000
# define R128_EXCL_HORZ_EXCLUSIVE_EN 0x80000000
#define R128_OV0_EXCLUSIVE_VERT 0x040C
# define R128_EXCL_VERT_START_MASK 0x000003ff
# define R128_EXCL_VERT_END_MASK 0x03ff0000
#define R128_OV0_REG_LOAD_CNTL 0x0410
# define R128_REG_LD_CTL_LOCK 0x00000001L
# define R128_REG_LD_CTL_VBLANK_DURING_LOCK 0x00000002L
# define R128_REG_LD_CTL_STALL_GUI_UNTIL_FLIP 0x00000004L
# define R128_REG_LD_CTL_LOCK_READBACK 0x00000008L
#define R128_OV0_SCALE_CNTL 0x0420
# define R128_SCALER_PIX_EXPAND 0x00000001L
# define R128_SCALER_Y2R_TEMP 0x00000002L
# define R128_SCALER_HORZ_PICK_NEAREST 0x00000003L
# define R128_SCALER_VERT_PICK_NEAREST 0x00000004L
# define R128_SCALER_SIGNED_UV 0x00000010L
# define R128_SCALER_GAMMA_SEL_MASK 0x00000060L
# define R128_SCALER_GAMMA_SEL_BRIGHT 0x00000000L
# define R128_SCALER_GAMMA_SEL_G22 0x00000020L
# define R128_SCALER_GAMMA_SEL_G18 0x00000040L
# define R128_SCALER_GAMMA_SEL_G14 0x00000060L
# define R128_SCALER_COMCORE_SHIFT_UP_ONE 0x00000080L
# define R128_SCALER_SURFAC_FORMAT 0x00000f00L
# define R128_SCALER_SOURCE_15BPP 0x00000300L
# define R128_SCALER_SOURCE_16BPP 0x00000400L
# define R128_SCALER_SOURCE_32BPP 0x00000600L
# define R128_SCALER_SOURCE_YUV9 0x00000900L
# define R128_SCALER_SOURCE_YUV12 0x00000A00L
# define R128_SCALER_SOURCE_VYUY422 0x00000B00L
# define R128_SCALER_SOURCE_YVYU422 0x00000C00L
# define R128_SCALER_SMART_SWITCH 0x00008000L
# define R128_SCALER_BURST_PER_PLANE 0x00ff0000L
# define R128_SCALER_DOUBLE_BUFFER 0x01000000L
# define R128_SCALER_DIS_LIMIT 0x08000000L
# define R128_SCALER_PRG_LOAD_START 0x10000000L
# define R128_SCALER_INT_EMU 0x20000000L
# define R128_SCALER_ENABLE 0x40000000L
# define R128_SCALER_SOFT_RESET 0x80000000L
#define R128_OV0_V_INC 0x0424
#define R128_OV0_P1_V_ACCUM_INIT 0x0428
# define R128_OV0_P1_MAX_LN_IN_PER_LN_OUT 0x00000003L
# define R128_OV0_P1_V_ACCUM_INIT_MASK 0x01ff8000L
#define R128_OV0_P23_V_ACCUM_INIT 0x042C
#define R128_OV0_P1_BLANK_LINES_AT_TOP 0x0430
# define R128_P1_BLNK_LN_AT_TOP_M1_MASK 0x00000fffL
# define R128_P1_ACTIVE_LINES_M1 0x0fff0000L
#define R128_OV0_P23_BLANK_LINES_AT_TOP 0x0434
# define R128_P23_BLNK_LN_AT_TOP_M1_MASK 0x000007ffL
# define R128_P23_ACTIVE_LINES_M1 0x07ff0000L
#define R128_OV0_VID_BUF0_BASE_ADRS 0x0440
# define R128_VIF_BUF0_PITCH_SEL 0x00000001L
# define R128_VIF_BUF0_TILE_ADRS 0x00000002L
# define R128_VIF_BUF0_BASE_ADRS_MASK 0x03fffff0L
# define R128_VIF_BUF0_1ST_LINE_LSBS_MASK 0x48000000L
#define R128_OV0_VID_BUF1_BASE_ADRS 0x0444
# define R128_VIF_BUF1_PITCH_SEL 0x00000001L
# define R128_VIF_BUF1_TILE_ADRS 0x00000002L
# define R128_VIF_BUF1_BASE_ADRS_MASK 0x03fffff0L
# define R128_VIF_BUF1_1ST_LINE_LSBS_MASK 0x48000000L
#define R128_OV0_VID_BUF2_BASE_ADRS 0x0448
# define R128_VIF_BUF2_PITCH_SEL 0x00000001L
# define R128_VIF_BUF2_TILE_ADRS 0x00000002L
# define R128_VIF_BUF2_BASE_ADRS_MASK 0x03fffff0L
# define R128_VIF_BUF2_1ST_LINE_LSBS_MASK 0x48000000L
#define R128_OV0_VID_BUF3_BASE_ADRS 0x044C
#define R128_OV0_VID_BUF4_BASE_ADRS 0x0450
#define R128_OV0_VID_BUF5_BASE_ADRS 0x0454
#define R128_OV0_VID_BUF_PITCH0_VALUE 0x0460
#define R128_OV0_VID_BUF_PITCH1_VALUE 0x0464
#define R128_OV0_AUTO_FLIP_CNTL 0x0470
#define R128_OV0_DEINTERLACE_PATTERN 0x0474
#define R128_OV0_H_INC 0x0480
#define R128_OV0_STEP_BY 0x0484
#define R128_OV0_P1_H_ACCUM_INIT 0x0488
#define R128_OV0_P23_H_ACCUM_INIT 0x048C
#define R128_OV0_P1_X_START_END 0x0494
#define R128_OV0_P2_X_START_END 0x0498
#define R128_OV0_P3_X_START_END 0x049C
#define R128_OV0_FILTER_CNTL 0x04A0
#define R128_OV0_FOUR_TAP_COEF_0 0x04B0
#define R128_OV0_FOUR_TAP_COEF_1 0x04B4
#define R128_OV0_FOUR_TAP_COEF_2 0x04B8
#define R128_OV0_FOUR_TAP_COEF_3 0x04BC
#define R128_OV0_FOUR_TAP_COEF_4 0x04C0
#define R128_OV0_COLOUR_CNTL 0x04E0
#define R128_OV0_VIDEO_KEY_CLR 0x04E4
#define R128_OV0_VIDEO_KEY_MSK 0x04E8
#define R128_OV0_GRAPHICS_KEY_CLR 0x04EC
#define R128_OV0_GRAPHICS_KEY_MSK 0x04F0
#define R128_OV0_KEY_CNTL 0x04F4
# define R128_VIDEO_KEY_FN_MASK 0x00000007L
# define R128_VIDEO_KEY_FN_FALSE 0x00000000L
# define R128_VIDEO_KEY_FN_TRUE 0x00000001L
# define R128_VIDEO_KEY_FN_EQ 0x00000004L
# define R128_VIDEO_KEY_FN_NE 0x00000005L
# define R128_GRAPHIC_KEY_FN_MASK 0x00000070L
# define R128_GRAPHIC_KEY_FN_FALSE 0x00000000L
# define R128_GRAPHIC_KEY_FN_TRUE 0x00000010L
# define R128_GRAPHIC_KEY_FN_EQ 0x00000040L
# define R128_GRAPHIC_KEY_FN_NE 0x00000050L
# define R128_CMP_MIX_MASK 0x00000100L
# define R128_CMP_MIX_OR 0x00000000L
# define R128_CMP_MIX_AND 0x00000100L
#define R128_OV0_TEST 0x04F8
 
 
#define R128_PALETTE_DATA 0x00b4
#define R128_PALETTE_INDEX 0x00b0
#define R128_PC_DEBUG_MODE 0x1760
#define R128_PC_GUI_CTLSTAT 0x1748
#define R128_PC_GUI_MODE 0x1744
# define R128_PC_IGNORE_UNIFY (1 << 5)
#define R128_PC_MISC_CNTL 0x0188
#define R128_PC_NGUI_CTLSTAT 0x0184
# define R128_PC_FLUSH_GUI (3 << 0)
# define R128_PC_RI_GUI (1 << 2)
# define R128_PC_FLUSH_ALL 0x00ff
# define R128_PC_BUSY (1 << 31)
#define R128_PC_NGUI_MODE 0x0180
#define R128_PCI_GART_PAGE 0x017c
#define R128_PLANE_3D_MASK_C 0x1d44
#define R128_PLL_TEST_CNTL 0x0013 /* PLL */
#define R128_PMI_CAP_ID 0x0f5c /* PCI */
#define R128_PMI_DATA 0x0f63 /* PCI */
#define R128_PMI_NXT_CAP_PTR 0x0f5d /* PCI */
#define R128_PMI_PMC_REG 0x0f5e /* PCI */
#define R128_PMI_PMCSR_REG 0x0f60 /* PCI */
#define R128_PMI_REGISTER 0x0f5c /* PCI */
#define R128_PPLL_CNTL 0x0002 /* PLL */
# define R128_PPLL_RESET (1 << 0)
# define R128_PPLL_SLEEP (1 << 1)
# define R128_PPLL_ATOMIC_UPDATE_EN (1 << 16)
# define R128_PPLL_VGA_ATOMIC_UPDATE_EN (1 << 17)
#define R128_PPLL_DIV_0 0x0004 /* PLL */
#define R128_PPLL_DIV_1 0x0005 /* PLL */
#define R128_PPLL_DIV_2 0x0006 /* PLL */
#define R128_PPLL_DIV_3 0x0007 /* PLL */
# define R128_PPLL_FB3_DIV_MASK 0x07ff
# define R128_PPLL_POST3_DIV_MASK 0x00070000
#define R128_PPLL_REF_DIV 0x0003 /* PLL */
# define R128_PPLL_REF_DIV_MASK 0x03ff
# define R128_PPLL_ATOMIC_UPDATE_R (1 << 15) /* same as _W */
# define R128_PPLL_ATOMIC_UPDATE_W (1 << 15) /* same as _R */
#define R128_PWR_MNGMT_CNTL_STATUS 0x0f60 /* PCI */
#define R128_REG_BASE 0x0f18 /* PCI */
#define R128_REGPROG_INF 0x0f09 /* PCI */
#define R128_REVISION_ID 0x0f08 /* PCI */
 
#define R128_SC_BOTTOM 0x164c
#define R128_SC_BOTTOM_RIGHT 0x16f0
#define R128_SC_BOTTOM_RIGHT_C 0x1c8c
#define R128_SC_LEFT 0x1640
#define R128_SC_RIGHT 0x1644
#define R128_SC_TOP 0x1648
#define R128_SC_TOP_LEFT 0x16ec
#define R128_SC_TOP_LEFT_C 0x1c88
#define R128_SEQ8_DATA 0x03c5 /* VGA */
#define R128_SEQ8_IDX 0x03c4 /* VGA */
#define R128_SNAPSHOT_F_COUNT 0x0244
#define R128_SNAPSHOT_VH_COUNTS 0x0240
#define R128_SNAPSHOT_VIF_COUNT 0x024c
#define R128_SRC_OFFSET 0x15ac
#define R128_SRC_PITCH 0x15b0
#define R128_SRC_PITCH_OFFSET 0x1428
#define R128_SRC_SC_BOTTOM 0x165c
#define R128_SRC_SC_BOTTOM_RIGHT 0x16f4
#define R128_SRC_SC_RIGHT 0x1654
#define R128_SRC_X 0x1414
#define R128_SRC_X_Y 0x1590
#define R128_SRC_Y 0x1418
#define R128_SRC_Y_X 0x1434
#define R128_STATUS 0x0f06 /* PCI */
#define R128_SUBPIC_CNTL 0x0540 /* ? */
#define R128_SUB_CLASS 0x0f0a /* PCI */
#define R128_SURFACE_DELAY 0x0b00
#define R128_SURFACE0_INFO 0x0b0c
#define R128_SURFACE0_LOWER_BOUND 0x0b04
#define R128_SURFACE0_UPPER_BOUND 0x0b08
#define R128_SURFACE1_INFO 0x0b1c
#define R128_SURFACE1_LOWER_BOUND 0x0b14
#define R128_SURFACE1_UPPER_BOUND 0x0b18
#define R128_SURFACE2_INFO 0x0b2c
#define R128_SURFACE2_LOWER_BOUND 0x0b24
#define R128_SURFACE2_UPPER_BOUND 0x0b28
#define R128_SURFACE3_INFO 0x0b3c
#define R128_SURFACE3_LOWER_BOUND 0x0b34
#define R128_SURFACE3_UPPER_BOUND 0x0b38
#define R128_SW_SEMAPHORE 0x013c
 
#define R128_TEST_DEBUG_CNTL 0x0120
#define R128_TEST_DEBUG_MUX 0x0124
#define R128_TEST_DEBUG_OUT 0x012c
#define R128_TMDS_CRC 0x02a0
#define R128_TRAIL_BRES_DEC 0x1614
#define R128_TRAIL_BRES_ERR 0x160c
#define R128_TRAIL_BRES_INC 0x1610
#define R128_TRAIL_X 0x1618
#define R128_TRAIL_X_SUB 0x1620
 
#define R128_VCLK_ECP_CNTL 0x0008 /* PLL */
#define R128_VENDOR_ID 0x0f00 /* PCI */
#define R128_VGA_DDA_CONFIG 0x02e8
#define R128_VGA_DDA_ON_OFF 0x02ec
#define R128_VID_BUFFER_CONTROL 0x0900
#define R128_VIDEOMUX_CNTL 0x0190
#define R128_VIPH_CONTROL 0x01D0 /* ? */
 
#define R128_WAIT_UNTIL 0x1720
 
#define R128_X_MPLL_REF_FB_DIV 0x000a /* PLL */
#define R128_XCLK_CNTL 0x000d /* PLL */
#define R128_XDLL_CNTL 0x000c /* PLL */
#define R128_XPLL_CNTL 0x000b /* PLL */
 
/* Registers for CCE and Microcode Engine */
#define R128_PM4_MICROCODE_ADDR 0x07d4
#define R128_PM4_MICROCODE_RADDR 0x07d8
#define R128_PM4_MICROCODE_DATAH 0x07dc
#define R128_PM4_MICROCODE_DATAL 0x07e0
 
#define R128_PM4_BUFFER_OFFSET 0x0700
#define R128_PM4_BUFFER_CNTL 0x0704
# define R128_PM4_NONPM4 (0 << 28)
# define R128_PM4_192PIO (1 << 28)
# define R128_PM4_192BM (2 << 28)
# define R128_PM4_128PIO_64INDBM (3 << 28)
# define R128_PM4_128BM_64INDBM (4 << 28)
# define R128_PM4_64PIO_128INDBM (5 << 28)
# define R128_PM4_64BM_128INDBM (6 << 28)
# define R128_PM4_64PIO_64VCBM_64INDBM (7 << 28)
# define R128_PM4_64BM_64VCBM_64INDBM (8 << 28)
# define R128_PM4_64PIO_64VCPIO_64INDPIO (15 << 28)
#define R128_PM4_BUFFER_WM_CNTL 0x0708
# define R128_WMA_SHIFT 0
# define R128_WMB_SHIFT 8
# define R128_WMC_SHIFT 16
# define R128_WB_WM_SHIFT 24
#define R128_PM4_BUFFER_DL_RPTR_ADDR 0x070c
#define R128_PM4_BUFFER_DL_RPTR 0x0710
#define R128_PM4_BUFFER_DL_WPTR 0x0714
# define R128_PM4_BUFFER_DL_DONE (1 << 31)
#define R128_PM4_BUFFER_DL_WPTR_DELAY 0x0718
# define R128_PRE_WRITE_TIMER_SHIFT 0
# define R128_PRE_WRITE_LIMIT_SHIFT 23
#define R128_PM4_VC_FPU_SETUP 0x071c
# define R128_FRONT_DIR_CW (0 << 0)
# define R128_FRONT_DIR_CCW (1 << 0)
# define R128_FRONT_DIR_MASK (1 << 0)
# define R128_BACKFACE_CULL (0 << 1)
# define R128_BACKFACE_POINTS (1 << 1)
# define R128_BACKFACE_LINES (2 << 1)
# define R128_BACKFACE_SOLID (3 << 1)
# define R128_BACKFACE_MASK (3 << 1)
# define R128_FRONTFACE_CULL (0 << 3)
# define R128_FRONTFACE_POINTS (1 << 3)
# define R128_FRONTFACE_LINES (2 << 3)
# define R128_FRONTFACE_SOLID (3 << 3)
# define R128_FRONTFACE_MASK (3 << 3)
# define R128_FPU_COLOR_SOLID (0 << 5)
# define R128_FPU_COLOR_FLAT (1 << 5)
# define R128_FPU_COLOR_GOURAUD (2 << 5)
# define R128_FPU_COLOR_GOURAUD2 (3 << 5)
# define R128_FPU_COLOR_MASK (3 << 5)
# define R128_FPU_SUB_PIX_2BITS (0 << 7)
# define R128_FPU_SUB_PIX_4BITS (1 << 7)
# define R128_FPU_MODE_2D (0 << 8)
# define R128_FPU_MODE_3D (1 << 8)
# define R128_TRAP_BITS_DISABLE (1 << 9)
# define R128_EDGE_ANTIALIAS (1 << 10)
# define R128_SUPERSAMPLE (1 << 11)
# define R128_XFACTOR_2 (0 << 12)
# define R128_XFACTOR_4 (1 << 12)
# define R128_YFACTOR_2 (0 << 13)
# define R128_YFACTOR_4 (1 << 13)
# define R128_FLAT_SHADE_VERTEX_D3D (0 << 14)
# define R128_FLAT_SHADE_VERTEX_OGL (1 << 14)
# define R128_FPU_ROUND_TRUNCATE (0 << 15)
# define R128_FPU_ROUND_NEAREST (1 << 15)
# define R128_WM_SEL_8DW (0 << 16)
# define R128_WM_SEL_16DW (1 << 16)
# define R128_WM_SEL_32DW (2 << 16)
#define R128_PM4_VC_DEBUG_CONFIG 0x07a4
#define R128_PM4_VC_STAT 0x07a8
#define R128_PM4_VC_TIMESTAMP0 0x07b0
#define R128_PM4_VC_TIMESTAMP1 0x07b4
#define R128_PM4_STAT 0x07b8
# define R128_PM4_FIFOCNT_MASK 0x0fff
# define R128_PM4_BUSY (1 << 16)
# define R128_PM4_GUI_ACTIVE (1 << 31)
#define R128_PM4_BUFFER_ADDR 0x07f0
#define R128_PM4_MICRO_CNTL 0x07fc
# define R128_PM4_MICRO_FREERUN (1 << 30)
#define R128_PM4_FIFO_DATA_EVEN 0x1000
#define R128_PM4_FIFO_DATA_ODD 0x1004
 
#define R128_SCALE_3D_CNTL 0x1a00
# define R128_SCALE_DITHER_ERR_DIFF (0 << 1)
# define R128_SCALE_DITHER_TABLE (1 << 1)
# define R128_TEX_CACHE_SIZE_FULL (0 << 2)
# define R128_TEX_CACHE_SIZE_HALF (1 << 2)
# define R128_DITHER_INIT_CURR (0 << 3)
# define R128_DITHER_INIT_RESET (1 << 3)
# define R128_ROUND_24BIT (1 << 4)
# define R128_TEX_CACHE_DISABLE (1 << 5)
# define R128_SCALE_3D_NOOP (0 << 6)
# define R128_SCALE_3D_SCALE (1 << 6)
# define R128_SCALE_3D_TEXMAP_SHADE (2 << 6)
# define R128_SCALE_PIX_BLEND (0 << 8)
# define R128_SCALE_PIX_REPLICATE (1 << 8)
# define R128_TEX_CACHE_SPLIT (1 << 9)
# define R128_APPLE_YUV_MODE (1 << 10)
# define R128_TEX_CACHE_PALLETE_MODE (1 << 11)
# define R128_ALPHA_COMB_ADD_CLAMP (0 << 12)
# define R128_ALPHA_COMB_ADD_NCLAMP (1 << 12)
# define R128_ALPHA_COMB_SUB_DST_SRC_CLAMP (2 << 12)
# define R128_ALPHA_COMB_SUB_DST_SRC_NCLAMP (3 << 12)
# define R128_FOG_TABLE (1 << 14)
# define R128_SIGNED_DST_CLAMP (1 << 15)
# define R128_ALPHA_BLEND_SRC_ZERO (0 << 16)
# define R128_ALPHA_BLEND_SRC_ONE (1 << 16)
# define R128_ALPHA_BLEND_SRC_SRCCOLOR (2 << 16)
# define R128_ALPHA_BLEND_SRC_INVSRCCOLOR (3 << 16)
# define R128_ALPHA_BLEND_SRC_SRCALPHA (4 << 16)
# define R128_ALPHA_BLEND_SRC_INVSRCALPHA (5 << 16)
# define R128_ALPHA_BLEND_SRC_DSTALPHA (6 << 16)
# define R128_ALPHA_BLEND_SRC_INVDSTALPHA (7 << 16)
# define R128_ALPHA_BLEND_SRC_DSTCOLOR (8 << 16)
# define R128_ALPHA_BLEND_SRC_INVDSTCOLOR (9 << 16)
# define R128_ALPHA_BLEND_SRC_SAT (10 << 16)
# define R128_ALPHA_BLEND_SRC_BLEND (11 << 16)
# define R128_ALPHA_BLEND_SRC_INVBLEND (12 << 16)
# define R128_ALPHA_BLEND_DST_ZERO (0 << 20)
# define R128_ALPHA_BLEND_DST_ONE (1 << 20)
# define R128_ALPHA_BLEND_DST_SRCCOLOR (2 << 20)
# define R128_ALPHA_BLEND_DST_INVSRCCOLOR (3 << 20)
# define R128_ALPHA_BLEND_DST_SRCALPHA (4 << 20)
# define R128_ALPHA_BLEND_DST_INVSRCALPHA (5 << 20)
# define R128_ALPHA_BLEND_DST_DSTALPHA (6 << 20)
# define R128_ALPHA_BLEND_DST_INVDSTALPHA (7 << 20)
# define R128_ALPHA_BLEND_DST_DSTCOLOR (8 << 20)
# define R128_ALPHA_BLEND_DST_INVDSTCOLOR (9 << 20)
# define R128_ALPHA_TEST_NEVER (0 << 24)
# define R128_ALPHA_TEST_LESS (1 << 24)
# define R128_ALPHA_TEST_LESSEQUAL (2 << 24)
# define R128_ALPHA_TEST_EQUAL (3 << 24)
# define R128_ALPHA_TEST_GREATEREQUAL (4 << 24)
# define R128_ALPHA_TEST_GREATER (5 << 24)
# define R128_ALPHA_TEST_NEQUAL (6 << 24)
# define R128_ALPHA_TEST_ALWAYS (7 << 24)
# define R128_COMPOSITE_SHADOW_CMP_EQUAL (0 << 28)
# define R128_COMPOSITE_SHADOW_CMP_NEQUAL (1 << 28)
# define R128_COMPOSITE_SHADOW (1 << 29)
# define R128_TEX_MAP_ALPHA_IN_TEXTURE (1 << 30)
# define R128_TEX_CACHE_LINE_SIZE_8QW (0 << 31)
# define R128_TEX_CACHE_LINE_SIZE_4QW (1 << 31)
#define R128_SCALE_3D_DATATYPE 0x1a20
 
#define R128_SETUP_CNTL 0x1bc4
# define R128_DONT_START_TRIANGLE (1 << 0)
# define R128_Z_BIAS (0 << 1)
# define R128_DONT_START_ANY_ON (1 << 2)
# define R128_COLOR_SOLID_COLOR (0 << 3)
# define R128_COLOR_FLAT_VERT_1 (1 << 3)
# define R128_COLOR_FLAT_VERT_2 (2 << 3)
# define R128_COLOR_FLAT_VERT_3 (3 << 3)
# define R128_COLOR_GOURAUD (4 << 3)
# define R128_PRIM_TYPE_TRI (0 << 7)
# define R128_PRIM_TYPE_LINE (1 << 7)
# define R128_PRIM_TYPE_POINT (2 << 7)
# define R128_PRIM_TYPE_POLY_EDGE (3 << 7)
# define R128_TEXTURE_ST_MULT_W (0 << 9)
# define R128_TEXTURE_ST_DIRECT (1 << 9)
# define R128_STARTING_VERTEX_1 (1 << 14)
# define R128_STARTING_VERTEX_2 (2 << 14)
# define R128_STARTING_VERTEX_3 (3 << 14)
# define R128_ENDING_VERTEX_1 (1 << 16)
# define R128_ENDING_VERTEX_2 (2 << 16)
# define R128_ENDING_VERTEX_3 (3 << 16)
# define R128_SU_POLY_LINE_LAST (0 << 18)
# define R128_SU_POLY_LINE_NOT_LAST (1 << 18)
# define R128_SUB_PIX_2BITS (0 << 19)
# define R128_SUB_PIX_4BITS (1 << 19)
# define R128_SET_UP_CONTINUE (1 << 31)
 
#define R128_WINDOW_XY_OFFSET 0x1bcc
# define R128_WINDOW_Y_SHIFT 4
# define R128_WINDOW_X_SHIFT 20
 
#define R128_Z_OFFSET_C 0x1c90
#define R128_Z_PITCH_C 0x1c94
# define R128_Z_TILE (1 << 16)
#define R128_Z_STEN_CNTL_C 0x1c98
# define R128_Z_PIX_WIDTH_16 (0 << 1)
# define R128_Z_PIX_WIDTH_24 (1 << 1)
# define R128_Z_PIX_WIDTH_32 (2 << 1)
# define R128_Z_PIX_WIDTH_MASK (3 << 1)
# define R128_Z_TEST_NEVER (0 << 4)
# define R128_Z_TEST_LESS (1 << 4)
# define R128_Z_TEST_LESSEQUAL (2 << 4)
# define R128_Z_TEST_EQUAL (3 << 4)
# define R128_Z_TEST_GREATEREQUAL (4 << 4)
# define R128_Z_TEST_GREATER (5 << 4)
# define R128_Z_TEST_NEQUAL (6 << 4)
# define R128_Z_TEST_ALWAYS (7 << 4)
# define R128_Z_TEST_MASK (7 << 4)
# define R128_STENCIL_TEST_NEVER (0 << 12)
# define R128_STENCIL_TEST_LESS (1 << 12)
# define R128_STENCIL_TEST_LESSEQUAL (2 << 12)
# define R128_STENCIL_TEST_EQUAL (3 << 12)
# define R128_STENCIL_TEST_GREATEREQUAL (4 << 12)
# define R128_STENCIL_TEST_GREATER (5 << 12)
# define R128_STENCIL_TEST_NEQUAL (6 << 12)
# define R128_STENCIL_TEST_ALWAYS (7 << 12)
# define R128_STENCIL_S_FAIL_KEEP (0 << 16)
# define R128_STENCIL_S_FAIL_ZERO (1 << 16)
# define R128_STENCIL_S_FAIL_REPLACE (2 << 16)
# define R128_STENCIL_S_FAIL_INC (3 << 16)
# define R128_STENCIL_S_FAIL_DEC (4 << 16)
# define R128_STENCIL_S_FAIL_INV (5 << 16)
# define R128_STENCIL_ZPASS_KEEP (0 << 20)
# define R128_STENCIL_ZPASS_ZERO (1 << 20)
# define R128_STENCIL_ZPASS_REPLACE (2 << 20)
# define R128_STENCIL_ZPASS_INC (3 << 20)
# define R128_STENCIL_ZPASS_DEC (4 << 20)
# define R128_STENCIL_ZPASS_INV (5 << 20)
# define R128_STENCIL_ZFAIL_KEEP (0 << 24)
# define R128_STENCIL_ZFAIL_ZERO (1 << 24)
# define R128_STENCIL_ZFAIL_REPLACE (2 << 24)
# define R128_STENCIL_ZFAIL_INC (3 << 24)
# define R128_STENCIL_ZFAIL_DEC (4 << 24)
# define R128_STENCIL_ZFAIL_INV (5 << 24)
#define R128_TEX_CNTL_C 0x1c9c
# define R128_Z_ENABLE (1 << 0)
# define R128_Z_WRITE_ENABLE (1 << 1)
# define R128_STENCIL_ENABLE (1 << 3)
# define R128_SHADE_ENABLE (0 << 4)
# define R128_TEXMAP_ENABLE (1 << 4)
# define R128_SEC_TEXMAP_ENABLE (1 << 5)
# define R128_FOG_ENABLE (1 << 7)
# define R128_DITHER_ENABLE (1 << 8)
# define R128_ALPHA_ENABLE (1 << 9)
# define R128_ALPHA_TEST_ENABLE (1 << 10)
# define R128_SPEC_LIGHT_ENABLE (1 << 11)
# define R128_TEX_CHROMA_KEY_ENABLE (1 << 12)
# define R128_ALPHA_IN_TEX_COMPLETE_A (0 << 13)
# define R128_ALPHA_IN_TEX_LSB_A (1 << 13)
# define R128_LIGHT_DIS (0 << 14)
# define R128_LIGHT_COPY (1 << 14)
# define R128_LIGHT_MODULATE (2 << 14)
# define R128_LIGHT_ADD (3 << 14)
# define R128_LIGHT_BLEND_CONSTANT (4 << 14)
# define R128_LIGHT_BLEND_TEXTURE (5 << 14)
# define R128_LIGHT_BLEND_VERTEX (6 << 14)
# define R128_LIGHT_BLEND_CONST_COLOR (7 << 14)
# define R128_ALPHA_LIGHT_DIS (0 << 18)
# define R128_ALPHA_LIGHT_COPY (1 << 18)
# define R128_ALPHA_LIGHT_MODULATE (2 << 18)
# define R128_ALPHA_LIGHT_ADD (3 << 18)
# define R128_ANTI_ALIAS (1 << 21)
# define R128_TEX_CACHE_FLUSH (1 << 23)
# define R128_LOD_BIAS_SHIFT 24
# define R128_LOD_BIAS_MASK (0xff << 24)
#define R128_MISC_3D_STATE_CNTL_REG 0x1ca0
# define R128_REF_ALPHA_MASK 0xff
# define R128_MISC_SCALE_3D_NOOP (0 << 8)
# define R128_MISC_SCALE_3D_SCALE (1 << 8)
# define R128_MISC_SCALE_3D_TEXMAP_SHADE (2 << 8)
# define R128_MISC_SCALE_PIX_BLEND (0 << 10)
# define R128_MISC_SCALE_PIX_REPLICATE (1 << 10)
# define R128_ALPHA_COMB_ADD_CLAMP (0 << 12)
# define R128_ALPHA_COMB_ADD_NO_CLAMP (1 << 12)
# define R128_ALPHA_COMB_SUB_SRC_DST_CLAMP (2 << 12)
# define R128_ALPHA_COMB_SUB_SRC_DST_NO_CLAMP (3 << 12)
# define R128_FOG_VERTEX (0 << 14)
# define R128_FOG_TABLE (1 << 14)
# define R128_ALPHA_BLEND_SRC_ZERO (0 << 16)
# define R128_ALPHA_BLEND_SRC_ONE (1 << 16)
# define R128_ALPHA_BLEND_SRC_SRCCOLOR (2 << 16)
# define R128_ALPHA_BLEND_SRC_INVSRCCOLOR (3 << 16)
# define R128_ALPHA_BLEND_SRC_SRCALPHA (4 << 16)
# define R128_ALPHA_BLEND_SRC_INVSRCALPHA (5 << 16)
# define R128_ALPHA_BLEND_SRC_DESTALPHA (6 << 16)
# define R128_ALPHA_BLEND_SRC_INVDESTALPHA (7 << 16)
# define R128_ALPHA_BLEND_SRC_DESTCOLOR (8 << 16)
# define R128_ALPHA_BLEND_SRC_INVDESTCOLOR (9 << 16)
# define R128_ALPHA_BLEND_SRC_SRCALPHASAT (10 << 16)
# define R128_ALPHA_BLEND_SRC_BOTHSRCALPHA (11 << 16)
# define R128_ALPHA_BLEND_SRC_BOTHINVSRCALPHA (12 << 16)
# define R128_ALPHA_BLEND_SRC_MASK (15 << 16)
# define R128_ALPHA_BLEND_DST_ZERO (0 << 20)
# define R128_ALPHA_BLEND_DST_ONE (1 << 20)
# define R128_ALPHA_BLEND_DST_SRCCOLOR (2 << 20)
# define R128_ALPHA_BLEND_DST_INVSRCCOLOR (3 << 20)
# define R128_ALPHA_BLEND_DST_SRCALPHA (4 << 20)
# define R128_ALPHA_BLEND_DST_INVSRCALPHA (5 << 20)
# define R128_ALPHA_BLEND_DST_DESTALPHA (6 << 20)
# define R128_ALPHA_BLEND_DST_INVDESTALPHA (7 << 20)
# define R128_ALPHA_BLEND_DST_DESTCOLOR (8 << 20)
# define R128_ALPHA_BLEND_DST_INVDESTCOLOR (9 << 20)
# define R128_ALPHA_BLEND_DST_SRCALPHASAT (10 << 20)
# define R128_ALPHA_BLEND_DST_MASK (15 << 20)
# define R128_ALPHA_TEST_NEVER (0 << 24)
# define R128_ALPHA_TEST_LESS (1 << 24)
# define R128_ALPHA_TEST_LESSEQUAL (2 << 24)
# define R128_ALPHA_TEST_EQUAL (3 << 24)
# define R128_ALPHA_TEST_GREATEREQUAL (4 << 24)
# define R128_ALPHA_TEST_GREATER (5 << 24)
# define R128_ALPHA_TEST_NEQUAL (6 << 24)
# define R128_ALPHA_TEST_ALWAYS (7 << 24)
# define R128_ALPHA_TEST_MASK (7 << 24)
#define R128_TEXTURE_CLR_CMP_CLR_C 0x1ca4
#define R128_TEXTURE_CLR_CMP_MSK_C 0x1ca8
#define R128_FOG_COLOR_C 0x1cac
# define R128_FOG_BLUE_SHIFT 0
# define R128_FOG_GREEN_SHIFT 8
# define R128_FOG_RED_SHIFT 16
#define R128_PRIM_TEX_CNTL_C 0x1cb0
# define R128_MIN_BLEND_NEAREST (0 << 1)
# define R128_MIN_BLEND_LINEAR (1 << 1)
# define R128_MIN_BLEND_MIPNEAREST (2 << 1)
# define R128_MIN_BLEND_MIPLINEAR (3 << 1)
# define R128_MIN_BLEND_LINEARMIPNEAREST (4 << 1)
# define R128_MIN_BLEND_LINEARMIPLINEAR (5 << 1)
# define R128_MIN_BLEND_MASK (7 << 1)
# define R128_MAG_BLEND_NEAREST (0 << 4)
# define R128_MAG_BLEND_LINEAR (1 << 4)
# define R128_MAG_BLEND_MASK (7 << 4)
# define R128_MIP_MAP_DISABLE (1 << 7)
# define R128_TEX_CLAMP_S_WRAP (0 << 8)
# define R128_TEX_CLAMP_S_MIRROR (1 << 8)
# define R128_TEX_CLAMP_S_CLAMP (2 << 8)
# define R128_TEX_CLAMP_S_BORDER_COLOR (3 << 8)
# define R128_TEX_CLAMP_S_MASK (3 << 8)
# define R128_TEX_WRAP_S (1 << 10)
# define R128_TEX_CLAMP_T_WRAP (0 << 11)
# define R128_TEX_CLAMP_T_MIRROR (1 << 11)
# define R128_TEX_CLAMP_T_CLAMP (2 << 11)
# define R128_TEX_CLAMP_T_BORDER_COLOR (3 << 11)
# define R128_TEX_CLAMP_T_MASK (3 << 11)
# define R128_TEX_WRAP_T (1 << 13)
# define R128_TEX_PERSPECTIVE_DISABLE (1 << 14)
# define R128_DATATYPE_VQ (0 << 16)
# define R128_DATATYPE_CI4 (1 << 16)
# define R128_DATATYPE_CI8 (2 << 16)
# define R128_DATATYPE_ARGB1555 (3 << 16)
# define R128_DATATYPE_RGB565 (4 << 16)
# define R128_DATATYPE_RGB888 (5 << 16)
# define R128_DATATYPE_ARGB8888 (6 << 16)
# define R128_DATATYPE_RGB332 (7 << 16)
# define R128_DATATYPE_Y8 (8 << 16)
# define R128_DATATYPE_RGB8 (9 << 16)
# define R128_DATATYPE_CI16 (10 << 16)
# define R128_DATATYPE_YUV422 (11 << 16)
# define R128_DATATYPE_YUV422_2 (12 << 16)
# define R128_DATATYPE_AYUV444 (14 << 16)
# define R128_DATATYPE_ARGB4444 (15 << 16)
# define R128_PALLETE_EITHER (0 << 20)
# define R128_PALLETE_1 (1 << 20)
# define R128_PALLETE_2 (2 << 20)
# define R128_PSEUDOCOLOR_DT_RGB565 (0 << 24)
# define R128_PSEUDOCOLOR_DT_ARGB1555 (1 << 24)
# define R128_PSEUDOCOLOR_DT_ARGB4444 (2 << 24)
#define R128_PRIM_TEXTURE_COMBINE_CNTL_C 0x1cb4
# define R128_COMB_DIS (0 << 0)
# define R128_COMB_COPY (1 << 0)
# define R128_COMB_COPY_INP (2 << 0)
# define R128_COMB_MODULATE (3 << 0)
# define R128_COMB_MODULATE2X (4 << 0)
# define R128_COMB_MODULATE4X (5 << 0)
# define R128_COMB_ADD (6 << 0)
# define R128_COMB_ADD_SIGNED (7 << 0)
# define R128_COMB_BLEND_VERTEX (8 << 0)
# define R128_COMB_BLEND_TEXTURE (9 << 0)
# define R128_COMB_BLEND_CONST (10 << 0)
# define R128_COMB_BLEND_PREMULT (11 << 0)
# define R128_COMB_BLEND_PREV (12 << 0)
# define R128_COMB_BLEND_PREMULT_INV (13 << 0)
# define R128_COMB_ADD_SIGNED2X (14 << 0)
# define R128_COMB_BLEND_CONST_COLOR (15 << 0)
# define R128_COMB_MASK (15 << 0)
# define R128_COLOR_FACTOR_TEX (4 << 4)
# define R128_COLOR_FACTOR_NTEX (5 << 4)
# define R128_COLOR_FACTOR_ALPHA (6 << 4)
# define R128_COLOR_FACTOR_NALPHA (7 << 4)
# define R128_COLOR_FACTOR_MASK (15 << 4)
# define R128_INPUT_FACTOR_CONST_COLOR (2 << 10)
# define R128_INPUT_FACTOR_CONST_ALPHA (3 << 10)
# define R128_INPUT_FACTOR_INT_COLOR (4 << 10)
# define R128_INPUT_FACTOR_INT_ALPHA (5 << 10)
# define R128_INPUT_FACTOR_MASK (15 << 10)
# define R128_COMB_ALPHA_DIS (0 << 14)
# define R128_COMB_ALPHA_COPY (1 << 14)
# define R128_COMB_ALPHA_COPY_INP (2 << 14)
# define R128_COMB_ALPHA_MODULATE (3 << 14)
# define R128_COMB_ALPHA_MODULATE2X (4 << 14)
# define R128_COMB_ALPHA_MODULATE4X (5 << 14)
# define R128_COMB_ALPHA_ADD (6 << 14)
# define R128_COMB_ALPHA_ADD_SIGNED (7 << 14)
# define R128_COMB_ALPHA_ADD_SIGNED2X (14 << 14)
# define R128_COMB_ALPHA_MASK (15 << 14)
# define R128_ALPHA_FACTOR_TEX_ALPHA (6 << 18)
# define R128_ALPHA_FACTOR_NTEX_ALPHA (7 << 18)
# define R128_ALPHA_FACTOR_MASK (15 << 18)
# define R128_INP_FACTOR_A_CONST_ALPHA (1 << 25)
# define R128_INP_FACTOR_A_INT_ALPHA (2 << 25)
# define R128_INP_FACTOR_A_MASK (7 << 25)
#define R128_TEX_SIZE_PITCH_C 0x1cb8
# define R128_TEX_PITCH_SHIFT 0
# define R128_TEX_SIZE_SHIFT 4
# define R128_TEX_HEIGHT_SHIFT 8
# define R128_TEX_MIN_SIZE_SHIFT 12
# define R128_SEC_TEX_PITCH_SHIFT 16
# define R128_SEC_TEX_SIZE_SHIFT 20
# define R128_SEC_TEX_HEIGHT_SHIFT 24
# define R128_SEC_TEX_MIN_SIZE_SHIFT 28
# define R128_TEX_PITCH_MASK (0x0f << 0)
# define R128_TEX_SIZE_MASK (0x0f << 4)
# define R128_TEX_HEIGHT_MASK (0x0f << 8)
# define R128_TEX_MIN_SIZE_MASK (0x0f << 12)
# define R128_SEC_TEX_PITCH_MASK (0x0f << 16)
# define R128_SEC_TEX_SIZE_MASK (0x0f << 20)
# define R128_SEC_TEX_HEIGHT_MASK (0x0f << 24)
# define R128_SEC_TEX_MIN_SIZE_MASK (0x0f << 28)
# define R128_TEX_SIZE_PITCH_SHIFT 0
# define R128_SEC_TEX_SIZE_PITCH_SHIFT 16
# define R128_TEX_SIZE_PITCH_MASK (0xffff << 0)
# define R128_SEC_TEX_SIZE_PITCH_MASK (0xffff << 16)
#define R128_PRIM_TEX_0_OFFSET_C 0x1cbc
#define R128_PRIM_TEX_1_OFFSET_C 0x1cc0
#define R128_PRIM_TEX_2_OFFSET_C 0x1cc4
#define R128_PRIM_TEX_3_OFFSET_C 0x1cc8
#define R128_PRIM_TEX_4_OFFSET_C 0x1ccc
#define R128_PRIM_TEX_5_OFFSET_C 0x1cd0
#define R128_PRIM_TEX_6_OFFSET_C 0x1cd4
#define R128_PRIM_TEX_7_OFFSET_C 0x1cd8
#define R128_PRIM_TEX_8_OFFSET_C 0x1cdc
#define R128_PRIM_TEX_9_OFFSET_C 0x1ce0
#define R128_PRIM_TEX_10_OFFSET_C 0x1ce4
# define R128_TEX_NO_TILE (0 << 30)
# define R128_TEX_TILED_BY_HOST (1 << 30)
# define R128_TEX_TILED_BY_STORAGE (2 << 30)
# define R128_TEX_TILED_BY_STORAGE2 (3 << 30)
 
#define R128_SEC_TEX_CNTL_C 0x1d00
# define R128_SEC_SELECT_PRIM_ST (0 << 0)
# define R128_SEC_SELECT_SEC_ST (1 << 0)
#define R128_SEC_TEX_COMBINE_CNTL_C 0x1d04
# define R128_INPUT_FACTOR_PREV_COLOR (8 << 10)
# define R128_INPUT_FACTOR_PREV_ALPHA (9 << 10)
# define R128_INP_FACTOR_A_PREV_ALPHA (4 << 25)
#define R128_SEC_TEX_0_OFFSET_C 0x1d08
#define R128_SEC_TEX_1_OFFSET_C 0x1d0c
#define R128_SEC_TEX_2_OFFSET_C 0x1d10
#define R128_SEC_TEX_3_OFFSET_C 0x1d14
#define R128_SEC_TEX_4_OFFSET_C 0x1d18
#define R128_SEC_TEX_5_OFFSET_C 0x1d1c
#define R128_SEC_TEX_6_OFFSET_C 0x1d20
#define R128_SEC_TEX_7_OFFSET_C 0x1d24
#define R128_SEC_TEX_8_OFFSET_C 0x1d28
#define R128_SEC_TEX_9_OFFSET_C 0x1d2c
#define R128_SEC_TEX_10_OFFSET_C 0x1d30
#define R128_CONSTANT_COLOR_C 0x1d34
# define R128_CONSTANT_BLUE_SHIFT 0
# define R128_CONSTANT_GREEN_SHIFT 8
# define R128_CONSTANT_RED_SHIFT 16
# define R128_CONSTANT_ALPHA_SHIFT 24
#define R128_PRIM_TEXTURE_BORDER_COLOR_C 0x1d38
# define R128_PRIM_TEX_BORDER_BLUE_SHIFT 0
# define R128_PRIM_TEX_BORDER_GREEN_SHIFT 8
# define R128_PRIM_TEX_BORDER_RED_SHIFT 16
# define R128_PRIM_TEX_BORDER_ALPHA_SHIFT 24
#define R128_SEC_TEXTURE_BORDER_COLOR_C 0x1d3c
# define R128_SEC_TEX_BORDER_BLUE_SHIFT 0
# define R128_SEC_TEX_BORDER_GREEN_SHIFT 8
# define R128_SEC_TEX_BORDER_RED_SHIFT 16
# define R128_SEC_TEX_BORDER_ALPHA_SHIFT 24
#define R128_STEN_REF_MASK_C 0x1d40
# define R128_STEN_REFERENCE_SHIFT 0
# define R128_STEN_MASK_SHIFT 16
# define R128_STEN_WRITE_MASK_SHIFT 24
#define R128_PLANE_3D_MASK_C 0x1d44
#define R128_TEX_CACHE_STAT_COUNT 0x1974
 
 
/* Constants */
#define R128_AGP_TEX_OFFSET 0x02000000
 
#define R128_LAST_FRAME_REG R128_GUI_SCRATCH_REG0
 
/* CCE packet types */
#define R128_CCE_PACKET0 0x00000000
#define R128_CCE_PACKET0_ONE_REG_WR 0x00008000
#define R128_CCE_PACKET1 0x40000000
#define R128_CCE_PACKET2 0x80000000
#define R128_CCE_PACKET3 0xC0000000
#define R128_CCE_PACKET3_NOP 0xC0001000
#define R128_CCE_PACKET3_PAINT 0xC0001100
#define R128_CCE_PACKET3_BITBLT 0xC0001200
#define R128_CCE_PACKET3_SMALLTEXT 0xC0001300
#define R128_CCE_PACKET3_HOSTDATA_BLT 0xC0001400
#define R128_CCE_PACKET3_POLYLINE 0xC0001500
#define R128_CCE_PACKET3_SCALING 0xC0001600
#define R128_CCE_PACKET3_TRANS_SCALING 0xC0001700
#define R128_CCE_PACKET3_POLYSCANLINES 0xC0001800
#define R128_CCE_PACKET3_NEXT_CHAR 0xC0001900
#define R128_CCE_PACKET3_PAINT_MULTI 0xC0001A00
#define R128_CCE_PACKET3_BITBLT_MULTI 0xC0001B00
#define R128_CCE_PACKET3_PLY_NEXTSCAN 0xC0001D00
#define R128_CCE_PACKET3_SET_SCISSORS 0xC0001E00
#define R128_CCE_PACKET3_SET_MODE24BPP 0xC0001F00
#define R128_CCE_PACKET3_CNTL_PAINT 0xC0009100
#define R128_CCE_PACKET3_CNTL_BITBLT 0xC0009200
#define R128_CCE_PACKET3_CNTL_SMALLTEXT 0xC0009300
#define R128_CCE_PACKET3_CNTL_HOSTDATA_BLT 0xC0009400
#define R128_CCE_PACKET3_CNTL_POLYLINE 0xC0009500
#define R128_CCE_PACKET3_CNTL_SCALING 0xC0009600
#define R128_CCE_PACKET3_CNTL_TRANS_SCALING 0xC0009700
#define R128_CCE_PACKET3_CNTL_POLYSCANLINES 0xC0009800
#define R128_CCE_PACKET3_CNTL_NEXT_CHAR 0xC0009900
#define R128_CCE_PACKET3_CNTL_PAINT_MULTI 0xC0009A00
#define R128_CCE_PACKET3_CNTL_BITBLT_MULTI 0xC0009B00
#define R128_CCE_PACKET3_CNTL_TRANS_BITBLT 0xC0009C00
#define R128_CCE_PACKET3_3D_SAVE_CONTEXT 0xC0002000
#define R128_CCE_PACKET3_3D_PLAY_CONTEXT 0xC0002100
#define R128_CCE_PACKET3_3D_RNDR_GEN_INDX_PRIM 0xC0002300
#define R128_CCE_PACKET3_3D_RNDR_GEN_PRIM 0xC0002500
#define R128_CCE_PACKET3_LOAD_PALETTE 0xC0002C00
#define R128_CCE_PACKET3_PURGE 0xC0002D00
#define R128_CCE_PACKET3_NEXT_VERTEX_BUNDLE 0xC0002E00
# define R128_CCE_PACKET_MASK 0xC0000000
# define R128_CCE_PACKET_COUNT_MASK 0x3fff0000
# define R128_CCE_PACKET_MAX_DWORDS (1 << 12)
# define R128_CCE_PACKET0_REG_MASK 0x000007ff
# define R128_CCE_PACKET1_REG0_MASK 0x000007ff
# define R128_CCE_PACKET1_REG1_MASK 0x003ff800
 
#define R128_CCE_VC_FRMT_RHW 0x00000001
#define R128_CCE_VC_FRMT_DIFFUSE_BGR 0x00000002
#define R128_CCE_VC_FRMT_DIFFUSE_A 0x00000004
#define R128_CCE_VC_FRMT_DIFFUSE_ARGB 0x00000008
#define R128_CCE_VC_FRMT_SPEC_BGR 0x00000010
#define R128_CCE_VC_FRMT_SPEC_F 0x00000020
#define R128_CCE_VC_FRMT_SPEC_FRGB 0x00000040
#define R128_CCE_VC_FRMT_S_T 0x00000080
#define R128_CCE_VC_FRMT_S2_T2 0x00000100
#define R128_CCE_VC_FRMT_RHW2 0x00000200
 
#define R128_CCE_VC_CNTL_PRIM_TYPE_NONE 0x00000000
#define R128_CCE_VC_CNTL_PRIM_TYPE_POINT 0x00000001
#define R128_CCE_VC_CNTL_PRIM_TYPE_LINE 0x00000002
#define R128_CCE_VC_CNTL_PRIM_TYPE_POLY_LINE 0x00000003
#define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_LIST 0x00000004
#define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_FAN 0x00000005
#define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_STRIP 0x00000006
#define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_TYPE2 0x00000007
#define R128_CCE_VC_CNTL_PRIM_WALK_IND 0x00000010
#define R128_CCE_VC_CNTL_PRIM_WALK_LIST 0x00000020
#define R128_CCE_VC_CNTL_PRIM_WALK_RING 0x00000030
#define R128_CCE_VC_CNTL_NUM_SHIFT 16
 
#define RADEON_DAC_CNTL2 0x007c
#define RADEON_CRTC_MORE_CNTL 0x027c
#define RADEON_DAC_EXT_CNTL 0x0280
#define RADEON_GRPH_BUF_CNTL 0x02f0
#define RADEON_VGA_BUF_CNTL 0x02f4
 
#define RADEON_SURFACE_CNTL 0x0b00
 
#define RADEON_VCLK_SRC_SEL_MASK 0x0003
#define RADEON_VCLK_SRC_SEL_CPUCLK 0x0000
#define RADEON_VCLK_SRC_SEL_PPLLCLK 0x0003
 
#define RADEON_BUS_READ_BURST (1<<30)
#define RADEON_BUS_RD_DISCARD_EN (1<<24)
 
#define RADEON_SURF_TRANSLATION_DIS (1<<8)
#endif
/shark/trunk/drivers/svga/grx/glib.h
20,11 → 20,11
 
/**
------------
CVS : $Id: glib.h,v 1.1 2003-02-28 11:23:40 pj Exp $
CVS : $Id: glib.h,v 1.2 2003-03-13 13:08:38 giacomo Exp $
 
File: $File$
Revision: $Revision: 1.1 $
Last update: $Date: 2003-02-28 11:23:40 $
Revision: $Revision: 1.2 $
Last update: $Date: 2003-03-13 13:08:38 $
------------
 
**/
53,12 → 53,12
 
#include <ll/sys/types.h>
 
int grx_setbuffer(unsigned char *vbuf,unsigned int w, unsigned int h);
int grx_setbuffer(BYTE *vbuf,WORD w, WORD h);
 
void grx_plot(WORD x, WORD y, DWORD color);
DWORD grx_getpixel(WORD x, WORD y);
//void grx_getimage(WORD x1, WORD y1, WORD x2, WORD y2, BYTE *buf);
void grx_putimage(WORD x1, WORD y1, WORD x2, WORD y2, BYTE *buf);
//void grx_putimage(WORD x1, WORD y1, WORD x2, WORD y2, BYTE *buf);
void grx_box(WORD x1, WORD y1, WORD x2, WORD y2, DWORD color);
void grx_rect(WORD x1, WORD y1, WORD x2, WORD y2, DWORD color);
void grx_line(WORD x1, WORD y1, WORD x2, WORD y2, DWORD color);
/shark/trunk/drivers/svga/grx/glib.c
5,10 → 5,28
 
#define fontaddr 0xffa6eL /* indirizzo set caratteri */
 
unsigned char * flbaddr;
unsigned int bpr;
unsigned int height, width;
BYTE * flbaddr;
WORD bpr;
WORD height, width;
 
inline void memsetw(void *dst, unsigned int c, unsigned long int memdiv2)
{
__asm__ __volatile__("push %%edi
push %%eax
push %%ecx
movl %2, %%edi
cld
rep
stosw
pop %%ecx
pop %%eax
pop %%edi"
:
: "c" (memdiv2), "a" (c), "b" (dst));
 
}
 
 
static void circlepixels(WORD x, WORD y, WORD sx, WORD sy, DWORD c)
{
grx_plot(sx + x, sy + y, c);
79,13 → 97,15
}
}
 
int grx_setbuffer(unsigned char *vbuf, unsigned int w, unsigned int h)
int grx_setbuffer(BYTE *vbuf, WORD w, WORD h)
{
 
//This functions are designed to work only whit 16 bpp
flbaddr = vbuf;
width = w;
height = h;
bpr = 4 * w;
bpr = 2 * w;
return 1;
105,14 → 125,14
 
void grx_box(WORD x1, WORD y1, WORD x2, WORD y2, DWORD color)
{
unsigned char * addr;
WORD dx, y;
BYTE * addr;
int dx, y;
addr = flbaddr + (x1 << 2) + bpr * y1;
dx = (x2 - x1 + 1);
addr = flbaddr + (x1 << 1) + bpr * y1;
dx = (x2 - x1 + 1) << 1;
 
for (y = y1; y <= y2; y++) {
memset((unsigned long int *)(addr),(DWORD)(color),dx);
memsetw(addr,color,(dx>>1));
addr += bpr;
}
}
119,39 → 139,40
 
void grx_rect(WORD x1, WORD y1, WORD x2, WORD y2, DWORD color)
{
unsigned char * addr;
WORD dx, y;
BYTE * addr;
int dx, y;
addr = flbaddr + (x1 << 2) + bpr * y1;
dx = (x2 - x1);
addr = flbaddr + (x1 << 1) + bpr * y1;
dx = (x2 - x1) << 1;
 
memset((unsigned long int *)(addr),(DWORD)color,dx+2);
memsetw(addr,color,(dx>>1)+1);
addr += bpr;
 
for (y = y1 + 1; y <= y2 - 1; y++) {
*(unsigned long int *)addr = (DWORD)color;
*(unsigned long int *)(addr + (dx<<2)) = (DWORD)color;
*(WORD *)(addr) = (WORD)(color);
*(WORD *)(addr + dx) = (WORD)(color);
addr += bpr;
}
memset((unsigned long int *)(addr),(DWORD)(color),dx+2);
memsetw(addr,color,(dx>>1)+1);
}
 
void grx_text(char *text, WORD x, WORD y, DWORD fg, DWORD bg)
{
unsigned char * fp, * addr;
BYTE * fp;
BYTE * addr;
int r, c, bits;
 
addr = flbaddr;
while (*text) {
fp = (unsigned char *)(fontaddr + (8 * *(BYTE *)text));
fp = (BYTE *)(fontaddr + (8 * *(BYTE *)text));
for (r=0; r<8; r++) {
bits = *(unsigned char *)(fp++);
bits = *(BYTE *)(fp++);
for (c=0; c<8; c++)
if (bits & (0x80>>c))
*(unsigned long int *)(addr + (y + r) * bpr + ((x + c) << 2)) = (DWORD)fg;
*(WORD *)(addr + (y + r) * bpr + ((x + c) << 1)) = (WORD)(fg);
else
*(unsigned long int *)(addr + (y + r) * bpr + ((x + c) << 2)) = (DWORD)bg;
*(WORD *)(addr + (y + r) * bpr + ((x + c) << 1)) = (WORD)(bg);
}
text++;
x += 8;
161,7 → 182,7
void grx_line(WORD x1, WORD y1, WORD x2, WORD y2, DWORD color)
{
register int t, distance;
unsigned char * addr;
BYTE * addr;
int xerr=0, yerr=0, deltax, deltay;
int incx, incy;
 
191,7 → 212,7
distance = deltay;
 
for (t=0; t<=distance+1; t++) { /* draw the line */
*(unsigned long int *)(addr + y1 * bpr + (x1 << 2)) = (DWORD)color;
*(WORD *)(addr + y1 * bpr + (x1 << 1)) = (WORD)color;
xerr += deltax;
yerr += deltay;
if (xerr > distance) {
207,7 → 228,7
 
void grx_plot(WORD x, WORD y, DWORD color)
{
*(unsigned long int *)(flbaddr + y * bpr + (x << 2)) = (DWORD)color;
*(WORD *)(flbaddr + y * bpr + (x << 1)) = (WORD)color;
}
 
DWORD grx_getpixel(WORD x, WORD y)
214,7 → 235,7
{
DWORD rv;
 
(DWORD)rv = *(unsigned long int *)(flbaddr + y * bpr + (x << 2));
(DWORD)rv = *(WORD *)(flbaddr + y * bpr + (x << 1));
return rv;
}
 
/shark/trunk/drivers/svga/r128io.h
0,0 → 1,115
#include "libvga.h"
#include <stdio.h>
 
static int __svgalib_r128_inmisc(void)
{
return 0;
}
 
static void __svgalib_r128_outmisc(int i)
{
}
 
static int __svgalib_r128_incrtc(int i)
{
return 0;
}
 
static void __svgalib_r128_outcrtc(int i, int d)
{
}
 
static int __svgalib_r128_inseq(int index)
{
return 0;
}
 
static void __svgalib_r128_outseq(int index, int val)
{
}
 
static int __svgalib_r128_ingra(int index)
{
return 0;
}
 
static void __svgalib_r128_outgra(int index, int val)
{
}
 
static int __svgalib_r128_inis1(void)
{
return 0;
}
 
static int __svgalib_r128_inatt(int index)
{
return 0;
}
 
static void __svgalib_r128_outatt(int index, int val)
{
}
 
static void __svgalib_r128_attscreen(int i)
{
}
 
static void __svgalib_r128_inpal(int i, int *r, int *g, int *b)
{
volatile int rgb;
if(chiptype==Radeon) {
OUTREG(R128_PALETTE_INDEX, i );
rgb=INREG(R128_PALETTE_DATA);
*r=(rgb>>16) & 0xff;
*g=(rgb>>8) & 0xff;
*b=rgb & 0xff;
if(dac6bits) {
*r>>=2;
*g>>=2;
*b>>=2;
}
} else {
OUTREG(R128_PALETTE_INDEX, i<<16 );
rgb=INREG(R128_PALETTE_DATA);
*r=(rgb>>16) & 0xff;
*g=(rgb>>8) & 0xff;
*b=rgb & 0xff;
}
}
 
static void __svgalib_r128_outpal(int i, int r, int g, int b)
{
OUTREG(R128_PALETTE_INDEX, i );
if((chiptype==Radeon) && dac6bits) {
r<<=2;
g<<=2;
b<<=2;
}
OUTREG(R128_PALETTE_DATA, b | (g<<8) | (r<<16) );
}
 
static void r128_mapio(void)
{
#ifndef __PPC
if(__svgalib_secondary) {
#endif
__svgalib_inmisc=__svgalib_r128_inmisc;
__svgalib_outmisc=__svgalib_r128_outmisc;
__svgalib_incrtc=__svgalib_r128_incrtc;
__svgalib_outcrtc=__svgalib_r128_outcrtc;
__svgalib_inseq=__svgalib_r128_inseq;
__svgalib_outseq=__svgalib_r128_outseq;
__svgalib_ingra=__svgalib_r128_ingra;
__svgalib_outgra=__svgalib_r128_outgra;
__svgalib_inatt=__svgalib_r128_inatt;
__svgalib_outatt=__svgalib_r128_outatt;
__svgalib_attscreen=__svgalib_r128_attscreen;
__svgalib_inis1=__svgalib_r128_inis1;
#ifndef __PPC
}
#endif
__svgalib_inpal=__svgalib_r128_inpal;
__svgalib_outpal=__svgalib_r128_outpal;
}
 
/shark/trunk/drivers/svga/r128.c
0,0 → 1,1436
/*
Rage 128 chipset driver
*/
 
#include <stdlib.h>
//#include <stdio.h>
#include <string.h>
#include <unistd.h>
//#include <sys/mman.h>
#include <errno.h>
#include "vga.h"
#include "libvga.h"
#include "driver.h"
#include "timing.h"
#include "vgaregs.h"
#include "interface.h"
#include "vgapci.h"
#include "endianess.h"
#include "r128_reg.h"
 
#include <kernel/log.h>
 
static enum { Rage128=0, Radeon } chiptype; /* r128io needs to know */
static int dac6bits;
#include "r128io.h"
 
#ifdef __PPC
#define NO_BIOS
#else
#undef NO_BIOS
#endif
 
typedef int Bool;
 
static int r128_ramtype;
static int BusCntl, CRTOnly, HasPanelRegs;
 
typedef struct {
uint16_t reference_freq;
uint16_t reference_div;
uint32_t min_pll_freq;
uint32_t max_pll_freq;
uint16_t xclk;
} R128PLLRec, *R128PLLPtr;
 
typedef struct {
/* Common registers */
uint32_t ovr_clr;
uint32_t ovr_wid_left_right;
uint32_t ovr_wid_top_bottom;
uint32_t ov0_scale_cntl;
uint32_t mpp_tb_config;
uint32_t mpp_gp_config;
uint32_t subpic_cntl;
uint32_t viph_control;
uint32_t i2c_cntl_1;
uint32_t gen_int_cntl;
uint32_t cap0_trig_cntl;
uint32_t cap1_trig_cntl;
uint32_t bus_cntl;
uint32_t bus_cntl1;
uint32_t mem_cntl;
uint32_t config_cntl;
uint32_t mem_vga_wp_sel;
uint32_t mem_vga_rp_sel;
uint32_t surface_cntl;
uint32_t dac_cntl2;
uint32_t crtc_more_cntl;
uint32_t dac_ext_cntl;
uint32_t grph_buf_cntl;
uint32_t vga_buf_cntl;
 
/* Other registers to save for VT switches */
uint32_t dp_datatype;
uint32_t gen_reset_cntl;
uint32_t clock_cntl_index;
uint32_t amcgpio_en_reg;
uint32_t amcgpio_mask;
/* CRTC registers */
uint32_t crtc_gen_cntl;
uint32_t crtc_ext_cntl;
uint32_t dac_cntl;
uint32_t crtc_h_total_disp;
uint32_t crtc_h_sync_strt_wid;
uint32_t crtc_v_total_disp;
uint32_t crtc_v_sync_strt_wid;
uint32_t crtc_offset;
uint32_t crtc_offset_cntl;
uint32_t crtc_pitch;
/* CRTC2 registers */
uint32_t crtc2_gen_cntl;
/* Flat panel registers */
uint32_t fp_crtc_h_total_disp;
uint32_t fp_crtc_v_total_disp;
uint32_t fp_gen_cntl;
uint32_t fp_h_sync_strt_wid;
uint32_t fp_horz_stretch;
uint32_t fp_panel_cntl;
uint32_t fp_v_sync_strt_wid;
uint32_t fp_vert_stretch;
uint32_t lvds_gen_cntl;
uint32_t tmds_crc;
/* Computed values for PLL */
uint32_t dot_clock_freq;
uint32_t pll_output_freq;
int feedback_div;
int post_div;
/* PLL registers */
uint32_t ppll_ref_div;
uint32_t ppll_div_3;
uint32_t htotal_cntl;
/* DDA register */
uint32_t dda_config;
uint32_t dda_on_off;
uint32_t vga_dda_config;
uint32_t vga_dda_on_off;
/* Pallet */
Bool palette_valid;
uint32_t palette[256];
} R128SaveRec, *R128SavePtr;
 
typedef struct { /* All values in XCLKS */
int ML; /* Memory Read Latency */
int MB; /* Memory Burst Length */
int Trcd; /* RAS to CAS delay */
int Trp; /* RAS percentage */
int Twr; /* Write Recovery */
int CL; /* CAS Latency */
int Tr2w; /* Read to Write Delay */
int Rloop; /* Loop Latency */
int Rloop_fudge; /* Add to ML to get Rloop */
char *name;
} R128RAMRec, *R128RAMPtr;
 
#define R128_TOTAL_REGS (VGA_TOTAL_REGS + sizeof(R128SaveRec))
static int R128MinBits(int val)
{
int bits;
 
if (!val) return 1;
for (bits = 0; val; val >>= 1, ++bits);
return bits;
}
static int R128Div(int n, int d)
{
return (n + (d / 2)) / d;
}
static R128PLLRec pll;
 
static R128RAMRec ram[] = { /* Memory Specifications
From RAGE 128 Software Development
Manual (Technical Reference Manual P/N
SDK-G04000 Rev 0.01), page 3-21. */
{ 4, 4, 3, 3, 1, 3, 1, 16, 12, "128-bit SDR SGRAM 1:1" },
{ 4, 8, 3, 3, 1, 3, 1, 17, 13, "64-bit SDR SGRAM 1:1" },
{ 4, 4, 1, 2, 1, 2, 1, 16, 12, "64-bit SDR SGRAM 2:1" },
{ 4, 4, 3, 3, 2, 3, 1, 16, 12, "64-bit DDR SGRAM" },
};
 
static unsigned R128INPLL(int addr)
{
OUTREG8(R128_CLOCK_CNTL_INDEX, addr & 0x1f);
return INREG(R128_CLOCK_CNTL_DATA);
}
 
static void R128WaitForVerticalSync(void)
{
volatile int i;
 
OUTREG(R128_GEN_INT_STATUS, R128_VSYNC_INT_AK);
for (i = 0; i < R128_TIMEOUT; i++) {
if (INREG(R128_GEN_INT_STATUS) & R128_VSYNC_INT) break;
}
}
 
/* Blank screen. */
static void R128Blank(void)
{
OUTREGP(R128_CRTC_EXT_CNTL, R128_CRTC_DISPLAY_DIS, ~R128_CRTC_DISPLAY_DIS);
}
 
/* Unblank screen. */
static void R128Unblank(void)
{
OUTREGP(R128_CRTC_EXT_CNTL, 0, ~R128_CRTC_DISPLAY_DIS);
}
 
static void R128RestoreCommonRegisters(R128SavePtr restore)
{
OUTREG(R128_OVR_CLR, restore->ovr_clr);
OUTREG(R128_OVR_WID_LEFT_RIGHT, restore->ovr_wid_left_right);
OUTREG(R128_OVR_WID_TOP_BOTTOM, restore->ovr_wid_top_bottom);
OUTREG(R128_OV0_SCALE_CNTL, restore->ov0_scale_cntl);
OUTREG(R128_MPP_TB_CONFIG, restore->mpp_tb_config );
OUTREG(R128_MPP_GP_CONFIG, restore->mpp_gp_config );
OUTREG(R128_SUBPIC_CNTL, restore->subpic_cntl);
OUTREG(R128_VIPH_CONTROL, restore->viph_control);
OUTREG(R128_I2C_CNTL_1, restore->i2c_cntl_1);
OUTREG(R128_GEN_INT_CNTL, restore->gen_int_cntl);
OUTREG(R128_CAP0_TRIG_CNTL, restore->cap0_trig_cntl);
OUTREG(R128_CAP1_TRIG_CNTL, restore->cap1_trig_cntl);
OUTREG(R128_BUS_CNTL, restore->bus_cntl);
OUTREG(R128_BUS_CNTL1, restore->bus_cntl1);
OUTREG(R128_CONFIG_CNTL, restore->config_cntl);
OUTREG(R128_MEM_VGA_WP_SEL, restore->mem_vga_wp_sel);
OUTREG(R128_MEM_VGA_RP_SEL, restore->mem_vga_rp_sel);
 
if(chiptype == Rage128) {
OUTREG(RADEON_SURFACE_CNTL, restore->surface_cntl);
OUTREG(RADEON_DAC_CNTL2, restore->dac_cntl2);
OUTREG(RADEON_CRTC_MORE_CNTL,restore->crtc_more_cntl);
OUTREG(RADEON_DAC_EXT_CNTL, restore->dac_ext_cntl);
OUTREG(RADEON_GRPH_BUF_CNTL, restore->grph_buf_cntl);
OUTREG(RADEON_VGA_BUF_CNTL, restore->vga_buf_cntl);
}
 
}
 
/* Write CRTC registers. */
static void R128RestoreCrtcRegisters(R128SavePtr restore)
{
OUTREG(R128_CRTC_GEN_CNTL, restore->crtc_gen_cntl);
 
OUTREGP(R128_CRTC_EXT_CNTL, restore->crtc_ext_cntl,
R128_CRTC_VSYNC_DIS | R128_CRTC_HSYNC_DIS | R128_CRTC_DISPLAY_DIS);
 
OUTREGP(R128_DAC_CNTL, restore->dac_cntl,
R128_DAC_RANGE_CNTL | R128_DAC_BLANKING);
 
OUTREG(R128_CRTC_H_TOTAL_DISP, restore->crtc_h_total_disp);
OUTREG(R128_CRTC_H_SYNC_STRT_WID, restore->crtc_h_sync_strt_wid);
OUTREG(R128_CRTC_V_TOTAL_DISP, restore->crtc_v_total_disp);
OUTREG(R128_CRTC_V_SYNC_STRT_WID, restore->crtc_v_sync_strt_wid);
OUTREG(R128_CRTC_OFFSET, restore->crtc_offset);
OUTREG(R128_CRTC_OFFSET_CNTL, restore->crtc_offset_cntl);
OUTREG(R128_CRTC_PITCH, restore->crtc_pitch);
}
 
/* Write flat panel registers */
#if 0
static void R128RestoreFPRegisters(R128SavePtr restore)
{
uint32_t tmp;
 
OUTREG(R128_CRTC2_GEN_CNTL, restore->crtc2_gen_cntl);
OUTREG(R128_FP_CRTC_H_TOTAL_DISP, restore->fp_crtc_h_total_disp);
OUTREG(R128_FP_CRTC_V_TOTAL_DISP, restore->fp_crtc_v_total_disp);
OUTREG(R128_FP_GEN_CNTL, restore->fp_gen_cntl);
OUTREG(R128_FP_H_SYNC_STRT_WID, restore->fp_h_sync_strt_wid);
OUTREG(R128_FP_HORZ_STRETCH, restore->fp_horz_stretch);
OUTREG(R128_FP_PANEL_CNTL, restore->fp_panel_cntl);
OUTREG(R128_FP_V_SYNC_STRT_WID, restore->fp_v_sync_strt_wid);
OUTREG(R128_FP_VERT_STRETCH, restore->fp_vert_stretch);
OUTREG(R128_TMDS_CRC, restore->tmds_crc);
 
tmp = INREG(R128_LVDS_GEN_CNTL);
if ((tmp & (R128_LVDS_ON | R128_LVDS_BLON)) ==
(restore->lvds_gen_cntl & (R128_LVDS_ON | R128_LVDS_BLON))) {
OUTREG(R128_LVDS_GEN_CNTL, restore->lvds_gen_cntl);
} else {
if (restore->lvds_gen_cntl & (R128_LVDS_ON | R128_LVDS_BLON)) {
OUTREG(R128_LVDS_GEN_CNTL, restore->lvds_gen_cntl & ~R128_LVDS_BLON);
// usleep(R128PTR(pScrn)->PanelPwrDly * 1000);
OUTREG(R128_LVDS_GEN_CNTL, restore->lvds_gen_cntl);
} else {
OUTREG(R128_LVDS_GEN_CNTL, restore->lvds_gen_cntl | R128_LVDS_BLON);
// usleep(R128PTR(pScrn)->PanelPwrDly * 1000);
OUTREG(R128_LVDS_GEN_CNTL, restore->lvds_gen_cntl);
}
}
}
#endif
static void R128PLLWaitForReadUpdateComplete(void)
{
while (INPLL(R128_PPLL_REF_DIV) & R128_PPLL_ATOMIC_UPDATE_R);
}
 
static void R128PLLWriteUpdate(void)
{
OUTPLLP(R128_PPLL_REF_DIV, R128_PPLL_ATOMIC_UPDATE_W, 0xffff);
}
 
/* Write PLL registers. */
static void RADEONRestorePLLRegisters(R128SavePtr restore)
{
OUTPLLP(R128_VCLK_ECP_CNTL,
RADEON_VCLK_SRC_SEL_CPUCLK,
~(RADEON_VCLK_SRC_SEL_MASK));
 
OUTPLLP(R128_PPLL_CNTL,
R128_PPLL_RESET
| R128_PPLL_ATOMIC_UPDATE_EN
| R128_PPLL_VGA_ATOMIC_UPDATE_EN,
~(R128_PPLL_RESET
| R128_PPLL_ATOMIC_UPDATE_EN
| R128_PPLL_VGA_ATOMIC_UPDATE_EN));
 
OUTREGP(R128_CLOCK_CNTL_INDEX,
R128_PLL_DIV_SEL,
~(R128_PLL_DIV_SEL));
 
OUTPLLP(R128_PPLL_REF_DIV,
restore->ppll_ref_div,
~R128_PPLL_REF_DIV_MASK);
 
OUTPLLP(R128_PPLL_DIV_3,
restore->ppll_div_3,
~R128_PPLL_FB3_DIV_MASK);
 
OUTPLLP(R128_PPLL_DIV_3,
restore->ppll_div_3,
~R128_PPLL_POST3_DIV_MASK);
 
R128PLLWriteUpdate();
R128PLLWaitForReadUpdateComplete();
 
OUTPLL(R128_HTOTAL_CNTL, restore->htotal_cntl);
 
OUTPLLP(R128_PPLL_CNTL,
0,
~(R128_PPLL_RESET
| R128_PPLL_SLEEP
| R128_PPLL_ATOMIC_UPDATE_EN
| R128_PPLL_VGA_ATOMIC_UPDATE_EN));
 
sleep(1); /* Let the clock to lock */
 
OUTPLLP(R128_VCLK_ECP_CNTL,
RADEON_VCLK_SRC_SEL_PPLLCLK,
~(RADEON_VCLK_SRC_SEL_MASK));
}
 
static void R128RestorePLLRegisters(R128SavePtr restore)
{
OUTREGP(R128_CLOCK_CNTL_INDEX, R128_PLL_DIV_SEL, 0xffff);
 
OUTPLLP(
R128_PPLL_CNTL,
R128_PPLL_RESET
| R128_PPLL_ATOMIC_UPDATE_EN,
0xffff);
 
R128PLLWaitForReadUpdateComplete();
OUTPLLP(R128_PPLL_REF_DIV,
restore->ppll_ref_div, ~R128_PPLL_REF_DIV_MASK);
R128PLLWriteUpdate();
 
R128PLLWaitForReadUpdateComplete();
OUTPLLP(R128_PPLL_DIV_3,
restore->ppll_div_3, ~R128_PPLL_FB3_DIV_MASK);
R128PLLWriteUpdate();
OUTPLLP(R128_PPLL_DIV_3,
restore->ppll_div_3, ~R128_PPLL_POST3_DIV_MASK);
R128PLLWriteUpdate();
 
R128PLLWaitForReadUpdateComplete();
OUTPLL(R128_HTOTAL_CNTL, restore->htotal_cntl);
R128PLLWriteUpdate();
 
OUTPLLP( R128_PPLL_CNTL, 0, ~R128_PPLL_RESET);
 
}
 
/* Write DDA registers. */
static void R128RestoreDDARegisters(R128SavePtr restore)
{
OUTREG(R128_DDA_CONFIG, restore->dda_config);
OUTREG(R128_DDA_ON_OFF, restore->dda_on_off);
// OUTREG(R128_VGA_DDA_CONFIG, restore->vga_dda_config);
// OUTREG(R128_VGA_DDA_ON_OFF, restore->vga_dda_on_off);
}
 
/* Write palette data. */
static void R128RestorePalette( R128SavePtr restore)
{
int i;
 
if (!restore->palette_valid) return;
 
/* Select palette 0 (main CRTC) if using FP-enabled chip */
// if (info->HasPanelRegs) PAL_SELECT(0);
 
OUTPAL_START(0);
for (i = 0; i < 256; i++) OUTPAL_NEXT_uint32_t(restore->palette[i]);
}
 
/* Write out state to define a new video mode. */
static void R128RestoreMode(R128SavePtr restore)
{
R128Blank();
 
OUTREG(R128_AMCGPIO_MASK, restore->amcgpio_mask);
OUTREG(R128_AMCGPIO_EN_REG, restore->amcgpio_en_reg);
OUTREG(R128_CLOCK_CNTL_INDEX, restore->clock_cntl_index);
#if 0 /* works without, and it causes problems with it */
OUTREG(R128_GEN_RESET_CNTL, restore->gen_reset_cntl);
#endif
OUTREG(R128_DP_DATATYPE, restore->dp_datatype);
 
R128RestoreCommonRegisters( restore);
R128RestoreCrtcRegisters( restore);
// if (info->HasPanelRegs)
// R128RestoreFPRegisters(restore);
// if (!info->HasPanelRegs || info->CRTOnly)
switch(chiptype) {
case Rage128:
R128RestorePLLRegisters(restore);
break;
case Radeon:
RADEONRestorePLLRegisters(restore);
break;
}
if(chiptype == Rage128) {
R128RestoreDDARegisters(restore);
}
R128RestorePalette(restore);
}
 
/* Read common registers. */
static void R128SaveCommonRegisters(R128SavePtr save)
{
save->ovr_clr = INREG(R128_OVR_CLR);
save->ovr_wid_left_right = INREG(R128_OVR_WID_LEFT_RIGHT);
save->ovr_wid_top_bottom = INREG(R128_OVR_WID_TOP_BOTTOM);
save->ov0_scale_cntl = INREG(R128_OV0_SCALE_CNTL);
save->mpp_tb_config = INREG(R128_MPP_TB_CONFIG);
save->mpp_gp_config = INREG(R128_MPP_GP_CONFIG);
save->subpic_cntl = INREG(R128_SUBPIC_CNTL);
save->viph_control = INREG(R128_VIPH_CONTROL);
save->i2c_cntl_1 = INREG(R128_I2C_CNTL_1);
save->gen_int_cntl = INREG(R128_GEN_INT_CNTL);
save->cap0_trig_cntl = INREG(R128_CAP0_TRIG_CNTL);
save->cap1_trig_cntl = INREG(R128_CAP1_TRIG_CNTL);
save->bus_cntl = INREG(R128_BUS_CNTL);
save->bus_cntl1 = INREG(R128_BUS_CNTL1);
save->mem_cntl = INREG(R128_MEM_CNTL);
save->config_cntl = INREG(R128_CONFIG_CNTL);
save->mem_vga_wp_sel = INREG(R128_MEM_VGA_WP_SEL);
save->mem_vga_rp_sel = INREG(R128_MEM_VGA_RP_SEL);
 
if(chiptype==Radeon) {
save->surface_cntl = INREG(RADEON_SURFACE_CNTL);
save->dac_cntl2 = INREG(RADEON_DAC_CNTL2);
save->crtc_more_cntl = INREG(RADEON_CRTC_MORE_CNTL);
save->dac_ext_cntl = INREG(RADEON_DAC_EXT_CNTL);
save->grph_buf_cntl = INREG(RADEON_GRPH_BUF_CNTL);
save->vga_buf_cntl = INREG(RADEON_VGA_BUF_CNTL);
}
}
 
/* Read CRTC registers. */
static void R128SaveCrtcRegisters(R128SavePtr save)
{
save->crtc_gen_cntl = INREG(R128_CRTC_GEN_CNTL);
save->crtc_ext_cntl = INREG(R128_CRTC_EXT_CNTL);
save->dac_cntl = INREG(R128_DAC_CNTL);
save->crtc_h_total_disp = INREG(R128_CRTC_H_TOTAL_DISP);
save->crtc_h_sync_strt_wid = INREG(R128_CRTC_H_SYNC_STRT_WID);
save->crtc_v_total_disp = INREG(R128_CRTC_V_TOTAL_DISP);
save->crtc_v_sync_strt_wid = INREG(R128_CRTC_V_SYNC_STRT_WID);
save->crtc_offset = INREG(R128_CRTC_OFFSET);
save->crtc_offset_cntl = INREG(R128_CRTC_OFFSET_CNTL);
save->crtc_pitch = INREG(R128_CRTC_PITCH);
}
 
#if 0
/* Read flat panel registers */
static void R128SaveFPRegisters(R128SavePtr save)
{
save->crtc2_gen_cntl = INREG(R128_CRTC2_GEN_CNTL);
save->fp_crtc_h_total_disp = INREG(R128_FP_CRTC_H_TOTAL_DISP);
save->fp_crtc_v_total_disp = INREG(R128_FP_CRTC_V_TOTAL_DISP);
save->fp_gen_cntl = INREG(R128_FP_GEN_CNTL);
save->fp_h_sync_strt_wid = INREG(R128_FP_H_SYNC_STRT_WID);
save->fp_horz_stretch = INREG(R128_FP_HORZ_STRETCH);
save->fp_panel_cntl = INREG(R128_FP_PANEL_CNTL);
save->fp_v_sync_strt_wid = INREG(R128_FP_V_SYNC_STRT_WID);
save->fp_vert_stretch = INREG(R128_FP_VERT_STRETCH);
save->lvds_gen_cntl = INREG(R128_LVDS_GEN_CNTL);
save->tmds_crc = INREG(R128_TMDS_CRC);
}
#endif
 
/* Read PLL registers. */
static void R128SavePLLRegisters(R128SavePtr save)
{
save->ppll_ref_div = INPLL(R128_PPLL_REF_DIV);
save->ppll_div_3 = INPLL(R128_PPLL_DIV_3);
save->htotal_cntl = INPLL(R128_HTOTAL_CNTL);
}
 
/* Read DDA registers. */
static void R128SaveDDARegisters(R128SavePtr save)
{
save->dda_config = INREG(R128_DDA_CONFIG);
save->dda_on_off = INREG(R128_DDA_ON_OFF);
save->vga_dda_config = INREG(R128_VGA_DDA_CONFIG);
save->vga_dda_on_off = INREG(R128_VGA_DDA_ON_OFF);
}
 
/* Read palette data. */
static void R128SavePalette(R128SavePtr save)
{
int i;
 
/* Select palette 0 (main CRTC) if using FP-enabled chip */
// if (info->HasPanelRegs) PAL_SELECT(0);
 
INPAL_START(0);
for (i = 0; i < 256; i++) save->palette[i] = INPAL_NEXT();
save->palette_valid = 1;
}
 
/* Save state that defines current video mode. */
static void R128SaveMode(R128SavePtr save)
{
R128SaveCommonRegisters(save);
R128SaveCrtcRegisters(save);
// if (R128PTR(pScrn)->HasPanelRegs)
// R128SaveFPRegisters(save);
R128SavePLLRegisters(save);
if(chiptype == Rage128)
R128SaveDDARegisters(save);
R128SavePalette(save);
 
save->dp_datatype = INREG(R128_DP_DATATYPE);
save->gen_reset_cntl = INREG(R128_GEN_RESET_CNTL);
save->clock_cntl_index = INREG(R128_CLOCK_CNTL_INDEX);
save->amcgpio_en_reg = INREG(R128_AMCGPIO_EN_REG);
save->amcgpio_mask = INREG(R128_AMCGPIO_MASK);
}
 
static void R128InitCommonRegisters(R128SavePtr save)
{
save->ovr_clr = 0;
save->ovr_wid_left_right = 0;
save->ovr_wid_top_bottom = 0;
save->ov0_scale_cntl = 0;
save->mpp_tb_config = 0;
save->mpp_gp_config = 0;
save->subpic_cntl = 0;
save->viph_control = 0;
save->i2c_cntl_1 = 0;
save->gen_int_cntl = 0;
save->cap0_trig_cntl = 0;
save->cap1_trig_cntl = 0;
save->mem_vga_wp_sel = 0;
save->mem_vga_rp_sel = 0;
save->config_cntl = INREG(R128_CONFIG_CNTL);
save->bus_cntl = BusCntl;
save->bus_cntl1 = INREG(R128_BUS_CNTL1);
if(chiptype == Radeon) {
if(save->bus_cntl & RADEON_BUS_READ_BURST)
save->bus_cntl |=RADEON_BUS_RD_DISCARD_EN;
}
 
save->amcgpio_en_reg = INREG(R128_AMCGPIO_EN_REG);
save->amcgpio_mask = INREG(R128_AMCGPIO_MASK);
 
/*
* If bursts are enabled, turn on discards and aborts
*/
if (save->bus_cntl & (R128_BUS_WRT_BURST|R128_BUS_READ_BURST))
save->bus_cntl |= R128_BUS_RD_DISCARD_EN | R128_BUS_RD_ABORT_EN;
}
 
/* Define CRTC registers for requested video mode. */
static Bool R128InitCrtcRegisters(R128SavePtr save,
ModeTiming *mode, ModeInfo *info)
{
int format;
int hsync_start;
int hsync_wid;
int hsync_fudge;
int vsync_wid;
int bytpp;
int hsync_fudge_default[] = { 0x00, 0x12, 0x09, 0x09, 0x06, 0x05 };
int hsync_fudge_fp[] = { 0x12, 0x11, 0x09, 0x09, 0x05, 0x05 };
int hsync_fudge_fp_crt[] = { 0x12, 0x10, 0x08, 0x08, 0x04, 0x04 };
 
dac6bits=0;
 
switch (info->bitsPerPixel) {
case 4: format = 1; bytpp = 0; dac6bits = 1; break;
case 8: format = 2; bytpp = 1; dac6bits = 1; break;
case 16:
if(info->greenWeight==5)
format = 3; else format = 4;
bytpp = 2;
break;
case 24: format = 5; bytpp = 3; break; /* RGB */
case 32: format = 6; bytpp = 4; break; /* xRGB */
default:
return 0;
}
if (HasPanelRegs)
if (CRTOnly) hsync_fudge = hsync_fudge_fp_crt[format-1];
else hsync_fudge = hsync_fudge_fp[format-1];
else
hsync_fudge = hsync_fudge_default[format-1];
 
save->crtc_gen_cntl = (R128_CRTC_EXT_DISP_EN
| R128_CRTC_EN
| (format << 8)
| ((mode->flags & DOUBLESCAN)
? R128_CRTC_DBL_SCAN_EN
: 0)
| ((mode->flags & INTERLACED)
? R128_CRTC_INTERLACE_EN
: 0));
 
save->crtc_ext_cntl = R128_VGA_ATI_LINEAR | R128_XCRT_CNT_EN | R128_VGA_MEM_PS_EN;
if(chiptype == Radeon) save->crtc_ext_cntl |= R128_CRTC_CRT_ON;
save->dac_cntl = (R128_DAC_MASK_ALL
| R128_DAC_VGA_ADR_EN
| (dac6bits ? 0 : R128_DAC_8BIT_EN));
 
save->crtc_h_total_disp = ((((mode->CrtcHTotal / 8) - 1) & 0xffff)
| (((mode->CrtcHDisplay / 8) - 1) << 16));
 
hsync_wid = (mode->CrtcHSyncEnd - mode->CrtcHSyncStart) / 8;
if (!hsync_wid) hsync_wid = 1;
if (hsync_wid > 0x3f) hsync_wid = 0x3f;
 
hsync_start = mode->CrtcHSyncStart - 8 + hsync_fudge;
 
save->crtc_h_sync_strt_wid = ((hsync_start & 0xfff)
| (hsync_wid << 16)
| ((mode->flags & NHSYNC)
? R128_CRTC_H_SYNC_POL
: 0));
 
#if 1
/* This works for double scan mode. */
save->crtc_v_total_disp = (((mode->CrtcVTotal - 1) & 0xffff)
| ((mode->CrtcVDisplay - 1) << 16));
#else
/* This is what cce/nbmode.c example code
does -- is this correct? */
save->crtc_v_total_disp = (((mode->CrtcVTotal - 1) & 0xffff)
| ((mode->CrtcVDisplay
* ((mode->Flags & DOUBLESCAN) ? 2 : 1) - 1)
<< 16));
#endif
 
vsync_wid = mode->CrtcVSyncEnd - mode->CrtcVSyncStart;
if (!vsync_wid) vsync_wid = 1;
if (vsync_wid > 0x1f) vsync_wid = 0x1f;
 
save->crtc_v_sync_strt_wid = (((mode->CrtcVSyncStart - 1) & 0xfff)
| (vsync_wid << 16)
| ((mode->flags & NVSYNC)
? R128_CRTC_V_SYNC_POL
: 0));
save->crtc_offset = 0;
save->crtc_offset_cntl = 0;
save->crtc_pitch = info->width / 8;
 
save->config_cntl |= R128_CFG_VGA_RAM_EN;
if(chiptype == Radeon) {
save->crtc_pitch |= save->crtc_pitch<<16;
save->surface_cntl = RADEON_SURF_TRANSLATION_DIS;
 
save->dac_cntl2 = INREG(RADEON_DAC_CNTL2);
save->crtc_more_cntl = INREG(RADEON_CRTC_MORE_CNTL);
save->dac_ext_cntl = INREG(RADEON_DAC_EXT_CNTL);
save->grph_buf_cntl = INREG(RADEON_GRPH_BUF_CNTL);
save->vga_buf_cntl = INREG(RADEON_VGA_BUF_CNTL);
 
}
 
#ifdef __PPC
/* Change the endianness of the aperture */
switch (info->bitsPerPixel) {
case 15:
case 16: save->config_cntl |= APER_0_BIG_ENDIAN_16BPP_SWAP; break;
case 32: save->config_cntl |= APER_0_BIG_ENDIAN_32BPP_SWAP; break;
default: break;
}
#endif
 
return 1;
}
 
#if 0
/* Define CRTC registers for requested video mode. */
static void R128InitFPRegisters(R128SavePtr orig, R128SavePtr save,
ModeTiming *mode, ModeInfo *info)
{
#if 0
int xres = mode->CrtcHDisplay;
int yres = mode->CrtcVDisplay;
float Hratio, Vratio;
 
if (CRTOnly) {
save->crtc_ext_cntl |= R128_CRTC_CRT_ON;
save->crtc2_gen_cntl = 0;
save->fp_gen_cntl = orig->fp_gen_cntl;
save->fp_gen_cntl &= ~(R128_FP_FPON |
R128_FP_CRTC_USE_SHADOW_VEND |
R128_FP_CRTC_HORZ_DIV2_EN |
R128_FP_CRTC_HOR_CRT_DIV2_DIS |
R128_FP_USE_SHADOW_EN);
save->fp_gen_cntl |= (R128_FP_SEL_CRTC2 |
R128_FP_CRTC_DONT_SHADOW_VPAR);
save->fp_panel_cntl = orig->fp_panel_cntl & ~R128_FP_DIGON;
save->lvds_gen_cntl = orig->lvds_gen_cntl & ~(R128_LVDS_ON |
R128_LVDS_BLON);
return;
}
 
 
if (xres > info->PanelXRes) xres = info->PanelXRes;
if (yres > info->PanelYRes) yres = info->PanelYRes;
 
Hratio = (float)xres/(float)info->PanelXRes;
Vratio = (float)yres/(float)info->PanelYRes;
 
save->fp_horz_stretch =
(((((int)(Hratio * R128_HORZ_STRETCH_RATIO_MAX + 0.5))
& R128_HORZ_STRETCH_RATIO_MASK) << R128_HORZ_STRETCH_RATIO_SHIFT) |
(orig->fp_horz_stretch & (R128_HORZ_PANEL_SIZE |
R128_HORZ_FP_LOOP_STRETCH |
R128_HORZ_STRETCH_RESERVED)));
save->fp_horz_stretch &= ~R128_HORZ_AUTO_RATIO_FIX_EN;
if (Hratio == 1.0) save->fp_horz_stretch &= ~(R128_HORZ_STRETCH_BLEND |
R128_HORZ_STRETCH_ENABLE);
else save->fp_horz_stretch |= (R128_HORZ_STRETCH_BLEND |
R128_HORZ_STRETCH_ENABLE);
 
save->fp_vert_stretch =
(((((int)(Vratio * R128_VERT_STRETCH_RATIO_MAX + 0.5))
& R128_VERT_STRETCH_RATIO_MASK) << R128_VERT_STRETCH_RATIO_SHIFT) |
(orig->fp_vert_stretch & (R128_VERT_PANEL_SIZE |
R128_VERT_STRETCH_RESERVED)));
save->fp_vert_stretch &= ~R128_VERT_AUTO_RATIO_EN;
if (Vratio == 1.0) save->fp_vert_stretch &= ~(R128_VERT_STRETCH_ENABLE |
R128_VERT_STRETCH_BLEND);
else save->fp_vert_stretch |= (R128_VERT_STRETCH_ENABLE |
R128_VERT_STRETCH_BLEND);
 
save->fp_gen_cntl = (orig->fp_gen_cntl & ~(R128_FP_SEL_CRTC2 |
R128_FP_CRTC_USE_SHADOW_VEND |
R128_FP_CRTC_HORZ_DIV2_EN |
R128_FP_CRTC_HOR_CRT_DIV2_DIS |
R128_FP_USE_SHADOW_EN));
if (orig->fp_gen_cntl & R128_FP_DETECT_SENSE) {
save->fp_gen_cntl |= (R128_FP_CRTC_DONT_SHADOW_VPAR |
R128_FP_TDMS_EN);
}
 
save->fp_panel_cntl = orig->fp_panel_cntl;
save->lvds_gen_cntl = orig->lvds_gen_cntl;
 
save->tmds_crc = orig->tmds_crc;
 
/* Disable CRT output by disabling CRT output and setting the CRT
DAC to use CRTC2, which we set to 0's. In the future, we will
want to use the dual CRTC capabilities of the R128 to allow both
the flat panel and external CRT to either simultaneously display
the same image or display two different images. */
save->crtc_ext_cntl &= ~R128_CRTC_CRT_ON;
save->dac_cntl |= R128_DAC_CRT_SEL_CRTC2;
save->crtc2_gen_cntl = 0;
 
/* WARNING: Be careful about turning on the flat panel */
#if 1
save->lvds_gen_cntl |= (R128_LVDS_ON | R128_LVDS_BLON);
#else
save->fp_panel_cntl |= (R128_FP_DIGON | R128_FP_BLON);
save->fp_gen_cntl |= (R128_FP_FPON);
#endif
 
save->fp_crtc_h_total_disp = save->crtc_h_total_disp;
save->fp_crtc_v_total_disp = save->crtc_v_total_disp;
save->fp_h_sync_strt_wid = save->crtc_h_sync_strt_wid;
save->fp_v_sync_strt_wid = save->crtc_v_sync_strt_wid;
#endif
}
#endif
 
/* Define PLL registers for requested video mode. */
static void RADEONInitPLLRegisters(R128SavePtr save, R128PLLPtr pll,
double dot_clock)
{
unsigned long freq = dot_clock * 100;
struct {
int divider;
int bitvalue;
} *post_div,
post_divs[] = {
/* From RAGE 128 VR/RAGE 128 GL Register
Reference Manual (Technical Reference
Manual P/N RRG-G04100-C Rev. 0.04), page
3-17 (PLL_DIV_[3:0]). */
{ 1, 0 }, /* VCLK_SRC */
{ 2, 1 }, /* VCLK_SRC/2 */
{ 4, 2 }, /* VCLK_SRC/4 */
{ 8, 3 }, /* VCLK_SRC/8 */
 
{ 3, 4 }, /* VCLK_SRC/3 */
{ 16, 5 },
{ 6, 6 }, /* VCLK_SRC/6 */
{ 12, 7 }, /* VCLK_SRC/12 */
{ 0, 0 }
};
 
if (freq > pll->max_pll_freq) freq = pll->max_pll_freq;
if (freq * 12 < pll->min_pll_freq) freq = pll->min_pll_freq / 12;
 
for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
save->pll_output_freq = post_div->divider * freq;
if (save->pll_output_freq >= pll->min_pll_freq
&& save->pll_output_freq <= pll->max_pll_freq) break;
}
 
save->dot_clock_freq = freq;
save->feedback_div = R128Div(pll->reference_div * save->pll_output_freq,
pll->reference_freq);
save->post_div = post_div->divider;
 
save->ppll_ref_div = pll->reference_div;
save->ppll_div_3 = (save->feedback_div | (post_div->bitvalue << 16));
save->htotal_cntl = 0;
}
 
static void R128InitPLLRegisters(R128SavePtr save, R128PLLPtr pll,
double dot_clock)
{
unsigned long freq = dot_clock * 100;
struct {
int divider;
int bitvalue;
} *post_div,
post_divs[] = {
/* From RAGE 128 VR/RAGE 128 GL Register
Reference Manual (Technical Reference
Manual P/N RRG-G04100-C Rev. 0.04), page
3-17 (PLL_DIV_[3:0]). */
{ 1, 0 }, /* VCLK_SRC */
{ 2, 1 }, /* VCLK_SRC/2 */
{ 4, 2 }, /* VCLK_SRC/4 */
{ 8, 3 }, /* VCLK_SRC/8 */
 
{ 3, 4 }, /* VCLK_SRC/3 */
/* bitvalue = 5 is reserved */
{ 6, 6 }, /* VCLK_SRC/6 */
{ 12, 7 }, /* VCLK_SRC/12 */
{ 0, 0 }
};
 
if (freq > pll->max_pll_freq) freq = pll->max_pll_freq;
if (freq * 12 < pll->min_pll_freq) freq = pll->min_pll_freq / 12;
 
for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
save->pll_output_freq = post_div->divider * freq;
if (save->pll_output_freq >= pll->min_pll_freq
&& save->pll_output_freq <= pll->max_pll_freq) break;
}
 
save->dot_clock_freq = freq;
save->feedback_div = R128Div(pll->reference_div * save->pll_output_freq,
pll->reference_freq);
save->post_div = post_div->divider;
 
save->ppll_ref_div = pll->reference_div;
save->ppll_div_3 = (save->feedback_div | (post_div->bitvalue << 16));
save->htotal_cntl = 0;
}
 
/* Define DDA registers for requested video mode. */
static Bool R128InitDDARegisters(R128SavePtr save,
R128PLLPtr pll, ModeInfo *info)
{
int DisplayFifoWidth = 128;
int DisplayFifoDepth = 32;
int XclkFreq;
int VclkFreq;
int XclksPerTransfer;
int XclksPerTransferPrecise;
int UseablePrecision;
int Roff;
int Ron;
 
XclkFreq = pll->xclk;
 
VclkFreq = R128Div(pll->reference_freq * save->feedback_div,
pll->reference_div * save->post_div);
 
XclksPerTransfer = R128Div(XclkFreq * DisplayFifoWidth,
VclkFreq * (info->bytesPerPixel * 8));
 
UseablePrecision = R128MinBits(XclksPerTransfer) + 1;
 
XclksPerTransferPrecise = R128Div((XclkFreq * DisplayFifoWidth)
<< (11 - UseablePrecision),
VclkFreq * (info->bytesPerPixel * 8));
 
Roff = XclksPerTransferPrecise * (DisplayFifoDepth - 4);
 
Ron = (4 * ram[r128_ramtype].MB
+ 3 * (((ram[r128_ramtype].Trcd - 2)>0)?(ram[r128_ramtype].Trcd - 2):0)
+ 2 * ram[r128_ramtype].Trp
+ ram[r128_ramtype].Twr
+ ram[r128_ramtype].CL
+ ram[r128_ramtype].Tr2w
+ XclksPerTransfer) << (11 - UseablePrecision);
 
if (Ron + ram[r128_ramtype].Rloop >= Roff) {
return 0;
}
 
save->dda_config = (XclksPerTransferPrecise
| (UseablePrecision << 16)
| (ram[r128_ramtype].Rloop << 20));
 
save->dda_on_off = (Ron << 16) | Roff;
 
return 1;
}
 
 
/* Define initial palette for requested video mode. This doesn't do
anything for XFree86 4.0. */
static void R128InitPalette(R128SavePtr save)
{
int i;
save->palette_valid = 1;
for(i=0;i<256;i++) save->palette[i]=i | (i<<8) | (i<<16);
}
 
/* Define registers for a requested video mode. */
static Bool R128Init(ModeTiming *mode, ModeInfo *info, R128SavePtr save)
{
double dot_clock = mode->pixelClock/1000.0;
 
R128InitCommonRegisters(save);
if (!R128InitCrtcRegisters(save, mode, info)) return 0;
#if 0
if (HasPanelRegs)
R128InitFPRegisters(&info->SavedReg, save, mode, info);
#endif
switch(chiptype) {
case Rage128:
R128InitPLLRegisters(save, &pll, dot_clock);
break;
case Radeon:
RADEONInitPLLRegisters(save, &pll, dot_clock);
break;
}
if (!R128InitDDARegisters(save, &pll, info))
return 0;
// if (!info->PaletteSavedOnVT)
R128InitPalette(save);
 
return 1;
}
 
static int r128_init(int, int, int);
static void r128_unlock(void);
static void r128_lock(void);
 
static int r128_memory;
static int r128_is_linear, r128_linear_base, r128_mmio_base;
 
static CardSpecs *cardspecs;
 
static void r128_setpage(int page)
{
page*=2;
OUTREG(R128_MEM_VGA_WP_SEL, page | ((page+1)<<16));
OUTREG(R128_MEM_VGA_RP_SEL, page | ((page+1)<<16));
 
}
 
static int __svgalib_r128_inlinearmode(void)
{
return r128_is_linear;
}
 
/* Fill in chipset specific mode information */
 
static void r128_getmodeinfo(int mode, vga_modeinfo *modeinfo)
{
 
if(modeinfo->colors==16)return;
 
modeinfo->maxpixels = r128_memory*1024/modeinfo->bytesperpixel;
modeinfo->maxlogicalwidth = 4088;
modeinfo->startaddressrange = r128_memory * 1024 - 1;
modeinfo->haveblit = 0;
modeinfo->flags &= ~HAVE_RWPAGE;
modeinfo->flags |= HAVE_EXT_SET;
 
if (modeinfo->bytesperpixel >= 1) {
if(r128_linear_base)modeinfo->flags |= CAPABLE_LINEAR;
if (__svgalib_r128_inlinearmode())
modeinfo->flags |= IS_LINEAR | LINEAR_MODE;
}
}
 
/* Read and save chipset-specific registers */
 
static int r128_saveregs(unsigned char regs[])
{
r128_unlock();
R128SaveMode((R128SavePtr)(regs+VGA_TOTAL_REGS));
return R128_TOTAL_REGS - VGA_TOTAL_REGS;
}
 
/* Set chipset-specific registers */
 
static void r128_setregs(const unsigned char regs[], int mode)
{
r128_unlock();
R128RestoreMode((R128SavePtr)(regs+VGA_TOTAL_REGS));
 
R128Unblank();
}
/* Return nonzero if mode is available */
 
static int r128_modeavailable(int mode)
{
struct info *info;
ModeTiming *modetiming;
ModeInfo *modeinfo;
 
modeinfo = __svgalib_createModeInfoStructureForSvgalibMode(mode);
 
if (IS_IN_STANDARD_VGA_DRIVER(mode))
return __svgalib_vga_driverspecs.modeavailable(mode);
 
info = &__svgalib_infotable[mode];
if (r128_memory * 1024 < info->ydim * info->xbytes)
return 0;
 
modeinfo = __svgalib_createModeInfoStructureForSvgalibMode(mode);
 
modetiming = malloc(sizeof(ModeTiming));
if (__svgalib_getmodetiming(modetiming, modeinfo, cardspecs)) {
free(modetiming);
free(modeinfo);
return 0;
}
free(modetiming);
free(modeinfo);
 
return SVGADRV;
}
 
/* Local, called by r128_setmode(). */
 
static void r128_initializemode(unsigned char *moderegs,
ModeTiming * modetiming, ModeInfo * modeinfo, int mode)
{ /* long k; */
__svgalib_setup_VGA_registers(moderegs, modetiming, modeinfo);
 
R128Init(modetiming, modeinfo, (R128SavePtr)(moderegs+VGA_TOTAL_REGS));
 
return ;
}
 
 
static int r128_setmode(int mode, int prv_mode)
{
unsigned char *moderegs;
ModeTiming *modetiming;
ModeInfo *modeinfo;
 
if (IS_IN_STANDARD_VGA_DRIVER(mode)) {
return __svgalib_vga_driverspecs.setmode(mode, prv_mode);
}
if (!r128_modeavailable(mode))
return 1;
 
modeinfo = __svgalib_createModeInfoStructureForSvgalibMode(mode);
 
modetiming = malloc(sizeof(ModeTiming));
if (__svgalib_getmodetiming(modetiming, modeinfo, cardspecs)) {
free(modetiming);
free(modeinfo);
return 1;
}
 
moderegs = malloc(R128_TOTAL_REGS);
 
r128_initializemode(moderegs, modetiming, modeinfo, mode);
free(modetiming);
 
__svgalib_setregs(moderegs); /* Set standard regs. */
r128_setregs(moderegs, mode); /* Set extended regs. */
free(moderegs);
 
free(modeinfo);
return 0;
}
 
 
/* Unlock chipset-specific registers */
static void r128_unlock(void)
{
__svgalib_outcrtc(0x11, __svgalib_incrtc(0x11) & 0x7f);
}
 
static void r128_lock(void)
{
}
 
/* Indentify chipset, initialize and return non-zero if detected */
int r128_test(void)
{
return r128_init(0,0,0);
return 1;
}
 
 
/* Set display start address (not for 16 color modes) */
/* Cirrus supports any address in video memory (up to 2Mb) */
 
static void r128_setdisplaystart(int address)
{
int naddress=address >> 2;
__svgalib_outcrtc(0x0c,(naddress>>8)&0xff);
__svgalib_outcrtc(0x0d,(naddress)&0xff);
OUTREG(R128_CRTC_OFFSET, address);
}
 
/* Set logical scanline length (usually multiple of 8) */
/* Cirrus supports multiples of 8, up to 4088 */
 
static void r128_setlogicalwidth(int width)
{
int offset = width >> 3;
if(CI.bytesperpixel>1) {
offset = offset/CI.bytesperpixel;
}
__svgalib_outcrtc(0x13,offset&0xff);
OUTREG(R128_CRTC_PITCH, offset);
}
 
static int r128_linear(int op, int param)
{
if (op==LINEAR_ENABLE){r128_is_linear=1; return 0;};
if (op==LINEAR_DISABLE){r128_is_linear=0; return 0;};
if (op==LINEAR_QUERY_BASE) return r128_linear_base;
if (op == LINEAR_QUERY_RANGE || op == LINEAR_QUERY_GRANULARITY) return 0; /* No granularity or range. */
else return -1; /* Unknown function. */
}
 
static int r128_match_programmable_clock(int clock)
{
return clock ;
}
 
static int r128_map_clock(int bpp, int clock)
{
return clock ;
}
 
static int r128_map_horizontal_crtc(int bpp, int pixelclock, int htiming)
{
return htiming;
}
 
static unsigned int cur_colors[16*2];
 
static int r128_cursor( int cmd, int p1, int p2, int p3, int p4, void *p5) {
int i, j;
unsigned long *b3;
unsigned long l1, l2;
switch(cmd){
case CURSOR_INIT:
return 1;
case CURSOR_HIDE:
OUTREG(R128_CRTC_GEN_CNTL,INREG(R128_CRTC_GEN_CNTL) & ~R128_CRTC_CUR_EN );
break;
case CURSOR_SHOW:
OUTREG(R128_CRTC_GEN_CNTL,INREG(R128_CRTC_GEN_CNTL) | R128_CRTC_CUR_EN );
break;
case CURSOR_POSITION:
OUTREG(R128_CUR_HORZ_VERT_OFF, R128_CUR_LOCK | 0);
OUTREG(R128_CUR_HORZ_VERT_POSN, p2|(p1<<16));
break;
case CURSOR_SELECT:
i=r128_memory*1024-(p1+1)*4096;
OUTREG(R128_CUR_OFFSET,i);
OUTREG(R128_CUR_CLR0,cur_colors[p1*2]);
OUTREG(R128_CUR_CLR1,cur_colors[p1*2+1]);
break;
case CURSOR_IMAGE:
i=r128_memory*1024-(p1+1)*4096;
b3=(unsigned long *)p5;
switch(p2) {
case 0:
cur_colors[p1*2]=p3;
cur_colors[p1*2+1]=p4;
 
for(j=0;j<32;j++) {
l1=*(b3+j); /* source */
l2=*(b3+32+j); /* mask */
l1=BE32(l1);
l2=BE32(l2);
*(unsigned long *)(LINEAR_POINTER+i+16*j)=~l2;
*(unsigned long *)(LINEAR_POINTER+i+16*j+4)=0xffffffff;
*(unsigned long *)(LINEAR_POINTER+i+16*j+8)=l1&l2;
*(unsigned long *)(LINEAR_POINTER+i+16*j+12)=0;
*(unsigned long *)(LINEAR_POINTER+i+512+16*j)=0xffffffff;
*(unsigned long *)(LINEAR_POINTER+i+512+16*j+4)=0xffffffff;
*(unsigned long *)(LINEAR_POINTER+i+512+16*j+8)=0;
*(unsigned long *)(LINEAR_POINTER+i+512+16*j+12)=0;
}
break;
}
break;
}
return 0;
}
 
static Emulation r128_emul =
{
0,
0,
0,
0,
0,
0,
0, /* screenoff */
0, /* screenon */
R128WaitForVerticalSync, /* waitretrace */
};
 
static int r128_ext_set( unsigned what, va_list params )
{
int param2;
param2 = va_arg(params, int);
 
switch (what) {
case VGA_EXT_AVAILABLE:
switch (param2) {
case VGA_AVAIL_SET:
return VGA_EXT_AVAILABLE | VGA_EXT_SET | VGA_EXT_CLEAR | VGA_EXT_RESET;
case VGA_AVAIL_ACCEL:
return 0;
case VGA_AVAIL_FLAGS:
return VGA_CLUT8;
}
break;
case VGA_EXT_SET:
if (param2 & VGA_CLUT8) OUTREGP( R128_DAC_CNTL, R128_DAC_8BIT_EN, R128_DAC_MASK_ALL );
return 1;
break;
}
return 0;
}
 
/* Function table (exported) */
 
DriverSpecs __svgalib_r128_driverspecs =
{
r128_saveregs,
r128_setregs,
r128_unlock,
r128_lock,
r128_test,
r128_init,
r128_setpage,
NULL,
NULL,
r128_setmode,
r128_modeavailable,
r128_setdisplaystart,
r128_setlogicalwidth,
r128_getmodeinfo,
0, /* old blit funcs */
0,
0,
0,
0,
r128_ext_set, /* ext_set */
0, /* accel */
r128_linear,
0, /* accelspecs, filled in during init. */
&r128_emul, /* Emulation */
r128_cursor,
};
 
#define VENDOR_ID 0x1002
 
/* Initialize chipset (called after detection) */
static int r128_init(int force, int par1, int par2)
{
unsigned long buf[64];
int found=0, id, NOBIOS=0;
unsigned char *BIOS_POINTER;
char chipnames[2][9]={"Rage 128", "Radeon"};
 
if (force) {
r128_memory = par1;
chiptype = par2;
} else {
 
};
 
found=__svgalib_pci_find_vendor_vga(VENDOR_ID,buf,0);
 
if(found) return 0;
chiptype=-1;
id=(buf[0]>>16)&0xffff;
if( (id==0x4c45) ||
(id==0x4c56) ||
(id==0x4d46) ||
(id==0x4d4c) ||
((id>>8)==0x50) ||
((id>>8)==0x52) ||
((id>>8)==0x53) ||
((id>>8)==0x54))
chiptype=Rage128;
if( (id==0x4242) ||
(id==0x4c57) ||
(id==0x4c59) ||
(id==0x4c5a) ||
((id>>8)==0x51))
chiptype = Radeon;
if(chiptype==-1) return 0;
r128_linear_base=buf[4]&0xffffff00;
r128_mmio_base=buf[6]&0xffffff00;
 
MMIO_POINTER = (void *)r128_mmio_base;
 
r128_memory = INREG(R128_CONFIG_MEMSIZE) / 1024;
BusCntl = INREG(R128_BUS_CNTL);
HasPanelRegs = 0;
CRTOnly = 1;
r128_ramtype = 1;
 
#ifndef __PPC
if(__svgalib_secondary)
#endif
NOBIOS=1;
 
if(NOBIOS) {
int x_mpll_ref_fb_div, xclk_cntl, Nx, M;
int PostDivSet[] = {0, 1, 2, 4, 8, 3, 6, 12};
switch(chiptype) {
case Rage128:
pll.reference_freq = 2950;
pll.min_pll_freq = 12500;
pll.max_pll_freq = 25000;
pll.reference_div = INPLL(R128_PPLL_REF_DIV) & R128_PPLL_REF_DIV_MASK;
x_mpll_ref_fb_div = INPLL(R128_X_MPLL_REF_FB_DIV);
xclk_cntl = INPLL(R128_XCLK_CNTL) & 0x7;
Nx = (x_mpll_ref_fb_div & 0x00FF00) >> 8;
M = (x_mpll_ref_fb_div & 0x0000FF);
pll.xclk = R128Div((2 * Nx * pll.reference_freq),
(M * PostDivSet[xclk_cntl]));
break;
case Radeon:
pll.reference_freq = 2700;
pll.min_pll_freq = 12500;
pll.max_pll_freq = 35000;
pll.reference_div = 67;
pll.xclk = 16667;
break;
}
} else
#define R128_BIOS16(x) (*(unsigned short *)(BIOS_POINTER + x))
#define R128_BIOS32(x) (*(unsigned int *)(BIOS_POINTER + x))
{
uint16_t bios_header;
uint16_t pll_info_block;
BIOS_POINTER = (void *)0xc0000;
bios_header = R128_BIOS16(0x48);
pll_info_block = R128_BIOS16(bios_header + 0x30);
pll.reference_freq = R128_BIOS16(pll_info_block + 0x0e);
pll.reference_div = R128_BIOS16(pll_info_block + 0x10);
pll.min_pll_freq = R128_BIOS32(pll_info_block + 0x12);
pll.max_pll_freq = R128_BIOS32(pll_info_block + 0x16);
pll.xclk = R128_BIOS16(pll_info_block + 0x08);
}
#if 1
printk(KERN_INFO "pll: %i %i %i %i %i\n",pll.reference_freq,pll.reference_div,
pll.min_pll_freq, pll.max_pll_freq, pll.xclk);
#endif
 
r128_mapio();
if (__svgalib_driver_report) {
printk(KERN_INFO "Using ATI %s driver, %iKB.\n",chipnames[chiptype],r128_memory);
};
__svgalib_modeinfo_linearset |= IS_LINEAR;
cardspecs = malloc(sizeof(CardSpecs));
cardspecs->videoMemory = r128_memory;
cardspecs->maxPixelClock4bpp = 75000;
cardspecs->maxPixelClock8bpp = 250000;
cardspecs->maxPixelClock16bpp = 250000;
cardspecs->maxPixelClock24bpp = 250000;
cardspecs->maxPixelClock32bpp = 250000;
cardspecs->flags = INTERLACE_DIVIDE_VERT | CLOCK_PROGRAMMABLE;
cardspecs->maxHorizontalCrtc = 4080;
cardspecs->maxPixelClock4bpp = 0;
cardspecs->nClocks =0;
cardspecs->mapClock = r128_map_clock;
cardspecs->mapHorizontalCrtc = r128_map_horizontal_crtc;
cardspecs->matchProgrammableClock=r128_match_programmable_clock;
__svgalib_driverspecs = &__svgalib_r128_driverspecs;
__svgalib_banked_mem_base=0xa0000;
__svgalib_banked_mem_size=0x10000;
__svgalib_linear_mem_base=r128_linear_base;
__svgalib_linear_mem_size=r128_memory*0x400;
__svgalib_mmio_base=r128_mmio_base;
__svgalib_mmio_size=16*1024;
if(chiptype==Radeon) {
__svgalib_banked_mem_base=r128_linear_base;
__svgalib_r128_driverspecs.__svgalib_setpage = __svgalib_emul_setpage;
}
 
sleep(4);
return 1;
}
/shark/trunk/drivers/svga/vga.c
34,6 → 34,7
extern int init_vgapci(void);
extern int nv3_test(void);
extern int savage_test(void);
extern int r128_test(void);
 
/* If == 0 then nothing is defined by the user... */
int __svgalib_default_mode = 10;
823,6 → 824,16
graph_mem = GM; /* Exported variable. */
}
 
void __svgalib_emul_setpage(int page)
{
static int oldpage = -2;
 
if (page != oldpage)
{
oldpage = page;
}
}
 
static void map_vgaio(void)
{
__svgalib_inmisc=__svgalib_vga_inmisc;
972,9 → 983,10
 
/* SHARK: Supported Graphics Drivers
*
* NVIDIA
* SAVAGE
*
* NV3 (NVIDIA: GEFORCE/TNT/TNT2)
* SAVAGE (S3: VIRGE/SAVAGE
* R128 (ATI: RAGE 128/RADEON)
*
*/
CHIPSET = set_chipset;
991,6 → 1003,9
case SAVAGE:
savage_test();
break;
case R128:
r128_test();
break;
}
}
999,6 → 1014,40
 
}
 
int vga_getxdim(void)
{
return CI.xdim;
}
 
 
int vga_getydim(void)
{
return CI.ydim;
}
 
 
int vga_getcolors(void)
{
return CI.colors;
}
 
int vga_white(void)
{
switch (CI.colors) {
case 2:
case 16:
case 256:
return 15;
case 1 << 15:
return 32767;
case 1 << 16:
return 65535;
case 1 << 24:
return (1 << 24) - 1;
}
return CI.colors - 1;
}
 
void __svgalib_delay(void)
{
int i;
1346,3 → 1395,20
: "c" (memdiv2), "a" (src), "b" (dst));
 
}
 
inline void copy_videomem_16to16(void *src, void *dst, unsigned long int memdiv4)
{
__asm__ __volatile__("push %%esi
push %%edi
movl %1, %%esi
movl %2, %%edi
cld
rep
movsl
pop %%edi
pop %%esi"
:
: "c" (memdiv4), "a" (src), "b" (dst));
 
}
/shark/trunk/drivers/svga/vga.h
11,7 → 11,7
 
#include <sys/types.h>
#include <sys/time.h>
#include "./grx/glib.h"
#include <drivers/grxsvga/glib.h>
#include <kernel/log.h>
 
#ifdef __cplusplus
427,6 → 427,7
extern void vga_setcursorimage(int, int, int, int, unsigned char *);
 
inline void copy_videomem_32to16(void *src, void *dst, unsigned long int memdiv2);
inline void copy_videomem_16to16(void *src, void *dst, unsigned long int memdiv4);
 
extern int vga_setcrtcregs(unsigned char *);
extern int vga_getcrtcregs(unsigned char *);
/shark/trunk/drivers/svga/makefile
14,7 → 14,7
MODULES = timing.o vgaregs.o interface.o accel.o modetab.o interrupt.o\
vgapci.o vga_helper.o nv3.o vga.o vgadrv.o vgaio.o vgapal.o\
vgaclear.o vgadraw.o vgaaccel.o vgaline.o icd2061a.o\
./grx/glib.o vgammvgaio.o vgarelvgaio.o savage.o
./grx/glib.o vgammvgaio.o vgarelvgaio.o savage.o r128.o
RAMDAC = ramdac.o normal.o attdacs.o sierra.o vgamisc.o\
icw.o s3dacs.o IBMRGB52x.o ics_gendac.o