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/* File name ......... : pcl833.c |
* Object ............ : Port per SHARK dei driver del encoder PCL833 della Advantech |
* scaricati per DOS al sito della Advantech www.advantech.com |
* Author ............ : Cerri Pietro, Fracassi Matteo |
* Language .......... : C |
* Operative system .. : SHARK |
* Creation data ..... : 26/06/2001 |
* Last modify ....... : 29/06/2001 |
*/ |
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#include <ll/ll.h> |
#include "drivers/pcl833.h" |
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//Output Registers and Input Registers |
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int OutReg[16]; |
int InReg[16]; |
int Base; |
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//All fuctions are called through pcl833() |
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int pcl833(int func, int option); |
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//Functions |
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int vCh_SetInputMode(int ChannelNo, int option); |
int vCh_SetInputMode(int ChannelNo, int option); |
int vCh_SetInputMode(int ChannelNo, int option); |
int vCh_DefineResetValue(int ChannelNo, int option); |
int vCh_DefineResetValue(int ChannelNo, int option); |
int vCh_DefineResetValue(int ChannelNo, int option); |
int vCh_SetLatchSource(int ChannelNo, int option); |
int vCh_SetLatchSource(int ChannelNo, int option); |
int vCh_SetLatchSource(int ChannelNo, int option); |
int vCh_IfResetOnLatch(int ChannelNo, int option); |
int vCh_IfResetOnLatch(int ChannelNo, int option); |
int vCh_IfResetOnLatch(int ChannelNo, int option); |
int vLatchWhenOverflow(int option); |
int vCounterReset(int option); |
int vChooseSysClock(int option); |
int vSetCascadeMode(int option); |
int vSet16C54TimeBase(int option); |
int vSetDI1orTimerInt(int option); |
int vSet16C54Divider(int option); |
int vCh_Read(int option); |
int vStatus_Read(void); |
int vOverflow_Read(void); |
int vInitialize833(int option); |
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//:::::::::::::::::::::::::::::::::::::::::::::::::::::::: |
//: : |
//: All fuctions are called through pcl833() : |
//: : |
//:::::::::::::::::::::::::::::::::::::::::::::::::::::::: |
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int pcl833(int func, int option) { |
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switch(func) { |
case Ch1_SetInputMode : return(vCh_SetInputMode(ch1, option)); |
case Ch2_SetInputMode : return(vCh_SetInputMode(ch2, option)); |
case Ch3_SetInputMode : return(vCh_SetInputMode(ch3, option)); |
case Ch1_DefineResetValue : return(vCh_DefineResetValue(ch1, option)); |
case Ch2_DefineResetValue : return(vCh_DefineResetValue(ch2, option)); |
case Ch3_DefineResetValue : return(vCh_DefineResetValue(ch3, option)); |
case Ch1_SetLatchSource : return(vCh_SetLatchSource(ch1, option)); |
case Ch2_SetLatchSource : return(vCh_SetLatchSource(ch2, option)); |
case Ch3_SetLatchSource : return(vCh_SetLatchSource(ch3, option)); |
case Ch1_IfResetOnLatch : return(vCh_IfResetOnLatch(ch1, option)); |
case Ch2_IfResetOnLatch : return(vCh_IfResetOnLatch(ch2, option)); |
case Ch3_IfResetOnLatch : return(vCh_IfResetOnLatch(ch3, option)); |
case LatchWhenOverflow : return(vLatchWhenOverflow(option)); |
case CounterReset : return(vCounterReset(option)); |
case ChooseSysClock : return(vChooseSysClock(option)); |
case SetCascadeMode : return(vSetCascadeMode(option)); |
case Set16C54TimeBase : return(vSet16C54TimeBase(option)); |
case SetDI1orTimerInt : return(vSetDI1orTimerInt(option)); |
case Set16C54Divider : return(vSet16C54Divider(option)); |
case Ch_Read : return(vCh_Read(option)); |
case Status_Read : return(vStatus_Read()); |
case Overflow_Read : return(vOverflow_Read()); |
case Initialize833 : return(vInitialize833(option)); |
default : return(FUNCTION_NUM_ERR); |
} |
} |
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//::::::::::::::::::::::::::::::::::::::::::::::::: |
//: |
//::::::::::::::::::::::::::::::::::::::::::::::::: |
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int vInitialize833(int option) { |
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register int i; |
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Base = option; |
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for(i = 0; i < 16; i++) |
OutReg[i] = InReg[i] = 0; |
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vCh_SetInputMode(ch1, PclDisable); |
vCh_SetInputMode(ch2, PclDisable); |
vCh_SetInputMode(ch3, PclDisable); |
vCh_DefineResetValue(ch1, start); |
vCh_DefineResetValue(ch2, start); |
vCh_DefineResetValue(ch3, start); |
vCh_SetLatchSource(ch1, SwReadLatch); |
vCh_SetLatchSource(ch2, SwReadLatch); |
vCh_SetLatchSource(ch3, SwReadLatch); |
vCh_IfResetOnLatch(ch1, ResetNo); |
vCh_IfResetOnLatch(ch2, ResetNo); |
vCh_IfResetOnLatch(ch3, ResetNo); |
vLatchWhenOverflow(Latch_Ch1); |
vLatchWhenOverflow(Latch_Ch2); |
vLatchWhenOverflow(Latch_Ch3); |
vCounterReset(Reset_Ch1); |
vCounterReset(Reset_Ch2); |
vCounterReset(Reset_Ch3); |
vChooseSysClock(Sys8MHZ); |
vSetCascadeMode(c24bits); //no cascade |
vSet16C54TimeBase(tPoint1ms); |
vSetDI1orTimerInt(TimerInt); |
vSet16C54Divider(0); // 0-255 divider |
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return(OK); |
} |
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//::::::::::::::::::::::::::::::::::::::::::::::::: |
//: |
//::::::::::::::::::::::::::::::::::::::::::::::::: |
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int vCh_SetInputMode(int ChannelNo, int option) { |
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int OutputReg, PortAddress, RegIndex; |
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switch(ChannelNo) { |
case ch1: PortAddress = Base + 0; RegIndex = 0; break; |
case ch2: PortAddress = Base + 1; RegIndex = 1; break; |
case ch3: PortAddress = Base + 2; RegIndex = 2; break; |
default: return(CHANNEL_NUM_ERR); |
} |
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OutputReg = OutReg[RegIndex] & 0x08; |
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switch(option) { |
case x1: |
case x2: |
case x4: |
case PclDisable: |
case TwoPulseIn: |
case OnePulseIn: outp(PortAddress, OutputReg | option); break; |
default: return(PARAMETER_ERR); |
} |
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OutReg[RegIndex] = OutputReg | option; |
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return(OK); |
} |
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//::::::::::::::::::::::::::::::::::::::::::::::::: |
//: |
//::::::::::::::::::::::::::::::::::::::::::::::::: |
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int vCh_DefineResetValue(int ChannelNo, int option) { |
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int OutputReg, PortAddress, RegIndex; |
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switch(ChannelNo) { |
case ch1: PortAddress = Base + 0; RegIndex = 0; break; |
case ch2: PortAddress = Base + 1; RegIndex = 1; break; |
case ch3: PortAddress = Base + 2; RegIndex = 2; break; |
default: return(CHANNEL_NUM_ERR); |
} |
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OutputReg = OutReg[RegIndex] & 0x07; |
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switch(option) { |
case start: |
case middle: outp(PortAddress, OutputReg | option); break; |
default: return(PARAMETER_ERR); |
} |
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OutReg[RegIndex] = OutputReg | option; |
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return(OK); |
} |
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//::::::::::::::::::::::::::::::::::::::::::::::::: |
//: |
//::::::::::::::::::::::::::::::::::::::::::::::::: |
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int vCh_SetLatchSource(int ChannelNo, int option) { |
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int OutputReg, PortAddress, RegIndex; |
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switch(ChannelNo) { |
case ch1: PortAddress = Base + 3; RegIndex = 3; break; |
case ch2: PortAddress = Base + 4; RegIndex = 4; break; |
case ch3: PortAddress = Base + 5; RegIndex = 5; break; |
default: return(CHANNEL_NUM_ERR); |
} |
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OutputReg = OutReg[RegIndex] & 0x08; |
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switch(option) { |
case SwReadLatch: |
case IndexInLatch: |
case DI0Latch: |
case DI1Latch: |
case TimerLatch: outp(PortAddress, OutputReg | option); break; |
default: return(PARAMETER_ERR); |
} |
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OutReg[RegIndex] = OutputReg | option; |
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return(OK); |
} |
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//::::::::::::::::::::::::::::::::::::::::::::::::: |
//: |
//::::::::::::::::::::::::::::::::::::::::::::::::: |
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int vCh_IfResetOnLatch(int ChannelNo, int option) { |
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int OutputReg, PortAddress, RegIndex; |
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switch(ChannelNo) { |
case ch1: PortAddress= Base + 3; RegIndex = 3; break; |
case ch2: PortAddress= Base + 4; RegIndex = 4; break; |
case ch3: PortAddress= Base + 5; RegIndex = 5; break; |
default: return(CHANNEL_NUM_ERR); |
} |
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OutputReg = OutReg[RegIndex] & 0x07; |
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switch(option) { |
case ResetNo: |
case ResetYes: outp(PortAddress, OutputReg | option); break; |
default: return(PARAMETER_ERR); |
} |
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OutReg[RegIndex] = OutputReg | option; |
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return(OK); |
} |
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//::::::::::::::::::::::::::::::::::::::::::::::::: |
//: |
//::::::::::::::::::::::::::::::::::::::::::::::::: |
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int vLatchWhenOverflow(int option) { |
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switch(option){ |
case Latch_Ch1: OutReg[6] &= 0x06; break; |
case Latch_Ch2: OutReg[6] &= 0x05; break; |
case Latch_Ch3: OutReg[6] &= 0x03; break; |
case FreeAll: OutReg[6] = 0x07; break; |
default: return(PARAMETER_ERR); |
} |
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outp(Base + 6, OutReg[6]); |
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return(OK); |
} |
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//::::::::::::::::::::::::::::::::::::::::::::::::: |
//: |
//::::::::::::::::::::::::::::::::::::::::::::::::: |
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int vCounterReset(int option) { |
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switch(option) { |
case Reset_Ch1: OutReg[7] &= 0x06; |
OutReg[7] |= 0x01; |
break; |
case Reset_Ch2: OutReg[7] &= 0x05; |
OutReg[7] |= 0x02; |
break; |
case Reset_Ch3: OutReg[7] &= 0x03; |
OutReg[7] |= 0x04; |
break; |
case NoneReset: OutReg[7] = 0; |
break; |
default: return(PARAMETER_ERR); |
} |
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outp(Base + 7, OutReg[7]); |
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return(OK); |
} |
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//::::::::::::::::::::::::::::::::::::::::::::::::: |
//: |
//::::::::::::::::::::::::::::::::::::::::::::::::: |
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int vChooseSysClock(option) { |
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int OutputReg; |
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OutputReg = OutReg[8] & 0x0c; |
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switch(option) { |
case Sys8MHZ: |
case Sys4MHZ: |
case Sys2MHZ: outp(Base + 8, OutputReg | option); break; |
default: return(PARAMETER_ERR); |
} |
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OutReg[8] = OutputReg | option; |
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return(OK); |
} |
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//::::::::::::::::::::::::::::::::::::::::::::::::: |
//: |
//::::::::::::::::::::::::::::::::::::::::::::::::: |
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int vSetCascadeMode(option) { |
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int OutputReg; |
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OutputReg = OutReg[8] & 0x03; |
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switch(option) { |
case c24bits: // no cascade |
outp(Base + 8, OutputReg | option); |
break; |
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case c48bits: // ch1 ch2 cascade |
OutReg[1] |= 0x07; // set ch2 cascade mode |
OutReg[0] &= 0x07; // set ch1 reset value '000000' |
outp(Base + 1, OutReg[1]); |
outp(Base, OutReg[0]); |
outp(Base + 8, OutputReg | option); |
vCh_SetInputMode(ch2, cascade); |
break; |
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default: |
return(PARAMETER_ERR); |
} |
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OutReg[8] = OutputReg | option; |
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return(OK); |
} |
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//::::::::::::::::::::::::::::::::::::::::::::::::: |
//: |
//::::::::::::::::::::::::::::::::::::::::::::::::: |
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int vSet16C54TimeBase(option) { |
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int OutputReg; |
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OutputReg = OutReg[9] & 0x08; |
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switch(option) { |
case tPoint1ms: |
case t1ms: |
case t10ms: |
case t100ms: |
case t1s: outp(Base + 9, OutputReg | option); break; |
default: return(PARAMETER_ERR); |
} |
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OutReg[9] = OutputReg | option; |
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return(OK); |
} |
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//::::::::::::::::::::::::::::::::::::::::::::::::: |
//: |
//::::::::::::::::::::::::::::::::::::::::::::::::: |
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int vSetDI1orTimerInt(option) { |
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int OutputReg; |
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OutputReg = OutReg[9] & 0x07; |
switch(option) { |
case DI1Int : |
case TimerInt : outp(Base + 9, OutputReg | option); break; |
default: return(PARAMETER_ERR); |
} |
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OutReg[9] = OutputReg | option; |
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return(OK); |
} |
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//::::::::::::::::::::::::::::::::::::::::::::::::: |
//: |
//::::::::::::::::::::::::::::::::::::::::::::::::: |
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int vSet16C54Divider(option) { |
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outp(Base + 10, option); |
OutReg[10] = option; |
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return(OK); |
} |
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//::::::::::::::::::::::::::::::::::::::::::::::::: |
//: READ FUNCTION |
//::::::::::::::::::::::::::::::::::::::::::::::::: |
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int vCh_Read(int ChannelNo) { |
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switch(ChannelNo) { |
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case ch1: |
InReg[2] = inp(Base + 2); |
InReg[0] = inp(Base); |
InReg[1] = inp(Base + 1); |
break; |
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case ch2: |
InReg[6] = inp(Base + 6); |
InReg[4] = inp(Base + 4); |
InReg[5] = inp(Base + 5); |
break; |
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case ch3: |
InReg[10] = inp(Base + 10); |
InReg[8] = inp(Base + 8); |
InReg[9] = inp(Base + 9); |
break; |
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default: |
return(CHANNEL_NUM_ERR); |
} |
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return(OK); |
} |
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//::::::::::::::::::::::::::::::::::::::::::::::::: |
//: |
//::::::::::::::::::::::::::::::::::::::::::::::::: |
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int vOverflow_Read(void) { |
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InReg[3] = inp(Base + 3); |
InReg[7] = inp(Base + 7); |
InReg[11] = inp(Base + 11); |
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return(OK); |
} |
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//::::::::::::::::::::::::::::::::::::::::::::::::: |
//: |
//::::::::::::::::::::::::::::::::::::::::::::::::: |
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int vStatus_Read(void) { |
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InReg[14] = inp(Base + 14); |
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return(OK); |
} |