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Ignore whitespace Rev 646 → Rev 648

/shark/trunk/oslib/kl/event.c
232,8 → 232,7
TIME t;
DWORD apic_clk;
 
if (use_tsc)
ll_init_advtimer();
ll_init_advtimer();
 
if (use_apic)
IDT_place(0x39,ll_apic_timer);
/shark/trunk/oslib/kl/advtimer.c
39,8 → 39,8
unsigned long long init_tsc;
unsigned long long * ptr_init_tsc = &init_tsc;
 
unsigned long long init_nsec;
unsigned long long * ptr_init_nsec = &init_nsec;
struct timespec init_time;
struct timespec * ptr_init_time = &init_time;
 
unsigned int clk_per_msec = 0;
unsigned int apic_clk_per_msec = 0;
443,7 → 443,8
#endif
 
rdtscll(init_tsc); // Read start TSC
init_nsec = 0;
init_time.tv_sec = 0;
init_time.tv_nsec = 0;
 
if (use_apic) {
rdmsr(APIC_BASE_MSR, msr_low_orig, tmp);
485,17 → 486,22
unsigned long temp;
SYS_FLAGS f;
 
f = ll_fsave();
if (use_tsc) {
f = ll_fsave();
 
mul32div32to32(clk_per_msec,new_f,old_f,temp); /* TODO */
clk_per_msec = temp;
dtsc = clk_per_msec * 500;
clk_opt_0 = (unsigned int)(dtsc);
clk_opt_1 = (unsigned int)((unsigned long long)(dtsc << 1));
clk_opt_2 = (unsigned int)((unsigned long long)(dtsc << 33) / 1000000000L);
clk_opt_3 = (unsigned int)((unsigned long long)(dtsc << 32) / 1000000000L);
clk_opt_4 = (unsigned int)((unsigned long long)(dtsc << 31) / 1000000000L);
clk_opt_5 = (unsigned int)((unsigned long long)(dtsc << 30) / 1000000000L);
rdtscll(init_tsc); // Set new start TSC
ll_read_timespec(&init_time); // Set new start TimeSpec
mul32div32to32(clk_per_msec,new_f,old_f,temp);
clk_per_msec = temp;
dtsc = (unsigned long long)(clk_per_msec) * 500;
clk_opt_0 = (unsigned int)(dtsc);
clk_opt_1 = (unsigned int)((unsigned long long)(dtsc << 1));
clk_opt_2 = (unsigned int)((unsigned long long)(dtsc << 33) / 1000000000L);
clk_opt_3 = (unsigned int)((unsigned long long)(dtsc << 32) / 1000000000L);
clk_opt_4 = (unsigned int)((unsigned long long)(dtsc << 31) / 1000000000L);
clk_opt_5 = (unsigned int)((unsigned long long)(dtsc << 30) / 1000000000L);
 
ll_frestore(f);
ll_frestore(f);
}
}
/shark/trunk/oslib/ll/i386/advtimer.h
36,31 → 36,31
/* TSC */
 
#define rdtsc(low,high) \
__asm__ __volatile__("xorl %%eax,%%eax\n\t" \
"cpuid\n\t" \
"rdtsc\n\t" \
: "=a" (low), "=d" (high) \
:: "ebx", "ecx")
__asm__ __volatile__("xorl %%eax,%%eax\n\t" \
"cpuid\n\t" \
"rdtsc\n\t" \
: "=a" (low), "=d" (high) \
:: "ebx", "ecx")
 
#define rdtscll(val) \
__asm__ __volatile__("xorl %%eax,%%eax\n\t" \
"cpuid\n\t" \
"rdtsc\n\t" \
: "=A" (val) \
:: "ebx","ecx")
__asm__ __volatile__("xorl %%eax,%%eax\n\t" \
"cpuid\n\t" \
"rdtsc\n\t" \
: "=A" (val) \
:: "ebx","ecx")
 
#ifdef __O1000__
#define ll_read_timespec ll_read_timespec_1000
#define ll_read_timespec ll_read_timespec_1000
#else
#ifdef __02000__
#define ll_read_timespec ll_read_timespec_2000
#else
#ifdef __O4000__
#define ll_read_timespec ll_read_timespec_4000
#else
#define ll_read_timespec ll_read_timespec_8000
#endif
#endif
#ifdef __02000__
#define ll_read_timespec ll_read_timespec_2000
#else
#ifdef __O4000__
#define ll_read_timespec ll_read_timespec_4000
#else
#define ll_read_timespec ll_read_timespec_8000
#endif
#endif
#endif
 
//Low level time read function: Optimized for CPU < 1 GHz
142,40 → 142,48
//Low level time read function
extern __inline__ void ll_read_timespec_8000(struct timespec *tspec)
{
extern unsigned int clk_opt_0,clk_opt_5;
extern unsigned long long *ptr_init_tsc;
extern unsigned int clk_opt_0,clk_opt_5;
extern unsigned long long *ptr_init_tsc;
extern struct timespec init_time;
if (clk_opt_0 == 0) {
NULL_TIMESPEC(tspec);
return;
}
 
if (clk_opt_0 == 0) {
NULL_TIMESPEC(tspec);
return;
}
 
__asm__("rdtsc\n\t"
"subl (%%edi),%%eax\n\t"
"sbbl 4(%%edi),%%edx\n\t"
"shrdl $1,%%edx,%%eax\n\t"
"shrl %%edx\n\t"
"divl %%ebx\n\t"
"movl %%eax,%%ebx\n\t"
"xorl %%eax,%%eax\n\t"
"shrdl $2,%%edx,%%eax\n\t"
"shrl $2,%%edx\n\t"
"divl %%ecx\n\t"
: "=b" (tspec->tv_sec), "=a" (tspec->tv_nsec)
: "D" (ptr_init_tsc), "b" (clk_opt_0), "c" (clk_opt_5)
: "edx");
__asm__("rdtsc\n\t"
"subl (%%edi),%%eax\n\t"
"sbbl 4(%%edi),%%edx\n\t"
"shrdl $1,%%edx,%%eax\n\t"
"shrl %%edx\n\t"
"divl %%ebx\n\t"
"movl %%eax,%%ebx\n\t"
"xorl %%eax,%%eax\n\t"
"shrdl $2,%%edx,%%eax\n\t"
"shrl $2,%%edx\n\t"
"divl %%ecx\n\t"
: "=b" (tspec->tv_sec), "=a" (tspec->tv_nsec)
: "D" (ptr_init_tsc), "b" (clk_opt_0), "c" (clk_opt_5)
: "edx");
if (init_time.tv_sec != 0 || init_time.tv_nsec != 0) {
__asm__("divl %%ecx\n\t"
"addl %%ebx,%%eax\n\t"
:"=a" (tspec->tv_sec), "=d" (tspec->tv_nsec)
:"a" (init_time.tv_nsec+tspec->tv_nsec), "b" (tspec->tv_sec+init_time.tv_sec), "c" (0x3B9ACA00), "d" (0));
};
}
 
#define rdmsr(msr,val1,val2) \
__asm__ __volatile__("rdmsr" \
: "=a" (val1), "=d" (val2) \
: "c" (msr))
__asm__ __volatile__("rdmsr" \
: "=a" (val1), "=d" (val2) \
: "c" (msr))
#define wrmsr(msr,val1,val2) \
__asm__ __volatile__("wrmsr" \
: /* no outputs */ \
: "c" (msr), "a" (val1), "d" (val2))
__asm__ __volatile__("wrmsr" \
: /* no outputs */ \
: "c" (msr), "a" (val1), "d" (val2))
 
/* RTC */
 
/shark/trunk/oslib/xlib/xinit.c
73,8 → 73,8
{
register int i;
struct ll_cpuInfo cpuInfo;
extern BYTE X86_apic;
extern BYTE X86_tsc;
extern unsigned char X86_apic;
extern unsigned char X86_tsc;
extern BYTE X86_fpu;
LIN_ADDR b;
89,8 → 89,8
ll_arch.x86.fpu = X86_fpu;
memcpy(&(ll_arch.x86.vendor), &(cpuInfo.X86_vendor_1), 12);
X86_apic = cpuInfo.X86_StandardFeature & (1<<4);
X86_tsc = cpuInfo.X86_StandardFeature & (1<<9);
X86_apic = (cpuInfo.X86_StandardFeature>>4) & 1;
X86_tsc = (cpuInfo.X86_StandardFeature>>9) & 1;
/* TODO! Need to map featuresXXX & Signature onto ll_arch! */
/* TODO! Need to check for CPU bugs!! */