| /shark/trunk/drivers/bttv/btcx-risc.c |
|---|
| 46,6 → 46,8 |
| static int memcnt; |
| extern void vfree_32(void *t); |
| void btcx_riscmem_free(struct pci_dev *pci, |
| struct btcx_riscmem *risc) |
| { |
| 52,6 → 54,7 |
| if (NULL == risc->cpu) |
| return; |
| pci_free_consistent(pci, risc->size, risc->cpu, risc->dma); |
| vfree_32((void *)risc->cpu); |
| memset(risc,0,sizeof(*risc)); |
| if (debug) { |
| memcnt--; |
| /shark/trunk/drivers/bttv/bttv-driver.c |
|---|
| 1005,8 → 1005,7 |
| btwrite(BT848_CONTROL_LDEC, BT848_E_CONTROL); |
| btwrite(BT848_CONTROL_LDEC, BT848_O_CONTROL); |
| } |
| /* interrupt */ |
| /* |
| btwrite(0xfffffUL, BT848_INT_STAT); |
| btwrite((btv->triton1) | |
| BT848_INT_GPINT | |
| 1015,6 → 1014,8 |
| BT848_INT_RISCI|BT848_INT_OCERR|BT848_INT_VPRES| |
| BT848_INT_FMTCHG|BT848_INT_HLOCK, |
| BT848_INT_MASK); |
| */ |
| } |
| extern void bttv_reinit_bt848(struct bttv *btv) |
| 3579,11 → 3580,13 |
| /* pci stuff (init, get irq/mmio, ... */ |
| btv->dev = dev; |
| btv->id = dev->device; |
| if (pci_enable_device(dev)) { |
| printk(KERN_WARNING "bttv%d: Can't enable device.\n", |
| btv->nr); |
| return -EIO; |
| } |
| if (pci_set_dma_mask(dev, 0xffffffff)) { |
| printk(KERN_WARNING "bttv%d: No suitable DMA available.\n", |
| btv->nr); |
| 3596,6 → 3599,7 |
| btv->nr, pci_resource_start(dev,0)); |
| return -EBUSY; |
| } |
| pci_set_master(dev); |
| pci_set_command(dev); |
| pci_set_drvdata(dev,btv); |
| 3611,8 → 3615,9 |
| bttv_num,btv->id, btv->revision, pci_name(dev)); |
| printk("irq: %d, latency: %d, mmio: 0x%lx\n", |
| btv->dev->irq, lat, pci_resource_start(dev,0)); |
| //schedule(); |
| udelay(1000); |
| btv->bt848_mmio=ioremap(pci_resource_start(dev,0), 0x1000); |
| if (NULL == ioremap(pci_resource_start(dev,0), 0x1000)) { |
| printk("bttv%d: ioremap() failed\n", btv->nr); |
| 3670,9 → 3675,17 |
| if (bttv_gpio) |
| bttv_gpio_tracking(btv,"init"); |
| cprintf("Critical Point 1\n"); |
| for (result=1;result<1000000000;result++); |
| cprintf("Critical Point End 1\n"); |
| /* needs to be done before i2c is registered */ |
| bttv_init_card1(btv); |
| cprintf("Critical Point 2\n"); |
| mdelay(1000); |
| cprintf("Critical Point End 2\n"); |
| /* register i2c */ |
| init_bttv_i2c(btv); |
| /shark/trunk/drivers/newpci/pool.c |
|---|
| 292,7 → 292,7 |
| if (mem_flags == SLAB_KERNEL) { |
| DECLARE_WAITQUEUE (wait, current); |
| current->state = TASK_INTERRUPTIBLE; |
| //current->state = TASK_INTERRUPTIBLE; |
| add_wait_queue (&pool->waitq, &wait); |
| spin_unlock_irqrestore (&pool->lock, flags); |
| /shark/trunk/drivers/newpci/pci.c |
|---|
| 1,5 → 1,5 |
| /* |
| * $Id: pci.c,v 1.7 2004-03-19 16:30:11 giacomo Exp $ |
| * $Id: pci.c,v 1.8 2004-03-29 18:19:41 giacomo Exp $ |
| * |
| * PCI Bus Services, see include/linux/pci.h for further explanation. |
| * |
| 270,7 → 270,7 |
| /* see PCI PM 1.1 5.6.1 table 18 */ |
| if(state == 3 || dev->current_state == 3) |
| { |
| set_current_state(TASK_UNINTERRUPTIBLE); |
| //set_current_state(TASK_UNINTERRUPTIBLE); |
| schedule_timeout(HZ/100); |
| } |
| else if(state == 2 || dev->current_state == 2) |
| 349,6 → 349,7 |
| pci_set_power_state(dev, 0); |
| if ((err = pcibios_enable_device(dev, bars)) < 0) |
| return err; |
| return 0; |
| } |
| /shark/trunk/drivers/newpci/shark_pci26.c |
|---|
| 22,6 → 22,7 |
| extern int pci_direct_init(void); |
| extern int pcibios_init(void); |
| extern int pcibios_irq_init(void); |
| extern int pci_driver_init(void); |
| extern int pci_legacy_init(void); |
| extern int pci_init(void); |
| 32,6 → 33,8 |
| pci_direct_init(); |
| pcibios_init(); |
| pcibios_irq_init(); |
| pci_driver_init(); |
| /shark/trunk/drivers/newpci/irq.c |
|---|
| 893,7 → 893,7 |
| } |
| } |
| static int __init pcibios_irq_init(void) |
| int __init pcibios_irq_init(void) |
| { |
| DBG("PCI: IRQ init\n"); |
| /shark/trunk/drivers/linuxc26/linuxcomp.c |
|---|
| 16,6 → 16,8 |
| #include <linux/tty.h> |
| #include <asm/setup.h> |
| #define memory_barrier __asm__("" ::: "memory") |
| extern unsigned long intr_count; |
| extern int activeInt; |
| 252,9 → 254,14 |
| ll_gettime(TIME_NEW,&s); |
| ADDTIMESPEC(&t,&s,&e); |
| memory_barrier; |
| while(TIMESPEC_A_LT_B(&s,&e)) { |
| memory_barrier; |
| ll_gettime(TIME_NEW,&s); |
| } |
| while(TIMESPEC_A_LT_B(&s,&e)) ll_gettime(TIME_NEW,&s); |
| } |
| return 0; |
| 277,13 → 284,21 |
| ll_gettime(TIME_NEW,&e); |
| ADDUSEC2TIMESPEC(usecs,&e); |
| memory_barrier; |
| ll_gettime(TIME_NEW,&s); |
| while(TIMESPEC_A_LT_B(&s,&e)) ll_gettime(TIME_NEW,&s); |
| while(TIMESPEC_A_LT_B(&s,&e)) { |
| memory_barrier; |
| ll_gettime(TIME_NEW,&s); |
| } |
| } |
| } |
| void * vmalloc_32(size_t size); |
| void vfree_32(void *ptr); |
| void *dma_alloc_coherent(struct device *dev, size_t size, |
| dma_addr_t *dma_handle, int gfp) |
| { |
| 293,7 → 308,7 |
| if (dev == NULL || (*dev->dma_mask < 0xffffffff)) |
| gfp |= GFP_DMA; |
| ret = (void *)malloc(size); |
| ret = (void *)vmalloc_32(size); |
| if (ret != NULL) { |
| memset(ret, 0, size); |
| 305,7 → 320,7 |
| void dma_free_coherent(struct device *dev, size_t size, |
| void *vaddr, dma_addr_t dma_handle) |
| { |
| free((void *)dma_handle); |
| vfree_32((void *)dma_handle); |
| } |
| void init_completion(struct completion *x) { |
| 345,6 → 360,28 |
| } |
| void * vmalloc_32(size_t size) |
| { |
| void *mem; |
| unsigned long diff; |
| mem = malloc(size+8); |
| diff = (unsigned long)((((unsigned long)mem/4)+1)*4-(unsigned long)mem); |
| *(unsigned long *)(mem+diff) = (unsigned long)diff; |
| return (mem+diff+4); |
| } |
| void vfree_32(void *ptr) |
| { |
| free(ptr-4-*(unsigned long *)(ptr-4)); |
| } |
| void vfree(void *addr) { |
| return free(addr); |