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• This comparison shows the changes necessary to convert path

  → /shark/trunk/drivers/fb/ @ 471

  → /shark/trunk/drivers/fb/ @ 472

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• Compare Path:	Rev

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Ignore whitespace Rev 471 → Rev 472

/shark/trunk/drivers/fb/radeonfb.c
0,0 → 1,3178
/*
* drivers/video/radeonfb.c
* framebuffer driver for ATI Radeon chipset video boards
*
* Copyright 2000 Ani Joshi <ajoshi@kernel.crashing.org>
*
*
* ChangeLog:
* 2000-08-03 initial version 0.0.1
* 2000-09-10 more bug fixes, public release 0.0.5
* 2001-02-19 mode bug fixes, 0.0.7
* 2001-07-05 fixed scrolling issues, engine initialization,
* and minor mode tweaking, 0.0.9
* 2001-09-07 Radeon VE support, Nick Kurshev
* blanking, pan_display, and cmap fixes, 0.1.0
* 2001-10-10 Radeon 7500 and 8500 support, and experimental
* flat panel support, 0.1.1
* 2001-11-17 Radeon M6 (ppc) support, Daniel Berlin, 0.1.2
* 2001-11-18 DFP fixes, Kevin Hendricks, 0.1.3
* 2001-11-29 more cmap, backlight fixes, Benjamin Herrenschmidt
* 2002-01-18 DFP panel detection via BIOS, Michael Clark, 0.1.4
* 2002-06-02 console switching, mode set fixes, accel fixes
* 2002-06-03 MTRR support, Peter Horton, 0.1.5
* 2002-09-21 rv250, r300, m9 initial support,
* added mirror option, 0.1.6
*
* Special thanks to ATI DevRel team for their hardware donations.
*
*/
#define RADEON_VERSION "0.1.6"
#include <linuxcomp.h>
#include <linux/config.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/string.h>
#include <linux/mm.h>
#include <linux/tty.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/fb.h>
#include <linux/ioport.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/vmalloc.h>
#include <asm/io.h>
#include <asm/uaccess.h>
#if defined(__powerpc__)
#include <asm/prom.h>
#include <asm/pci-bridge.h>
#include "macmodes.h"
#ifdef CONFIG_NVRAM
#include <linux/nvram.h>
#endif
#ifdef CONFIG_PMAC_BACKLIGHT
#include <asm/backlight.h>
#endif
#ifdef CONFIG_BOOTX_TEXT
#include <asm/btext.h>
#endif
#ifdef CONFIG_ADB_PMU
#include <linux/adb.h>
#include <linux/pmu.h>
#endif
#endif /* __powerpc__ */
#ifdef CONFIG_MTRR
#include <asm/mtrr.h>
#endif
#include <video/radeon.h>
#include <linux/radeonfb.h>
#define DEBUG 1
#if DEBUG
#define RTRACE printk
#else
#define RTRACE if(0) printk
#endif
// XXX
#undef CONFIG_PMAC_PBOOK
enum radeon_chips {
RADEON_QD,
RADEON_QE,
RADEON_QF,
RADEON_QG,
RADEON_QY,
RADEON_QZ,
RADEON_LW,
RADEON_LX,
RADEON_LY,
RADEON_LZ,
RADEON_QL,
RADEON_QN,
RADEON_QO,
RADEON_Ql,
RADEON_BB,
RADEON_QW,
RADEON_QX,
RADEON_Id,
RADEON_Ie,
RADEON_If,
RADEON_Ig,
RADEON_Ld,
RADEON_Le,
RADEON_Lf,
RADEON_Lg,
RADEON_ND,
RADEON_NE,
RADEON_NF,
RADEON_NG,
RADEON_QM
};
enum radeon_arch {
RADEON_R100,
RADEON_RV100,
RADEON_R200,
RADEON_RV200,
RADEON_RV250,
RADEON_R300,
RADEON_M6,
RADEON_M7,
RADEON_M9
};
static struct radeon_chip_info {
const char *name;
unsigned char arch;
} radeon_chip_info[] __devinitdata = {
{ "QD", RADEON_R100 },
{ "QE", RADEON_R100 },
{ "QF", RADEON_R100 },
{ "QG", RADEON_R100 },
{ "VE QY", RADEON_RV100 },
{ "VE QZ", RADEON_RV100 },
{ "M7 LW", RADEON_M7 },
{ "M7 LX", RADEON_M7 },
{ "M6 LY", RADEON_M6 },
{ "M6 LZ", RADEON_M6 },
{ "8500 QL", RADEON_R200 },
{ "8500 QN", RADEON_R200 },
{ "8500 QO", RADEON_R200 },
{ "8500 Ql", RADEON_R200 },
{ "8500 BB", RADEON_R200 },
{ "7500 QW", RADEON_RV200 },
{ "7500 QX", RADEON_RV200 },
{ "9000 Id", RADEON_RV250 },
{ "9000 Ie", RADEON_RV250 },
{ "9000 If", RADEON_RV250 },
{ "9000 Ig", RADEON_RV250 },
{ "M9 Ld", RADEON_M9 },
{ "M9 Le", RADEON_M9 },
{ "M9 Lf", RADEON_M9 },
{ "M9 Lg", RADEON_M9 },
{ "9700 ND", RADEON_R300 },
{ "9700 NE", RADEON_R300 },
{ "9700 NF", RADEON_R300 },
{ "9700 NG", RADEON_R300 },
{ "9100 QM", RADEON_R200 }
};
enum radeon_montype
{
MT_NONE,
MT_CRT, /* CRT */
MT_LCD, /* LCD */
MT_DFP, /* DVI */
MT_CTV, /* composite TV */
MT_STV /* S-Video out */
};
static struct pci_device_id radeonfb_pci_table[] = {
{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_QD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QD},
{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_QE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QE},
{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_QF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QF},
{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_QG, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QG},
{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_QY, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QY},
{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_QZ, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QZ},
{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_LW, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_LW},
{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_LX, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_LX},
{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_LY, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_LY},
{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_LZ, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_LZ},
{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_QL, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QL},
{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_QN, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QN},
{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_QO, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QO},
{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_Ql, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_Ql},
{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_BB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_BB},
{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_QW, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QW},
{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_QX, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QX},
{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_Id, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_Id},
{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_Ie, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_Ie},
{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_If, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_If},
{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_Ig, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_Ig},
{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_Ld, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_Ld},
{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_Le, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_Le},
{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_Lf, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_Lf},
{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_Lg, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_Lg},
{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_ND, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_ND},
{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_NE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_NE},
{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_NF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_NF},
{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_NG, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_NG},
{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_QM, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QM},
{ 0, }
};
MODULE_DEVICE_TABLE(pci, radeonfb_pci_table);
typedef struct {
u16 reg;
u32 val;
} reg_val;
/* these common regs are cleared before mode setting so they do not
* interfere with anything
*/
reg_val common_regs[] = {
{ OVR_CLR, 0 },
{ OVR_WID_LEFT_RIGHT, 0 },
{ OVR_WID_TOP_BOTTOM, 0 },
{ OV0_SCALE_CNTL, 0 },
{ SUBPIC_CNTL, 0 },
{ VIPH_CONTROL, 0 },
{ I2C_CNTL_1, 0 },
{ GEN_INT_CNTL, 0 },
{ CAP0_TRIG_CNTL, 0 },
};
reg_val common_regs_m6[] = {
{ OVR_CLR, 0 },
{ OVR_WID_LEFT_RIGHT, 0 },
{ OVR_WID_TOP_BOTTOM, 0 },
{ OV0_SCALE_CNTL, 0 },
{ SUBPIC_CNTL, 0 },
{ GEN_INT_CNTL, 0 },
{ CAP0_TRIG_CNTL, 0 }
};
typedef struct {
u8 clock_chip_type;
u8 struct_size;
u8 accelerator_entry;
u8 VGA_entry;
u16 VGA_table_offset;
u16 POST_table_offset;
u16 XCLK;
u16 MCLK;
u8 num_PLL_blocks;
u8 size_PLL_blocks;
u16 PCLK_ref_freq;
u16 PCLK_ref_divider;
u32 PCLK_min_freq;
u32 PCLK_max_freq;
u16 MCLK_ref_freq;
u16 MCLK_ref_divider;
u32 MCLK_min_freq;
u32 MCLK_max_freq;
u16 XCLK_ref_freq;
u16 XCLK_ref_divider;
u32 XCLK_min_freq;
u32 XCLK_max_freq;
} __attribute__ ((packed)) PLL_BLOCK;
struct pll_info {
int ppll_max;
int ppll_min;
int xclk;
int ref_div;
int ref_clk;
};
struct ram_info {
int ml;
int mb;
int trcd;
int trp;
int twr;
int cl;
int tr2w;
int loop_latency;
int rloop;
};
struct radeon_regs {
/* CRTC regs */
u32 crtc_h_total_disp;
u32 crtc_h_sync_strt_wid;
u32 crtc_v_total_disp;
u32 crtc_v_sync_strt_wid;
u32 crtc_pitch;
u32 crtc_gen_cntl;
u32 crtc_ext_cntl;
u32 dac_cntl;
u32 flags;
u32 pix_clock;
int xres, yres;
/* DDA regs */
u32 dda_config;
u32 dda_on_off;
/* PLL regs */
u32 ppll_div_3;
u32 ppll_ref_div;
u32 vclk_ecp_cntl;
/* Flat panel regs */
u32 fp_crtc_h_total_disp;
u32 fp_crtc_v_total_disp;
u32 fp_gen_cntl;
u32 fp_h_sync_strt_wid;
u32 fp_horz_stretch;
u32 fp_panel_cntl;
u32 fp_v_sync_strt_wid;
u32 fp_vert_stretch;
u32 lvds_gen_cntl;
u32 lvds_pll_cntl;
u32 tmds_crc;
u32 tmds_transmitter_cntl;
#if defined(__BIG_ENDIAN)
u32 surface_cntl;
#endif
};
struct radeonfb_info {
struct fb_info info;
struct radeon_regs state;
struct radeon_regs init_state;
char name[32];
char ram_type[12];
unsigned long mmio_base_phys;
unsigned long fb_base_phys;
unsigned long mmio_base;
unsigned long fb_base;
struct pci_dev *pdev;
unsigned char *EDID;
unsigned char *bios_seg;
u32 pseudo_palette[17];
struct { u8 red, green, blue, pad; } palette[256];
int chipset;
unsigned char arch;
int video_ram;
u8 rev;
int pitch, bpp, depth;
int xres, yres, pixclock;
int xres_virtual, yres_virtual;
u32 accel_flags;
int use_default_var;
int got_dfpinfo;
int hasCRTC2;
int crtDisp_type;
int dviDisp_type;
int panel_xres, panel_yres;
int clock;
int hOver_plus, hSync_width, hblank;
int vOver_plus, vSync_width, vblank;
int hAct_high, vAct_high, interlaced;
int synct, misc;
u32 dp_gui_master_cntl;
struct pll_info pll;
int pll_output_freq, post_div, fb_div;
struct ram_info ram;
int mtrr_hdl;
#ifdef CONFIG_PMAC_PBOOK
int pm_reg;
u32 save_regs[64];
u32 mdll, mdll2;
#endif /* CONFIG_PMAC_PBOOK */
int asleep;
struct radeonfb_info *next;
};
static struct fb_var_screeninfo radeonfb_default_var = {
640, 480, 640, 480, 0, 0, 8, 0,
{0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0},
0, 0, -1, -1, 0, 39721, 40, 24, 32, 11, 96, 2,
0, FB_VMODE_NONINTERLACED
};
/*
* IO macros
*/
#define INREG8(addr) readb((rinfo->mmio_base)+addr)
#define OUTREG8(addr,val) writeb(val, (rinfo->mmio_base)+addr)
#define INREG(addr) readl((rinfo->mmio_base)+addr)
#define OUTREG(addr,val) writel(val, (rinfo->mmio_base)+addr)
#define OUTPLL(addr,val) \
do { \
OUTREG8(CLOCK_CNTL_INDEX, (addr & 0x0000003f) | 0x00000080); \
OUTREG(CLOCK_CNTL_DATA, val); \
} while(0)
#define OUTPLLP(addr,val,mask) \
do { \
unsigned int _tmp = INPLL(addr); \
_tmp &= (mask); \
_tmp |= (val); \
OUTPLL(addr, _tmp); \
} while (0)
#define OUTREGP(addr,val,mask) \
do { \
unsigned int _tmp = INREG(addr); \
_tmp &= (mask); \
_tmp |= (val); \
OUTREG(addr, _tmp); \
} while (0)
static __inline__ u32 _INPLL(struct radeonfb_info *rinfo, u32 addr)
{
OUTREG8(CLOCK_CNTL_INDEX, addr & 0x0000003f);
return (INREG(CLOCK_CNTL_DATA));
}
#define INPLL(addr) _INPLL(rinfo, addr)
#define PRIMARY_MONITOR(rinfo) ((rinfo->dviDisp_type != MT_NONE) && \
(rinfo->dviDisp_type != MT_STV) && \
(rinfo->dviDisp_type != MT_CTV) ? \
rinfo->dviDisp_type : rinfo->crtDisp_type)
static char *GET_MON_NAME(int type)
{
char *pret = NULL;
switch (type) {
case MT_NONE:
pret = "no";
break;
case MT_CRT:
pret = "CRT";
break;
case MT_DFP:
pret = "DFP";
break;
case MT_LCD:
pret = "LCD";
break;
case MT_CTV:
pret = "CTV";
break;
case MT_STV:
pret = "STV";
break;
}
return pret;
}
/*
* 2D engine routines
*/
static __inline__ void radeon_engine_flush (struct radeonfb_info *rinfo)
{
int i;
/* initiate flush */
OUTREGP(RB2D_DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL,
~RB2D_DC_FLUSH_ALL);
for (i=0; i < 2000000; i++) {
if (!(INREG(RB2D_DSTCACHE_CTLSTAT) & RB2D_DC_BUSY))
break;
}
}
static __inline__ void _radeon_fifo_wait (struct radeonfb_info *rinfo, int entries)
{
int i;
for (i=0; i<2000000; i++)
if ((INREG(RBBM_STATUS) & 0x7f) >= entries)
return;
}
static __inline__ void _radeon_engine_idle (struct radeonfb_info *rinfo)
{
int i;
/* ensure FIFO is empty before waiting for idle */
_radeon_fifo_wait (rinfo, 64);
for (i=0; i<2000000; i++) {
if (((INREG(RBBM_STATUS) & GUI_ACTIVE)) == 0) {
radeon_engine_flush (rinfo);
return;
}
}
}
#define radeon_engine_idle() _radeon_engine_idle(rinfo)
#define radeon_fifo_wait(entries) _radeon_fifo_wait(rinfo,entries)
/*
* helper routines
*/
static __inline__ u32 radeon_get_dstbpp(u16 depth)
{
switch (depth) {
case 8:
return DST_8BPP;
case 15:
return DST_15BPP;
case 16:
return DST_16BPP;
case 32:
return DST_32BPP;
default:
return 0;
}
}
static inline int var_to_depth(const struct fb_var_screeninfo *var)
{
if (var->bits_per_pixel != 16)
return var->bits_per_pixel;
return (var->green.length == 6) ? 16 : 15;
}
static void _radeon_engine_reset(struct radeonfb_info *rinfo)
{
u32 clock_cntl_index, mclk_cntl, rbbm_soft_reset;
radeon_engine_flush (rinfo);
clock_cntl_index = INREG(CLOCK_CNTL_INDEX);
mclk_cntl = INPLL(MCLK_CNTL);
OUTPLL(MCLK_CNTL, (mclk_cntl |
FORCEON_MCLKA |
FORCEON_MCLKB |
FORCEON_YCLKA |
FORCEON_YCLKB |
FORCEON_MC |
FORCEON_AIC));
rbbm_soft_reset = INREG(RBBM_SOFT_RESET);
OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset |
SOFT_RESET_CP |
SOFT_RESET_HI |
SOFT_RESET_SE |
SOFT_RESET_RE |
SOFT_RESET_PP |
SOFT_RESET_E2 |
SOFT_RESET_RB);
INREG(RBBM_SOFT_RESET);
OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset & (u32)
~(SOFT_RESET_CP |
SOFT_RESET_HI |
SOFT_RESET_SE |
SOFT_RESET_RE |
SOFT_RESET_PP |
SOFT_RESET_E2 |
SOFT_RESET_RB));
INREG(RBBM_SOFT_RESET);
OUTPLL(MCLK_CNTL, mclk_cntl);
OUTREG(CLOCK_CNTL_INDEX, clock_cntl_index);
OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset);
return;
}
#define radeon_engine_reset() _radeon_engine_reset(rinfo)
static __inline__ u8 radeon_get_post_div_bitval(int post_div)
{
switch (post_div) {
case 1:
return 0x00;
case 2:
return 0x01;
case 3:
return 0x04;
case 4:
return 0x02;
case 6:
return 0x06;
case 8:
return 0x03;
case 12:
return 0x07;
default:
return 0x02;
}
}
static __inline__ int round_div(int num, int den)
{
return (num + (den / 2)) / den;
}
static __inline__ int min_bits_req(int val)
{
int bits_req = 0;
if (val == 0)
bits_req = 1;
while (val) {
val >>= 1;
bits_req++;
}
return (bits_req);
}
static __inline__ int _max(int val1, int val2)
{
if (val1 >= val2)
return val1;
else
return val2;
}
/*
* globals
*/
static char *mode_option __initdata;
static char noaccel = 1;
static char mirror = 0;
static int panel_yres __initdata = 0;
static char force_dfp __initdata = 0;
static struct radeonfb_info *board_list = NULL;
static char nomtrr __initdata = 0;
/*
* prototypes
*/
static void radeon_save_state (struct radeonfb_info *rinfo,
struct radeon_regs *save);
static void radeon_engine_init (struct radeonfb_info *rinfo);
static void radeon_write_mode (struct radeonfb_info *rinfo,
struct radeon_regs *mode);
static int __devinit radeon_set_fbinfo (struct radeonfb_info *rinfo);
static int __devinit radeon_init_disp (struct radeonfb_info *rinfo);
static int radeon_init_disp_var (struct radeonfb_info *rinfo, struct fb_var_screeninfo *var);
static char *radeon_find_rom(struct radeonfb_info *rinfo);
static void radeon_get_pllinfo(struct radeonfb_info *rinfo, char *bios_seg);
static void radeon_get_moninfo (struct radeonfb_info *rinfo);
static int radeon_get_dfpinfo (struct radeonfb_info *rinfo);
static int radeon_get_dfpinfo_BIOS(struct radeonfb_info *rinfo);
static void radeon_get_EDID(struct radeonfb_info *rinfo);
static int radeon_dfp_parse_EDID(struct radeonfb_info *rinfo);
static void radeon_update_default_var(struct radeonfb_info *rinfo);
#ifdef CONFIG_PPC_OF
static int radeon_read_OF (struct radeonfb_info *rinfo);
static int radeon_get_EDID_OF(struct radeonfb_info *rinfo);
extern struct device_node *pci_device_to_OF_node(struct pci_dev *dev);
#ifdef CONFIG_PMAC_PBOOK
int radeon_sleep_notify(struct pmu_sleep_notifier *self, int when);
static struct pmu_sleep_notifier radeon_sleep_notifier = {
radeon_sleep_notify, SLEEP_LEVEL_VIDEO,
};
#endif /* CONFIG_PMAC_PBOOK */
#ifdef CONFIG_PMAC_BACKLIGHT
static int radeon_set_backlight_enable(int on, int level, void *data);
static int radeon_set_backlight_level(int level, void *data);
static struct backlight_controller radeon_backlight_controller = {
radeon_set_backlight_enable,
radeon_set_backlight_level
};
#endif /* CONFIG_PMAC_BACKLIGHT */
#endif /* CONFIG_PPC_OF */
static char *radeon_find_rom(struct radeonfb_info *rinfo)
{
#if defined(__i386__)
u32 segstart;
char *rom_base;
char *rom;
int stage;
int i,j;
char aty_rom_sig[] = "761295520";
char *radeon_sig[] = {
"RG6",
"RADEON"
};
for(segstart=0x000c0000; segstart<0x000f0000; segstart+=0x00001000) {
stage = 1;
rom_base = (char *)ioremap(segstart, 0x1000);
if ((*rom_base == 0x55) && (((*(rom_base + 1)) & 0xff) == 0xaa))
stage = 2;
if (stage != 2) {
iounmap(rom_base);
continue;
}
rom = rom_base;
for (i = 0; (i < 128 - strlen(aty_rom_sig)) && (stage != 3); i++) {
if (aty_rom_sig[0] == *rom)
if (strncmp(aty_rom_sig, rom,
strlen(aty_rom_sig)) == 0)
stage = 3;
rom++;
}
if (stage != 3) {
iounmap(rom_base);
continue;
}
rom = rom_base;
for (i = 0; (i < 512) && (stage != 4); i++) {
for(j = 0;j < sizeof(radeon_sig)/sizeof(char *);j++) {
if (radeon_sig[j][0] == *rom)
if (strncmp(radeon_sig[j], rom,
strlen(radeon_sig[j])) == 0) {
stage = 4;
break;
}
}
rom++;
}
if (stage != 4) {
iounmap(rom_base);
continue;
}
return rom_base;
}
#endif
return NULL;
}
static void radeon_get_pllinfo(struct radeonfb_info *rinfo, char *bios_seg)
{
void *bios_header;
void *header_ptr;
u16 bios_header_offset, pll_info_offset;
PLL_BLOCK pll;
if (bios_seg) {
bios_header = bios_seg + 0x48L;
header_ptr = bios_header;
bios_header_offset = readw(header_ptr);
bios_header = bios_seg + bios_header_offset;
bios_header += 0x30;
header_ptr = bios_header;
pll_info_offset = readw(header_ptr);
header_ptr = bios_seg + pll_info_offset;
memcpy_fromio(&pll, header_ptr, 50);
rinfo->pll.xclk = (u32)pll.XCLK;
rinfo->pll.ref_clk = (u32)pll.PCLK_ref_freq;
rinfo->pll.ref_div = (u32)pll.PCLK_ref_divider;
rinfo->pll.ppll_min = pll.PCLK_min_freq;
rinfo->pll.ppll_max = pll.PCLK_max_freq;
printk("radeonfb: ref_clk=%d, ref_div=%d, xclk=%d from BIOS\n",
rinfo->pll.ref_clk, rinfo->pll.ref_div, rinfo->pll.xclk);
} else {
#ifdef CONFIG_PPC_OF
if (radeon_read_OF(rinfo)) {
unsigned int tmp, Nx, M, ref_div, xclk;
tmp = INPLL(M_SPLL_REF_FB_DIV);
ref_div = INPLL(PPLL_REF_DIV) & 0x3ff;
Nx = (tmp & 0xff00) >> 8;
M = (tmp & 0xff);
xclk = ((((2 * Nx * rinfo->pll.ref_clk) + (M)) /
(2 * M)));
rinfo->pll.xclk = xclk;
rinfo->pll.ref_div = ref_div;
rinfo->pll.ppll_min = 12000;
rinfo->pll.ppll_max = 35000;
printk("radeonfb: ref_clk=%d, ref_div=%d, xclk=%d from OF\n",
rinfo->pll.ref_clk, rinfo->pll.ref_div, rinfo->pll.xclk);
return;
}
#endif
/* no BIOS or BIOS not found, use defaults */
switch (rinfo->chipset) {
case PCI_DEVICE_ID_ATI_RADEON_QW:
case PCI_DEVICE_ID_ATI_RADEON_QX:
rinfo->pll.ppll_max = 35000;
rinfo->pll.ppll_min = 12000;
rinfo->pll.xclk = 23000;
rinfo->pll.ref_div = 12;
rinfo->pll.ref_clk = 2700;
break;
case PCI_DEVICE_ID_ATI_RADEON_QL:
case PCI_DEVICE_ID_ATI_RADEON_QN:
case PCI_DEVICE_ID_ATI_RADEON_QO:
case PCI_DEVICE_ID_ATI_RADEON_Ql:
case PCI_DEVICE_ID_ATI_RADEON_BB:
rinfo->pll.ppll_max = 35000;
rinfo->pll.ppll_min = 12000;
rinfo->pll.xclk = 27500;
rinfo->pll.ref_div = 12;
rinfo->pll.ref_clk = 2700;
break;
case PCI_DEVICE_ID_ATI_RADEON_Id:
case PCI_DEVICE_ID_ATI_RADEON_Ie:
case PCI_DEVICE_ID_ATI_RADEON_If:
case PCI_DEVICE_ID_ATI_RADEON_Ig:
rinfo->pll.ppll_max = 35000;
rinfo->pll.ppll_min = 12000;
rinfo->pll.xclk = 25000;
rinfo->pll.ref_div = 12;
rinfo->pll.ref_clk = 2700;
break;
case PCI_DEVICE_ID_ATI_RADEON_ND:
case PCI_DEVICE_ID_ATI_RADEON_NE:
case PCI_DEVICE_ID_ATI_RADEON_NF:
case PCI_DEVICE_ID_ATI_RADEON_NG:
rinfo->pll.ppll_max = 40000;
rinfo->pll.ppll_min = 20000;
rinfo->pll.xclk = 27000;
rinfo->pll.ref_div = 12;
rinfo->pll.ref_clk = 2700;
break;
case PCI_DEVICE_ID_ATI_RADEON_QD:
case PCI_DEVICE_ID_ATI_RADEON_QE:
case PCI_DEVICE_ID_ATI_RADEON_QF:
case PCI_DEVICE_ID_ATI_RADEON_QG:
default:
rinfo->pll.ppll_max = 35000;
rinfo->pll.ppll_min = 12000;
rinfo->pll.xclk = 16600;
rinfo->pll.ref_div = 67;
rinfo->pll.ref_clk = 2700;
break;
}
printk("radeonfb: ref_clk=%d, ref_div=%d, xclk=%d defaults\n",
rinfo->pll.ref_clk, rinfo->pll.ref_div, rinfo->pll.xclk);
}
}
static void radeon_get_moninfo (struct radeonfb_info *rinfo)
{
unsigned int tmp;
if (force_dfp) {
rinfo->dviDisp_type = MT_DFP;
return;
}
tmp = INREG(RADEON_BIOS_4_SCRATCH);
printk(KERN_DEBUG "radeon_get_moninfo: bios 4 scratch = %x\n", tmp);
if (rinfo->hasCRTC2) {
/* primary DVI port */
if (tmp & 0x08)
rinfo->dviDisp_type = MT_DFP;
else if (tmp & 0x4)
rinfo->dviDisp_type = MT_LCD;
else if (tmp & 0x200)
rinfo->dviDisp_type = MT_CRT;
else if (tmp & 0x10)
rinfo->dviDisp_type = MT_CTV;
else if (tmp & 0x20)
rinfo->dviDisp_type = MT_STV;
/* secondary CRT port */
if (tmp & 0x2)
rinfo->crtDisp_type = MT_CRT;
else if (tmp & 0x800)
rinfo->crtDisp_type = MT_DFP;
else if (tmp & 0x400)
rinfo->crtDisp_type = MT_LCD;
else if (tmp & 0x1000)
rinfo->crtDisp_type = MT_CTV;
else if (tmp & 0x2000)
rinfo->crtDisp_type = MT_STV;
} else {
rinfo->dviDisp_type = MT_NONE;
tmp = INREG(FP_GEN_CNTL);
if (tmp & FP_EN_TMDS)
rinfo->crtDisp_type = MT_DFP;
else
rinfo->crtDisp_type = MT_CRT;
}
}
static void radeon_get_EDID(struct radeonfb_info *rinfo)
{
#ifdef CONFIG_PPC_OF
if (!radeon_get_EDID_OF(rinfo))
RTRACE("radeonfb: could not retrieve EDID from OF\n");
#else
/* XXX use other methods later */
#endif
}
#ifdef CONFIG_PPC_OF
static int radeon_get_EDID_OF(struct radeonfb_info *rinfo)
{
struct device_node *dp;
unsigned char *pedid = NULL;
static char *propnames[] = { "DFP,EDID", "LCD,EDID", "EDID", "EDID1", NULL };
int i;
dp = pci_device_to_OF_node(rinfo->pdev);
while (dp != NULL) {
for (i = 0; propnames[i] != NULL; ++i) {
pedid = (unsigned char *)
get_property(dp, propnames[i], NULL);
if (pedid != NULL) {
rinfo->EDID = pedid;
return 1;
}
}
dp = dp->child;
}
return 0;
}
#endif /* CONFIG_PPC_OF */
static int radeon_dfp_parse_EDID(struct radeonfb_info *rinfo)
{
unsigned char *block = rinfo->EDID;
if (!block)
return 0;
/* jump to the detailed timing block section */
block += 54;
rinfo->clock = (block[0] + (block[1] << 8));
rinfo->panel_xres = (block[2] + ((block[4] & 0xf0) << 4));
rinfo->hblank = (block[3] + ((block[4] & 0x0f) << 8));
rinfo->panel_yres = (block[5] + ((block[7] & 0xf0) << 4));
rinfo->vblank = (block[6] + ((block[7] & 0x0f) << 8));
rinfo->hOver_plus = (block[8] + ((block[11] & 0xc0) << 2));
rinfo->hSync_width = (block[9] + ((block[11] & 0x30) << 4));
rinfo->vOver_plus = ((block[10] >> 4) + ((block[11] & 0x0c) << 2));
rinfo->vSync_width = ((block[10] & 0x0f) + ((block[11] & 0x03) << 4));
rinfo->interlaced = ((block[17] & 0x80) >> 7);
rinfo->synct = ((block[17] & 0x18) >> 3);
rinfo->misc = ((block[17] & 0x06) >> 1);
rinfo->hAct_high = rinfo->vAct_high = 0;
if (rinfo->synct == 3) {
if (rinfo->misc & 2)
rinfo->hAct_high = 1;
if (rinfo->misc & 1)
rinfo->vAct_high = 1;
}
printk("radeonfb: detected DFP panel size from EDID: %dx%d\n",
rinfo->panel_xres, rinfo->panel_yres);
rinfo->got_dfpinfo = 1;
return 1;
}
static void radeon_update_default_var(struct radeonfb_info *rinfo)
{
struct fb_var_screeninfo *var = &radeonfb_default_var;
var->xres = rinfo->panel_xres;
var->yres = rinfo->panel_yres;
var->xres_virtual = rinfo->panel_xres;
var->yres_virtual = rinfo->panel_yres;
var->xoffset = var->yoffset = 0;
var->bits_per_pixel = 8;
var->pixclock = 100000000 / rinfo->clock;
var->left_margin = (rinfo->hblank - rinfo->hOver_plus - rinfo->hSync_width);
var->right_margin = rinfo->hOver_plus;
var->upper_margin = (rinfo->vblank - rinfo->vOver_plus - rinfo->vSync_width);
var->lower_margin = rinfo->vOver_plus;
var->hsync_len = rinfo->hSync_width;
var->vsync_len = rinfo->vSync_width;
var->sync = 0;
if (rinfo->synct == 3) {
if (rinfo->hAct_high)
var->sync |= FB_SYNC_HOR_HIGH_ACT;
if (rinfo->vAct_high)
var->sync |= FB_SYNC_VERT_HIGH_ACT;
}
var->vmode = 0;
if (rinfo->interlaced)
var->vmode |= FB_VMODE_INTERLACED;
rinfo->use_default_var = 1;
}
static int radeon_get_dfpinfo_BIOS(struct radeonfb_info *rinfo)
{
char *fpbiosstart, *tmp, *tmp0;
char stmp[30];
int i;
if (!rinfo->bios_seg)
return 0;
if (!(fpbiosstart = rinfo->bios_seg + readw(rinfo->bios_seg + 0x48))) {
printk("radeonfb: Failed to detect DFP panel info using BIOS\n");
return 0;
}
if (!(tmp = rinfo->bios_seg + readw(fpbiosstart + 0x40))) {
printk("radeonfb: Failed to detect DFP panel info using BIOS\n");
return 0;
}
for(i=0; i<24; i++)
stmp[i] = readb(tmp+i+1);
stmp[24] = 0;
printk("radeonfb: panel ID string: %s\n", stmp);
rinfo->panel_xres = readw(tmp + 25);
rinfo->panel_yres = readw(tmp + 27);
printk("radeonfb: detected DFP panel size from BIOS: %dx%d\n",
rinfo->panel_xres, rinfo->panel_yres);
for(i=0; i<20; i++) {
tmp0 = rinfo->bios_seg + readw(tmp+64+i*2);
if (tmp0 == 0)
break;
if ((readw(tmp0) == rinfo->panel_xres) &&
(readw(tmp0+2) == rinfo->panel_yres)) {
rinfo->hblank = (readw(tmp0+17) - readw(tmp0+19)) * 8;
rinfo->hOver_plus = ((readw(tmp0+21) - readw(tmp0+19) -1) * 8) & 0x7fff;
rinfo->hSync_width = readb(tmp0+23) * 8;
rinfo->vblank = readw(tmp0+24) - readw(tmp0+26);
rinfo->vOver_plus = (readw(tmp0+28) & 0x7ff) - readw(tmp0+26);
rinfo->vSync_width = (readw(tmp0+28) & 0xf800) >> 11;
rinfo->clock = readw(tmp0+9);
rinfo->got_dfpinfo = 1;
return 1;
}
}
return 0;
}
static int radeon_get_dfpinfo (struct radeonfb_info *rinfo)
{
unsigned int tmp;
unsigned short a, b;
if (radeon_get_dfpinfo_BIOS(rinfo))
radeon_update_default_var(rinfo);
if (radeon_dfp_parse_EDID(rinfo))
radeon_update_default_var(rinfo);
if (!rinfo->got_dfpinfo) {
/*
* it seems all else has failed now and we
* resort to probing registers for our DFP info
*/
if (panel_yres) {
rinfo->panel_yres = panel_yres;
} else {
tmp = INREG(FP_VERT_STRETCH);
tmp &= 0x00fff000;
rinfo->panel_yres = (unsigned short)(tmp >> 0x0c) + 1;
}
switch (rinfo->panel_yres) {
case 480:
rinfo->panel_xres = 640;
break;
case 600:
rinfo->panel_xres = 800;
break;
case 768:
#if defined(__powerpc__)
if (rinfo->dviDisp_type == MT_LCD)
rinfo->panel_xres = 1152;
else
#endif
rinfo->panel_xres = 1024;
break;
case 1024:
rinfo->panel_xres = 1280;
break;
case 1050:
rinfo->panel_xres = 1400;
break;
case 1200:
rinfo->panel_xres = 1600;
break;
default:
printk("radeonfb: Failed to detect DFP panel size\n");
return 0;
}
printk("radeonfb: detected DFP panel size from registers: %dx%d\n",
rinfo->panel_xres, rinfo->panel_yres);
tmp = INREG(FP_CRTC_H_TOTAL_DISP);
a = (tmp & FP_CRTC_H_TOTAL_MASK) + 4;
b = (tmp & 0x01ff0000) >> FP_CRTC_H_DISP_SHIFT;
rinfo->hblank = (a - b + 1) * 8;
tmp = INREG(FP_H_SYNC_STRT_WID);
rinfo->hOver_plus = (unsigned short) ((tmp & FP_H_SYNC_STRT_CHAR_MASK) >>
FP_H_SYNC_STRT_CHAR_SHIFT) - b - 1;
rinfo->hOver_plus *= 8;
rinfo->hSync_width = (unsigned short) ((tmp & FP_H_SYNC_WID_MASK) >>
FP_H_SYNC_WID_SHIFT);
rinfo->hSync_width *= 8;
tmp = INREG(FP_CRTC_V_TOTAL_DISP);
a = (tmp & FP_CRTC_V_TOTAL_MASK) + 1;
b = (tmp & FP_CRTC_V_DISP_MASK) >> FP_CRTC_V_DISP_SHIFT;
rinfo->vblank = a - b /* + 24 */ ;
tmp = INREG(FP_V_SYNC_STRT_WID);
rinfo->vOver_plus = (unsigned short) (tmp & FP_V_SYNC_STRT_MASK)
- b + 1;
rinfo->vSync_width = (unsigned short) ((tmp & FP_V_SYNC_WID_MASK) >>
FP_V_SYNC_WID_SHIFT);
return 1;
}
return 1;
}
#ifdef CONFIG_PPC_OF
static int radeon_read_OF (struct radeonfb_info *rinfo)
{
struct device_node *dp;
unsigned int *xtal;
dp = pci_device_to_OF_node(rinfo->pdev);
xtal = (unsigned int *) get_property(dp, "ATY,RefCLK", 0);
rinfo->pll.ref_clk = *xtal / 10;
if (*xtal)
return 1;
else
return 0;
}
#endif
static void radeon_engine_init (struct radeonfb_info *rinfo)
{
u32 temp;
/* disable 3D engine */
OUTREG(RB3D_CNTL, 0);
radeon_engine_reset ();
radeon_fifo_wait (1);
OUTREG(RB2D_DSTCACHE_MODE, 0);
/* XXX */
rinfo->pitch = ((rinfo->xres_virtual * (rinfo->bpp / 8) + 0x3f)) >> 6;
radeon_fifo_wait (1);
temp = INREG(DEFAULT_PITCH_OFFSET);
OUTREG(DEFAULT_PITCH_OFFSET, ((temp & 0xc0000000) |
(rinfo->pitch << 0x16)));
radeon_fifo_wait (1);
OUTREGP(DP_DATATYPE, 0, ~HOST_BIG_ENDIAN_EN);
radeon_fifo_wait (1);
OUTREG(DEFAULT_SC_BOTTOM_RIGHT, (DEFAULT_SC_RIGHT_MAX |
DEFAULT_SC_BOTTOM_MAX));
temp = radeon_get_dstbpp(rinfo->depth);
rinfo->dp_gui_master_cntl = ((temp << 8) | GMC_CLR_CMP_CNTL_DIS);
radeon_fifo_wait (1);
OUTREG(DP_GUI_MASTER_CNTL, (rinfo->dp_gui_master_cntl |
GMC_BRUSH_SOLID_COLOR |
GMC_SRC_DATATYPE_COLOR));
radeon_fifo_wait (7);
/* clear line drawing regs */
OUTREG(DST_LINE_START, 0);
OUTREG(DST_LINE_END, 0);
/* set brush color regs */
OUTREG(DP_BRUSH_FRGD_CLR, 0xffffffff);
OUTREG(DP_BRUSH_BKGD_CLR, 0x00000000);
/* set source color regs */
OUTREG(DP_SRC_FRGD_CLR, 0xffffffff);
OUTREG(DP_SRC_BKGD_CLR, 0x00000000);
/* default write mask */
OUTREG(DP_WRITE_MSK, 0xffffffff);
radeon_engine_idle ();
}
static int __devinit radeon_init_disp (struct radeonfb_info *rinfo)
{
struct fb_info *info = &rinfo->info;
struct fb_var_screeninfo var;
var = radeonfb_default_var;
if ((radeon_init_disp_var(rinfo, &var)) < 0)
return -1;
rinfo->depth = var_to_depth(&var);
rinfo->bpp = var.bits_per_pixel;
info->var = var;
fb_alloc_cmap(&info->cmap, 256, 0);
var.activate = FB_ACTIVATE_NOW;
return 0;
}
static int radeon_init_disp_var (struct radeonfb_info *rinfo,
struct fb_var_screeninfo *var)
{
#ifndef MODULE
if (mode_option)
fb_find_mode (var, &rinfo->info, mode_option,
NULL, 0, NULL, 8);
else
#endif
if (rinfo->use_default_var)
/* We will use the modified default far */
*var = radeonfb_default_var;
else
fb_find_mode (var, &rinfo->info, "640x480-8@60",
NULL, 0, NULL, 0);
if (noaccel)
var->accel_flags &= ~FB_ACCELF_TEXT;
else
var->accel_flags |= FB_ACCELF_TEXT;
return 0;
}
static int radeon_do_maximize(struct radeonfb_info *rinfo,
struct fb_var_screeninfo *var,
struct fb_var_screeninfo *v,
int nom, int den)
{
static struct {
int xres, yres;
} modes[] = {
{1600, 1280},
{1280, 1024},
{1024, 768},
{800, 600},
{640, 480},
{-1, -1}
};
int i;
/* use highest possible virtual resolution */
if (v->xres_virtual == -1 && v->yres_virtual == -1) {
printk("radeonfb: using max available virtual resolution\n");
for (i=0; modes[i].xres != -1; i++) {
if (modes[i].xres * nom / den * modes[i].yres <
rinfo->video_ram / 2)
break;
}
if (modes[i].xres == -1) {
printk("radeonfb: could not find virtual resolution that fits into video memory!\n");
return -EINVAL;
}
v->xres_virtual = modes[i].xres;
v->yres_virtual = modes[i].yres;
printk("radeonfb: virtual resolution set to max of %dx%d\n",
v->xres_virtual, v->yres_virtual);
} else if (v->xres_virtual == -1) {
v->xres_virtual = (rinfo->video_ram * den /
(nom * v->yres_virtual * 2)) & ~15;
} else if (v->yres_virtual == -1) {
v->xres_virtual = (v->xres_virtual + 15) & ~15;
v->yres_virtual = rinfo->video_ram * den /
(nom * v->xres_virtual *2);
} else {
if (v->xres_virtual * nom / den * v->yres_virtual >
rinfo->video_ram) {
return -EINVAL;
}
}
if (v->xres_virtual * nom / den >= 8192) {
v->xres_virtual = 8192 * den / nom - 16;
}
if (v->xres_virtual < v->xres)
return -EINVAL;
if (v->yres_virtual < v->yres)
return -EINVAL;
return 0;
}
static int radeonfb_check_var (struct fb_var_screeninfo *var, struct fb_info *info)
{
struct radeonfb_info *rinfo = (struct radeonfb_info *) info->par;
struct fb_var_screeninfo v;
int nom, den;
memcpy (&v, var, sizeof (v));
switch (v.bits_per_pixel) {
case 0 ... 8:
v.bits_per_pixel = 8;
break;
case 9 ... 16:
v.bits_per_pixel = 16;
break;
case 17 ... 24:
#if 0 /* Doesn't seem to work */
v.bits_per_pixel = 24;
break;
#endif
return -EINVAL;
case 25 ... 32:
v.bits_per_pixel = 32;
break;
default:
return -EINVAL;
}
switch (var_to_depth(&v)) {
case 8:
nom = den = 1;
v.red.offset = v.green.offset = v.blue.offset = 0;
v.red.length = v.green.length = v.blue.length = 8;
v.transp.offset = v.transp.length = 0;
break;
case 15:
nom = 2;
den = 1;
v.red.offset = 10;
v.green.offset = 5;
v.blue.offset = 0;
v.red.length = v.green.length = v.blue.length = 5;
v.transp.offset = v.transp.length = 0;
break;
case 16:
nom = 2;
den = 1;
v.red.offset = 11;
v.green.offset = 5;
v.blue.offset = 0;
v.red.length = 5;
v.green.length = 6;
v.blue.length = 5;
v.transp.offset = v.transp.length = 0;
break;
case 24:
nom = 4;
den = 1;
v.red.offset = 16;
v.green.offset = 8;
v.blue.offset = 0;
v.red.length = v.blue.length = v.green.length = 8;
v.transp.offset = v.transp.length = 0;
break;
case 32:
nom = 4;
den = 1;
v.red.offset = 16;
v.green.offset = 8;
v.blue.offset = 0;
v.red.length = v.blue.length = v.green.length = 8;
v.transp.offset = 24;
v.transp.length = 8;
break;
default:
printk ("radeonfb: mode %dx%dx%d rejected, color depth invalid\n",
var->xres, var->yres, var->bits_per_pixel);
return -EINVAL;
}
if (radeon_do_maximize(rinfo, var, &v, nom, den) < 0)
return -EINVAL;
if (v.xoffset < 0)
v.xoffset = 0;
if (v.yoffset < 0)
v.yoffset = 0;
if (v.xoffset > v.xres_virtual - v.xres)
v.xoffset = v.xres_virtual - v.xres - 1;
if (v.yoffset > v.yres_virtual - v.yres)
v.yoffset = v.yres_virtual - v.yres - 1;
v.red.msb_right = v.green.msb_right = v.blue.msb_right =
v.transp.offset = v.transp.length =
v.transp.msb_right = 0;
if (noaccel)
v.accel_flags = 0;
memcpy(var, &v, sizeof(v));
return 0;
}
static int radeonfb_pan_display (struct fb_var_screeninfo *var,
struct fb_info *info)
{
struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
if ((var->xoffset + var->xres > var->xres_virtual)
|| (var->yoffset + var->yres > var->yres_virtual))
return -EINVAL;
if (rinfo->asleep)
return 0;
OUTREG(CRTC_OFFSET, ((var->yoffset * var->xres_virtual + var->xoffset)
* var->bits_per_pixel / 8) & ~7);
return 0;
}
static int radeonfb_ioctl (struct inode *inode, struct file *file, unsigned int cmd,
unsigned long arg, struct fb_info *info)
{
struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
unsigned int tmp;
u32 value = 0;
int rc;
switch (cmd) {
/*
* TODO: set mirror accordingly for non-Mobility chipsets with 2 CRTC's
*/
case FBIO_RADEON_SET_MIRROR:
switch (rinfo->arch) {
case RADEON_R100:
case RADEON_RV100:
case RADEON_R200:
case RADEON_RV200:
case RADEON_RV250:
case RADEON_R300:
return -EINVAL;
default:
/* RADEON M6, RADEON_M7, RADEON_M9 */
break;
}
rc = 0;
value = (__u32*)arg; //get_user(value, (__u32*)arg);
if (rc)
return rc;
if (value & 0x01) {
tmp = INREG(LVDS_GEN_CNTL);
tmp |= (LVDS_ON | LVDS_BLON);
} else {
tmp = INREG(LVDS_GEN_CNTL);
tmp &= ~(LVDS_ON | LVDS_BLON);
}
OUTREG(LVDS_GEN_CNTL, tmp);
if (value & 0x02) {
tmp = INREG(CRTC_EXT_CNTL);
tmp |= CRTC_CRT_ON;
mirror = 1;
} else {
tmp = INREG(CRTC_EXT_CNTL);
tmp &= ~CRTC_CRT_ON;
mirror = 0;
}
OUTREG(CRTC_EXT_CNTL, tmp);
break;
case FBIO_RADEON_GET_MIRROR:
switch (rinfo->arch) {
case RADEON_R100:
case RADEON_RV100:
case RADEON_R200:
case RADEON_RV200:
case RADEON_RV250:
case RADEON_R300:
return -EINVAL;
default:
/* RADEON M6, RADEON_M7, RADEON_M9 */
break;
}
tmp = INREG(LVDS_GEN_CNTL);
if ((LVDS_ON | LVDS_BLON) & tmp)
value |= 0x01;
tmp = INREG(CRTC_EXT_CNTL);
if (CRTC_CRT_ON & tmp)
value |= 0x02;
return put_user(value, (__u32*)arg);
default:
return -EINVAL;
}
return -EINVAL;
}
static int radeonfb_blank (int blank, struct fb_info *info)
{
struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
u32 val = INREG(CRTC_EXT_CNTL);
u32 val2 = INREG(LVDS_GEN_CNTL);
if (rinfo->asleep)
return 0;
#ifdef CONFIG_PMAC_BACKLIGHT
if (rinfo->dviDisp_type == MT_LCD && _machine == _MACH_Pmac) {
set_backlight_enable(!blank);
return 0;
}
#endif
/* reset it */
val &= ~(CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS |
CRTC_VSYNC_DIS);
val2 &= ~(LVDS_DISPLAY_DIS);
switch (blank) {
case VESA_NO_BLANKING:
break;
case VESA_VSYNC_SUSPEND:
val |= (CRTC_DISPLAY_DIS | CRTC_VSYNC_DIS);
break;
case VESA_HSYNC_SUSPEND:
val |= (CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS);
break;
case VESA_POWERDOWN:
val |= (CRTC_DISPLAY_DIS | CRTC_VSYNC_DIS |
CRTC_HSYNC_DIS);
val2 |= (LVDS_DISPLAY_DIS);
break;
}
switch (rinfo->dviDisp_type) {
case MT_LCD:
OUTREG(LVDS_GEN_CNTL, val2);
break;
case MT_CRT:
default:
OUTREG(CRTC_EXT_CNTL, val);
break;
}
return 0;
}
static int radeonfb_setcolreg (unsigned regno, unsigned red, unsigned green,
unsigned blue, unsigned transp, struct fb_info *info)
{
struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
u32 pindex, vclk_cntl;
unsigned int i;
if (regno > 255)
return 1;
red >>= 8;
green >>= 8;
blue >>= 8;
rinfo->palette[regno].red = red;
rinfo->palette[regno].green = green;
rinfo->palette[regno].blue = blue;
/* default */
pindex = regno;
if (!rinfo->asleep) {
vclk_cntl = INPLL(VCLK_ECP_CNTL);
OUTPLL(VCLK_ECP_CNTL, vclk_cntl & ~PIXCLK_DAC_ALWAYS_ONb);
if (rinfo->bpp == 16) {
pindex = regno * 8;
if (rinfo->depth == 16 && regno > 63)
return 1;
if (rinfo->depth == 15 && regno > 31)
return 1;
/* For 565, the green component is mixed one order below */
if (rinfo->depth == 16) {
OUTREG(PALETTE_INDEX, pindex>>1);
OUTREG(PALETTE_DATA, (rinfo->palette[regno>>1].red << 16) |
(green << 8) | (rinfo->palette[regno>>1].blue));
green = rinfo->palette[regno<<1].green;
}
}
if (rinfo->depth != 16 || regno < 32) {
OUTREG(PALETTE_INDEX, pindex);
OUTREG(PALETTE_DATA, (red << 16) | (green << 8) | blue);
}
OUTPLL(VCLK_ECP_CNTL, vclk_cntl);
}
if (regno < 16) {
switch (rinfo->depth) {
case 15:
((u16 *) (info->pseudo_palette))[regno] =
(regno << 10) | (regno << 5) | regno;
break;
case 16:
((u16 *) (info->pseudo_palette))[regno] =
(regno << 11) | (regno << 6) | regno;
break;
case 24:
((u32 *) (info->pseudo_palette))[regno] =
(regno << 16) | (regno << 8) | regno;
break;
case 32:
i = (regno << 8) | regno;
((u32 *) (info->pseudo_palette))[regno] =
(i << 16) | i;
break;
}
}
return 0;
}
static void radeon_save_state (struct radeonfb_info *rinfo,
struct radeon_regs *save)
{
/* CRTC regs */
save->crtc_gen_cntl = INREG(CRTC_GEN_CNTL);
save->crtc_ext_cntl = INREG(CRTC_EXT_CNTL);
save->dac_cntl = INREG(DAC_CNTL);
save->crtc_h_total_disp = INREG(CRTC_H_TOTAL_DISP);
save->crtc_h_sync_strt_wid = INREG(CRTC_H_SYNC_STRT_WID);
save->crtc_v_total_disp = INREG(CRTC_V_TOTAL_DISP);
save->crtc_v_sync_strt_wid = INREG(CRTC_V_SYNC_STRT_WID);
save->crtc_pitch = INREG(CRTC_PITCH);
#if defined(__BIG_ENDIAN)
save->surface_cntl = INREG(SURFACE_CNTL);
#endif
/* FP regs */
save->fp_crtc_h_total_disp = INREG(FP_CRTC_H_TOTAL_DISP);
save->fp_crtc_v_total_disp = INREG(FP_CRTC_V_TOTAL_DISP);
save->fp_gen_cntl = INREG(FP_GEN_CNTL);
save->fp_h_sync_strt_wid = INREG(FP_H_SYNC_STRT_WID);
save->fp_horz_stretch = INREG(FP_HORZ_STRETCH);
save->fp_v_sync_strt_wid = INREG(FP_V_SYNC_STRT_WID);
save->fp_vert_stretch = INREG(FP_VERT_STRETCH);
save->lvds_gen_cntl = INREG(LVDS_GEN_CNTL);
save->lvds_pll_cntl = INREG(LVDS_PLL_CNTL);
save->tmds_crc = INREG(TMDS_CRC);
save->tmds_transmitter_cntl = INREG(TMDS_TRANSMITTER_CNTL);
save->vclk_ecp_cntl = INPLL(VCLK_ECP_CNTL);
}
static int radeonfb_set_par (struct fb_info *info)
{
struct radeonfb_info *rinfo = (struct radeonfb_info *)info->par;
struct fb_var_screeninfo *mode = &info->var;
struct radeon_regs newmode;
int hTotal, vTotal, hSyncStart, hSyncEnd,
hSyncPol, vSyncStart, vSyncEnd, vSyncPol, cSync;
u8 hsync_adj_tab[] = {0, 0x12, 9, 9, 6, 5};
u8 hsync_fudge_fp[] = {2, 2, 0, 0, 5, 5};
u32 dotClock = 1000000000 / mode->pixclock,
sync, h_sync_pol, v_sync_pol;
int freq = dotClock / 10; /* x 100 */
int xclk_freq, vclk_freq, xclk_per_trans, xclk_per_trans_precise;
int useable_precision, roff, ron;
int min_bits, format = 0;
int hsync_start, hsync_fudge, bytpp, hsync_wid, vsync_wid;
int primary_mon = PRIMARY_MONITOR(rinfo);
int depth = var_to_depth(mode);
rinfo->xres = mode->xres;
rinfo->yres = mode->yres;
rinfo->xres_virtual = mode->xres_virtual;
rinfo->yres_virtual = mode->yres_virtual;
rinfo->pixclock = mode->pixclock;
hSyncStart = mode->xres + mode->right_margin;
hSyncEnd = hSyncStart + mode->hsync_len;
hTotal = hSyncEnd + mode->left_margin;
vSyncStart = mode->yres + mode->lower_margin;
vSyncEnd = vSyncStart + mode->vsync_len;
vTotal = vSyncEnd + mode->upper_margin;
if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
if (rinfo->panel_xres < mode->xres)
rinfo->xres = mode->xres = rinfo->panel_xres;
if (rinfo->panel_yres < mode->yres)
rinfo->yres = mode->yres = rinfo->panel_yres;
hTotal = mode->xres + rinfo->hblank;
hSyncStart = mode->xres + rinfo->hOver_plus;
hSyncEnd = hSyncStart + rinfo->hSync_width;
vTotal = mode->yres + rinfo->vblank;
vSyncStart = mode->yres + rinfo->vOver_plus;
vSyncEnd = vSyncStart + rinfo->vSync_width;
}
sync = mode->sync;
h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
RTRACE("hStart = %d, hEnd = %d, hTotal = %d\n",
hSyncStart, hSyncEnd, hTotal);
RTRACE("vStart = %d, vEnd = %d, vTotal = %d\n",
vSyncStart, vSyncEnd, vTotal);
hsync_wid = (hSyncEnd - hSyncStart) / 8;
vsync_wid = vSyncEnd - vSyncStart;
if (hsync_wid == 0)
hsync_wid = 1;
else if (hsync_wid > 0x3f) /* max */
hsync_wid = 0x3f;
if (vsync_wid == 0)
vsync_wid = 1;
else if (vsync_wid > 0x1f) /* max */
vsync_wid = 0x1f;
hSyncPol = mode->sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
vSyncPol = mode->sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
cSync = mode->sync & FB_SYNC_COMP_HIGH_ACT ? (1 << 4) : 0;
format = radeon_get_dstbpp(depth);
bytpp = mode->bits_per_pixel >> 3;
if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD))
hsync_fudge = hsync_fudge_fp[format-1];
else
hsync_fudge = hsync_adj_tab[format-1];
hsync_start = hSyncStart - 8 + hsync_fudge;
newmode.crtc_gen_cntl = CRTC_EXT_DISP_EN | CRTC_EN |
(format << 8);
if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
newmode.crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN;
if (mirror)
newmode.crtc_ext_cntl |= CRTC_CRT_ON;
newmode.crtc_gen_cntl &= ~(CRTC_DBL_SCAN_EN |
CRTC_INTERLACE_EN);
} else {
newmode.crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN |
CRTC_CRT_ON;
}
newmode.dac_cntl = /* INREG(DAC_CNTL) | */ DAC_MASK_ALL | DAC_VGA_ADR_EN |
DAC_8BIT_EN;
newmode.crtc_h_total_disp = ((((hTotal / 8) - 1) & 0x3ff) |
(((mode->xres / 8) - 1) << 16));
newmode.crtc_h_sync_strt_wid = ((hsync_start & 0x1fff) |
(hsync_wid << 16) | (h_sync_pol << 23));
newmode.crtc_v_total_disp = ((vTotal - 1) & 0xffff) |
((mode->yres - 1) << 16);
newmode.crtc_v_sync_strt_wid = (((vSyncStart - 1) & 0xfff) |
(vsync_wid << 16) | (v_sync_pol << 23));
newmode.crtc_pitch = (mode->xres_virtual >> 3);
newmode.crtc_pitch |= (newmode.crtc_pitch << 16);
#if defined(__BIG_ENDIAN)
/*
* It looks like recent chips have a problem with SURFACE_CNTL,
* setting SURF_TRANSLATION_DIS completely disables the
* swapper as well, so we leave it unset now.
*/
newmode.surface_cntl = 0;
/* Setup swapping on both apertures, though we currently
* only use aperture 0, enabling swapper on aperture 1
* won't harm
*/
switch (mode->bits_per_pixel) {
case 16:
newmode.surface_cntl |= NONSURF_AP0_SWP_16BPP;
newmode.surface_cntl |= NONSURF_AP1_SWP_16BPP;
break;
case 24:
case 32:
newmode.surface_cntl |= NONSURF_AP0_SWP_32BPP;
newmode.surface_cntl |= NONSURF_AP1_SWP_32BPP;
break;
}
#endif
rinfo->pitch = ((mode->xres_virtual * ((mode->bits_per_pixel + 1) / 8) + 0x3f)
& ~(0x3f)) / 64;
RTRACE("h_total_disp = 0x%x\t hsync_strt_wid = 0x%x\n",
newmode.crtc_h_total_disp, newmode.crtc_h_sync_strt_wid);
RTRACE("v_total_disp = 0x%x\t vsync_strt_wid = 0x%x\n",
newmode.crtc_v_total_disp, newmode.crtc_v_sync_strt_wid);
newmode.xres = mode->xres;
newmode.yres = mode->yres;
rinfo->bpp = mode->bits_per_pixel;
rinfo->depth = depth;
if (freq > rinfo->pll.ppll_max)
freq = rinfo->pll.ppll_max;
if (freq*12 < rinfo->pll.ppll_min)
freq = rinfo->pll.ppll_min / 12;
{
struct {
int divider;
int bitvalue;
} *post_div,
post_divs[] = {
{ 1, 0 },
{ 2, 1 },
{ 4, 2 },
{ 8, 3 },
{ 3, 4 },
{ 16, 5 },
{ 6, 6 },
{ 12, 7 },
{ 0, 0 },
};
for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
rinfo->pll_output_freq = post_div->divider * freq;
if (rinfo->pll_output_freq >= rinfo->pll.ppll_min &&
rinfo->pll_output_freq <= rinfo->pll.ppll_max)
break;
}
rinfo->post_div = post_div->divider;
rinfo->fb_div = round_div(rinfo->pll.ref_div*rinfo->pll_output_freq,
rinfo->pll.ref_clk);
newmode.ppll_ref_div = rinfo->pll.ref_div;
newmode.ppll_div_3 = rinfo->fb_div | (post_div->bitvalue << 16);
}
newmode.vclk_ecp_cntl = rinfo->init_state.vclk_ecp_cntl;
#ifdef CONFIG_PPC_OF
/* Gross hack for iBook with M7 until I find out a proper fix */
if (machine_is_compatible("PowerBook4,3") && rinfo->arch == RADEON_M7)
newmode.ppll_div_3 = 0x000600ad;
#endif /* CONFIG_PPC_OF */
RTRACE("post div = 0x%x\n", rinfo->post_div);
RTRACE("fb_div = 0x%x\n", rinfo->fb_div);
RTRACE("ppll_div_3 = 0x%x\n", newmode.ppll_div_3);
/* DDA */
vclk_freq = round_div(rinfo->pll.ref_clk * rinfo->fb_div,
rinfo->pll.ref_div * rinfo->post_div);
xclk_freq = rinfo->pll.xclk;
xclk_per_trans = round_div(xclk_freq * 128, vclk_freq * mode->bits_per_pixel);
min_bits = min_bits_req(xclk_per_trans);
useable_precision = min_bits + 1;
xclk_per_trans_precise = round_div((xclk_freq * 128) << (11 - useable_precision),
vclk_freq * mode->bits_per_pixel);
ron = (4 * rinfo->ram.mb + 3 * _max(rinfo->ram.trcd - 2, 0) +
2 * rinfo->ram.trp + rinfo->ram.twr + rinfo->ram.cl + rinfo->ram.tr2w +
xclk_per_trans) << (11 - useable_precision);
roff = xclk_per_trans_precise * (32 - 4);
RTRACE("ron = %d, roff = %d\n", ron, roff);
RTRACE("vclk_freq = %d, per = %d\n", vclk_freq, xclk_per_trans_precise);
if ((ron + rinfo->ram.rloop) >= roff) {
printk("radeonfb: error ron out of range\n");
return -EINVAL;
}
newmode.dda_config = (xclk_per_trans_precise |
(useable_precision << 16) |
(rinfo->ram.rloop << 20));
newmode.dda_on_off = (ron << 16) | roff;
if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
unsigned int hRatio, vRatio;
/* We force the pixel clock to be always enabled. Allowing it
* to be power managed during blanking would save power, but has
* nasty interactions with the 2D engine & sleep code that haven't
* been solved yet. --BenH
*/
newmode.vclk_ecp_cntl &= ~PIXCLK_DAC_ALWAYS_ONb;
if (mode->xres > rinfo->panel_xres)
mode->xres = rinfo->panel_xres;
if (mode->yres > rinfo->panel_yres)
mode->yres = rinfo->panel_yres;
newmode.fp_horz_stretch = (((rinfo->panel_xres / 8) - 1)
<< HORZ_PANEL_SHIFT);
newmode.fp_vert_stretch = ((rinfo->panel_yres - 1)
<< VERT_PANEL_SHIFT);
if (mode->xres != rinfo->panel_xres) {
hRatio = round_div(mode->xres * HORZ_STRETCH_RATIO_MAX,
rinfo->panel_xres);
newmode.fp_horz_stretch = (((((unsigned long)hRatio) & HORZ_STRETCH_RATIO_MASK)) |
(newmode.fp_horz_stretch &
(HORZ_PANEL_SIZE | HORZ_FP_LOOP_STRETCH |
HORZ_AUTO_RATIO_INC)));
newmode.fp_horz_stretch |= (HORZ_STRETCH_BLEND |
HORZ_STRETCH_ENABLE);
}
newmode.fp_horz_stretch &= ~HORZ_AUTO_RATIO;
if (mode->yres != rinfo->panel_yres) {
vRatio = round_div(mode->yres * VERT_STRETCH_RATIO_MAX,
rinfo->panel_yres);
newmode.fp_vert_stretch = (((((unsigned long)vRatio) & VERT_STRETCH_RATIO_MASK)) |
(newmode.fp_vert_stretch &
(VERT_PANEL_SIZE | VERT_STRETCH_RESERVED)));
newmode.fp_vert_stretch |= (VERT_STRETCH_BLEND |
VERT_STRETCH_ENABLE);
}
newmode.fp_vert_stretch &= ~VERT_AUTO_RATIO_EN;
newmode.fp_gen_cntl = (rinfo->init_state.fp_gen_cntl & (u32)
~(FP_SEL_CRTC2 |
FP_RMX_HVSYNC_CONTROL_EN |
FP_DFP_SYNC_SEL |
FP_CRT_SYNC_SEL |
FP_CRTC_LOCK_8DOT |
FP_USE_SHADOW_EN |
FP_CRTC_USE_SHADOW_VEND |
FP_CRT_SYNC_ALT));
newmode.fp_gen_cntl |= (FP_CRTC_DONT_SHADOW_VPAR |
FP_CRTC_DONT_SHADOW_HEND);
newmode.lvds_gen_cntl = rinfo->init_state.lvds_gen_cntl;
newmode.lvds_pll_cntl = rinfo->init_state.lvds_pll_cntl;
newmode.tmds_crc = rinfo->init_state.tmds_crc;
newmode.tmds_transmitter_cntl = rinfo->init_state.tmds_transmitter_cntl;
if (primary_mon == MT_LCD) {
newmode.lvds_gen_cntl |= (LVDS_ON | LVDS_BLON);
newmode.fp_gen_cntl &= ~(FP_FPON | FP_TMDS_EN);
} else {
/* DFP */
newmode.fp_gen_cntl |= (FP_FPON | FP_TMDS_EN);
newmode.tmds_transmitter_cntl = (TMDS_RAN_PAT_RST |
ICHCSEL | TMDS_PLL_EN) &
~(TMDS_PLLRST);
newmode.crtc_ext_cntl &= ~CRTC_CRT_ON;
}
newmode.fp_crtc_h_total_disp = (((rinfo->hblank / 8) & 0x3ff) |
(((mode->xres / 8) - 1) << 16));
newmode.fp_crtc_v_total_disp = (rinfo->vblank & 0xffff) |
((mode->yres - 1) << 16);
newmode.fp_h_sync_strt_wid = ((rinfo->hOver_plus & 0x1fff) |
(hsync_wid << 16) | (h_sync_pol << 23));
newmode.fp_v_sync_strt_wid = ((rinfo->vOver_plus & 0xfff) |
(vsync_wid << 16) | (v_sync_pol << 23));
}
/* do it! */
if (!rinfo->asleep) {
radeon_write_mode (rinfo, &newmode);
/* (re)initialize the engine */
if (!noaccel)
radeon_engine_init (rinfo);
}
/* Update fix */
info->fix.line_length = rinfo->pitch*64;
info->fix.visual = rinfo->depth == 8 ? FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
#ifdef CONFIG_BOOTX_TEXT
/* Update debug text engine */
btext_update_display(rinfo->fb_base_phys, mode->xres, mode->yres,
rinfo->depth, rinfo->pitch*64);
#endif
return 0;
}
static void radeon_write_mode (struct radeonfb_info *rinfo,
struct radeon_regs *mode)
{
int i;
int primary_mon = PRIMARY_MONITOR(rinfo);
radeonfb_blank(VESA_POWERDOWN, (struct fb_info *)rinfo);
if (rinfo->arch == RADEON_M6) {
for (i=0; i<8; i++)
OUTREG(common_regs_m6[i].reg, common_regs_m6[i].val);
} else {
for (i=0; i<9; i++)
OUTREG(common_regs[i].reg, common_regs[i].val);
}
OUTREG(CRTC_GEN_CNTL, mode->crtc_gen_cntl);
OUTREGP(CRTC_EXT_CNTL, mode->crtc_ext_cntl,
CRTC_HSYNC_DIS | CRTC_VSYNC_DIS | CRTC_DISPLAY_DIS);
OUTREGP(DAC_CNTL, mode->dac_cntl, DAC_RANGE_CNTL | DAC_BLANKING);
OUTREG(CRTC_H_TOTAL_DISP, mode->crtc_h_total_disp);
OUTREG(CRTC_H_SYNC_STRT_WID, mode->crtc_h_sync_strt_wid);
OUTREG(CRTC_V_TOTAL_DISP, mode->crtc_v_total_disp);
OUTREG(CRTC_V_SYNC_STRT_WID, mode->crtc_v_sync_strt_wid);
OUTREG(CRTC_OFFSET, 0);
OUTREG(CRTC_OFFSET_CNTL, 0);
OUTREG(CRTC_PITCH, mode->crtc_pitch);
#if defined(__BIG_ENDIAN)
OUTREG(SURFACE_CNTL, mode->surface_cntl);
#endif
while ((INREG(CLOCK_CNTL_INDEX) & PPLL_DIV_SEL_MASK) !=
PPLL_DIV_SEL_MASK) {
OUTREGP(CLOCK_CNTL_INDEX, PPLL_DIV_SEL_MASK, 0xffff);
}
OUTPLLP(PPLL_CNTL, PPLL_RESET, 0xffff);
while ((INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK) !=
(mode->ppll_ref_div & PPLL_REF_DIV_MASK)) {
OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, ~PPLL_REF_DIV_MASK);
}
while ((INPLL(PPLL_DIV_3) & PPLL_FB3_DIV_MASK) !=
(mode->ppll_div_3 & PPLL_FB3_DIV_MASK)) {
OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_FB3_DIV_MASK);
}
while ((INPLL(PPLL_DIV_3) & PPLL_POST3_DIV_MASK) !=
(mode->ppll_div_3 & PPLL_POST3_DIV_MASK)) {
OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_POST3_DIV_MASK);
}
OUTPLL(HTOTAL_CNTL, 0);
OUTPLLP(PPLL_CNTL, 0, ~PPLL_RESET);
// OUTREG(DDA_CONFIG, mode->dda_config);
// OUTREG(DDA_ON_OFF, mode->dda_on_off);
if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
OUTREG(FP_CRTC_H_TOTAL_DISP, mode->fp_crtc_h_total_disp);
OUTREG(FP_CRTC_V_TOTAL_DISP, mode->fp_crtc_v_total_disp);
OUTREG(FP_H_SYNC_STRT_WID, mode->fp_h_sync_strt_wid);
OUTREG(FP_V_SYNC_STRT_WID, mode->fp_v_sync_strt_wid);
OUTREG(FP_HORZ_STRETCH, mode->fp_horz_stretch);
OUTREG(FP_VERT_STRETCH, mode->fp_vert_stretch);
OUTREG(FP_GEN_CNTL, mode->fp_gen_cntl);
OUTREG(TMDS_CRC, mode->tmds_crc);
OUTREG(TMDS_TRANSMITTER_CNTL, mode->tmds_transmitter_cntl);
if (primary_mon == MT_LCD) {
unsigned int tmp = INREG(LVDS_GEN_CNTL);
mode->lvds_gen_cntl &= ~LVDS_STATE_MASK;
mode->lvds_gen_cntl |= (rinfo->init_state.lvds_gen_cntl & LVDS_STATE_MASK);
if ((tmp & (LVDS_ON | LVDS_BLON)) ==
(mode->lvds_gen_cntl & (LVDS_ON | LVDS_BLON))) {
OUTREG(LVDS_GEN_CNTL, mode->lvds_gen_cntl);
} else {
if (mode->lvds_gen_cntl & (LVDS_ON | LVDS_BLON)) {
udelay(1000);
OUTREG(LVDS_GEN_CNTL, mode->lvds_gen_cntl);
} else {
OUTREG(LVDS_GEN_CNTL, mode->lvds_gen_cntl |
LVDS_BLON);
udelay(1000);
OUTREG(LVDS_GEN_CNTL, mode->lvds_gen_cntl);
}
}
}
}
radeonfb_blank(VESA_NO_BLANKING, (struct fb_info *)rinfo);
OUTPLL(VCLK_ECP_CNTL, mode->vclk_ecp_cntl);
return;
}
static struct fb_ops radeonfb_ops = {
.owner = THIS_MODULE,
.fb_check_var = radeonfb_check_var,
.fb_set_par = radeonfb_set_par,
.fb_setcolreg = radeonfb_setcolreg,
.fb_pan_display = radeonfb_pan_display,
.fb_blank = radeonfb_blank,
.fb_ioctl = radeonfb_ioctl,
#if 0
.fb_fillrect = radeonfb_fillrect,
.fb_copyarea = radeonfb_copyarea,
.fb_imageblit = radeonfb_imageblit,
.fb_rasterimg = radeonfb_rasterimg,
#else
.fb_fillrect = cfb_fillrect,
.fb_copyarea = cfb_copyarea,
.fb_imageblit = cfb_imageblit,
#endif
.fb_cursor = soft_cursor,
};
static int __devinit radeon_set_fbinfo (struct radeonfb_info *rinfo)
{
struct fb_info *info;
info = &rinfo->info;
info->currcon = -1;
info->par = rinfo;
info->pseudo_palette = rinfo->pseudo_palette;
info->flags = FBINFO_FLAG_DEFAULT;
info->fbops = &radeonfb_ops;
info->display_fg = NULL;
info->screen_base = (char *)rinfo->fb_base;
/* Fill fix common fields */
strncpy(info->fix.id, rinfo->name, sizeof(info->fix.id));
info->fix.smem_start = rinfo->fb_base_phys;
info->fix.smem_len = rinfo->video_ram;
info->fix.type = FB_TYPE_PACKED_PIXELS;
info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
info->fix.xpanstep = 8;
info->fix.ypanstep = 1;
info->fix.ywrapstep = 0;
info->fix.type_aux = 0;
info->fix.mmio_start = rinfo->mmio_base_phys;
info->fix.mmio_len = RADEON_REGSIZE;
if (noaccel)
info->fix.accel = FB_ACCEL_NONE;
else
info->fix.accel = FB_ACCEL_ATI_RADEON;
if (radeon_init_disp (rinfo) < 0)
return -1;
return 0;
}
#ifdef CONFIG_PMAC_BACKLIGHT
/* TODO: Dbl check these tables, we don't go up to full ON backlight
* in these, possibly because we noticed MacOS doesn't, but I'd prefer
* having some more official numbers from ATI
*/
static int backlight_conv_m6[] = {
0xff, 0xc0, 0xb5, 0xaa, 0x9f, 0x94, 0x89, 0x7e,
0x73, 0x68, 0x5d, 0x52, 0x47, 0x3c, 0x31, 0x24
};
static int backlight_conv_m7[] = {
0x00, 0x3f, 0x4a, 0x55, 0x60, 0x6b, 0x76, 0x81,
0x8c, 0x97, 0xa2, 0xad, 0xb8, 0xc3, 0xce, 0xd9
};
#define BACKLIGHT_LVDS_OFF
#undef BACKLIGHT_DAC_OFF
/* We turn off the LCD completely instead of just dimming the backlight.
* This provides some greater power saving and the display is useless
* without backlight anyway.
*/
static int radeon_set_backlight_enable(int on, int level, void *data)
{
struct radeonfb_info *rinfo = (struct radeonfb_info *)data;
unsigned int lvds_gen_cntl = INREG(LVDS_GEN_CNTL);
int* conv_table;
/* Pardon me for that hack... maybe some day we can figure
* out in what direction backlight should work on a given
* panel ?
*/
if ((rinfo->arch == RADEON_M7 || rinfo->arch == RADEON_M9)
&& !machine_is_compatible("PowerBook4,3"))
conv_table = backlight_conv_m7;
else
conv_table = backlight_conv_m6;
lvds_gen_cntl |= (LVDS_BL_MOD_EN | LVDS_BLON);
if (on && (level > BACKLIGHT_OFF)) {
lvds_gen_cntl |= LVDS_DIGON;
if (!lvds_gen_cntl & LVDS_ON) {
lvds_gen_cntl &= ~LVDS_BLON;
OUTREG(LVDS_GEN_CNTL, lvds_gen_cntl);
(void)INREG(LVDS_GEN_CNTL);
mdelay(10);
lvds_gen_cntl |= LVDS_BLON;
OUTREG(LVDS_GEN_CNTL, lvds_gen_cntl);
}
lvds_gen_cntl &= ~LVDS_BL_MOD_LEVEL_MASK;
lvds_gen_cntl |= (conv_table[level] <<
LVDS_BL_MOD_LEVEL_SHIFT);
lvds_gen_cntl |= (LVDS_ON | LVDS_EN);
lvds_gen_cntl &= ~LVDS_DISPLAY_DIS;
} else {
lvds_gen_cntl &= ~LVDS_BL_MOD_LEVEL_MASK;
lvds_gen_cntl |= (conv_table[0] <<
LVDS_BL_MOD_LEVEL_SHIFT);
lvds_gen_cntl |= LVDS_DISPLAY_DIS;
OUTREG(LVDS_GEN_CNTL, lvds_gen_cntl);
udelay(10);
lvds_gen_cntl &= ~(LVDS_ON | LVDS_EN | LVDS_BLON | LVDS_DIGON);
}
OUTREG(LVDS_GEN_CNTL, lvds_gen_cntl);
rinfo->init_state.lvds_gen_cntl &= ~LVDS_STATE_MASK;
rinfo->init_state.lvds_gen_cntl |= (lvds_gen_cntl & LVDS_STATE_MASK);
return 0;
}
static int radeon_set_backlight_level(int level, void *data)
{
return radeon_set_backlight_enable(1, level, data);
}
#endif /* CONFIG_PMAC_BACKLIGHT */
#ifdef CONFIG_PMAC_PBOOK
static u32 dbg_clk;
/*
* Radeon M6 Power Management code. This code currently only supports
* the mobile chips, it's based from some informations provided by ATI
* along with hours of tracing of MacOS drivers
*/
static void radeon_pm_save_regs(struct radeonfb_info *rinfo)
{
rinfo->save_regs[0] = INPLL(PLL_PWRMGT_CNTL);
rinfo->save_regs[1] = INPLL(CLK_PWRMGT_CNTL);
rinfo->save_regs[2] = INPLL(MCLK_CNTL);
rinfo->save_regs[3] = INPLL(SCLK_CNTL);
rinfo->save_regs[4] = INPLL(CLK_PIN_CNTL);
rinfo->save_regs[5] = INPLL(VCLK_ECP_CNTL);
rinfo->save_regs[6] = INPLL(PIXCLKS_CNTL);
rinfo->save_regs[7] = INPLL(MCLK_MISC);
rinfo->save_regs[8] = INPLL(P2PLL_CNTL);
rinfo->save_regs[9] = INREG(DISP_MISC_CNTL);
rinfo->save_regs[10] = INREG(DISP_PWR_MAN);
rinfo->save_regs[11] = INREG(LVDS_GEN_CNTL);
rinfo->save_regs[12] = INREG(LVDS_PLL_CNTL);
rinfo->save_regs[13] = INREG(TV_DAC_CNTL);
rinfo->save_regs[14] = INREG(BUS_CNTL1);
rinfo->save_regs[15] = INREG(CRTC_OFFSET_CNTL);
rinfo->save_regs[16] = INREG(AGP_CNTL);
rinfo->save_regs[17] = (INREG(CRTC_GEN_CNTL) & 0xfdffffff) | 0x04000000;
rinfo->save_regs[18] = (INREG(CRTC2_GEN_CNTL) & 0xfdffffff) | 0x04000000;
rinfo->save_regs[19] = INREG(GPIOPAD_A);
rinfo->save_regs[20] = INREG(GPIOPAD_EN);
rinfo->save_regs[21] = INREG(GPIOPAD_MASK);
rinfo->save_regs[22] = INREG(ZV_LCDPAD_A);
rinfo->save_regs[23] = INREG(ZV_LCDPAD_EN);
rinfo->save_regs[24] = INREG(ZV_LCDPAD_MASK);
rinfo->save_regs[25] = INREG(GPIO_VGA_DDC);
rinfo->save_regs[26] = INREG(GPIO_DVI_DDC);
rinfo->save_regs[27] = INREG(GPIO_MONID);
rinfo->save_regs[28] = INREG(GPIO_CRT2_DDC);
rinfo->save_regs[29] = INREG(SURFACE_CNTL);
rinfo->save_regs[30] = INREG(MC_FB_LOCATION);
rinfo->save_regs[31] = INREG(DISPLAY_BASE_ADDR);
rinfo->save_regs[32] = INREG(MC_AGP_LOCATION);
rinfo->save_regs[33] = INREG(CRTC2_DISPLAY_BASE_ADDR);
}
static void radeon_pm_restore_regs(struct radeonfb_info *rinfo)
{
OUTPLL(P2PLL_CNTL, rinfo->save_regs[8] & 0xFFFFFFFE); /* First */
OUTPLL(PLL_PWRMGT_CNTL, rinfo->save_regs[0]);
OUTPLL(CLK_PWRMGT_CNTL, rinfo->save_regs[1]);
OUTPLL(MCLK_CNTL, rinfo->save_regs[2]);
OUTPLL(SCLK_CNTL, rinfo->save_regs[3]);
OUTPLL(CLK_PIN_CNTL, rinfo->save_regs[4]);
OUTPLL(VCLK_ECP_CNTL, rinfo->save_regs[5]);
OUTPLL(PIXCLKS_CNTL, rinfo->save_regs[6]);
OUTPLL(MCLK_MISC, rinfo->save_regs[7]);
OUTREG(DISP_MISC_CNTL, rinfo->save_regs[9]);
OUTREG(DISP_PWR_MAN, rinfo->save_regs[10]);
OUTREG(LVDS_GEN_CNTL, rinfo->save_regs[11]);
OUTREG(LVDS_PLL_CNTL,rinfo->save_regs[12]);
OUTREG(TV_DAC_CNTL, rinfo->save_regs[13]);
OUTREG(BUS_CNTL1, rinfo->save_regs[14]);
OUTREG(CRTC_OFFSET_CNTL, rinfo->save_regs[15]);
OUTREG(AGP_CNTL, rinfo->save_regs[16]);
OUTREG(CRTC_GEN_CNTL, rinfo->save_regs[17]);
OUTREG(CRTC2_GEN_CNTL, rinfo->save_regs[18]);
// wait VBL before that one ?
OUTPLL(P2PLL_CNTL, rinfo->save_regs[8]);
OUTREG(GPIOPAD_A, rinfo->save_regs[19]);
OUTREG(GPIOPAD_EN, rinfo->save_regs[20]);
OUTREG(GPIOPAD_MASK, rinfo->save_regs[21]);
OUTREG(ZV_LCDPAD_A, rinfo->save_regs[22]);
OUTREG(ZV_LCDPAD_EN, rinfo->save_regs[23]);
OUTREG(ZV_LCDPAD_MASK, rinfo->save_regs[24]);
OUTREG(GPIO_VGA_DDC, rinfo->save_regs[25]);
OUTREG(GPIO_DVI_DDC, rinfo->save_regs[26]);
OUTREG(GPIO_MONID, rinfo->save_regs[27]);
OUTREG(GPIO_CRT2_DDC, rinfo->save_regs[28]);
}
static void radeon_pm_disable_iopad(struct radeonfb_info *rinfo)
{
OUTREG(GPIOPAD_MASK, 0x0001ffff);
OUTREG(GPIOPAD_EN, 0x00000400);
OUTREG(GPIOPAD_A, 0x00000000);
OUTREG(ZV_LCDPAD_MASK, 0x00000000);
OUTREG(ZV_LCDPAD_EN, 0x00000000);
OUTREG(ZV_LCDPAD_A, 0x00000000);
OUTREG(GPIO_VGA_DDC, 0x00030000);
OUTREG(GPIO_DVI_DDC, 0x00000000);
OUTREG(GPIO_MONID, 0x00030000);
OUTREG(GPIO_CRT2_DDC, 0x00000000);
}
static void radeon_pm_program_v2clk(struct radeonfb_info *rinfo)
{
//
// u32 reg;
//
// OUTPLL(P2PLL_REF_DIV, 0x0c);
//
// .../... figure out what macos does here
}
static void radeon_pm_low_current(struct radeonfb_info *rinfo)
{
u32 reg;
reg = INREG(BUS_CNTL1);
reg &= ~BUS_CNTL1_MOBILE_PLATFORM_SEL_MASK;
reg |= BUS_CNTL1_AGPCLK_VALID | (1<<BUS_CNTL1_MOBILE_PLATFORM_SEL_SHIFT);
OUTREG(BUS_CNTL1, reg);
reg = INPLL(PLL_PWRMGT_CNTL);
reg |= PLL_PWRMGT_CNTL_SPLL_TURNOFF | PLL_PWRMGT_CNTL_PPLL_TURNOFF |
PLL_PWRMGT_CNTL_P2PLL_TURNOFF | PLL_PWRMGT_CNTL_TVPLL_TURNOFF;
reg &= ~PLL_PWRMGT_CNTL_SU_MCLK_USE_BCLK;
reg &= ~PLL_PWRMGT_CNTL_MOBILE_SU;
OUTPLL(PLL_PWRMGT_CNTL, reg);
// reg = INPLL(TV_PLL_CNTL1);
// reg |= TV_PLL_CNTL1__TVPLL_RESET | TV_PLL_CNTL1__TVPLL_SLEEP;
// OUTPLL(TV_PLL_CNTL1, reg);
reg = INREG(TV_DAC_CNTL);
reg &= ~(TV_DAC_CNTL_BGADJ_MASK |TV_DAC_CNTL_DACADJ_MASK);
reg |=TV_DAC_CNTL_BGSLEEP | TV_DAC_CNTL_RDACPD | TV_DAC_CNTL_GDACPD |
TV_DAC_CNTL_BDACPD |
(8<<TV_DAC_CNTL_BGADJ__SHIFT) | (8<<TV_DAC_CNTL_DACADJ__SHIFT);
OUTREG(TV_DAC_CNTL, reg);
reg = INREG(TMDS_TRANSMITTER_CNTL);
reg &= ~(TMDS_PLL_EN |TMDS_PLLRST);
OUTREG(TMDS_TRANSMITTER_CNTL, reg);
// lvds_pll_cntl = regr32(g, LVDS_PLL_CNTL);
// lvds_pll_cntl &= ~LVDS_PLL_CNTL__LVDS_PLL_EN;
// lvds_pll_cntl |= LVDS_PLL_CNTL__LVDS_PLL_RESET;
// regw32(g, LVDS_PLL_CNTL, lvds_pll_cntl);
reg = INREG(DAC_CNTL);
reg &= ~DAC_CMP_EN;
OUTREG(DAC_CNTL, reg);
reg = INREG(DAC_CNTL2);
reg &= ~DAC2_CMP_EN;
OUTREG(DAC_CNTL2, reg);
reg = INREG(TV_DAC_CNTL);
reg &= ~TV_DAC_CNTL_DETECT;
OUTREG(TV_DAC_CNTL, reg);
}
static void radeon_pm_setup_for_suspend(struct radeonfb_info *rinfo)
{
/* This code is disabled. It does what is in the pm_init
* function of the MacOS driver code ATI sent me. However,
* it doesn't fix my sleep problem, and is causing other issues
* on wakeup (bascially the machine dying when switching consoles
* I haven't had time to investigate this yet
*/
#if 0
u32 disp_misc_cntl;
u32 disp_pwr_man;
u32 temp;
// set SPLL, MPLL, PPLL, P2PLL, TVPLL, SCLK, MCLK, PCLK, P2CLK,
// TCLK and TEST_MODE to 0
temp = INPLL(CLK_PWRMGT_CNTL);
OUTPLL(CLK_PWRMGT_CNTL , temp & ~0xc00002ff);
// Turn on Power Management
temp = INPLL(CLK_PWRMGT_CNTL);
OUTPLL(CLK_PWRMGT_CNTL , temp | 0x00000400);
// Turn off display clock if using mobile chips
temp = INPLL(CLK_PWRMGT_CNTL);
OUTREG(CLK_PWRMGT_CNTL , temp | 0x00100000);
// Force PIXCLK_ALWAYS_ON and PIXCLK_DAC_ALWAYS_ON
temp = INPLL(VCLK_ECP_CNTL);
OUTPLL(VCLK_ECP_CNTL, temp & ~0x000000c0);
// Force ECP_FORCE_ON to 1
temp = INPLL(VCLK_ECP_CNTL);
OUTPLL(VCLK_ECP_CNTL, temp | 0x00040000);
// Force PIXCLK_BLEND_ALWAYS_ON and PIXCLK_GV_ALWAYS_ON
temp = INPLL(PIXCLKS_CNTL);
OUTPLL(PIXCLKS_CNTL, temp & ~0x00001800);
// Forcing SCLK_CNTL to ON
OUTPLL(SCLK_CNTL, (INPLL(SCLK_CNTL)& 0x00000007) | 0xffff8000 );
// Set PM control over XTALIN pad
temp = INPLL(CLK_PIN_CNTL);
OUTPLL(CLK_PIN_CNTL, temp | 0x00080000);
// Force MCLK and YCLK and MC as dynamic
temp = INPLL(MCLK_CNTL);
OUTPLL(MCLK_CNTL, temp & 0xffeaffff);
// PLL_TURNOFF
temp = INPLL(PLL_PWRMGT_CNTL);
OUTPLL(PLL_PWRMGT_CNTL, temp | 0x0000001f);
// set MOBILE_SU to 1 if M6 or DDR64 is detected
temp = INPLL(PLL_PWRMGT_CNTL);
OUTPLL(PLL_PWRMGT_CNTL, temp | 0x00010000);
// select PM access mode (PM_MODE_SEL) (use ACPI mode)
// temp = INPLL(PLL_PWRMGT_CNTL);
// OUTPLL(PLL_PWRMGT_CNTL, temp | 0x00002000);
temp = INPLL(PLL_PWRMGT_CNTL);
OUTPLL(PLL_PWRMGT_CNTL, temp & ~0x00002000);
// set DISP_MISC_CNTL register
disp_misc_cntl = INREG(DISP_MISC_CNTL);
disp_misc_cntl &= ~( DISP_MISC_CNTL_SOFT_RESET_GRPH_PP |
DISP_MISC_CNTL_SOFT_RESET_SUBPIC_PP |
DISP_MISC_CNTL_SOFT_RESET_OV0_PP |
DISP_MISC_CNTL_SOFT_RESET_GRPH_SCLK |
DISP_MISC_CNTL_SOFT_RESET_SUBPIC_SCLK |
DISP_MISC_CNTL_SOFT_RESET_OV0_SCLK |
DISP_MISC_CNTL_SOFT_RESET_GRPH2_PP |
DISP_MISC_CNTL_SOFT_RESET_GRPH2_SCLK |
DISP_MISC_CNTL_SOFT_RESET_LVDS |
DISP_MISC_CNTL_SOFT_RESET_TMDS |
DISP_MISC_CNTL_SOFT_RESET_DIG_TMDS |
DISP_MISC_CNTL_SOFT_RESET_TV);
OUTREG(DISP_MISC_CNTL, disp_misc_cntl);
// set DISP_PWR_MAN register
disp_pwr_man = INREG(DISP_PWR_MAN);
// clau - 9.29.2000 - changes made to bit23:18 to set to 1 as requested by George
disp_pwr_man |= (DISP_PWR_MAN_DIG_TMDS_ENABLE_RST |
DISP_PWR_MAN_TV_ENABLE_RST |
// DISP_PWR_MAN_AUTO_PWRUP_EN |
DISP_PWR_MAN_DISP_D3_GRPH_RST |
DISP_PWR_MAN_DISP_D3_SUBPIC_RST |
DISP_PWR_MAN_DISP_D3_OV0_RST |
DISP_PWR_MAN_DISP_D1D2_GRPH_RST |
DISP_PWR_MAN_DISP_D1D2_SUBPIC_RST |
DISP_PWR_MAN_DISP_D1D2_OV0_RST);
disp_pwr_man &= ~(DISP_PWR_MAN_DISP_PWR_MAN_D3_CRTC_EN |
DISP_PWR_MAN_DISP2_PWR_MAN_D3_CRTC2_EN|
DISP_PWR_MAN_DISP_D3_RST |
DISP_PWR_MAN_DISP_D3_REG_RST);
OUTREG(DISP_PWR_MAN, disp_pwr_man);
// clau - 10.24.2000
// - add in setting for BUS_CNTL1 b27:26 = 0x01 and b31 = 0x1
// - add in setting for AGP_CNTL b7:0 = 0x20
// - add in setting for DVI_DDC_DATA_OUT_EN b17:16 = 0x0
// the following settings (two lines) are applied at a later part of this function, only on mobile platform
// requres -mobile flag
OUTREG(BUS_CNTL1, (INREG(BUS_CNTL1) & 0xf3ffffff) | 0x04000000);
OUTREG(BUS_CNTL1, INREG(BUS_CNTL1) | 0x80000000);
OUTREG(AGP_CNTL, (INREG(AGP_CNTL) & 0xffffff00) | 0x20);
OUTREG(GPIO_DVI_DDC, INREG(GPIO_DVI_DDC) & 0xfffcffff);
// yulee - 12.12.2000
// A12 only
// EN_MCLK_TRISTATE_IN_SUSPEND@MCLK_MISC = 1
// ACCESS_REGS_IN_SUSPEND@CLK_PIN_CNTL = 0
// only on mobile platform
OUTPLL(MCLK_MISC, INPLL(MCLK_MISC) | 0x00040000 );
// yulee -12.12.2000
// AGPCLK_VALID@BUS_CNTL1 = 1
// MOBILE_PLATFORM_SEL@BUS_CNTL1 = 01
// CRTC_STEREO_SYNC_OUT_EN@CRTC_OFFSET_CNTL = 0
// CG_CLK_TO_OUTPIN@CLK_PIN_CNTL = 0
// only on mobile platform
OUTPLL(CLK_PIN_CNTL, INPLL(CLK_PIN_CNTL ) & 0xFFFFF7FF );
OUTREG(BUS_CNTL1, (INREG(BUS_CNTL1 ) & 0xF3FFFFFF) | 0x84000000 );
OUTREG(CRTC_OFFSET_CNTL, INREG(CRTC_OFFSET_CNTL ) & 0xFFEFFFFF );
mdelay(100);
#endif
/* Disable CRTCs */
OUTREG(CRTC_GEN_CNTL, (INREG(CRTC_GEN_CNTL) & ~CRTC_EN) | CRTC_DISP_REQ_EN_B);
OUTREG(CRTC2_GEN_CNTL, (INREG(CRTC2_GEN_CNTL) & ~CRTC2_EN) | CRTC2_DISP_REQ_EN_B);
(void)INREG(CRTC2_GEN_CNTL);
mdelay(17);
}
static void radeon_set_suspend(struct radeonfb_info *rinfo, int suspend)
{
u16 pwr_cmd;
if (!rinfo->pm_reg)
return;
/* Set the chip into appropriate suspend mode (we use D2,
* D3 would require a compete re-initialization of the chip,
* including PCI config registers, clocks, AGP conf, ...)
*/
if (suspend) {
/* According to ATI, we should program V2CLK here, I have
* to verify what's up exactly
*/
/* Save some registers */
radeon_pm_save_regs(rinfo);
/* Check that on M7 too, might work might not. M7 may also
* need explicit enabling of PM
*/
if (rinfo->arch == RADEON_M6) {
/* Program V2CLK */
radeon_pm_program_v2clk(rinfo);
/* Disable IO PADs */
radeon_pm_disable_iopad(rinfo);
/* Set low current */
radeon_pm_low_current(rinfo);
/* Prepare chip for power management */
radeon_pm_setup_for_suspend(rinfo);
/* Reset the MDLL */
OUTPLL(MDLL_CKO, INPLL(MDLL_CKO) | MCKOA_RESET);
(void)INPLL(MDLL_RDCKA);
OUTPLL(MDLL_CKO, INPLL(MDLL_CKO) & ~MCKOA_RESET);
(void)INPLL(MDLL_RDCKA);
}
/* Switch PCI power managment to D2. */
for (;;) {
pci_read_config_word(
rinfo->pdev, rinfo->pm_reg+PCI_PM_CTRL,
&pwr_cmd);
if (pwr_cmd & 2)
break;
pci_write_config_word(
rinfo->pdev, rinfo->pm_reg+PCI_PM_CTRL,
(pwr_cmd & ~PCI_PM_CTRL_STATE_MASK) | 2);
mdelay(500);
}
} else {
/* Switch back PCI powermanagment to D0 */
mdelay(200);
pci_write_config_word(rinfo->pdev, rinfo->pm_reg+PCI_PM_CTRL, 0);
mdelay(500);
dbg_clk = INPLL(1);
/* Do we need that on M7 ? */
if (rinfo->arch == RADEON_M6) {
/* Restore the MDLL */
OUTPLL(MDLL_CKO, INPLL(MDLL_CKO) & ~MCKOA_RESET);
(void)INPLL(MDLL_CKO);
}
/* Restore some registers */
radeon_pm_restore_regs(rinfo);
}
}
/*
* Save the contents of the framebuffer when we go to sleep,
* and restore it when we wake up again.
*/
int radeon_sleep_notify(struct pmu_sleep_notifier *self, int when)
{
struct radeonfb_info *rinfo;
for (rinfo = board_list; rinfo != NULL; rinfo = rinfo->next) {
struct fb_fix_screeninfo fix;
int nb;
struct display *disp;
disp = (rinfo->currcon < 0) ? rinfo->info.disp : &fb_display[rinfo->currcon];
switch (rinfo->arch) {
case RADEON_M6:
case RADEON_M7:
case RADEON_M9:
break;
default:
return PBOOK_SLEEP_REFUSE;
}
radeonfb_get_fix(&fix, fg_console, (struct fb_info *)rinfo);
nb = fb_display[fg_console].var.yres * fix.line_length;
switch (when) {
case PBOOK_SLEEP_NOW:
acquire_console_sem();
disp->dispsw = &fbcon_dummy;
if (!noaccel) {
/* Make sure engine is reset */
radeon_engine_reset();
radeon_engine_idle();
}
/* Blank display and LCD */
radeonfb_blank(VESA_POWERDOWN+1,
(struct fb_info *)rinfo);
/* Sleep */
rinfo->asleep = 1;
radeon_set_suspend(rinfo, 1);
release_console_sem();
break;
case PBOOK_WAKE:
acquire_console_sem();
/* Wakeup */
radeon_set_suspend(rinfo, 0);
if (!noaccel)
radeon_engine_init(rinfo);
rinfo->asleep = 0;
radeon_set_dispsw(rinfo, disp);
radeon_load_video_mode(rinfo, &disp->var);
do_install_cmap(rinfo->currcon < 0 ? 0 : rinfo->currcon,
(struct fb_info *)rinfo);
radeonfb_blank(0, (struct fb_info *)rinfo);
release_console_sem();
printk("CLK_PIN_CNTL on wakeup was: %08x\n", dbg_clk);
break;
}
}
return PBOOK_SLEEP_OK;
}
#endif /* CONFIG_PMAC_PBOOK */
static int radeonfb_pci_register (struct pci_dev *pdev,
const struct pci_device_id *ent)
{
struct radeonfb_info *rinfo;
struct radeon_chip_info *rci = &radeon_chip_info[ent->driver_data];
u32 tmp;
RTRACE("radeonfb_pci_register BEGIN\n");
/* Enable device in PCI config */
if (pci_enable_device(pdev) != 0) {
printk(KERN_ERR "radeonfb: Cannot enable PCI device\n");
return -ENODEV;
}
rinfo = kmalloc (sizeof (struct radeonfb_info), GFP_KERNEL);
if (!rinfo) {
printk ("radeonfb: could not allocate memory\n");
return -ENODEV;
}
memset (rinfo, 0, sizeof (struct radeonfb_info));
//info = &rinfo->info;
rinfo->pdev = pdev;
strcpy(rinfo->name, rci->name);
rinfo->arch = rci->arch;
/* Set base addrs */
rinfo->fb_base_phys = pci_resource_start (pdev, 0);
rinfo->mmio_base_phys = pci_resource_start (pdev, 2);
/* request the mem regions */
if (!request_mem_region (rinfo->fb_base_phys,
pci_resource_len(pdev, 0), "radeonfb")) {
printk ("radeonfb: cannot reserve FB region\n");
kfree (rinfo);
return -ENODEV;
}
if (!request_mem_region (rinfo->mmio_base_phys,
pci_resource_len(pdev, 2), "radeonfb")) {
printk ("radeonfb: cannot reserve MMIO region\n");
release_mem_region (rinfo->fb_base_phys,
pci_resource_len(pdev, 0));
kfree (rinfo);
return -ENODEV;
}
/* map the regions */
rinfo->mmio_base = (unsigned long) ioremap (rinfo->mmio_base_phys, RADEON_REGSIZE);
if (!rinfo->mmio_base) {
printk ("radeonfb: cannot map MMIO\n");
release_mem_region (rinfo->mmio_base_phys,
pci_resource_len(pdev, 2));
release_mem_region (rinfo->fb_base_phys,
pci_resource_len(pdev, 0));
kfree (rinfo);
return -ENODEV;
}
rinfo->chipset = pdev->device;
switch (rinfo->arch) {
case RADEON_R100:
rinfo->hasCRTC2 = 0;
break;
default:
/* all the rest have it */
rinfo->hasCRTC2 = 1;
break;
}
#if 0
if (rinfo->arch == RADEON_M7) {
/*
* Noticed some errors in accel with M7, will have to work these out...
*/
noaccel = 1;
}
#endif
if (mirror)
printk("radeonfb: mirroring display to CRT\n");
/* framebuffer size */
tmp = INREG(CONFIG_MEMSIZE);
/* mem size is bits [28:0], mask off the rest */
rinfo->video_ram = tmp & CONFIG_MEMSIZE_MASK;
/* ram type */
tmp = INREG(MEM_SDRAM_MODE_REG);
switch ((MEM_CFG_TYPE & tmp) >> 30) {
case 0:
/* SDR SGRAM (2:1) */
strcpy(rinfo->ram_type, "SDR SGRAM");
rinfo->ram.ml = 4;
rinfo->ram.mb = 4;
rinfo->ram.trcd = 1;
rinfo->ram.trp = 2;
rinfo->ram.twr = 1;
rinfo->ram.cl = 2;
rinfo->ram.loop_latency = 16;
rinfo->ram.rloop = 16;
break;
case 1:
/* DDR SGRAM */
strcpy(rinfo->ram_type, "DDR SGRAM");
rinfo->ram.ml = 4;
rinfo->ram.mb = 4;
rinfo->ram.trcd = 3;
rinfo->ram.trp = 3;
rinfo->ram.twr = 2;
rinfo->ram.cl = 3;
rinfo->ram.tr2w = 1;
rinfo->ram.loop_latency = 16;
rinfo->ram.rloop = 16;
break;
default:
/* 64-bit SDR SGRAM */
strcpy(rinfo->ram_type, "SDR SGRAM 64");
rinfo->ram.ml = 4;
rinfo->ram.mb = 8;
rinfo->ram.trcd = 3;
rinfo->ram.trp = 3;
rinfo->ram.twr = 1;
rinfo->ram.cl = 3;
rinfo->ram.tr2w = 1;
rinfo->ram.loop_latency = 17;
rinfo->ram.rloop = 17;
break;
}
rinfo->bios_seg = radeon_find_rom(rinfo);
radeon_get_pllinfo(rinfo, rinfo->bios_seg);
/*
* Hack to get around some busted production M6's
* reporting no ram
*/
if (rinfo->video_ram == 0) {
switch (pdev->device) {
case PCI_DEVICE_ID_ATI_RADEON_LY:
case PCI_DEVICE_ID_ATI_RADEON_LZ:
rinfo->video_ram = 8192 * 1024;
break;
default:
break;
}
}
RTRACE("radeonfb: probed %s %dk videoram\n", (rinfo->ram_type), (rinfo->video_ram/1024));
#if !defined(__powerpc__)
radeon_get_moninfo(rinfo);
#else
switch (pdev->device) {
case PCI_DEVICE_ID_ATI_RADEON_LW:
case PCI_DEVICE_ID_ATI_RADEON_LX:
case PCI_DEVICE_ID_ATI_RADEON_LY:
case PCI_DEVICE_ID_ATI_RADEON_LZ:
rinfo->dviDisp_type = MT_LCD;
break;
default:
radeon_get_moninfo(rinfo);
break;
}
#endif
radeon_get_EDID(rinfo);
if ((rinfo->dviDisp_type == MT_DFP) || (rinfo->dviDisp_type == MT_LCD) ||
(rinfo->crtDisp_type == MT_DFP)) {
if (!radeon_get_dfpinfo(rinfo)) {
iounmap ((void*)rinfo->mmio_base);
release_mem_region (rinfo->mmio_base_phys,
pci_resource_len(pdev, 2));
release_mem_region (rinfo->fb_base_phys,
pci_resource_len(pdev, 0));
kfree (rinfo);
return -ENODEV;
}
}
rinfo->fb_base = (unsigned long) ioremap (rinfo->fb_base_phys, rinfo->video_ram);
if (!rinfo->fb_base) {
printk ("radeonfb: cannot map FB\n");
iounmap ((void*)rinfo->mmio_base);
release_mem_region (rinfo->mmio_base_phys,
pci_resource_len(pdev, 2));
release_mem_region (rinfo->fb_base_phys,
pci_resource_len(pdev, 0));
kfree (rinfo);
return -ENODEV;
}
/* I SHOULD FIX THAT CRAP ! I should probably mimmic XFree DRI
* driver setup here.
*
* On PPC, OF based cards setup the internal memory
* mapping in strange ways. We change it so that the
* framebuffer is mapped at 0 and given half of the card's
* address space (2Gb). AGP is mapped high (0xe0000000) and
* can use up to 512Mb. Once DRI is fully implemented, we
* will have to setup the PCI remapper to remap the agp_special_page
* memory page somewhere between those regions so that the card
* use a normal PCI bus master cycle to access the ring read ptr.
* --BenH.
*/
#ifdef CONFIG_ALL_PPC
if (rinfo->hasCRTC2)
OUTREG(CRTC2_GEN_CNTL,
(INREG(CRTC2_GEN_CNTL) & ~CRTC2_EN) | CRTC2_DISP_REQ_EN_B);
OUTREG(CRTC_EXT_CNTL, INREG(CRTC_EXT_CNTL) | CRTC_DISPLAY_DIS);
OUTREG(MC_FB_LOCATION, 0x7fff0000);
OUTREG(MC_AGP_LOCATION, 0xffffe000);
OUTREG(DISPLAY_BASE_ADDR, 0x00000000);
if (rinfo->hasCRTC2)
OUTREG(CRTC2_DISPLAY_BASE_ADDR, 0x00000000);
OUTREG(SRC_OFFSET, 0x00000000);
OUTREG(DST_OFFSET, 0x00000000);
mdelay(10);
OUTREG(CRTC_EXT_CNTL, INREG(CRTC_EXT_CNTL) & ~CRTC_DISPLAY_DIS);
#endif /* CONFIG_ALL_PPC */
/* save current mode regs before we switch into the new one
* so we can restore this upon __exit
*/
radeon_save_state (rinfo, &rinfo->init_state);
if (!noaccel) {
/* initialize the engine */
radeon_engine_init (rinfo);
}
/* set all the vital stuff */
radeon_set_fbinfo (rinfo);
pci_set_drvdata(pdev, rinfo);
rinfo->next = board_list;
board_list = rinfo;
if (register_framebuffer ((struct fb_info *) rinfo) < 0) {
printk ("radeonfb: could not register framebuffer\n");
iounmap ((void*)rinfo->fb_base);
iounmap ((void*)rinfo->mmio_base);
release_mem_region (rinfo->mmio_base_phys,
pci_resource_len(pdev, 2));
release_mem_region (rinfo->fb_base_phys,
pci_resource_len(pdev, 0));
kfree (rinfo);
return -ENODEV;
}
#ifdef CONFIG_MTRR
rinfo->mtrr_hdl = nomtrr ? -1 : mtrr_add(rinfo->fb_base_phys,
rinfo->video_ram,
MTRR_TYPE_WRCOMB, 1);
#endif
#ifdef CONFIG_PMAC_BACKLIGHT
if (rinfo->dviDisp_type == MT_LCD)
register_backlight_controller(&radeon_backlight_controller,
rinfo, "ati");
#endif
#ifdef CONFIG_PMAC_PBOOK
if (rinfo->dviDisp_type == MT_LCD) {
rinfo->pm_reg = pci_find_capability(pdev, PCI_CAP_ID_PM);
pmu_register_sleep_notifier(&radeon_sleep_notifier);
}
#endif
printk ("radeonfb: ATI Radeon %s %s %d MB\n", rinfo->name, rinfo->ram_type,
(rinfo->video_ram/(1024*1024)));
if (rinfo->hasCRTC2) {
printk("radeonfb: DVI port %s monitor connected\n",
GET_MON_NAME(rinfo->dviDisp_type));
printk("radeonfb: CRT port %s monitor connected\n",
GET_MON_NAME(rinfo->crtDisp_type));
} else {
printk("radeonfb: CRT port %s monitor connected\n",
GET_MON_NAME(rinfo->crtDisp_type));
}
RTRACE("radeonfb_pci_register END\n");
return 0;
}
static void __devexit radeonfb_pci_unregister (struct pci_dev *pdev)
{
struct radeonfb_info *rinfo = pci_get_drvdata(pdev);
if (!rinfo)
return;
/* restore original state
*
* Doesn't quite work yet, possibly because of the PPC hacking
* I do on startup, disable for now. --BenH
*/
radeon_write_mode (rinfo, &rinfo->init_state);
#ifdef CONFIG_MTRR
if (rinfo->mtrr_hdl >= 0)
mtrr_del(rinfo->mtrr_hdl, 0, 0);
#endif
unregister_framebuffer ((struct fb_info *) rinfo);
iounmap ((void*)rinfo->mmio_base);
iounmap ((void*)rinfo->fb_base);
release_mem_region (rinfo->mmio_base_phys,
pci_resource_len(pdev, 2));
release_mem_region (rinfo->fb_base_phys,
pci_resource_len(pdev, 0));
kfree (rinfo);
}
static struct pci_driver radeonfb_driver = {
.name = "radeonfb",
.id_table = radeonfb_pci_table,
.probe = radeonfb_pci_register,
.remove = __devexit_p(radeonfb_pci_unregister),
};
int __init radeonfb_init (void)
{
return pci_module_init (&radeonfb_driver);
}
void __exit radeonfb_exit (void)
{
pci_unregister_driver (&radeonfb_driver);
}
int __init radeonfb_setup (char *options)
{
char *this_opt;
if (!options || !*options)
return 0;
while ((this_opt = strsep (&options, ",")) != NULL) {
if (!*this_opt)
continue;
if (!strncmp(this_opt, "noaccel", 7)) {
noaccel = 1;
} else if (!strncmp(this_opt, "mirror", 6)) {
mirror = 1;
} else if (!strncmp(this_opt, "dfp", 3)) {
force_dfp = 1;
} else if (!strncmp(this_opt, "panel_yres:", 11)) {
panel_yres = simple_strtoul((this_opt+11), NULL, 0);
} else if (!strncmp(this_opt, "nomtrr", 6)) {
nomtrr = 1;
} else
mode_option = this_opt;
}
return 0;
}
#ifdef MODULE
module_init(radeonfb_init);
module_exit(radeonfb_exit);
#endif
MODULE_AUTHOR("Ani Joshi");
MODULE_DESCRIPTION("framebuffer driver for ATI Radeon chipset");
MODULE_LICENSE("GPL");

/shark/trunk/drivers/fb/riva/rivafb.h
0,0 → 1,61
#ifndef __RIVAFB_H
#define __RIVAFB_H
#include <linux/config.h>
#include <linux/fb.h>
#include <video/vga.h>
#include "riva_hw.h"
/* GGI compatibility macros */
#define NUM_SEQ_REGS 0x05
#define NUM_CRT_REGS 0x41
#define NUM_GRC_REGS 0x09
#define NUM_ATC_REGS 0x15
/* holds the state of the VGA core and extended Riva hw state from riva_hw.c.
* From KGI originally. */
struct riva_regs {
u8 attr[NUM_ATC_REGS];
u8 crtc[NUM_CRT_REGS];
u8 gra[NUM_GRC_REGS];
u8 seq[NUM_SEQ_REGS];
u8 misc_output;
RIVA_HW_STATE ext;
};
struct riva_par {
RIVA_HW_INST riva; /* interface to riva_hw.c */
caddr_t ctrl_base; /* virtual control register base addr */
unsigned dclk_max; /* max DCLK */
struct riva_regs initial_state; /* initial startup video mode */
struct riva_regs current_state;
struct vgastate state;
atomic_t ref_count;
u32 cursor_data[32 * 32/4];
int cursor_reset;
unsigned char *EDID;
int panel_xres, panel_yres;
int hOver_plus, hSync_width, hblank;
int vOver_plus, vSync_width, vblank;
int hAct_high, vAct_high, interlaced;
int synct, misc, clock;
int use_default_var;
int got_dfpinfo;
unsigned int Chipset;
int forceCRTC;
Bool SecondCRTC;
int FlatPanel;
#ifdef CONFIG_MTRR
struct { int vram; int vram_valid; } mtrr;
#endif
};
void riva_common_setup(struct riva_par *);
unsigned long riva_get_memlen(struct riva_par *);
unsigned long riva_get_maxdclk(struct riva_par *);
#endif /* __RIVAFB_H */

/shark/trunk/drivers/fb/riva/nv_driver.c
0,0 → 1,366
/* $XConsortium: nv_driver.c /main/3 1996/10/28 05:13:37 kaleb $ */
/*
* Copyright 1996-1997 David J. McKay
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* DAVID J. MCKAY BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
/*
* GPL licensing note -- nVidia is allowing a liberal interpretation of
* the documentation restriction above, to merely say that this nVidia's
* copyright and disclaimer should be included with all code derived
* from this source. -- Jeff Garzik <jgarzik@pobox.com>, 01/Nov/99
*/
/* Hacked together from mga driver and 3.3.4 NVIDIA driver by Jarno Paananen
<jpaana@s2.org> */
/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/nv_setup.c,v 1.18 2002/08/0
5 20:47:06 mvojkovi Exp $ */
#include <linuxcomp.h>
#include <linux/delay.h>
#include <linux/pci.h>
#include <linux/pci_ids.h>
#include "nv_type.h"
#include "rivafb.h"
#include "nvreg.h"
#ifndef CONFIG_PCI /* sanity check */
#error This driver requires PCI support.
#endif
#define PFX "rivafb: "
static inline unsigned char MISCin(struct riva_par *par)
{
return (VGA_RD08(par->riva.PVIO, 0x3cc));
}
static Bool
riva_is_connected(struct riva_par *par, Bool second)
{
volatile U032 *PRAMDAC = par->riva.PRAMDAC0;
U032 reg52C, reg608;
Bool present;
if(second) PRAMDAC += 0x800;
reg52C = PRAMDAC[0x052C/4];
reg608 = PRAMDAC[0x0608/4];
PRAMDAC[0x0608/4] = reg608 & ~0x00010000;
PRAMDAC[0x052C/4] = reg52C & 0x0000FEEE;
mdelay(1);
PRAMDAC[0x052C/4] |= 1;
par->riva.PRAMDAC0[0x0610/4] = 0x94050140;
par->riva.PRAMDAC0[0x0608/4] |= 0x00001000;
mdelay(1);
present = (PRAMDAC[0x0608/4] & (1 << 28)) ? TRUE : FALSE;
par->riva.PRAMDAC0[0x0608/4] &= 0x0000EFFF;
PRAMDAC[0x052C/4] = reg52C;
PRAMDAC[0x0608/4] = reg608;
return present;
}
static void
riva_override_CRTC(struct riva_par *par)
{
printk(KERN_INFO PFX
"Detected CRTC controller %i being used\n",
par->SecondCRTC ? 1 : 0);
if(par->forceCRTC != -1) {
printk(KERN_INFO PFX
"Forcing usage of CRTC %i\n", par->forceCRTC);
par->SecondCRTC = par->forceCRTC;
}
}
static void
riva_is_second(struct riva_par *par)
{
if (par->FlatPanel == 1) {
switch(par->Chipset) {
case NV_CHIP_GEFORCE4_440_GO:
case NV_CHIP_GEFORCE4_440_GO_M64:
case NV_CHIP_GEFORCE4_420_GO:
case NV_CHIP_GEFORCE4_420_GO_M32:
case NV_CHIP_QUADRO4_500_GOGL:
par->SecondCRTC = TRUE;
break;
default:
par->SecondCRTC = FALSE;
break;
}
} else {
if(riva_is_connected(par, 0)) {
if(par->riva.PRAMDAC0[0x0000052C/4] & 0x100)
par->SecondCRTC = TRUE;
else
par->SecondCRTC = FALSE;
} else
if (riva_is_connected(par, 1)) {
if(par->riva.PRAMDAC0[0x0000252C/4] & 0x100)
par->SecondCRTC = TRUE;
else
par->SecondCRTC = FALSE;
} else /* default */
par->SecondCRTC = FALSE;
}
riva_override_CRTC(par);
}
unsigned long riva_get_memlen(struct riva_par *par)
{
RIVA_HW_INST *chip = &par->riva;
unsigned long memlen = 0;
unsigned int chipset = par->Chipset;
struct pci_dev* dev;
int amt;
switch (chip->Architecture) {
case NV_ARCH_03:
if (chip->PFB[0x00000000/4] & 0x00000020) {
if (((chip->PMC[0x00000000/4] & 0xF0) == 0x20)
&& ((chip->PMC[0x00000000/4] & 0x0F) >= 0x02)) {
/*
* SDRAM 128 ZX.
*/
switch (chip->PFB[0x00000000/4] & 0x03) {
case 2:
memlen = 1024 * 4;
break;
case 1:
memlen = 1024 * 2;
break;
default:
memlen = 1024 * 8;
break;
}
} else {
memlen = 1024 * 8;
}
} else {
/*
* SGRAM 128.
*/
switch (chip->PFB[0x00000000/4] & 0x00000003) {
case 0:
memlen = 1024 * 8;
break;
case 2:
memlen = 1024 * 4;
break;
default:
memlen = 1024 * 2;
break;
}
}
break;
case NV_ARCH_04:
if (chip->PFB[0x00000000/4] & 0x00000100) {
memlen = ((chip->PFB[0x00000000/4] >> 12) & 0x0F) *
1024 * 2 + 1024 * 2;
} else {
switch (chip->PFB[0x00000000/4] & 0x00000003) {
case 0:
memlen = 1024 * 32;
break;
case 1:
memlen = 1024 * 4;
break;
case 2:
memlen = 1024 * 8;
break;
case 3:
default:
memlen = 1024 * 16;
break;
}
}
break;
case NV_ARCH_10:
case NV_ARCH_20:
if(chipset == NV_CHIP_IGEFORCE2) {
dev = pci_find_slot(0, 1);
pci_read_config_dword(dev, 0x7C, &amt);
memlen = (((amt >> 6) & 31) + 1) * 1024;
} else if (chipset == NV_CHIP_0x01F0) {
dev = pci_find_slot(0, 1);
pci_read_config_dword(dev, 0x84, &amt);
memlen = (((amt >> 4) & 127) + 1) * 1024;
} else {
switch ((chip->PFB[0x0000020C/4] >> 20) & 0x000000FF){
case 0x02:
memlen = 1024 * 2;
break;
case 0x04:
memlen = 1024 * 4;
break;
case 0x08:
memlen = 1024 * 8;
break;
case 0x10:
memlen = 1024 * 16;
break;
case 0x20:
memlen = 1024 * 32;
break;
case 0x40:
memlen = 1024 * 64;
break;
case 0x80:
memlen = 1024 * 128;
break;
default:
memlen = 1024 * 16;
break;
}
}
break;
}
return memlen;
}
unsigned long riva_get_maxdclk(struct riva_par *par)
{
RIVA_HW_INST *chip = &par->riva;
unsigned long dclk = 0;
switch (chip->Architecture) {
case NV_ARCH_03:
if (chip->PFB[0x00000000/4] & 0x00000020) {
if (((chip->PMC[0x00000000/4] & 0xF0) == 0x20)
&& ((chip->PMC[0x00000000/4] & 0x0F) >= 0x02)) {
/*
* SDRAM 128 ZX.
*/
dclk = 800000;
} else {
dclk = 1000000;
}
} else {
/*
* SGRAM 128.
*/
dclk = 1000000;
}
break;
case NV_ARCH_04:
case NV_ARCH_10:
case NV_ARCH_20:
switch ((chip->PFB[0x00000000/4] >> 3) & 0x00000003) {
case 3:
dclk = 800000;
break;
default:
dclk = 1000000;
break;
}
break;
}
return dclk;
}
void
riva_common_setup(struct riva_par *par)
{
par->riva.EnableIRQ = 0;
par->riva.PRAMDAC0 = (unsigned *)(par->ctrl_base + 0x00680000);
par->riva.PFB = (unsigned *)(par->ctrl_base + 0x00100000);
par->riva.PFIFO = (unsigned *)(par->ctrl_base + 0x00002000);
par->riva.PGRAPH = (unsigned *)(par->ctrl_base + 0x00400000);
par->riva.PEXTDEV = (unsigned *)(par->ctrl_base + 0x00101000);
par->riva.PTIMER = (unsigned *)(par->ctrl_base + 0x00009000);
par->riva.PMC = (unsigned *)(par->ctrl_base + 0x00000000);
par->riva.FIFO = (unsigned *)(par->ctrl_base + 0x00800000);
par->riva.PCIO0 = (U008 *)(par->ctrl_base + 0x00601000);
par->riva.PDIO0 = (U008 *)(par->ctrl_base + 0x00681000);
par->riva.PVIO = (U008 *)(par->ctrl_base + 0x000C0000);
par->riva.IO = (MISCin(par) & 0x01) ? 0x3D0 : 0x3B0;
if (par->FlatPanel == -1) {
switch (par->Chipset) {
case NV_CHIP_GEFORCE4_440_GO:
case NV_CHIP_GEFORCE4_440_GO_M64:
case NV_CHIP_GEFORCE4_420_GO:
case NV_CHIP_GEFORCE4_420_GO_M32:
case NV_CHIP_QUADRO4_500_GOGL:
case NV_CHIP_GEFORCE2_GO:
printk(KERN_INFO PFX
"On a laptop. Assuming Digital Flat Panel\n");
par->FlatPanel = 1;
break;
default:
break;
}
}
switch (par->Chipset & 0x0ff0) {
case 0x0110:
if (par->Chipset == NV_CHIP_GEFORCE2_GO)
par->SecondCRTC = TRUE;
#if defined(__powerpc__)
if (par->FlatPanel == 1)
par->SecondCRTC = TRUE;
#endif
riva_override_CRTC(par);
break;
case 0x0170:
case 0x0180:
case 0x01F0:
case 0x0250:
case 0x0280:
riva_is_second(par);
break;
default:
break;
}
if (par->SecondCRTC) {
par->riva.PCIO = par->riva.PCIO0 + 0x2000;
par->riva.PCRTC = par->riva.PCRTC0 + 0x800;
par->riva.PRAMDAC = par->riva.PRAMDAC0 + 0x800;
par->riva.PDIO = par->riva.PDIO0 + 0x2000;
} else {
par->riva.PCIO = par->riva.PCIO0;
par->riva.PCRTC = par->riva.PCRTC0;
par->riva.PRAMDAC = par->riva.PRAMDAC0;
par->riva.PDIO = par->riva.PDIO0;
}
if (par->FlatPanel == -1) {
/* Fix me, need x86 DDC code */
par->FlatPanel = 0;
}
par->riva.flatPanel = (par->FlatPanel > 0) ? TRUE : FALSE;
}

/shark/trunk/drivers/fb/riva/riva_hw.c
0,0 → 1,2207
/***************************************************************************\
|* *|
|* Copyright 1993-1999 NVIDIA, Corporation. All rights reserved. *|
|* *|
|* NOTICE TO USER: The source code is copyrighted under U.S. and *|
|* international laws. Users and possessors of this source code are *|
|* hereby granted a nonexclusive, royalty-free copyright license to *|
|* use this code in individual and commercial software. *|
|* *|
|* Any use of this source code must include, in the user documenta- *|
|* tion and internal comments to the code, notices to the end user *|
|* as follows: *|
|* *|
|* Copyright 1993-1999 NVIDIA, Corporation. All rights reserved. *|
|* *|
|* NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY *|
|* OF THIS SOURCE CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" *|
|* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *|
|* ATION DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOURCE CODE, *|
|* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *|
|* MENT, AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL *|
|* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *|
|* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *|
|* SULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION *|
|* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF *|
|* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE. *|
|* *|
|* U.S. Government End Users. This source code is a "commercial *|
|* item," as that term is defined at 48 C.F.R. 2.101 (OCT 1995), *|
|* consisting of "commercial computer software" and "commercial *|
|* computer software documentation," as such terms are used in *|
|* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *|
|* ment only as a commercial end item. Consistent with 48 C.F.R. *|
|* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *|
|* all U.S. Government End Users acquire the source code with only *|
|* those rights set forth herein. *|
|* *|
\***************************************************************************/
/*
* GPL licensing note -- nVidia is allowing a liberal interpretation of
* the documentation restriction above, to merely say that this nVidia's
* copyright and disclaimer should be included with all code derived
* from this source. -- Jeff Garzik <jgarzik@pobox.com>, 01/Nov/99
*/
/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/riva_hw.c,v 1.33 2002/08/05 20:47:06 mvojkovi Exp $ */
#include <linuxcomp.h>
#include <linux/pci.h>
#include <linux/pci_ids.h>
#include "riva_hw.h"
#include "riva_tbl.h"
#include "nv_type.h"
/*
* This file is an OS-agnostic file used to make RIVA 128 and RIVA TNT
* operate identically (except TNT has more memory and better 3D quality.
*/
static int nv3Busy
(
RIVA_HW_INST *chip
)
{
return ((chip->Rop->FifoFree < chip->FifoEmptyCount) || (chip->PGRAPH[0x000006B0/4] & 0x01));
}
static int nv4Busy
(
RIVA_HW_INST *chip
)
{
return ((chip->Rop->FifoFree < chip->FifoEmptyCount) || (chip->PGRAPH[0x00000700/4] & 0x01));
}
static int nv10Busy
(
RIVA_HW_INST *chip
)
{
return ((chip->Rop->FifoFree < chip->FifoEmptyCount) || (chip->PGRAPH[0x00000700/4] & 0x01));
}
static void vgaLockUnlock
(
RIVA_HW_INST *chip,
int Lock
)
{
U008 cr11;
VGA_WR08(chip->PCIO, 0x3D4, 0x11);
cr11 = VGA_RD08(chip->PCIO, 0x3D5);
if(Lock) cr11 |= 0x80;
else cr11 &= ~0x80;
VGA_WR08(chip->PCIO, 0x3D5, cr11);
}
static void nv3LockUnlock
(
RIVA_HW_INST *chip,
int Lock
)
{
VGA_WR08(chip->PVIO, 0x3C4, 0x06);
VGA_WR08(chip->PVIO, 0x3C5, Lock ? 0x99 : 0x57);
vgaLockUnlock(chip, Lock);
}
static void nv4LockUnlock
(
RIVA_HW_INST *chip,
int Lock
)
{
VGA_WR08(chip->PCIO, 0x3D4, 0x1F);
VGA_WR08(chip->PCIO, 0x3D5, Lock ? 0x99 : 0x57);
vgaLockUnlock(chip, Lock);
}
static int ShowHideCursor
(
RIVA_HW_INST *chip,
int ShowHide
)
{
int cursor;
cursor = chip->CurrentState->cursor1;
chip->CurrentState->cursor1 = (chip->CurrentState->cursor1 & 0xFE) |
(ShowHide & 0x01);
VGA_WR08(chip->PCIO, 0x3D4, 0x31);
VGA_WR08(chip->PCIO, 0x3D5, chip->CurrentState->cursor1);
return (cursor & 0x01);
}
/****************************************************************************\
* *
* The video arbitration routines calculate some "magic" numbers. Fixes *
* the snow seen when accessing the framebuffer without it. *
* It just works (I hope). *
* *
\****************************************************************************/
#define DEFAULT_GR_LWM 100
#define DEFAULT_VID_LWM 100
#define DEFAULT_GR_BURST_SIZE 256
#define DEFAULT_VID_BURST_SIZE 128
#define VIDEO 0
#define GRAPHICS 1
#define MPORT 2
#define ENGINE 3
#define GFIFO_SIZE 320
#define GFIFO_SIZE_128 256
#define MFIFO_SIZE 120
#define VFIFO_SIZE 256
#define ABS(a) (a>0?a:-a)
typedef struct {
int gdrain_rate;
int vdrain_rate;
int mdrain_rate;
int gburst_size;
int vburst_size;
char vid_en;
char gr_en;
int wcmocc, wcgocc, wcvocc, wcvlwm, wcglwm;
int by_gfacc;
char vid_only_once;
char gr_only_once;
char first_vacc;
char first_gacc;
char first_macc;
int vocc;
int gocc;
int mocc;
char cur;
char engine_en;
char converged;
int priority;
} nv3_arb_info;
typedef struct {
int graphics_lwm;
int video_lwm;
int graphics_burst_size;
int video_burst_size;
int graphics_hi_priority;
int media_hi_priority;
int rtl_values;
int valid;
} nv3_fifo_info;
typedef struct {
char pix_bpp;
char enable_video;
char gr_during_vid;
char enable_mp;
int memory_width;
int video_scale;
int pclk_khz;
int mclk_khz;
int mem_page_miss;
int mem_latency;
char mem_aligned;
} nv3_sim_state;
typedef struct {
int graphics_lwm;
int video_lwm;
int graphics_burst_size;
int video_burst_size;
int valid;
} nv4_fifo_info;
typedef struct {
int pclk_khz;
int mclk_khz;
int nvclk_khz;
char mem_page_miss;
char mem_latency;
int memory_width;
char enable_video;
char gr_during_vid;
char pix_bpp;
char mem_aligned;
char enable_mp;
} nv4_sim_state;
typedef struct {
int graphics_lwm;
int video_lwm;
int graphics_burst_size;
int video_burst_size;
int valid;
} nv10_fifo_info;
typedef struct {
int pclk_khz;
int mclk_khz;
int nvclk_khz;
char mem_page_miss;
char mem_latency;
int memory_type;
int memory_width;
char enable_video;
char gr_during_vid;
char pix_bpp;
char mem_aligned;
char enable_mp;
} nv10_sim_state;
static int nv3_iterate(nv3_fifo_info *res_info, nv3_sim_state * state, nv3_arb_info *ainfo)
{
int iter = 0;
int tmp;
int vfsize, mfsize, gfsize;
int mburst_size = 32;
int mmisses, gmisses, vmisses;
int misses;
int vlwm, glwm, mlwm;
int last, next, cur;
int max_gfsize ;
long ns;
vlwm = 0;
glwm = 0;
mlwm = 0;
vfsize = 0;
gfsize = 0;
cur = ainfo->cur;
mmisses = 2;
gmisses = 2;
vmisses = 2;
if (ainfo->gburst_size == 128) max_gfsize = GFIFO_SIZE_128;
else max_gfsize = GFIFO_SIZE;
max_gfsize = GFIFO_SIZE;
while (1)
{
if (ainfo->vid_en)
{
if (ainfo->wcvocc > ainfo->vocc) ainfo->wcvocc = ainfo->vocc;
if (ainfo->wcvlwm > vlwm) ainfo->wcvlwm = vlwm ;
ns = 1000000 * ainfo->vburst_size/(state->memory_width/8)/state->mclk_khz;
vfsize = ns * ainfo->vdrain_rate / 1000000;
vfsize = ainfo->wcvlwm - ainfo->vburst_size + vfsize;
}
if (state->enable_mp)
{
if (ainfo->wcmocc > ainfo->mocc) ainfo->wcmocc = ainfo->mocc;
}
if (ainfo->gr_en)
{
if (ainfo->wcglwm > glwm) ainfo->wcglwm = glwm ;
if (ainfo->wcgocc > ainfo->gocc) ainfo->wcgocc = ainfo->gocc;
ns = 1000000 * (ainfo->gburst_size/(state->memory_width/8))/state->mclk_khz;
gfsize = (ns * (long) ainfo->gdrain_rate)/1000000;
gfsize = ainfo->wcglwm - ainfo->gburst_size + gfsize;
}
mfsize = 0;
if (!state->gr_during_vid && ainfo->vid_en)
if (ainfo->vid_en && (ainfo->vocc < 0) && !ainfo->vid_only_once)
next = VIDEO;
else if (ainfo->mocc < 0)
next = MPORT;
else if (ainfo->gocc< ainfo->by_gfacc)
next = GRAPHICS;
else return (0);
else switch (ainfo->priority)
{
case VIDEO:
if (ainfo->vid_en && ainfo->vocc<0 && !ainfo->vid_only_once)
next = VIDEO;
else if (ainfo->gr_en && ainfo->gocc<0 && !ainfo->gr_only_once)
next = GRAPHICS;
else if (ainfo->mocc<0)
next = MPORT;
else return (0);
break;
case GRAPHICS:
if (ainfo->gr_en && ainfo->gocc<0 && !ainfo->gr_only_once)
next = GRAPHICS;
else if (ainfo->vid_en && ainfo->vocc<0 && !ainfo->vid_only_once)
next = VIDEO;
else if (ainfo->mocc<0)
next = MPORT;
else return (0);
break;
default:
if (ainfo->mocc<0)
next = MPORT;
else if (ainfo->gr_en && ainfo->gocc<0 && !ainfo->gr_only_once)
next = GRAPHICS;
else if (ainfo->vid_en && ainfo->vocc<0 && !ainfo->vid_only_once)
next = VIDEO;
else return (0);
break;
}
last = cur;
cur = next;
iter++;
switch (cur)
{
case VIDEO:
if (last==cur) misses = 0;
else if (ainfo->first_vacc) misses = vmisses;
else misses = 1;
ainfo->first_vacc = 0;
if (last!=cur)
{
ns = 1000000 * (vmisses*state->mem_page_miss + state->mem_latency)/state->mclk_khz;
vlwm = ns * ainfo->vdrain_rate/ 1000000;
vlwm = ainfo->vocc - vlwm;
}
ns = 1000000*(misses*state->mem_page_miss + ainfo->vburst_size)/(state->memory_width/8)/state->mclk_khz;
ainfo->vocc = ainfo->vocc + ainfo->vburst_size - ns*ainfo->vdrain_rate/1000000;
ainfo->gocc = ainfo->gocc - ns*ainfo->gdrain_rate/1000000;
ainfo->mocc = ainfo->mocc - ns*ainfo->mdrain_rate/1000000;
break;
case GRAPHICS:
if (last==cur) misses = 0;
else if (ainfo->first_gacc) misses = gmisses;
else misses = 1;
ainfo->first_gacc = 0;
if (last!=cur)
{
ns = 1000000*(gmisses*state->mem_page_miss + state->mem_latency)/state->mclk_khz ;
glwm = ns * ainfo->gdrain_rate/1000000;
glwm = ainfo->gocc - glwm;
}
ns = 1000000*(misses*state->mem_page_miss + ainfo->gburst_size/(state->memory_width/8))/state->mclk_khz;
ainfo->vocc = ainfo->vocc + 0 - ns*ainfo->vdrain_rate/1000000;
ainfo->gocc = ainfo->gocc + ainfo->gburst_size - ns*ainfo->gdrain_rate/1000000;
ainfo->mocc = ainfo->mocc + 0 - ns*ainfo->mdrain_rate/1000000;
break;
default:
if (last==cur) misses = 0;
else if (ainfo->first_macc) misses = mmisses;
else misses = 1;
ainfo->first_macc = 0;
ns = 1000000*(misses*state->mem_page_miss + mburst_size/(state->memory_width/8))/state->mclk_khz;
ainfo->vocc = ainfo->vocc + 0 - ns*ainfo->vdrain_rate/1000000;
ainfo->gocc = ainfo->gocc + 0 - ns*ainfo->gdrain_rate/1000000;
ainfo->mocc = ainfo->mocc + mburst_size - ns*ainfo->mdrain_rate/1000000;
break;
}
if (iter>100)
{
ainfo->converged = 0;
return (1);
}
ns = 1000000*ainfo->gburst_size/(state->memory_width/8)/state->mclk_khz;
tmp = ns * ainfo->gdrain_rate/1000000;
if (ABS(ainfo->gburst_size) + ((ABS(ainfo->wcglwm) + 16 ) & ~0x7) - tmp > max_gfsize)
{
ainfo->converged = 0;
return (1);
}
ns = 1000000*ainfo->vburst_size/(state->memory_width/8)/state->mclk_khz;
tmp = ns * ainfo->vdrain_rate/1000000;
if (ABS(ainfo->vburst_size) + (ABS(ainfo->wcvlwm + 32) & ~0xf) - tmp> VFIFO_SIZE)
{
ainfo->converged = 0;
return (1);
}
if (ABS(ainfo->gocc) > max_gfsize)
{
ainfo->converged = 0;
return (1);
}
if (ABS(ainfo->vocc) > VFIFO_SIZE)
{
ainfo->converged = 0;
return (1);
}
if (ABS(ainfo->mocc) > MFIFO_SIZE)
{
ainfo->converged = 0;
return (1);
}
if (ABS(vfsize) > VFIFO_SIZE)
{
ainfo->converged = 0;
return (1);
}
if (ABS(gfsize) > max_gfsize)
{
ainfo->converged = 0;
return (1);
}
if (ABS(mfsize) > MFIFO_SIZE)
{
ainfo->converged = 0;
return (1);
}
}
}
static char nv3_arb(nv3_fifo_info * res_info, nv3_sim_state * state, nv3_arb_info *ainfo)
{
long ens, vns, mns, gns;
int mmisses, gmisses, vmisses, eburst_size, mburst_size;
int refresh_cycle;
refresh_cycle = 0;
refresh_cycle = 2*(state->mclk_khz/state->pclk_khz) + 5;
mmisses = 2;
if (state->mem_aligned) gmisses = 2;
else gmisses = 3;
vmisses = 2;
eburst_size = state->memory_width * 1;
mburst_size = 32;
gns = 1000000 * (gmisses*state->mem_page_miss + state->mem_latency)/state->mclk_khz;
ainfo->by_gfacc = gns*ainfo->gdrain_rate/1000000;
ainfo->wcmocc = 0;
ainfo->wcgocc = 0;
ainfo->wcvocc = 0;
ainfo->wcvlwm = 0;
ainfo->wcglwm = 0;
ainfo->engine_en = 1;
ainfo->converged = 1;
if (ainfo->engine_en)
{
ens = 1000000*(state->mem_page_miss + eburst_size/(state->memory_width/8) +refresh_cycle)/state->mclk_khz;
ainfo->mocc = state->enable_mp ? 0-ens*ainfo->mdrain_rate/1000000 : 0;
ainfo->vocc = ainfo->vid_en ? 0-ens*ainfo->vdrain_rate/1000000 : 0;
ainfo->gocc = ainfo->gr_en ? 0-ens*ainfo->gdrain_rate/1000000 : 0;
ainfo->cur = ENGINE;
ainfo->first_vacc = 1;
ainfo->first_gacc = 1;
ainfo->first_macc = 1;
nv3_iterate(res_info, state,ainfo);
}
if (state->enable_mp)
{
mns = 1000000 * (mmisses*state->mem_page_miss + mburst_size/(state->memory_width/8) + refresh_cycle)/state->mclk_khz;
ainfo->mocc = state->enable_mp ? 0 : mburst_size - mns*ainfo->mdrain_rate/1000000;
ainfo->vocc = ainfo->vid_en ? 0 : 0- mns*ainfo->vdrain_rate/1000000;
ainfo->gocc = ainfo->gr_en ? 0: 0- mns*ainfo->gdrain_rate/1000000;
ainfo->cur = MPORT;
ainfo->first_vacc = 1;
ainfo->first_gacc = 1;
ainfo->first_macc = 0;
nv3_iterate(res_info, state,ainfo);
}
if (ainfo->gr_en)
{
ainfo->first_vacc = 1;
ainfo->first_gacc = 0;
ainfo->first_macc = 1;
gns = 1000000*(gmisses*state->mem_page_miss + ainfo->gburst_size/(state->memory_width/8) + refresh_cycle)/state->mclk_khz;
ainfo->gocc = ainfo->gburst_size - gns*ainfo->gdrain_rate/1000000;
ainfo->vocc = ainfo->vid_en? 0-gns*ainfo->vdrain_rate/1000000 : 0;
ainfo->mocc = state->enable_mp ? 0-gns*ainfo->mdrain_rate/1000000: 0;
ainfo->cur = GRAPHICS;
nv3_iterate(res_info, state,ainfo);
}
if (ainfo->vid_en)
{
ainfo->first_vacc = 0;
ainfo->first_gacc = 1;
ainfo->first_macc = 1;
vns = 1000000*(vmisses*state->mem_page_miss + ainfo->vburst_size/(state->memory_width/8) + refresh_cycle)/state->mclk_khz;
ainfo->vocc = ainfo->vburst_size - vns*ainfo->vdrain_rate/1000000;
ainfo->gocc = ainfo->gr_en? (0-vns*ainfo->gdrain_rate/1000000) : 0;
ainfo->mocc = state->enable_mp? 0-vns*ainfo->mdrain_rate/1000000 :0 ;
ainfo->cur = VIDEO;
nv3_iterate(res_info, state, ainfo);
}
if (ainfo->converged)
{
res_info->graphics_lwm = (int)ABS(ainfo->wcglwm) + 16;
res_info->video_lwm = (int)ABS(ainfo->wcvlwm) + 32;
res_info->graphics_burst_size = ainfo->gburst_size;
res_info->video_burst_size = ainfo->vburst_size;
res_info->graphics_hi_priority = (ainfo->priority == GRAPHICS);
res_info->media_hi_priority = (ainfo->priority == MPORT);
if (res_info->video_lwm > 160)
{
res_info->graphics_lwm = 256;
res_info->video_lwm = 128;
res_info->graphics_burst_size = 64;
res_info->video_burst_size = 64;
res_info->graphics_hi_priority = 0;
res_info->media_hi_priority = 0;
ainfo->converged = 0;
return (0);
}
if (res_info->video_lwm > 128)
{
res_info->video_lwm = 128;
}
return (1);
}
else
{
res_info->graphics_lwm = 256;
res_info->video_lwm = 128;
res_info->graphics_burst_size = 64;
res_info->video_burst_size = 64;
res_info->graphics_hi_priority = 0;
res_info->media_hi_priority = 0;
return (0);
}
}
static char nv3_get_param(nv3_fifo_info *res_info, nv3_sim_state * state, nv3_arb_info *ainfo)
{
int done, g,v, p;
done = 0;
for (p=0; p < 2; p++)
{
for (g=128 ; g > 32; g= g>> 1)
{
for (v=128; v >=32; v = v>> 1)
{
ainfo->priority = p;
ainfo->gburst_size = g;
ainfo->vburst_size = v;
done = nv3_arb(res_info, state,ainfo);
if (done && (g==128))
if ((res_info->graphics_lwm + g) > 256)
done = 0;
if (done)
goto Done;
}
}
}
Done:
return done;
}
static void nv3CalcArbitration
(
nv3_fifo_info * res_info,
nv3_sim_state * state
)
{
nv3_fifo_info save_info;
nv3_arb_info ainfo;
char res_gr, res_vid;
ainfo.gr_en = 1;
ainfo.vid_en = state->enable_video;
ainfo.vid_only_once = 0;
ainfo.gr_only_once = 0;
ainfo.gdrain_rate = (int) state->pclk_khz * (state->pix_bpp/8);
ainfo.vdrain_rate = (int) state->pclk_khz * 2;
if (state->video_scale != 0)
ainfo.vdrain_rate = ainfo.vdrain_rate/state->video_scale;
ainfo.mdrain_rate = 33000;
res_info->rtl_values = 0;
if (!state->gr_during_vid && state->enable_video)
{
ainfo.gr_only_once = 1;
ainfo.gr_en = 1;
ainfo.gdrain_rate = 0;
res_vid = nv3_get_param(res_info, state, &ainfo);
res_vid = ainfo.converged;
save_info.video_lwm = res_info->video_lwm;
save_info.video_burst_size = res_info->video_burst_size;
ainfo.vid_en = 1;
ainfo.vid_only_once = 1;
ainfo.gr_en = 1;
ainfo.gdrain_rate = (int) state->pclk_khz * (state->pix_bpp/8);
ainfo.vdrain_rate = 0;
res_gr = nv3_get_param(res_info, state, &ainfo);
res_gr = ainfo.converged;
res_info->video_lwm = save_info.video_lwm;
res_info->video_burst_size = save_info.video_burst_size;
res_info->valid = res_gr & res_vid;
}
else
{
if (!ainfo.gr_en) ainfo.gdrain_rate = 0;
if (!ainfo.vid_en) ainfo.vdrain_rate = 0;
res_gr = nv3_get_param(res_info, state, &ainfo);
res_info->valid = ainfo.converged;
}
}
static void nv3UpdateArbitrationSettings
(
unsigned VClk,
unsigned pixelDepth,
unsigned *burst,
unsigned *lwm,
RIVA_HW_INST *chip
)
{
nv3_fifo_info fifo_data;
nv3_sim_state sim_data;
unsigned int M, N, P, pll, MClk;
pll = chip->PRAMDAC0[0x00000504/4];
M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F;
MClk = (N * chip->CrystalFreqKHz / M) >> P;
sim_data.pix_bpp = (char)pixelDepth;
sim_data.enable_video = 0;
sim_data.enable_mp = 0;
sim_data.video_scale = 1;
sim_data.memory_width = (chip->PEXTDEV[0x00000000/4] & 0x10) ? 128 : 64;
sim_data.memory_width = 128;
sim_data.mem_latency = 9;
sim_data.mem_aligned = 1;
sim_data.mem_page_miss = 11;
sim_data.gr_during_vid = 0;
sim_data.pclk_khz = VClk;
sim_data.mclk_khz = MClk;
nv3CalcArbitration(&fifo_data, &sim_data);
if (fifo_data.valid)
{
int b = fifo_data.graphics_burst_size >> 4;
*burst = 0;
while (b >>= 1) (*burst)++;
*lwm = fifo_data.graphics_lwm >> 3;
}
else
{
*lwm = 0x24;
*burst = 0x2;
}
}
static void nv4CalcArbitration
(
nv4_fifo_info *fifo,
nv4_sim_state *arb
)
{
int data, pagemiss, cas,width, video_enable, color_key_enable, bpp, align;
int nvclks, mclks, pclks, vpagemiss, crtpagemiss, vbs;
int found, mclk_extra, mclk_loop, cbs, m1, p1;
int mclk_freq, pclk_freq, nvclk_freq, mp_enable;
int us_m, us_n, us_p, video_drain_rate, crtc_drain_rate;
int vpm_us, us_video, vlwm, video_fill_us, cpm_us, us_crt,clwm;
int craw, vraw;
fifo->valid = 1;
pclk_freq = arb->pclk_khz;
mclk_freq = arb->mclk_khz;
nvclk_freq = arb->nvclk_khz;
pagemiss = arb->mem_page_miss;
cas = arb->mem_latency;
width = arb->memory_width >> 6;
video_enable = arb->enable_video;
color_key_enable = arb->gr_during_vid;
bpp = arb->pix_bpp;
align = arb->mem_aligned;
mp_enable = arb->enable_mp;
clwm = 0;
vlwm = 0;
cbs = 128;
pclks = 2;
nvclks = 2;
nvclks += 2;
nvclks += 1;
mclks = 5;
mclks += 3;
mclks += 1;
mclks += cas;
mclks += 1;
mclks += 1;
mclks += 1;
mclks += 1;
mclk_extra = 3;
nvclks += 2;
nvclks += 1;
nvclks += 1;
nvclks += 1;
if (mp_enable)
mclks+=4;
nvclks += 0;
pclks += 0;
found = 0;
vbs = 0;
while (found != 1)
{
fifo->valid = 1;
found = 1;
mclk_loop = mclks+mclk_extra;
us_m = mclk_loop *1000*1000 / mclk_freq;
us_n = nvclks*1000*1000 / nvclk_freq;
us_p = nvclks*1000*1000 / pclk_freq;
if (video_enable)
{
video_drain_rate = pclk_freq * 2;
crtc_drain_rate = pclk_freq * bpp/8;
vpagemiss = 2;
vpagemiss += 1;
crtpagemiss = 2;
vpm_us = (vpagemiss * pagemiss)*1000*1000/mclk_freq;
if (nvclk_freq * 2 > mclk_freq * width)
video_fill_us = cbs*1000*1000 / 16 / nvclk_freq ;
else
video_fill_us = cbs*1000*1000 / (8 * width) / mclk_freq;
us_video = vpm_us + us_m + us_n + us_p + video_fill_us;
vlwm = us_video * video_drain_rate/(1000*1000);
vlwm++;
vbs = 128;
if (vlwm > 128) vbs = 64;
if (vlwm > (256-64)) vbs = 32;
if (nvclk_freq * 2 > mclk_freq * width)
video_fill_us = vbs *1000*1000/ 16 / nvclk_freq ;
else
video_fill_us = vbs*1000*1000 / (8 * width) / mclk_freq;
cpm_us = crtpagemiss * pagemiss *1000*1000/ mclk_freq;
us_crt =
us_video
+video_fill_us
+cpm_us
+us_m + us_n +us_p
;
clwm = us_crt * crtc_drain_rate/(1000*1000);
clwm++;
}
else
{
crtc_drain_rate = pclk_freq * bpp/8;
crtpagemiss = 2;
crtpagemiss += 1;
cpm_us = crtpagemiss * pagemiss *1000*1000/ mclk_freq;
us_crt = cpm_us + us_m + us_n + us_p ;
clwm = us_crt * crtc_drain_rate/(1000*1000);
clwm++;
}
m1 = clwm + cbs - 512;
p1 = m1 * pclk_freq / mclk_freq;
p1 = p1 * bpp / 8;
if ((p1 < m1) && (m1 > 0))
{
fifo->valid = 0;
found = 0;
if (mclk_extra ==0) found = 1;
mclk_extra--;
}
else if (video_enable)
{
if ((clwm > 511) || (vlwm > 255))
{
fifo->valid = 0;
found = 0;
if (mclk_extra ==0) found = 1;
mclk_extra--;
}
}
else
{
if (clwm > 519)
{
fifo->valid = 0;
found = 0;
if (mclk_extra ==0) found = 1;
mclk_extra--;
}
}
craw = clwm;
vraw = vlwm;
if (clwm < 384) clwm = 384;
if (vlwm < 128) vlwm = 128;
data = (int)(clwm);
fifo->graphics_lwm = data;
fifo->graphics_burst_size = 128;
data = (int)((vlwm+15));
fifo->video_lwm = data;
fifo->video_burst_size = vbs;
}
}
static void nv4UpdateArbitrationSettings
(
unsigned VClk,
unsigned pixelDepth,
unsigned *burst,
unsigned *lwm,
RIVA_HW_INST *chip
)
{
nv4_fifo_info fifo_data;
nv4_sim_state sim_data;
unsigned int M, N, P, pll, MClk, NVClk, cfg1;
pll = chip->PRAMDAC0[0x00000504/4];
M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F;
MClk = (N * chip->CrystalFreqKHz / M) >> P;
pll = chip->PRAMDAC0[0x00000500/4];
M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F;
NVClk = (N * chip->CrystalFreqKHz / M) >> P;
cfg1 = chip->PFB[0x00000204/4];
sim_data.pix_bpp = (char)pixelDepth;
sim_data.enable_video = 0;
sim_data.enable_mp = 0;
sim_data.memory_width = (chip->PEXTDEV[0x00000000/4] & 0x10) ? 128 : 64;
sim_data.mem_latency = (char)cfg1 & 0x0F;
sim_data.mem_aligned = 1;
sim_data.mem_page_miss = (char)(((cfg1 >> 4) &0x0F) + ((cfg1 >> 31) & 0x01));
sim_data.gr_during_vid = 0;
sim_data.pclk_khz = VClk;
sim_data.mclk_khz = MClk;
sim_data.nvclk_khz = NVClk;
nv4CalcArbitration(&fifo_data, &sim_data);
if (fifo_data.valid)
{
int b = fifo_data.graphics_burst_size >> 4;
*burst = 0;
while (b >>= 1) (*burst)++;
*lwm = fifo_data.graphics_lwm >> 3;
}
}
static void nv10CalcArbitration
(
nv10_fifo_info *fifo,
nv10_sim_state *arb
)
{
int data, pagemiss, cas,width, video_enable, color_key_enable, bpp, align;
int nvclks, mclks, pclks, vpagemiss, crtpagemiss, vbs;
int nvclk_fill, us_extra;
int found, mclk_extra, mclk_loop, cbs, m1;
int mclk_freq, pclk_freq, nvclk_freq, mp_enable;
int us_m, us_m_min, us_n, us_p, video_drain_rate, crtc_drain_rate;
int vus_m, vus_n, vus_p;
int vpm_us, us_video, vlwm, cpm_us, us_crt,clwm;
int clwm_rnd_down;
int craw, m2us, us_pipe, us_pipe_min, vus_pipe, p1clk, p2;
int pclks_2_top_fifo, min_mclk_extra;
int us_min_mclk_extra;
fifo->valid = 1;
pclk_freq = arb->pclk_khz; /* freq in KHz */
mclk_freq = arb->mclk_khz;
nvclk_freq = arb->nvclk_khz;
pagemiss = arb->mem_page_miss;
cas = arb->mem_latency;
width = arb->memory_width/64;
video_enable = arb->enable_video;
color_key_enable = arb->gr_during_vid;
bpp = arb->pix_bpp;
align = arb->mem_aligned;
mp_enable = arb->enable_mp;
clwm = 0;
vlwm = 1024;
cbs = 512;
vbs = 512;
pclks = 4; /* lwm detect. */
nvclks = 3; /* lwm -> sync. */
nvclks += 2; /* fbi bus cycles (1 req + 1 busy) */
mclks = 1; /* 2 edge sync. may be very close to edge so just put one. */
mclks += 1; /* arb_hp_req */
mclks += 5; /* ap_hp_req tiling pipeline */
mclks += 2; /* tc_req latency fifo */
mclks += 2; /* fb_cas_n_ memory request to fbio block */
mclks += 7; /* sm_d_rdv data returned from fbio block */
/* fb.rd.d.Put_gc need to accumulate 256 bits for read */
if (arb->memory_type == 0)
if (arb->memory_width == 64) /* 64 bit bus */
mclks += 4;
else
mclks += 2;
else
if (arb->memory_width == 64) /* 64 bit bus */
mclks += 2;
else
mclks += 1;
if ((!video_enable) && (arb->memory_width == 128))
{
mclk_extra = (bpp == 32) ? 31 : 42; /* Margin of error */
min_mclk_extra = 17;
}
else
{
mclk_extra = (bpp == 32) ? 8 : 4; /* Margin of error */
/* mclk_extra = 4; */ /* Margin of error */
min_mclk_extra = 18;
}
nvclks += 1; /* 2 edge sync. may be very close to edge so just put one. */
nvclks += 1; /* fbi_d_rdv_n */
nvclks += 1; /* Fbi_d_rdata */
nvclks += 1; /* crtfifo load */
if(mp_enable)
mclks+=4; /* Mp can get in with a burst of 8. */
/* Extra clocks determined by heuristics */
nvclks += 0;
pclks += 0;
found = 0;
while(found != 1) {
fifo->valid = 1;
found = 1;
mclk_loop = mclks+mclk_extra;
us_m = mclk_loop *1000*1000 / mclk_freq; /* Mclk latency in us */
us_m_min = mclks * 1000*1000 / mclk_freq; /* Minimum Mclk latency in us */
us_min_mclk_extra = min_mclk_extra *1000*1000 / mclk_freq;
us_n = nvclks*1000*1000 / nvclk_freq;/* nvclk latency in us */
us_p = pclks*1000*1000 / pclk_freq;/* nvclk latency in us */
us_pipe = us_m + us_n + us_p;
us_pipe_min = us_m_min + us_n + us_p;
us_extra = 0;
vus_m = mclk_loop *1000*1000 / mclk_freq; /* Mclk latency in us */
vus_n = (4)*1000*1000 / nvclk_freq;/* nvclk latency in us */
vus_p = 0*1000*1000 / pclk_freq;/* pclk latency in us */
vus_pipe = vus_m + vus_n + vus_p;
if(video_enable) {
video_drain_rate = pclk_freq * 4; /* MB/s */
crtc_drain_rate = pclk_freq * bpp/8; /* MB/s */
vpagemiss = 1; /* self generating page miss */
vpagemiss += 1; /* One higher priority before */
crtpagemiss = 2; /* self generating page miss */
if(mp_enable)
crtpagemiss += 1; /* if MA0 conflict */
vpm_us = (vpagemiss * pagemiss)*1000*1000/mclk_freq;
us_video = vpm_us + vus_m; /* Video has separate read return path */
cpm_us = crtpagemiss * pagemiss *1000*1000/ mclk_freq;
us_crt =
us_video /* Wait for video */
+cpm_us /* CRT Page miss */
+us_m + us_n +us_p /* other latency */
;
clwm = us_crt * crtc_drain_rate/(1000*1000);
clwm++; /* fixed point <= float_point - 1. Fixes that */
} else {
crtc_drain_rate = pclk_freq * bpp/8; /* bpp * pclk/8 */
crtpagemiss = 1; /* self generating page miss */
crtpagemiss += 1; /* MA0 page miss */
if(mp_enable)
crtpagemiss += 1; /* if MA0 conflict */
cpm_us = crtpagemiss * pagemiss *1000*1000/ mclk_freq;
us_crt = cpm_us + us_m + us_n + us_p ;
clwm = us_crt * crtc_drain_rate/(1000*1000);
clwm++; /* fixed point <= float_point - 1. Fixes that */
/*
//
// Another concern, only for high pclks so don't do this
// with video:
// What happens if the latency to fetch the cbs is so large that
// fifo empties. In that case we need to have an alternate clwm value
// based off the total burst fetch
//
us_crt = (cbs * 1000 * 1000)/ (8*width)/mclk_freq ;
us_crt = us_crt + us_m + us_n + us_p + (4 * 1000 * 1000)/mclk_freq;
clwm_mt = us_crt * crtc_drain_rate/(1000*1000);
clwm_mt ++;
if(clwm_mt > clwm)
clwm = clwm_mt;
*/
/* Finally, a heuristic check when width == 64 bits */
if(width == 1){
nvclk_fill = nvclk_freq * 8;
if(crtc_drain_rate * 100 >= nvclk_fill * 102)
clwm = 0xfff; /*Large number to fail */
else if(crtc_drain_rate * 100 >= nvclk_fill * 98) {
clwm = 1024;
cbs = 512;
us_extra = (cbs * 1000 * 1000)/ (8*width)/mclk_freq ;
}
}
}
/*
Overfill check:
*/
clwm_rnd_down = ((int)clwm/8)*8;
if (clwm_rnd_down < clwm)
clwm += 8;
m1 = clwm + cbs - 1024; /* Amount of overfill */
m2us = us_pipe_min + us_min_mclk_extra;
pclks_2_top_fifo = (1024-clwm)/(8*width);
/* pclk cycles to drain */
p1clk = m2us * pclk_freq/(1000*1000);
p2 = p1clk * bpp / 8; /* bytes drained. */
if((p2 < m1) && (m1 > 0)) {
fifo->valid = 0;
found = 0;
if(min_mclk_extra == 0) {
if(cbs <= 32) {
found = 1; /* Can't adjust anymore! */
} else {
cbs = cbs/2; /* reduce the burst size */
}
} else {
min_mclk_extra--;
}
} else {
if (clwm > 1023){ /* Have some margin */
fifo->valid = 0;
found = 0;
if(min_mclk_extra == 0)
found = 1; /* Can't adjust anymore! */
else
min_mclk_extra--;
}
}
craw = clwm;
if(clwm < (1024-cbs+8)) clwm = 1024-cbs+8;
data = (int)(clwm);
/* printf("CRT LWM: %f bytes, prog: 0x%x, bs: 256\n", clwm, data ); */
fifo->graphics_lwm = data; fifo->graphics_burst_size = cbs;
/* printf("VID LWM: %f bytes, prog: 0x%x, bs: %d\n, ", vlwm, data, vbs ); */
fifo->video_lwm = 1024; fifo->video_burst_size = 512;
}
}
static void nv10UpdateArbitrationSettings
(
unsigned VClk,
unsigned pixelDepth,
unsigned *burst,
unsigned *lwm,
RIVA_HW_INST *chip
)
{
nv10_fifo_info fifo_data;
nv10_sim_state sim_data;
unsigned int M, N, P, pll, MClk, NVClk, cfg1;
pll = chip->PRAMDAC0[0x00000504/4];
M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F;
MClk = (N * chip->CrystalFreqKHz / M) >> P;
pll = chip->PRAMDAC0[0x00000500/4];
M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F;
NVClk = (N * chip->CrystalFreqKHz / M) >> P;
cfg1 = chip->PFB[0x00000204/4];
sim_data.pix_bpp = (char)pixelDepth;
sim_data.enable_video = 0;
sim_data.enable_mp = 0;
sim_data.memory_type = (chip->PFB[0x00000200/4] & 0x01) ? 1 : 0;
sim_data.memory_width = (chip->PEXTDEV[0x00000000/4] & 0x10) ? 128 : 64;
sim_data.mem_latency = (char)cfg1 & 0x0F;
sim_data.mem_aligned = 1;
sim_data.mem_page_miss = (char)(((cfg1 >> 4) &0x0F) + ((cfg1 >> 31) & 0x01));
sim_data.gr_during_vid = 0;
sim_data.pclk_khz = VClk;
sim_data.mclk_khz = MClk;
sim_data.nvclk_khz = NVClk;
nv10CalcArbitration(&fifo_data, &sim_data);
if (fifo_data.valid)
{
int b = fifo_data.graphics_burst_size >> 4;
*burst = 0;
while (b >>= 1) (*burst)++;
*lwm = fifo_data.graphics_lwm >> 3;
}
}
static void nForceUpdateArbitrationSettings
(
unsigned VClk,
unsigned pixelDepth,
unsigned *burst,
unsigned *lwm,
RIVA_HW_INST *chip
)
{
nv10_fifo_info fifo_data;
nv10_sim_state sim_data;
unsigned int M, N, P, pll, MClk, NVClk;
unsigned int uMClkPostDiv;
struct pci_dev *dev;
dev = pci_find_slot(0, 3);
pci_read_config_dword(dev, 0x6C, &uMClkPostDiv);
uMClkPostDiv = (uMClkPostDiv >> 8) & 0xf;
if(!uMClkPostDiv) uMClkPostDiv = 4;
MClk = 400000 / uMClkPostDiv;
pll = chip->PRAMDAC0[0x00000500/4];
M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F;
NVClk = (N * chip->CrystalFreqKHz / M) >> P;
sim_data.pix_bpp = (char)pixelDepth;
sim_data.enable_video = 0;
sim_data.enable_mp = 0;
dev = pci_find_slot(0, 1);
pci_read_config_dword(dev, 0x7C, &sim_data.memory_type);
sim_data.memory_type = (sim_data.memory_type >> 12) & 1;
sim_data.memory_width = 64;
sim_data.mem_latency = 3;
sim_data.mem_aligned = 1;
sim_data.mem_page_miss = 10;
sim_data.gr_during_vid = 0;
sim_data.pclk_khz = VClk;
sim_data.mclk_khz = MClk;
sim_data.nvclk_khz = NVClk;
nv10CalcArbitration(&fifo_data, &sim_data);
if (fifo_data.valid)
{
int b = fifo_data.graphics_burst_size >> 4;
*burst = 0;
while (b >>= 1) (*burst)++;
*lwm = fifo_data.graphics_lwm >> 3;
}
}
/****************************************************************************\
* *
* RIVA Mode State Routines *
* *
\****************************************************************************/
/*
* Calculate the Video Clock parameters for the PLL.
*/
static int CalcVClock
(
int clockIn,
int *clockOut,
int *mOut,
int *nOut,
int *pOut,
RIVA_HW_INST *chip
)
{
unsigned lowM, highM, highP;
unsigned DeltaNew, DeltaOld;
unsigned VClk, Freq;
unsigned M, N, P;
DeltaOld = 0xFFFFFFFF;
VClk = (unsigned)clockIn;
if (chip->CrystalFreqKHz == 13500)
{
lowM = 7;
highM = 13 - (chip->Architecture == NV_ARCH_03);
}
else
{
lowM = 8;
highM = 14 - (chip->Architecture == NV_ARCH_03);
}
highP = 4 - (chip->Architecture == NV_ARCH_03);
for (P = 0; P <= highP; P ++)
{
Freq = VClk << P;
if ((Freq >= 128000) && (Freq <= chip->MaxVClockFreqKHz))
{
for (M = lowM; M <= highM; M++)
{
N = (VClk << P) * M / chip->CrystalFreqKHz;
if(N <= 255) {
Freq = (chip->CrystalFreqKHz * N / M) >> P;
if (Freq > VClk)
DeltaNew = Freq - VClk;
else
DeltaNew = VClk - Freq;
if (DeltaNew < DeltaOld)
{
*mOut = M;
*nOut = N;
*pOut = P;
*clockOut = Freq;
DeltaOld = DeltaNew;
}
}
}
}
}
return (DeltaOld != 0xFFFFFFFF);
}
/*
* Calculate extended mode parameters (SVGA) and save in a
* mode state structure.
*/
static void CalcStateExt
(
RIVA_HW_INST *chip,
RIVA_HW_STATE *state,
int bpp,
int width,
int hDisplaySize,
int height,
int dotClock
)
{
int pixelDepth, VClk, m, n, p;
/*
* Save mode parameters.
*/
state->bpp = bpp; /* this is not bitsPerPixel, it's 8,15,16,32 */
state->width = width;
state->height = height;
/*
* Extended RIVA registers.
*/
pixelDepth = (bpp + 1)/8;
CalcVClock(dotClock, &VClk, &m, &n, &p, chip);
switch (chip->Architecture)
{
case NV_ARCH_03:
nv3UpdateArbitrationSettings(VClk,
pixelDepth * 8,
&(state->arbitration0),
&(state->arbitration1),
chip);
state->cursor0 = 0x00;
state->cursor1 = 0x78;
state->cursor2 = 0x00000000;
state->pllsel = 0x10010100;
state->config = ((width + 31)/32)
| (((pixelDepth > 2) ? 3 : pixelDepth) << 8)
| 0x1000;
state->general = 0x00100100;
state->repaint1 = hDisplaySize < 1280 ? 0x06 : 0x02;
break;
case NV_ARCH_04:
nv4UpdateArbitrationSettings(VClk,
pixelDepth * 8,
&(state->arbitration0),
&(state->arbitration1),
chip);
state->cursor0 = 0x00;
state->cursor1 = 0xFC;
state->cursor2 = 0x00000000;
state->pllsel = 0x10000700;
state->config = 0x00001114;
state->general = bpp == 16 ? 0x00101100 : 0x00100100;
state->repaint1 = hDisplaySize < 1280 ? 0x04 : 0x00;
break;
case NV_ARCH_10:
case NV_ARCH_20:
if((chip->Chipset == NV_CHIP_IGEFORCE2) ||
(chip->Chipset == NV_CHIP_0x01F0))
{
nForceUpdateArbitrationSettings(VClk,
pixelDepth * 8,
&(state->arbitration0),
&(state->arbitration1),
chip);
} else {
nv10UpdateArbitrationSettings(VClk,
pixelDepth * 8,
&(state->arbitration0),
&(state->arbitration1),
chip);
}
state->cursor0 = 0x80 | (chip->CursorStart >> 17);
state->cursor1 = (chip->CursorStart >> 11) << 2;
state->cursor2 = chip->CursorStart >> 24;
state->pllsel = 0x10000700;
state->config = chip->PFB[0x00000200/4];
state->general = bpp == 16 ? 0x00101100 : 0x00100100;
state->repaint1 = hDisplaySize < 1280 ? 0x04 : 0x00;
break;
}
/* Paul Richards: below if block borks things in kernel for some reason */
/* if((bpp != 8) && (chip->Architecture != NV_ARCH_03))
state->general |= 0x00000030; */
state->vpll = (p << 16) | (n << 8) | m;
state->repaint0 = (((width/8)*pixelDepth) & 0x700) >> 3;
state->pixel = pixelDepth > 2 ? 3 : pixelDepth;
state->offset0 =
state->offset1 =
state->offset2 =
state->offset3 = 0;
state->pitch0 =
state->pitch1 =
state->pitch2 =
state->pitch3 = pixelDepth * width;
}
/*
* Load fixed function state and pre-calculated/stored state.
*/
#define LOAD_FIXED_STATE(tbl,dev) \
for (i = 0; i < sizeof(tbl##Table##dev)/8; i++) \
chip->dev[tbl##Table##dev[i][0]] = tbl##Table##dev[i][1]
#define LOAD_FIXED_STATE_8BPP(tbl,dev) \
for (i = 0; i < sizeof(tbl##Table##dev##_8BPP)/8; i++) \
chip->dev[tbl##Table##dev##_8BPP[i][0]] = tbl##Table##dev##_8BPP[i][1]
#define LOAD_FIXED_STATE_15BPP(tbl,dev) \
for (i = 0; i < sizeof(tbl##Table##dev##_15BPP)/8; i++) \
chip->dev[tbl##Table##dev##_15BPP[i][0]] = tbl##Table##dev##_15BPP[i][1]
#define LOAD_FIXED_STATE_16BPP(tbl,dev) \
for (i = 0; i < sizeof(tbl##Table##dev##_16BPP)/8; i++) \
chip->dev[tbl##Table##dev##_16BPP[i][0]] = tbl##Table##dev##_16BPP[i][1]
#define LOAD_FIXED_STATE_32BPP(tbl,dev) \
for (i = 0; i < sizeof(tbl##Table##dev##_32BPP)/8; i++) \
chip->dev[tbl##Table##dev##_32BPP[i][0]] = tbl##Table##dev##_32BPP[i][1]
static void UpdateFifoState
(
RIVA_HW_INST *chip
)
{
int i;
switch (chip->Architecture)
{
case NV_ARCH_04:
LOAD_FIXED_STATE(nv4,FIFO);
chip->Tri03 = 0L;
chip->Tri05 = (RivaTexturedTriangle05 *)&(chip->FIFO[0x0000E000/4]);
break;
case NV_ARCH_10:
case NV_ARCH_20:
/*
* Initialize state for the RivaTriangle3D05 routines.
*/
LOAD_FIXED_STATE(nv10tri05,PGRAPH);
LOAD_FIXED_STATE(nv10,FIFO);
chip->Tri03 = 0L;
chip->Tri05 = (RivaTexturedTriangle05 *)&(chip->FIFO[0x0000E000/4]);
break;
}
}
static void LoadStateExt
(
RIVA_HW_INST *chip,
RIVA_HW_STATE *state
)
{
int i;
/*
* Load HW fixed function state.
*/
LOAD_FIXED_STATE(Riva,PMC);
LOAD_FIXED_STATE(Riva,PTIMER);
switch (chip->Architecture)
{
case NV_ARCH_03:
/*
* Make sure frame buffer config gets set before loading PRAMIN.
*/
chip->PFB[0x00000200/4] = state->config;
LOAD_FIXED_STATE(nv3,PFIFO);
LOAD_FIXED_STATE(nv3,PRAMIN);
LOAD_FIXED_STATE(nv3,PGRAPH);
switch (state->bpp)
{
case 15:
case 16:
LOAD_FIXED_STATE_15BPP(nv3,PRAMIN);
LOAD_FIXED_STATE_15BPP(nv3,PGRAPH);
chip->Tri03 = (RivaTexturedTriangle03 *)&(chip->FIFO[0x0000E000/4]);
break;
case 24:
case 32:
LOAD_FIXED_STATE_32BPP(nv3,PRAMIN);
LOAD_FIXED_STATE_32BPP(nv3,PGRAPH);
chip->Tri03 = 0L;
break;
case 8:
default:
LOAD_FIXED_STATE_8BPP(nv3,PRAMIN);
LOAD_FIXED_STATE_8BPP(nv3,PGRAPH);
chip->Tri03 = 0L;
break;
}
for (i = 0x00000; i < 0x00800; i++)
chip->PRAMIN[0x00000502 + i] = (i << 12) | 0x03;
chip->PGRAPH[0x00000630/4] = state->offset0;
chip->PGRAPH[0x00000634/4] = state->offset1;
chip->PGRAPH[0x00000638/4] = state->offset2;
chip->PGRAPH[0x0000063C/4] = state->offset3;
chip->PGRAPH[0x00000650/4] = state->pitch0;
chip->PGRAPH[0x00000654/4] = state->pitch1;
chip->PGRAPH[0x00000658/4] = state->pitch2;
chip->PGRAPH[0x0000065C/4] = state->pitch3;
break;
case NV_ARCH_04:
/*
* Make sure frame buffer config gets set before loading PRAMIN.
*/
chip->PFB[0x00000200/4] = state->config;
LOAD_FIXED_STATE(nv4,PFIFO);
LOAD_FIXED_STATE(nv4,PRAMIN);
LOAD_FIXED_STATE(nv4,PGRAPH);
switch (state->bpp)
{
case 15:
LOAD_FIXED_STATE_15BPP(nv4,PRAMIN);
LOAD_FIXED_STATE_15BPP(nv4,PGRAPH);
chip->Tri03 = (RivaTexturedTriangle03 *)&(chip->FIFO[0x0000E000/4]);
break;
case 16:
LOAD_FIXED_STATE_16BPP(nv4,PRAMIN);
LOAD_FIXED_STATE_16BPP(nv4,PGRAPH);
chip->Tri03 = (RivaTexturedTriangle03 *)&(chip->FIFO[0x0000E000/4]);
break;
case 24:
case 32:
LOAD_FIXED_STATE_32BPP(nv4,PRAMIN);
LOAD_FIXED_STATE_32BPP(nv4,PGRAPH);
chip->Tri03 = 0L;
break;
case 8:
default:
LOAD_FIXED_STATE_8BPP(nv4,PRAMIN);
LOAD_FIXED_STATE_8BPP(nv4,PGRAPH);
chip->Tri03 = 0L;
break;
}
chip->PGRAPH[0x00000640/4] = state->offset0;
chip->PGRAPH[0x00000644/4] = state->offset1;
chip->PGRAPH[0x00000648/4] = state->offset2;
chip->PGRAPH[0x0000064C/4] = state->offset3;
chip->PGRAPH[0x00000670/4] = state->pitch0;
chip->PGRAPH[0x00000674/4] = state->pitch1;
chip->PGRAPH[0x00000678/4] = state->pitch2;
chip->PGRAPH[0x0000067C/4] = state->pitch3;
break;
case NV_ARCH_10:
case NV_ARCH_20:
if(chip->twoHeads) {
VGA_WR08(chip->PCIO, 0x03D4, 0x44);
VGA_WR08(chip->PCIO, 0x03D5, state->crtcOwner);
chip->LockUnlock(chip, 0);
}
LOAD_FIXED_STATE(nv10,PFIFO);
LOAD_FIXED_STATE(nv10,PRAMIN);
LOAD_FIXED_STATE(nv10,PGRAPH);
switch (state->bpp)
{
case 15:
LOAD_FIXED_STATE_15BPP(nv10,PRAMIN);
LOAD_FIXED_STATE_15BPP(nv10,PGRAPH);
chip->Tri03 = (RivaTexturedTriangle03 *)&(chip->FIFO[0x0000E000/4]);
break;
case 16:
LOAD_FIXED_STATE_16BPP(nv10,PRAMIN);
LOAD_FIXED_STATE_16BPP(nv10,PGRAPH);
chip->Tri03 = (RivaTexturedTriangle03 *)&(chip->FIFO[0x0000E000/4]);
break;
case 24:
case 32:
LOAD_FIXED_STATE_32BPP(nv10,PRAMIN);
LOAD_FIXED_STATE_32BPP(nv10,PGRAPH);
chip->Tri03 = 0L;
break;
case 8:
default:
LOAD_FIXED_STATE_8BPP(nv10,PRAMIN);
LOAD_FIXED_STATE_8BPP(nv10,PGRAPH);
chip->Tri03 = 0L;
break;
}
if(chip->Architecture == NV_ARCH_10) {
chip->PGRAPH[0x00000640/4] = state->offset0;
chip->PGRAPH[0x00000644/4] = state->offset1;
chip->PGRAPH[0x00000648/4] = state->offset2;
chip->PGRAPH[0x0000064C/4] = state->offset3;
chip->PGRAPH[0x00000670/4] = state->pitch0;
chip->PGRAPH[0x00000674/4] = state->pitch1;
chip->PGRAPH[0x00000678/4] = state->pitch2;
chip->PGRAPH[0x0000067C/4] = state->pitch3;
chip->PGRAPH[0x00000680/4] = state->pitch3;
} else {
chip->PGRAPH[0x00000820/4] = state->offset0;
chip->PGRAPH[0x00000824/4] = state->offset1;
chip->PGRAPH[0x00000828/4] = state->offset2;
chip->PGRAPH[0x0000082C/4] = state->offset3;
chip->PGRAPH[0x00000850/4] = state->pitch0;
chip->PGRAPH[0x00000854/4] = state->pitch1;
chip->PGRAPH[0x00000858/4] = state->pitch2;
chip->PGRAPH[0x0000085C/4] = state->pitch3;
chip->PGRAPH[0x00000860/4] = state->pitch3;
chip->PGRAPH[0x00000864/4] = state->pitch3;
chip->PGRAPH[0x000009A4/4] = chip->PFB[0x00000200/4];
chip->PGRAPH[0x000009A8/4] = chip->PFB[0x00000204/4];
}
if(chip->twoHeads) {
chip->PCRTC0[0x00000860/4] = state->head;
chip->PCRTC0[0x00002860/4] = state->head2;
}
chip->PRAMDAC[0x00000404/4] |= (1 << 25);
chip->PMC[0x00008704/4] = 1;
chip->PMC[0x00008140/4] = 0;
chip->PMC[0x00008920/4] = 0;
chip->PMC[0x00008924/4] = 0;
chip->PMC[0x00008908/4] = 0x01ffffff;
chip->PMC[0x0000890C/4] = 0x01ffffff;
chip->PMC[0x00001588/4] = 0;
chip->PFB[0x00000240/4] = 0;
chip->PFB[0x00000244/4] = 0;
chip->PFB[0x00000248/4] = 0;
chip->PFB[0x0000024C/4] = 0;
chip->PFB[0x00000250/4] = 0;
chip->PFB[0x00000254/4] = 0;
chip->PFB[0x00000258/4] = 0;
chip->PFB[0x0000025C/4] = 0;
chip->PGRAPH[0x00000B00/4] = chip->PFB[0x00000240/4];
chip->PGRAPH[0x00000B04/4] = chip->PFB[0x00000244/4];
chip->PGRAPH[0x00000B08/4] = chip->PFB[0x00000248/4];
chip->PGRAPH[0x00000B0C/4] = chip->PFB[0x0000024C/4];
chip->PGRAPH[0x00000B10/4] = chip->PFB[0x00000250/4];
chip->PGRAPH[0x00000B14/4] = chip->PFB[0x00000254/4];
chip->PGRAPH[0x00000B18/4] = chip->PFB[0x00000258/4];
chip->PGRAPH[0x00000B1C/4] = chip->PFB[0x0000025C/4];
chip->PGRAPH[0x00000B20/4] = chip->PFB[0x00000260/4];
chip->PGRAPH[0x00000B24/4] = chip->PFB[0x00000264/4];
chip->PGRAPH[0x00000B28/4] = chip->PFB[0x00000268/4];
chip->PGRAPH[0x00000B2C/4] = chip->PFB[0x0000026C/4];
chip->PGRAPH[0x00000B30/4] = chip->PFB[0x00000270/4];
chip->PGRAPH[0x00000B34/4] = chip->PFB[0x00000274/4];
chip->PGRAPH[0x00000B38/4] = chip->PFB[0x00000278/4];
chip->PGRAPH[0x00000B3C/4] = chip->PFB[0x0000027C/4];
chip->PGRAPH[0x00000B40/4] = chip->PFB[0x00000280/4];
chip->PGRAPH[0x00000B44/4] = chip->PFB[0x00000284/4];
chip->PGRAPH[0x00000B48/4] = chip->PFB[0x00000288/4];
chip->PGRAPH[0x00000B4C/4] = chip->PFB[0x0000028C/4];
chip->PGRAPH[0x00000B50/4] = chip->PFB[0x00000290/4];
chip->PGRAPH[0x00000B54/4] = chip->PFB[0x00000294/4];
chip->PGRAPH[0x00000B58/4] = chip->PFB[0x00000298/4];
chip->PGRAPH[0x00000B5C/4] = chip->PFB[0x0000029C/4];
chip->PGRAPH[0x00000B60/4] = chip->PFB[0x000002A0/4];
chip->PGRAPH[0x00000B64/4] = chip->PFB[0x000002A4/4];
chip->PGRAPH[0x00000B68/4] = chip->PFB[0x000002A8/4];
chip->PGRAPH[0x00000B6C/4] = chip->PFB[0x000002AC/4];
chip->PGRAPH[0x00000B70/4] = chip->PFB[0x000002B0/4];
chip->PGRAPH[0x00000B74/4] = chip->PFB[0x000002B4/4];
chip->PGRAPH[0x00000B78/4] = chip->PFB[0x000002B8/4];
chip->PGRAPH[0x00000B7C/4] = chip->PFB[0x000002BC/4];
chip->PGRAPH[0x00000F40/4] = 0x10000000;
chip->PGRAPH[0x00000F44/4] = 0x00000000;
chip->PGRAPH[0x00000F50/4] = 0x00000040;
chip->PGRAPH[0x00000F54/4] = 0x00000008;
chip->PGRAPH[0x00000F50/4] = 0x00000200;
for (i = 0; i < (3*16); i++)
chip->PGRAPH[0x00000F54/4] = 0x00000000;
chip->PGRAPH[0x00000F50/4] = 0x00000040;
chip->PGRAPH[0x00000F54/4] = 0x00000000;
chip->PGRAPH[0x00000F50/4] = 0x00000800;
for (i = 0; i < (16*16); i++)
chip->PGRAPH[0x00000F54/4] = 0x00000000;
chip->PGRAPH[0x00000F40/4] = 0x30000000;
chip->PGRAPH[0x00000F44/4] = 0x00000004;
chip->PGRAPH[0x00000F50/4] = 0x00006400;
for (i = 0; i < (59*4); i++)
chip->PGRAPH[0x00000F54/4] = 0x00000000;
chip->PGRAPH[0x00000F50/4] = 0x00006800;
for (i = 0; i < (47*4); i++)
chip->PGRAPH[0x00000F54/4] = 0x00000000;
chip->PGRAPH[0x00000F50/4] = 0x00006C00;
for (i = 0; i < (3*4); i++)
chip->PGRAPH[0x00000F54/4] = 0x00000000;
chip->PGRAPH[0x00000F50/4] = 0x00007000;
for (i = 0; i < (19*4); i++)
chip->PGRAPH[0x00000F54/4] = 0x00000000;
chip->PGRAPH[0x00000F50/4] = 0x00007400;
for (i = 0; i < (12*4); i++)
chip->PGRAPH[0x00000F54/4] = 0x00000000;
chip->PGRAPH[0x00000F50/4] = 0x00007800;
for (i = 0; i < (12*4); i++)
chip->PGRAPH[0x00000F54/4] = 0x00000000;
chip->PGRAPH[0x00000F50/4] = 0x00004400;
for (i = 0; i < (8*4); i++)
chip->PGRAPH[0x00000F54/4] = 0x00000000;
chip->PGRAPH[0x00000F50/4] = 0x00000000;
for (i = 0; i < 16; i++)
chip->PGRAPH[0x00000F54/4] = 0x00000000;
chip->PGRAPH[0x00000F50/4] = 0x00000040;
for (i = 0; i < 4; i++)
chip->PGRAPH[0x00000F54/4] = 0x00000000;
chip->PCRTC[0x00000810/4] = state->cursorConfig;
if(chip->flatPanel) {
if((chip->Chipset & 0x0ff0) == 0x0110) {
chip->PRAMDAC[0x0528/4] = state->dither;
} else
if((chip->Chipset & 0x0ff0) >= 0x0170) {
chip->PRAMDAC[0x083C/4] = state->dither;
}
VGA_WR08(chip->PCIO, 0x03D4, 0x53);
VGA_WR08(chip->PCIO, 0x03D5, 0);
VGA_WR08(chip->PCIO, 0x03D4, 0x54);
VGA_WR08(chip->PCIO, 0x03D5, 0);
VGA_WR08(chip->PCIO, 0x03D4, 0x21);
VGA_WR08(chip->PCIO, 0x03D5, 0xfa);
}
VGA_WR08(chip->PCIO, 0x03D4, 0x41);
VGA_WR08(chip->PCIO, 0x03D5, state->extra);
}
LOAD_FIXED_STATE(Riva,FIFO);
UpdateFifoState(chip);
/*
* Load HW mode state.
*/
VGA_WR08(chip->PCIO, 0x03D4, 0x19);
VGA_WR08(chip->PCIO, 0x03D5, state->repaint0);
VGA_WR08(chip->PCIO, 0x03D4, 0x1A);
VGA_WR08(chip->PCIO, 0x03D5, state->repaint1);
VGA_WR08(chip->PCIO, 0x03D4, 0x25);
VGA_WR08(chip->PCIO, 0x03D5, state->screen);
VGA_WR08(chip->PCIO, 0x03D4, 0x28);
VGA_WR08(chip->PCIO, 0x03D5, state->pixel);
VGA_WR08(chip->PCIO, 0x03D4, 0x2D);
VGA_WR08(chip->PCIO, 0x03D5, state->horiz);
VGA_WR08(chip->PCIO, 0x03D4, 0x1B);
VGA_WR08(chip->PCIO, 0x03D5, state->arbitration0);
VGA_WR08(chip->PCIO, 0x03D4, 0x20);
VGA_WR08(chip->PCIO, 0x03D5, state->arbitration1);
VGA_WR08(chip->PCIO, 0x03D4, 0x30);
VGA_WR08(chip->PCIO, 0x03D5, state->cursor0);
VGA_WR08(chip->PCIO, 0x03D4, 0x31);
VGA_WR08(chip->PCIO, 0x03D5, state->cursor1);
VGA_WR08(chip->PCIO, 0x03D4, 0x2F);
VGA_WR08(chip->PCIO, 0x03D5, state->cursor2);
VGA_WR08(chip->PCIO, 0x03D4, 0x39);
VGA_WR08(chip->PCIO, 0x03D5, state->interlace);
if(!chip->flatPanel) {
chip->PRAMDAC0[0x00000508/4] = state->vpll;
chip->PRAMDAC0[0x0000050C/4] = state->pllsel;
if(chip->twoHeads)
chip->PRAMDAC0[0x00000520/4] = state->vpll2;
} else {
chip->PRAMDAC[0x00000848/4] = state->scale;
}
chip->PRAMDAC[0x00000600/4] = state->general;
/*
* Turn off VBlank enable and reset.
*/
chip->PCRTC[0x00000140/4] = 0;
chip->PCRTC[0x00000100/4] = chip->VBlankBit;
/*
* Set interrupt enable.
*/
chip->PMC[0x00000140/4] = chip->EnableIRQ & 0x01;
/*
* Set current state pointer.
*/
chip->CurrentState = state;
/*
* Reset FIFO free and empty counts.
*/
chip->FifoFreeCount = 0;
/* Free count from first subchannel */
chip->FifoEmptyCount = chip->Rop->FifoFree;
}
static void UnloadStateExt
(
RIVA_HW_INST *chip,
RIVA_HW_STATE *state
)
{
/*
* Save current HW state.
*/
VGA_WR08(chip->PCIO, 0x03D4, 0x19);
state->repaint0 = VGA_RD08(chip->PCIO, 0x03D5);
VGA_WR08(chip->PCIO, 0x03D4, 0x1A);
state->repaint1 = VGA_RD08(chip->PCIO, 0x03D5);
VGA_WR08(chip->PCIO, 0x03D4, 0x25);
state->screen = VGA_RD08(chip->PCIO, 0x03D5);
VGA_WR08(chip->PCIO, 0x03D4, 0x28);
state->pixel = VGA_RD08(chip->PCIO, 0x03D5);
VGA_WR08(chip->PCIO, 0x03D4, 0x2D);
state->horiz = VGA_RD08(chip->PCIO, 0x03D5);
VGA_WR08(chip->PCIO, 0x03D4, 0x1B);
state->arbitration0 = VGA_RD08(chip->PCIO, 0x03D5);
VGA_WR08(chip->PCIO, 0x03D4, 0x20);
state->arbitration1 = VGA_RD08(chip->PCIO, 0x03D5);
VGA_WR08(chip->PCIO, 0x03D4, 0x30);
state->cursor0 = VGA_RD08(chip->PCIO, 0x03D5);
VGA_WR08(chip->PCIO, 0x03D4, 0x31);
state->cursor1 = VGA_RD08(chip->PCIO, 0x03D5);
VGA_WR08(chip->PCIO, 0x03D4, 0x2F);
state->cursor2 = VGA_RD08(chip->PCIO, 0x03D5);
VGA_WR08(chip->PCIO, 0x03D4, 0x39);
state->interlace = VGA_RD08(chip->PCIO, 0x03D5);
state->vpll = chip->PRAMDAC0[0x00000508/4];
state->vpll2 = chip->PRAMDAC0[0x00000520/4];
state->pllsel = chip->PRAMDAC0[0x0000050C/4];
state->general = chip->PRAMDAC[0x00000600/4];
state->scale = chip->PRAMDAC[0x00000848/4];
state->config = chip->PFB[0x00000200/4];
switch (chip->Architecture)
{
case NV_ARCH_03:
state->offset0 = chip->PGRAPH[0x00000630/4];
state->offset1 = chip->PGRAPH[0x00000634/4];
state->offset2 = chip->PGRAPH[0x00000638/4];
state->offset3 = chip->PGRAPH[0x0000063C/4];
state->pitch0 = chip->PGRAPH[0x00000650/4];
state->pitch1 = chip->PGRAPH[0x00000654/4];
state->pitch2 = chip->PGRAPH[0x00000658/4];
state->pitch3 = chip->PGRAPH[0x0000065C/4];
break;
case NV_ARCH_04:
state->offset0 = chip->PGRAPH[0x00000640/4];
state->offset1 = chip->PGRAPH[0x00000644/4];
state->offset2 = chip->PGRAPH[0x00000648/4];
state->offset3 = chip->PGRAPH[0x0000064C/4];
state->pitch0 = chip->PGRAPH[0x00000670/4];
state->pitch1 = chip->PGRAPH[0x00000674/4];
state->pitch2 = chip->PGRAPH[0x00000678/4];
state->pitch3 = chip->PGRAPH[0x0000067C/4];
break;
case NV_ARCH_10:
case NV_ARCH_20:
state->offset0 = chip->PGRAPH[0x00000640/4];
state->offset1 = chip->PGRAPH[0x00000644/4];
state->offset2 = chip->PGRAPH[0x00000648/4];
state->offset3 = chip->PGRAPH[0x0000064C/4];
state->pitch0 = chip->PGRAPH[0x00000670/4];
state->pitch1 = chip->PGRAPH[0x00000674/4];
state->pitch2 = chip->PGRAPH[0x00000678/4];
state->pitch3 = chip->PGRAPH[0x0000067C/4];
if(chip->twoHeads) {
state->head = chip->PCRTC0[0x00000860/4];
state->head2 = chip->PCRTC0[0x00002860/4];
VGA_WR08(chip->PCIO, 0x03D4, 0x44);
state->crtcOwner = VGA_RD08(chip->PCIO, 0x03D5);
}
VGA_WR08(chip->PCIO, 0x03D4, 0x41);
state->extra = VGA_RD08(chip->PCIO, 0x03D5);
state->cursorConfig = chip->PCRTC[0x00000810/4];
if((chip->Chipset & 0x0ff0) == 0x0110) {
state->dither = chip->PRAMDAC[0x0528/4];
} else
if((chip->Chipset & 0x0ff0) >= 0x0170) {
state->dither = chip->PRAMDAC[0x083C/4];
}
break;
}
}
static void SetStartAddress
(
RIVA_HW_INST *chip,
unsigned start
)
{
chip->PCRTC[0x800/4] = start;
}
static void SetStartAddress3
(
RIVA_HW_INST *chip,
unsigned start
)
{
int offset = start >> 2;
int pan = (start & 3) << 1;
unsigned char tmp;
/*
* Unlock extended registers.
*/
chip->LockUnlock(chip, 0);
/*
* Set start address.
*/
VGA_WR08(chip->PCIO, 0x3D4, 0x0D); VGA_WR08(chip->PCIO, 0x3D5, offset);
offset >>= 8;
VGA_WR08(chip->PCIO, 0x3D4, 0x0C); VGA_WR08(chip->PCIO, 0x3D5, offset);
offset >>= 8;
VGA_WR08(chip->PCIO, 0x3D4, 0x19); tmp = VGA_RD08(chip->PCIO, 0x3D5);
VGA_WR08(chip->PCIO, 0x3D5, (offset & 0x01F) | (tmp & ~0x1F));
VGA_WR08(chip->PCIO, 0x3D4, 0x2D); tmp = VGA_RD08(chip->PCIO, 0x3D5);
VGA_WR08(chip->PCIO, 0x3D5, (offset & 0x60) | (tmp & ~0x60));
/*
* 4 pixel pan register.
*/
offset = VGA_RD08(chip->PCIO, chip->IO + 0x0A);
VGA_WR08(chip->PCIO, 0x3C0, 0x13);
VGA_WR08(chip->PCIO, 0x3C0, pan);
}
static void nv3SetSurfaces2D
(
RIVA_HW_INST *chip,
unsigned surf0,
unsigned surf1
)
{
RivaSurface *Surface = (RivaSurface *)&(chip->FIFO[0x0000E000/4]);
RIVA_FIFO_FREE(*chip,Tri03,5);
chip->FIFO[0x00003800] = 0x80000003;
Surface->Offset = surf0;
chip->FIFO[0x00003800] = 0x80000004;
Surface->Offset = surf1;
chip->FIFO[0x00003800] = 0x80000013;
}
static void nv4SetSurfaces2D
(
RIVA_HW_INST *chip,
unsigned surf0,
unsigned surf1
)
{
RivaSurface *Surface = (RivaSurface *)&(chip->FIFO[0x0000E000/4]);
chip->FIFO[0x00003800] = 0x80000003;
Surface->Offset = surf0;
chip->FIFO[0x00003800] = 0x80000004;
Surface->Offset = surf1;
chip->FIFO[0x00003800] = 0x80000014;
}
static void nv10SetSurfaces2D
(
RIVA_HW_INST *chip,
unsigned surf0,
unsigned surf1
)
{
RivaSurface *Surface = (RivaSurface *)&(chip->FIFO[0x0000E000/4]);
chip->FIFO[0x00003800] = 0x80000003;
Surface->Offset = surf0;
chip->FIFO[0x00003800] = 0x80000004;
Surface->Offset = surf1;
chip->FIFO[0x00003800] = 0x80000014;
}
static void nv3SetSurfaces3D
(
RIVA_HW_INST *chip,
unsigned surf0,
unsigned surf1
)
{
RivaSurface *Surface = (RivaSurface *)&(chip->FIFO[0x0000E000/4]);
RIVA_FIFO_FREE(*chip,Tri03,5);
chip->FIFO[0x00003800] = 0x80000005;
Surface->Offset = surf0;
chip->FIFO[0x00003800] = 0x80000006;
Surface->Offset = surf1;
chip->FIFO[0x00003800] = 0x80000013;
}
static void nv4SetSurfaces3D
(
RIVA_HW_INST *chip,
unsigned surf0,
unsigned surf1
)
{
RivaSurface *Surface = (RivaSurface *)&(chip->FIFO[0x0000E000/4]);
chip->FIFO[0x00003800] = 0x80000005;
Surface->Offset = surf0;
chip->FIFO[0x00003800] = 0x80000006;
Surface->Offset = surf1;
chip->FIFO[0x00003800] = 0x80000014;
}
static void nv10SetSurfaces3D
(
RIVA_HW_INST *chip,
unsigned surf0,
unsigned surf1
)
{
RivaSurface3D *Surfaces3D = (RivaSurface3D *)&(chip->FIFO[0x0000E000/4]);
RIVA_FIFO_FREE(*chip,Tri03,4);
chip->FIFO[0x00003800] = 0x80000007;
Surfaces3D->RenderBufferOffset = surf0;
Surfaces3D->ZBufferOffset = surf1;
chip->FIFO[0x00003800] = 0x80000014;
}
/****************************************************************************\
* *
* Probe RIVA Chip Configuration *
* *
\****************************************************************************/
static void nv3GetConfig
(
RIVA_HW_INST *chip
)
{
/*
* Fill in chip configuration.
*/
if (chip->PFB[0x00000000/4] & 0x00000020)
{
if (((chip->PMC[0x00000000/4] & 0xF0) == 0x20)
&& ((chip->PMC[0x00000000/4] & 0x0F) >= 0x02))
{
/*
* SDRAM 128 ZX.
*/
chip->RamBandwidthKBytesPerSec = 800000;
switch (chip->PFB[0x00000000/4] & 0x03)
{
case 2:
chip->RamAmountKBytes = 1024 * 4;
break;
case 1:
chip->RamAmountKBytes = 1024 * 2;
break;
default:
chip->RamAmountKBytes = 1024 * 8;
break;
}
}
else
{
chip->RamBandwidthKBytesPerSec = 1000000;
chip->RamAmountKBytes = 1024 * 8;
}
}
else
{
/*
* SGRAM 128.
*/
chip->RamBandwidthKBytesPerSec = 1000000;
switch (chip->PFB[0x00000000/4] & 0x00000003)
{
case 0:
chip->RamAmountKBytes = 1024 * 8;
break;
case 2:
chip->RamAmountKBytes = 1024 * 4;
break;
default:
chip->RamAmountKBytes = 1024 * 2;
break;
}
}
chip->CrystalFreqKHz = (chip->PEXTDEV[0x00000000/4] & 0x00000040) ? 14318 : 13500;
chip->CURSOR = &(chip->PRAMIN[0x00008000/4 - 0x0800/4]);
chip->VBlankBit = 0x00000100;
chip->MaxVClockFreqKHz = 256000;
/*
* Set chip functions.
*/
chip->Busy = nv3Busy;
chip->ShowHideCursor = ShowHideCursor;
chip->CalcStateExt = CalcStateExt;
chip->LoadStateExt = LoadStateExt;
chip->UnloadStateExt = UnloadStateExt;
chip->SetStartAddress = SetStartAddress3;
chip->SetSurfaces2D = nv3SetSurfaces2D;
chip->SetSurfaces3D = nv3SetSurfaces3D;
chip->LockUnlock = nv3LockUnlock;
}
static void nv4GetConfig
(
RIVA_HW_INST *chip
)
{
/*
* Fill in chip configuration.
*/
if (chip->PFB[0x00000000/4] & 0x00000100)
{
chip->RamAmountKBytes = ((chip->PFB[0x00000000/4] >> 12) & 0x0F) * 1024 * 2
+ 1024 * 2;
}
else
{
switch (chip->PFB[0x00000000/4] & 0x00000003)
{
case 0:
chip->RamAmountKBytes = 1024 * 32;
break;
case 1:
chip->RamAmountKBytes = 1024 * 4;
break;
case 2:
chip->RamAmountKBytes = 1024 * 8;
break;
case 3:
default:
chip->RamAmountKBytes = 1024 * 16;
break;
}
}
switch ((chip->PFB[0x00000000/4] >> 3) & 0x00000003)
{
case 3:
chip->RamBandwidthKBytesPerSec = 800000;
break;
default:
chip->RamBandwidthKBytesPerSec = 1000000;
break;
}
chip->CrystalFreqKHz = (chip->PEXTDEV[0x00000000/4] & 0x00000040) ? 14318 : 13500;
chip->CURSOR = &(chip->PRAMIN[0x00010000/4 - 0x0800/4]);
chip->VBlankBit = 0x00000001;
chip->MaxVClockFreqKHz = 350000;
/*
* Set chip functions.
*/
chip->Busy = nv4Busy;
chip->ShowHideCursor = ShowHideCursor;
chip->CalcStateExt = CalcStateExt;
chip->LoadStateExt = LoadStateExt;
chip->UnloadStateExt = UnloadStateExt;
chip->SetStartAddress = SetStartAddress;
chip->SetSurfaces2D = nv4SetSurfaces2D;
chip->SetSurfaces3D = nv4SetSurfaces3D;
chip->LockUnlock = nv4LockUnlock;
}
static void nv10GetConfig
(
RIVA_HW_INST *chip,
unsigned int chipset
)
{
struct pci_dev* dev;
int amt;
#ifdef __BIG_ENDIAN
/* turn on big endian register access */
chip->PMC[0x00000004/4] = 0x01000001;
#endif
/*
* Fill in chip configuration.
*/
if(chipset == NV_CHIP_IGEFORCE2) {
dev = pci_find_slot(0, 1);
pci_read_config_dword(dev, 0x7C, &amt);
chip->RamAmountKBytes = (((amt >> 6) & 31) + 1) * 1024;
} else if(chipset == NV_CHIP_0x01F0) {
dev = pci_find_slot(0, 1);
pci_read_config_dword(dev, 0x84, &amt);
chip->RamAmountKBytes = (((amt >> 4) & 127) + 1) * 1024;
} else {
switch ((chip->PFB[0x0000020C/4] >> 20) & 0x000000FF)
{
case 0x02:
chip->RamAmountKBytes = 1024 * 2;
break;
case 0x04:
chip->RamAmountKBytes = 1024 * 4;
break;
case 0x08:
chip->RamAmountKBytes = 1024 * 8;
break;
case 0x10:
chip->RamAmountKBytes = 1024 * 16;
break;
case 0x20:
chip->RamAmountKBytes = 1024 * 32;
break;
case 0x40:
chip->RamAmountKBytes = 1024 * 64;
break;
case 0x80:
chip->RamAmountKBytes = 1024 * 128;
break;
default:
chip->RamAmountKBytes = 1024 * 16;
break;
}
}
switch ((chip->PFB[0x00000000/4] >> 3) & 0x00000003)
{
case 3:
chip->RamBandwidthKBytesPerSec = 800000;
break;
default:
chip->RamBandwidthKBytesPerSec = 1000000;
break;
}
chip->CrystalFreqKHz = (chip->PEXTDEV[0x0000/4] & (1 << 6)) ? 14318 :
13500;
switch (chipset & 0x0ff0) {
case 0x0170:
case 0x0180:
case 0x01F0:
case 0x0250:
case 0x0280:
if(chip->PEXTDEV[0x0000/4] & (1 << 22))
chip->CrystalFreqKHz = 27000;
break;
default:
break;
}
chip->CursorStart = (chip->RamAmountKBytes - 128) * 1024;
chip->CURSOR = NULL; /* can't set this here */
chip->VBlankBit = 0x00000001;
chip->MaxVClockFreqKHz = 350000;
/*
* Set chip functions.
*/
chip->Busy = nv10Busy;
chip->ShowHideCursor = ShowHideCursor;
chip->CalcStateExt = CalcStateExt;
chip->LoadStateExt = LoadStateExt;
chip->UnloadStateExt = UnloadStateExt;
chip->SetStartAddress = SetStartAddress;
chip->SetSurfaces2D = nv10SetSurfaces2D;
chip->SetSurfaces3D = nv10SetSurfaces3D;
chip->LockUnlock = nv4LockUnlock;
switch(chipset & 0x0ff0) {
case 0x0110:
case 0x0170:
case 0x0180:
case 0x01F0:
case 0x0250:
case 0x0280:
chip->twoHeads = TRUE;
break;
default:
chip->twoHeads = FALSE;
break;
}
}
int RivaGetConfig
(
RIVA_HW_INST *chip,
unsigned int chipset
)
{
/*
* Save this so future SW know whats it's dealing with.
*/
chip->Version = RIVA_SW_VERSION;
/*
* Chip specific configuration.
*/
switch (chip->Architecture)
{
case NV_ARCH_03:
nv3GetConfig(chip);
break;
case NV_ARCH_04:
nv4GetConfig(chip);
break;
case NV_ARCH_10:
case NV_ARCH_20:
nv10GetConfig(chip, chipset);
break;
default:
return (-1);
}
chip->Chipset = chipset;
/*
* Fill in FIFO pointers.
*/
chip->Rop = (RivaRop *)&(chip->FIFO[0x00000000/4]);
chip->Clip = (RivaClip *)&(chip->FIFO[0x00002000/4]);
chip->Patt = (RivaPattern *)&(chip->FIFO[0x00004000/4]);
chip->Pixmap = (RivaPixmap *)&(chip->FIFO[0x00006000/4]);
chip->Blt = (RivaScreenBlt *)&(chip->FIFO[0x00008000/4]);
chip->Bitmap = (RivaBitmap *)&(chip->FIFO[0x0000A000/4]);
chip->Line = (RivaLine *)&(chip->FIFO[0x0000C000/4]);
chip->Tri03 = (RivaTexturedTriangle03 *)&(chip->FIFO[0x0000E000/4]);
return (0);
}

/shark/trunk/drivers/fb/riva/riva_hw.h
0,0 → 1,547
/***************************************************************************\
|* *|
|* Copyright 1993-1999 NVIDIA, Corporation. All rights reserved. *|
|* *|
|* NOTICE TO USER: The source code is copyrighted under U.S. and *|
|* international laws. Users and possessors of this source code are *|
|* hereby granted a nonexclusive, royalty-free copyright license to *|
|* use this code in individual and commercial software. *|
|* *|
|* Any use of this source code must include, in the user documenta- *|
|* tion and internal comments to the code, notices to the end user *|
|* as follows: *|
|* *|
|* Copyright 1993-1999 NVIDIA, Corporation. All rights reserved. *|
|* *|
|* NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY *|
|* OF THIS SOURCE CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" *|
|* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *|
|* ATION DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOURCE CODE, *|
|* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *|
|* MENT, AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL *|
|* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *|
|* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *|
|* SULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION *|
|* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF *|
|* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE. *|
|* *|
|* U.S. Government End Users. This source code is a "commercial *|
|* item," as that term is defined at 48 C.F.R. 2.101 (OCT 1995), *|
|* consisting of "commercial computer software" and "commercial *|
|* computer software documentation," as such terms are used in *|
|* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *|
|* ment only as a commercial end item. Consistent with 48 C.F.R. *|
|* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *|
|* all U.S. Government End Users acquire the source code with only *|
|* those rights set forth herein. *|
|* *|
\***************************************************************************/
/*
* GPL licensing note -- nVidia is allowing a liberal interpretation of
* the documentation restriction above, to merely say that this nVidia's
* copyright and disclaimer should be included with all code derived
* from this source. -- Jeff Garzik <jgarzik@pobox.com>, 01/Nov/99
*/
/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/riva_hw.h,v 1.21 2002/10/14 18:22:46 mvojkovi Exp $ */
#ifndef __RIVA_HW_H__
#define __RIVA_HW_H__
#define RIVA_SW_VERSION 0x00010003
#ifndef Bool
typedef int Bool;
#endif
#ifndef TRUE
#define TRUE 1
#endif
#ifndef FALSE
#define FALSE 0
#endif
#ifndef NULL
#define NULL 0
#endif
/*
* Typedefs to force certain sized values.
*/
typedef unsigned char U008;
typedef unsigned short U016;
typedef unsigned int U032;
/*
* HW access macros.
*/
#if defined(__powerpc__)
#include <asm/io.h>
#define NV_WR08(p,i,d) out_8(p+i, d)
#define NV_RD08(p,i) in_8(p+i)
#else
#define NV_WR08(p,i,d) (((U008 *)(p))[i]=(d))
#define NV_RD08(p,i) (((U008 *)(p))[i])
#endif
#define NV_WR16(p,i,d) (((U016 *)(p))[(i)/2]=(d))
#define NV_RD16(p,i) (((U016 *)(p))[(i)/2])
#define NV_WR32(p,i,d) (((U032 *)(p))[(i)/4]=(d))
#define NV_RD32(p,i) (((U032 *)(p))[(i)/4])
#define VGA_WR08(p,i,d) NV_WR08(p,i,d)
#define VGA_RD08(p,i) NV_RD08(p,i)
/*
* Define supported architectures.
*/
#define NV_ARCH_03 0x03
#define NV_ARCH_04 0x04
#define NV_ARCH_10 0x10
#define NV_ARCH_20 0x20
/***************************************************************************\
* *
* FIFO registers. *
* *
\***************************************************************************/
/*
* Raster OPeration. Windows style ROP3.
*/
typedef volatile struct
{
U032 reserved00[4];
#ifdef __BIG_ENDIAN
U032 FifoFree;
#else
U016 FifoFree;
U016 Nop;
#endif
U032 reserved01[0x0BB];
U032 Rop3;
} RivaRop;
/*
* 8X8 Monochrome pattern.
*/
typedef volatile struct
{
U032 reserved00[4];
#ifdef __BIG_ENDIAN
U032 FifoFree;
#else
U016 FifoFree;
U016 Nop;
#endif
U032 reserved01[0x0BD];
U032 Shape;
U032 reserved03[0x001];
U032 Color0;
U032 Color1;
U032 Monochrome[2];
} RivaPattern;
/*
* Scissor clip rectangle.
*/
typedef volatile struct
{
U032 reserved00[4];
#ifdef __BIG_ENDIAN
U032 FifoFree;
#else
U016 FifoFree;
U016 Nop;
#endif
U032 reserved01[0x0BB];
U032 TopLeft;
U032 WidthHeight;
} RivaClip;
/*
* 2D filled rectangle.
*/
typedef volatile struct
{
U032 reserved00[4];
#ifdef __BIG_ENDIAN
U032 FifoFree;
#else
U016 FifoFree;
U016 Nop[1];
#endif
U032 reserved01[0x0BC];
U032 Color;
U032 reserved03[0x03E];
U032 TopLeft;
U032 WidthHeight;
} RivaRectangle;
/*
* 2D screen-screen BLT.
*/
typedef volatile struct
{
U032 reserved00[4];
#ifdef __BIG_ENDIAN
U032 FifoFree;
#else
U016 FifoFree;
U016 Nop;
#endif
U032 reserved01[0x0BB];
U032 TopLeftSrc;
U032 TopLeftDst;
U032 WidthHeight;
} RivaScreenBlt;
/*
* 2D pixel BLT.
*/
typedef volatile struct
{
U032 reserved00[4];
#ifdef __BIG_ENDIAN
U032 FifoFree;
#else
U016 FifoFree;
U016 Nop[1];
#endif
U032 reserved01[0x0BC];
U032 TopLeft;
U032 WidthHeight;
U032 WidthHeightIn;
U032 reserved02[0x03C];
U032 Pixels;
} RivaPixmap;
/*
* Filled rectangle combined with monochrome expand. Useful for glyphs.
*/
typedef volatile struct
{
U032 reserved00[4];
#ifdef __BIG_ENDIAN
U032 FifoFree;
#else
U016 FifoFree;
U016 Nop;
#endif
U032 reserved01[0x0BB];
U032 reserved03[(0x040)-1];
U032 Color1A;
struct
{
U032 TopLeft;
U032 WidthHeight;
} UnclippedRectangle[64];
U032 reserved04[(0x080)-3];
struct
{
U032 TopLeft;
U032 BottomRight;
} ClipB;
U032 Color1B;
struct
{
U032 TopLeft;
U032 BottomRight;
} ClippedRectangle[64];
U032 reserved05[(0x080)-5];
struct
{
U032 TopLeft;
U032 BottomRight;
} ClipC;
U032 Color1C;
U032 WidthHeightC;
U032 PointC;
U032 MonochromeData1C;
U032 reserved06[(0x080)+121];
struct
{
U032 TopLeft;
U032 BottomRight;
} ClipD;
U032 Color1D;
U032 WidthHeightInD;
U032 WidthHeightOutD;
U032 PointD;
U032 MonochromeData1D;
U032 reserved07[(0x080)+120];
struct
{
U032 TopLeft;
U032 BottomRight;
} ClipE;
U032 Color0E;
U032 Color1E;
U032 WidthHeightInE;
U032 WidthHeightOutE;
U032 PointE;
U032 MonochromeData01E;
} RivaBitmap;
/*
* 3D textured, Z buffered triangle.
*/
typedef volatile struct
{
U032 reserved00[4];
#ifdef __BIG_ENDIAN
U032 FifoFree;
#else
U016 FifoFree;
U016 Nop;
#endif
U032 reserved01[0x0BC];
U032 TextureOffset;
U032 TextureFormat;
U032 TextureFilter;
U032 FogColor;
/* This is a problem on LynxOS */
#ifdef Control
#undef Control
#endif
U032 Control;
U032 AlphaTest;
U032 reserved02[0x339];
U032 FogAndIndex;
U032 Color;
float ScreenX;
float ScreenY;
float ScreenZ;
float EyeM;
float TextureS;
float TextureT;
} RivaTexturedTriangle03;
typedef volatile struct
{
U032 reserved00[4];
#ifdef __BIG_ENDIAN
U032 FifoFree;
#else
U016 FifoFree;
U016 Nop;
#endif
U032 reserved01[0x0BB];
U032 ColorKey;
U032 TextureOffset;
U032 TextureFormat;
U032 TextureFilter;
U032 Blend;
/* This is a problem on LynxOS */
#ifdef Control
#undef Control
#endif
U032 Control;
U032 FogColor;
U032 reserved02[0x39];
struct
{
float ScreenX;
float ScreenY;
float ScreenZ;
float EyeM;
U032 Color;
U032 Specular;
float TextureS;
float TextureT;
} Vertex[16];
U032 DrawTriangle3D;
} RivaTexturedTriangle05;
/*
* 2D line.
*/
typedef volatile struct
{
U032 reserved00[4];
#ifdef __BIG_ENDIAN
U032 FifoFree;
#else
U016 FifoFree;
U016 Nop[1];
#endif
U032 reserved01[0x0BC];
U032 Color; /* source color 0304-0307*/
U032 Reserved02[0x03e];
struct { /* start aliased methods in array 0400- */
U032 point0; /* y_x S16_S16 in pixels 0- 3*/
U032 point1; /* y_x S16_S16 in pixels 4- 7*/
} Lin[16]; /* end of aliased methods in array -047f*/
struct { /* start aliased methods in array 0480- */
U032 point0X; /* in pixels, 0 at left 0- 3*/
U032 point0Y; /* in pixels, 0 at top 4- 7*/
U032 point1X; /* in pixels, 0 at left 8- b*/
U032 point1Y; /* in pixels, 0 at top c- f*/
} Lin32[8]; /* end of aliased methods in array -04ff*/
U032 PolyLin[32]; /* y_x S16_S16 in pixels 0500-057f*/
struct { /* start aliased methods in array 0580- */
U032 x; /* in pixels, 0 at left 0- 3*/
U032 y; /* in pixels, 0 at top 4- 7*/
} PolyLin32[16]; /* end of aliased methods in array -05ff*/
struct { /* start aliased methods in array 0600- */
U032 color; /* source color 0- 3*/
U032 point; /* y_x S16_S16 in pixels 4- 7*/
} ColorPolyLin[16]; /* end of aliased methods in array -067f*/
} RivaLine;
/*
* 2D/3D surfaces
*/
typedef volatile struct
{
U032 reserved00[4];
#ifdef __BIG_ENDIAN
U032 FifoFree;
#else
U016 FifoFree;
U016 Nop;
#endif
U032 reserved01[0x0BE];
U032 Offset;
} RivaSurface;
typedef volatile struct
{
U032 reserved00[4];
#ifdef __BIG_ENDIAN
U032 FifoFree;
#else
U016 FifoFree;
U016 Nop;
#endif
U032 reserved01[0x0BD];
U032 Pitch;
U032 RenderBufferOffset;
U032 ZBufferOffset;
} RivaSurface3D;
/***************************************************************************\
* *
* Virtualized RIVA H/W interface. *
* *
\***************************************************************************/
#define FP_ENABLE 1
#define FP_DITHER 2
struct _riva_hw_inst;
struct _riva_hw_state;
/*
* Virtialized chip interface. Makes RIVA 128 and TNT look alike.
*/
typedef struct _riva_hw_inst
{
/*
* Chip specific settings.
*/
U032 Architecture;
U032 Version;
U032 Chipset;
U032 CrystalFreqKHz;
U032 RamAmountKBytes;
U032 MaxVClockFreqKHz;
U032 RamBandwidthKBytesPerSec;
U032 EnableIRQ;
U032 IO;
U032 VBlankBit;
U032 FifoFreeCount;
U032 FifoEmptyCount;
U032 CursorStart;
U032 flatPanel;
Bool twoHeads;
/*
* Non-FIFO registers.
*/
volatile U032 *PCRTC0;
volatile U032 *PCRTC;
volatile U032 *PRAMDAC0;
volatile U032 *PFB;
volatile U032 *PFIFO;
volatile U032 *PGRAPH;
volatile U032 *PEXTDEV;
volatile U032 *PTIMER;
volatile U032 *PMC;
volatile U032 *PRAMIN;
volatile U032 *FIFO;
volatile U032 *CURSOR;
volatile U008 *PCIO0;
volatile U008 *PCIO;
volatile U008 *PVIO;
volatile U008 *PDIO0;
volatile U008 *PDIO;
volatile U032 *PRAMDAC;
/*
* Common chip functions.
*/
int (*Busy)(struct _riva_hw_inst *);
void (*CalcStateExt)(struct _riva_hw_inst *,struct _riva_hw_state *,int,int,int,int,int);
void (*LoadStateExt)(struct _riva_hw_inst *,struct _riva_hw_state *);
void (*UnloadStateExt)(struct _riva_hw_inst *,struct _riva_hw_state *);
void (*SetStartAddress)(struct _riva_hw_inst *,U032);
void (*SetSurfaces2D)(struct _riva_hw_inst *,U032,U032);
void (*SetSurfaces3D)(struct _riva_hw_inst *,U032,U032);
int (*ShowHideCursor)(struct _riva_hw_inst *,int);
void (*LockUnlock)(struct _riva_hw_inst *, int);
/*
* Current extended mode settings.
*/
struct _riva_hw_state *CurrentState;
/*
* FIFO registers.
*/
RivaRop *Rop;
RivaPattern *Patt;
RivaClip *Clip;
RivaPixmap *Pixmap;
RivaScreenBlt *Blt;
RivaBitmap *Bitmap;
RivaLine *Line;
RivaTexturedTriangle03 *Tri03;
RivaTexturedTriangle05 *Tri05;
} RIVA_HW_INST;
/*
* Extended mode state information.
*/
typedef struct _riva_hw_state
{
U032 bpp;
U032 width;
U032 height;
U032 interlace;
U032 repaint0;
U032 repaint1;
U032 screen;
U032 scale;
U032 dither;
U032 extra;
U032 pixel;
U032 horiz;
U032 arbitration0;
U032 arbitration1;
U032 vpll;
U032 vpll2;
U032 pllsel;
U032 general;
U032 crtcOwner;
U032 head;
U032 head2;
U032 config;
U032 cursorConfig;
U032 cursor0;
U032 cursor1;
U032 cursor2;
U032 offset0;
U032 offset1;
U032 offset2;
U032 offset3;
U032 pitch0;
U032 pitch1;
U032 pitch2;
U032 pitch3;
} RIVA_HW_STATE;
/*
* External routines.
*/
int RivaGetConfig(RIVA_HW_INST *, unsigned int);
/*
* FIFO Free Count. Should attempt to yield processor if RIVA is busy.
*/
#define RIVA_FIFO_FREE(hwinst,hwptr,cnt) \
{ \
while ((hwinst).FifoFreeCount < (cnt)) \
(hwinst).FifoFreeCount = (hwinst).hwptr->FifoFree >> 2; \
(hwinst).FifoFreeCount -= (cnt); \
}
#endif /* __RIVA_HW_H__ */

/shark/trunk/drivers/fb/riva/fbdev.c
0,0 → 1,2027
/*
* linux/drivers/video/riva/fbdev.c - nVidia RIVA 128/TNT/TNT2 fb driver
*
* Maintained by Ani Joshi <ajoshi@shell.unixbox.com>
*
* Copyright 1999-2000 Jeff Garzik
*
* Contributors:
*
* Ani Joshi: Lots of debugging and cleanup work, really helped
* get the driver going
*
* Ferenc Bakonyi: Bug fixes, cleanup, modularization
*
* Jindrich Makovicka: Accel code help, hw cursor, mtrr
*
* Paul Richards: Bug fixes, updates
*
* Initial template from skeletonfb.c, created 28 Dec 1997 by Geert Uytterhoeven
* Includes riva_hw.c from nVidia, see copyright below.
* KGI code provided the basis for state storage, init, and mode switching.
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive
* for more details.
*
* Known bugs and issues:
* restoring text mode fails
* doublescan modes are broken
*/
#include <linuxcomp.h>
#include <linux/config.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/string.h>
#include <linux/mm.h>
#include <linux/tty.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/fb.h>
#include <linux/init.h>
#include <linux/pci.h>
#ifdef CONFIG_MTRR
#include <asm/mtrr.h>
#endif
#include "rivafb.h"
#include "nvreg.h"
#ifndef CONFIG_PCI /* sanity check */
#error This driver requires PCI support.
#endif
/* version number of this driver */
#define RIVAFB_VERSION "0.9.5b"
/* ------------------------------------------------------------------------- *
*
* various helpful macros and constants
*
* ------------------------------------------------------------------------- */
#undef RIVAFBDEBUG
#ifdef RIVAFBDEBUG
#define DPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt, __FUNCTION__ , ## args)
#else
#define DPRINTK(fmt, args...)
#endif
#ifndef RIVA_NDEBUG
#define assert(expr) \
if(!(expr)) { \
printk( "Assertion failed! %s,%s,%s,line=%d\n",\
#expr,__FILE__,__FUNCTION__,__LINE__); \
BUG(); \
}
#else
#define assert(expr)
#endif
#define PFX "rivafb: "
/* macro that allows you to set overflow bits */
#define SetBitField(value,from,to) SetBF(to,GetBF(value,from))
#define SetBit(n) (1<<(n))
#define Set8Bits(value) ((value)&0xff)
/* HW cursor parameters */
#define MAX_CURS 32
/* ------------------------------------------------------------------------- *
*
* prototypes
*
* ------------------------------------------------------------------------- */
static int rivafb_blank(int blank, struct fb_info *info);
/* ------------------------------------------------------------------------- *
*
* card identification
*
* ------------------------------------------------------------------------- */
enum riva_chips {
CH_RIVA_128 = 0,
CH_RIVA_TNT,
CH_RIVA_TNT2,
CH_RIVA_UTNT2,
CH_RIVA_VTNT2,
CH_RIVA_UVTNT2,
CH_RIVA_ITNT2,
CH_GEFORCE_SDR,
CH_GEFORCE_DDR,
CH_QUADRO,
CH_GEFORCE2_MX,
CH_GEFORCE2_MX2,
CH_GEFORCE2_GO,
CH_QUADRO2_MXR,
CH_GEFORCE2_GTS,
CH_GEFORCE2_GTS2,
CH_GEFORCE2_ULTRA,
CH_QUADRO2_PRO,
CH_GEFORCE4_MX_460,
CH_GEFORCE4_MX_440,
CH_GEFORCE4_MX_420,
CH_GEFORCE4_440_GO,
CH_GEFORCE4_420_GO,
CH_GEFORCE4_420_GO_M32,
CH_QUADRO4_500XGL,
CH_GEFORCE4_440_GO_M64,
CH_QUADRO4_200,
CH_QUADRO4_550XGL,
CH_QUADRO4_500_GOGL,
CH_IGEFORCE2,
CH_GEFORCE3,
CH_GEFORCE3_1,
CH_GEFORCE3_2,
CH_QUADRO_DDC,
CH_GEFORCE4_TI_4600,
CH_GEFORCE4_TI_4400,
CH_GEFORCE4_TI_4200,
CH_QUADRO4_900XGL,
CH_QUADRO4_750XGL,
CH_QUADRO4_700XGL
};
/* directly indexed by riva_chips enum, above */
static struct riva_chip_info {
const char *name;
unsigned arch_rev;
} riva_chip_info[] __initdata = {
{ "RIVA-128", NV_ARCH_03 },
{ "RIVA-TNT", NV_ARCH_04 },
{ "RIVA-TNT2", NV_ARCH_04 },
{ "RIVA-UTNT2", NV_ARCH_04 },
{ "RIVA-VTNT2", NV_ARCH_04 },
{ "RIVA-UVTNT2", NV_ARCH_04 },
{ "RIVA-ITNT2", NV_ARCH_04 },
{ "GeForce-SDR", NV_ARCH_10 },
{ "GeForce-DDR", NV_ARCH_10 },
{ "Quadro", NV_ARCH_10 },
{ "GeForce2-MX", NV_ARCH_10 },
{ "GeForce2-MX", NV_ARCH_10 },
{ "GeForce2-GO", NV_ARCH_10 },
{ "Quadro2-MXR", NV_ARCH_10 },
{ "GeForce2-GTS", NV_ARCH_10 },
{ "GeForce2-GTS", NV_ARCH_10 },
{ "GeForce2-ULTRA", NV_ARCH_10 },
{ "Quadro2-PRO", NV_ARCH_10 },
{ "GeForce4-MX-460", NV_ARCH_20 },
{ "GeForce4-MX-440", NV_ARCH_20 },
{ "GeForce4-MX-420", NV_ARCH_20 },
{ "GeForce4-440-GO", NV_ARCH_20 },
{ "GeForce4-420-GO", NV_ARCH_20 },
{ "GeForce4-420-GO-M32", NV_ARCH_20 },
{ "Quadro4-500-XGL", NV_ARCH_20 },
{ "GeForce4-440-GO-M64", NV_ARCH_20 },
{ "Quadro4-200", NV_ARCH_20 },
{ "Quadro4-550-XGL", NV_ARCH_20 },
{ "Quadro4-500-GOGL", NV_ARCH_20 },
{ "GeForce2", NV_ARCH_20 },
{ "GeForce3", NV_ARCH_20 },
{ "GeForce3 Ti 200", NV_ARCH_20 },
{ "GeForce3 Ti 500", NV_ARCH_20 },
{ "Quadro DDC", NV_ARCH_20 },
{ "GeForce4 Ti 4600", NV_ARCH_20 },
{ "GeForce4 Ti 4400", NV_ARCH_20 },
{ "GeForce4 Ti 4200", NV_ARCH_20 },
{ "Quadro4-900-XGL", NV_ARCH_20 },
{ "Quadro4-750-XGL", NV_ARCH_20 },
{ "Quadro4-700-XGL", NV_ARCH_20 }
};
static struct pci_device_id rivafb_pci_tbl[] = {
{ PCI_VENDOR_ID_NVIDIA_SGS, PCI_DEVICE_ID_NVIDIA_SGS_RIVA128,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_RIVA_128 },
{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TNT,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_RIVA_TNT },
{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TNT2,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_RIVA_TNT2 },
{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_UTNT2,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_RIVA_UTNT2 },
{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_VTNT2,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_RIVA_VTNT2 },
{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_UVTNT2,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_RIVA_VTNT2 },
{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_ITNT2,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_RIVA_ITNT2 },
{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_SDR,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE_SDR },
{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_DDR,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE_DDR },
{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_QUADRO },
{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE2_MX },
{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX2,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE2_MX2 },
{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GO,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE2_GO },
{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO2_MXR,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_QUADRO2_MXR },
{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE2_GTS },
{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS2,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE2_GTS2 },
{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_ULTRA,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE2_ULTRA },
{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO2_PRO,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_QUADRO2_PRO },
{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_460,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE4_MX_460 },
{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE4_MX_440 },
{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_420,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE4_MX_420 },
{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE4_440_GO },
{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE4_420_GO },
{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO_M32,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE4_420_GO_M32 },
{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_500XGL,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_QUADRO4_500XGL },
{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO_M64,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE4_440_GO_M64 },
{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_200,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_QUADRO4_200 },
{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_550XGL,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_QUADRO4_550XGL },
{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_500_GOGL,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_QUADRO4_500_GOGL },
{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_IGEFORCE2,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_IGEFORCE2 },
{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE3 },
{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3_1,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE3_1 },
{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3_2,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE3_2 },
{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_DDC,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_QUADRO_DDC },
{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4600,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE4_TI_4600 },
{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4400,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE4_TI_4400 },
{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4200,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE4_TI_4200 },
{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_900XGL,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_QUADRO4_900XGL },
{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_750XGL,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_QUADRO4_750XGL },
{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_700XGL,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_QUADRO4_700XGL },
{ 0, } /* terminate list */
};
MODULE_DEVICE_TABLE(pci, rivafb_pci_tbl);
/* ------------------------------------------------------------------------- *
*
* global variables
*
* ------------------------------------------------------------------------- */
/* command line data, set in rivafb_setup() */
static u32 pseudo_palette[17];
static int flatpanel __initdata = -1; /* Autodetect later */
static int forceCRTC __initdata = -1;
#ifdef CONFIG_MTRR
static int nomtrr __initdata = 0;
#endif
#ifndef MODULE
static char *mode_option __initdata = NULL;
#endif
static struct fb_fix_screeninfo rivafb_fix = {
.id = "nVidia",
.type = FB_TYPE_PACKED_PIXELS,
.xpanstep = 1,
.ypanstep = 1,
};
static struct fb_var_screeninfo rivafb_default_var = {
.xres = 640,
.yres = 480,
.xres_virtual = 640,
.yres_virtual = 480,
.bits_per_pixel = 8,
.red = {0, 8, 0},
.green = {0, 8, 0},
.blue = {0, 8, 0},
.transp = {0, 0, 0},
.activate = FB_ACTIVATE_NOW,
.height = -1,
.width = -1,
.accel_flags = FB_ACCELF_TEXT,
.pixclock = 39721,
.left_margin = 40,
.right_margin = 24,
.upper_margin = 32,
.lower_margin = 11,
.hsync_len = 96,
.vsync_len = 2,
.vmode = FB_VMODE_NONINTERLACED
};
/* from GGI */
static const struct riva_regs reg_template = {
{0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, /* ATTR */
0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F,
0x41, 0x01, 0x0F, 0x00, 0x00},
{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* CRT */
0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE3, /* 0x10 */
0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x20 */
0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x30 */
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, /* 0x40 */
},
{0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0F, /* GRA */
0xFF},
{0x03, 0x01, 0x0F, 0x00, 0x0E}, /* SEQ */
0xEB /* MISC */
};
/* ------------------------------------------------------------------------- *
*
* MMIO access macros
*
* ------------------------------------------------------------------------- */
static inline void CRTCout(struct riva_par *par, unsigned char index,
unsigned char val)
{
VGA_WR08(par->riva.PCIO, 0x3d4, index);
VGA_WR08(par->riva.PCIO, 0x3d5, val);
}
static inline unsigned char CRTCin(struct riva_par *par,
unsigned char index)
{
VGA_WR08(par->riva.PCIO, 0x3d4, index);
return (VGA_RD08(par->riva.PCIO, 0x3d5));
}
static inline void GRAout(struct riva_par *par, unsigned char index,
unsigned char val)
{
VGA_WR08(par->riva.PVIO, 0x3ce, index);
VGA_WR08(par->riva.PVIO, 0x3cf, val);
}
static inline unsigned char GRAin(struct riva_par *par,
unsigned char index)
{
VGA_WR08(par->riva.PVIO, 0x3ce, index);
return (VGA_RD08(par->riva.PVIO, 0x3cf));
}
static inline void SEQout(struct riva_par *par, unsigned char index,
unsigned char val)
{
VGA_WR08(par->riva.PVIO, 0x3c4, index);
VGA_WR08(par->riva.PVIO, 0x3c5, val);
}
static inline unsigned char SEQin(struct riva_par *par,
unsigned char index)
{
VGA_WR08(par->riva.PVIO, 0x3c4, index);
return (VGA_RD08(par->riva.PVIO, 0x3c5));
}
static inline void ATTRout(struct riva_par *par, unsigned char index,
unsigned char val)
{
VGA_WR08(par->riva.PCIO, 0x3c0, index);
VGA_WR08(par->riva.PCIO, 0x3c0, val);
}
static inline unsigned char ATTRin(struct riva_par *par,
unsigned char index)
{
VGA_WR08(par->riva.PCIO, 0x3c0, index);
return (VGA_RD08(par->riva.PCIO, 0x3c1));
}
static inline void MISCout(struct riva_par *par, unsigned char val)
{
VGA_WR08(par->riva.PVIO, 0x3c2, val);
}
static inline unsigned char MISCin(struct riva_par *par)
{
return (VGA_RD08(par->riva.PVIO, 0x3cc));
}
static u8 byte_rev[256] = {
0x00, 0x80, 0x40, 0xc0, 0x20, 0xa0, 0x60, 0xe0,
0x10, 0x90, 0x50, 0xd0, 0x30, 0xb0, 0x70, 0xf0,
0x08, 0x88, 0x48, 0xc8, 0x28, 0xa8, 0x68, 0xe8,
0x18, 0x98, 0x58, 0xd8, 0x38, 0xb8, 0x78, 0xf8,
0x04, 0x84, 0x44, 0xc4, 0x24, 0xa4, 0x64, 0xe4,
0x14, 0x94, 0x54, 0xd4, 0x34, 0xb4, 0x74, 0xf4,
0x0c, 0x8c, 0x4c, 0xcc, 0x2c, 0xac, 0x6c, 0xec,
0x1c, 0x9c, 0x5c, 0xdc, 0x3c, 0xbc, 0x7c, 0xfc,
0x02, 0x82, 0x42, 0xc2, 0x22, 0xa2, 0x62, 0xe2,
0x12, 0x92, 0x52, 0xd2, 0x32, 0xb2, 0x72, 0xf2,
0x0a, 0x8a, 0x4a, 0xca, 0x2a, 0xaa, 0x6a, 0xea,
0x1a, 0x9a, 0x5a, 0xda, 0x3a, 0xba, 0x7a, 0xfa,
0x06, 0x86, 0x46, 0xc6, 0x26, 0xa6, 0x66, 0xe6,
0x16, 0x96, 0x56, 0xd6, 0x36, 0xb6, 0x76, 0xf6,
0x0e, 0x8e, 0x4e, 0xce, 0x2e, 0xae, 0x6e, 0xee,
0x1e, 0x9e, 0x5e, 0xde, 0x3e, 0xbe, 0x7e, 0xfe,
0x01, 0x81, 0x41, 0xc1, 0x21, 0xa1, 0x61, 0xe1,
0x11, 0x91, 0x51, 0xd1, 0x31, 0xb1, 0x71, 0xf1,
0x09, 0x89, 0x49, 0xc9, 0x29, 0xa9, 0x69, 0xe9,
0x19, 0x99, 0x59, 0xd9, 0x39, 0xb9, 0x79, 0xf9,
0x05, 0x85, 0x45, 0xc5, 0x25, 0xa5, 0x65, 0xe5,
0x15, 0x95, 0x55, 0xd5, 0x35, 0xb5, 0x75, 0xf5,
0x0d, 0x8d, 0x4d, 0xcd, 0x2d, 0xad, 0x6d, 0xed,
0x1d, 0x9d, 0x5d, 0xdd, 0x3d, 0xbd, 0x7d, 0xfd,
0x03, 0x83, 0x43, 0xc3, 0x23, 0xa3, 0x63, 0xe3,
0x13, 0x93, 0x53, 0xd3, 0x33, 0xb3, 0x73, 0xf3,
0x0b, 0x8b, 0x4b, 0xcb, 0x2b, 0xab, 0x6b, 0xeb,
0x1b, 0x9b, 0x5b, 0xdb, 0x3b, 0xbb, 0x7b, 0xfb,
0x07, 0x87, 0x47, 0xc7, 0x27, 0xa7, 0x67, 0xe7,
0x17, 0x97, 0x57, 0xd7, 0x37, 0xb7, 0x77, 0xf7,
0x0f, 0x8f, 0x4f, 0xcf, 0x2f, 0xaf, 0x6f, 0xef,
0x1f, 0x9f, 0x5f, 0xdf, 0x3f, 0xbf, 0x7f, 0xff,
};
static inline void reverse_order(u32 *l)
{
u8 *a = (u8 *)l;
*a = byte_rev[*a], a++;
*a = byte_rev[*a], a++;
*a = byte_rev[*a], a++;
*a = byte_rev[*a];
}
/* ------------------------------------------------------------------------- *
*
* cursor stuff
*
* ------------------------------------------------------------------------- */
/**
* rivafb_load_cursor_image - load cursor image to hardware
* @data: address to monochrome bitmap (1 = foreground color, 0 = background)
* @par: pointer to private data
* @w: width of cursor image in pixels
* @h: height of cursor image in scanlines
* @bg: background color (ARGB1555) - alpha bit determines opacity
* @fg: foreground color (ARGB1555)
*
* DESCRIPTiON:
* Loads cursor image based on a monochrome source and mask bitmap. The
* image bits determines the color of the pixel, 0 for background, 1 for
* foreground. Only the affected region (as determined by @w and @h
* parameters) will be updated.
*
* CALLED FROM:
* rivafb_cursor()
*/
static void rivafb_load_cursor_image(struct riva_par *par, u8 *data,
u8 *mask, u16 bg, u16 fg, u32 w, u32 h)
{
int i, j, k = 0;
u32 b, m, tmp;
for (i = 0; i < h; i++) {
b = *((u32 *)data)++;
m = *((u32 *)mask)++;
reverse_order(&b);
for (j = 0; j < w/2; j++) {
tmp = 0;
#if defined (__BIG_ENDIAN)
if (m & (1 << 31)) {
fg |= 1 << 15;
bg |= 1 << 15;
}
tmp = (b & (1 << 31)) ? fg << 16 : bg << 16;
b <<= 1;
m <<= 1;
if (m & (1 << 31)) {
fg |= 1 << 15;
bg |= 1 << 15;
}
tmp |= (b & (1 << 31)) ? fg : bg;
b <<= 1;
m <<= 1;
#else
if (m & 1) {
fg |= 1 << 15;
bg |= 1 << 15;
}
tmp = (b & 1) ? fg : bg;
b >>= 1;
m >>= 1;
if (m & 1) {
fg |= 1 << 15;
bg |= 1 << 15;
}
tmp |= (b & 1) ? fg << 16 : bg << 16;
b >>= 1;
m >>= 1;
#endif
writel(tmp, par->riva.CURSOR + k++);
}
k += (MAX_CURS - w)/2;
}
}
/* ------------------------------------------------------------------------- *
*
* general utility functions
*
* ------------------------------------------------------------------------- */
/**
* riva_wclut - set CLUT entry
* @chip: pointer to RIVA_HW_INST object
* @regnum: register number
* @red: red component
* @green: green component
* @blue: blue component
*
* DESCRIPTION:
* Sets color register @regnum.
*
* CALLED FROM:
* rivafb_setcolreg()
*/
static void riva_wclut(RIVA_HW_INST *chip,
unsigned char regnum, unsigned char red,
unsigned char green, unsigned char blue)
{
VGA_WR08(chip->PDIO, 0x3c8, regnum);
VGA_WR08(chip->PDIO, 0x3c9, red);
VGA_WR08(chip->PDIO, 0x3c9, green);
VGA_WR08(chip->PDIO, 0x3c9, blue);
}
/**
* riva_rclut - read fromCLUT register
* @chip: pointer to RIVA_HW_INST object
* @regnum: register number
* @red: red component
* @green: green component
* @blue: blue component
*
* DESCRIPTION:
* Reads red, green, and blue from color register @regnum.
*
* CALLED FROM:
* rivafb_setcolreg()
*/
static void riva_rclut(RIVA_HW_INST *chip,
unsigned char regnum, unsigned char *red,
unsigned char *green, unsigned char *blue)
{
VGA_WR08(chip->PDIO, 0x3c8, regnum);
*red = VGA_RD08(chip->PDIO, 0x3c9);
*green = VGA_RD08(chip->PDIO, 0x3c9);
*blue = VGA_RD08(chip->PDIO, 0x3c9);
}
/**
* riva_save_state - saves current chip state
* @par: pointer to riva_par object containing info for current riva board
* @regs: pointer to riva_regs object
*
* DESCRIPTION:
* Saves current chip state to @regs.
*
* CALLED FROM:
* rivafb_probe()
*/
/* from GGI */
static void riva_save_state(struct riva_par *par, struct riva_regs *regs)
{
int i;
par->riva.LockUnlock(&par->riva, 0);
par->riva.UnloadStateExt(&par->riva, &regs->ext);
regs->misc_output = MISCin(par);
for (i = 0; i < NUM_CRT_REGS; i++)
regs->crtc[i] = CRTCin(par, i);
for (i = 0; i < NUM_ATC_REGS; i++)
regs->attr[i] = ATTRin(par, i);
for (i = 0; i < NUM_GRC_REGS; i++)
regs->gra[i] = GRAin(par, i);
for (i = 0; i < NUM_SEQ_REGS; i++)
regs->seq[i] = SEQin(par, i);
}
/**
* riva_load_state - loads current chip state
* @par: pointer to riva_par object containing info for current riva board
* @regs: pointer to riva_regs object
*
* DESCRIPTION:
* Loads chip state from @regs.
*
* CALLED FROM:
* riva_load_video_mode()
* rivafb_probe()
* rivafb_remove()
*/
/* from GGI */
static void riva_load_state(struct riva_par *par, struct riva_regs *regs)
{
RIVA_HW_STATE *state = &regs->ext;
int i;
CRTCout(par, 0x11, 0x00);
par->riva.LockUnlock(&par->riva, 0);
par->riva.LoadStateExt(&par->riva, state);
MISCout(par, regs->misc_output);
for (i = 0; i < NUM_CRT_REGS; i++) {
switch (i) {
case 0x19:
case 0x20 ... 0x40:
break;
default:
CRTCout(par, i, regs->crtc[i]);
}
}
for (i = 0; i < NUM_ATC_REGS; i++)
ATTRout(par, i, regs->attr[i]);
for (i = 0; i < NUM_GRC_REGS; i++)
GRAout(par, i, regs->gra[i]);
for (i = 0; i < NUM_SEQ_REGS; i++)
SEQout(par, i, regs->seq[i]);
}
/**
* riva_load_video_mode - calculate timings
* @info: pointer to fb_info object containing info for current riva board
*
* DESCRIPTION:
* Calculate some timings and then send em off to riva_load_state().
*
* CALLED FROM:
* rivafb_set_par()
*/
static void riva_load_video_mode(struct fb_info *info)
{
int bpp, width, hDisplaySize, hDisplay, hStart,
hEnd, hTotal, height, vDisplay, vStart, vEnd, vTotal, dotClock;
int hBlankStart, hBlankEnd, vBlankStart, vBlankEnd;
struct riva_par *par = (struct riva_par *) info->par;
struct riva_regs newmode;
/* time to calculate */
rivafb_blank(1, info);
bpp = info->var.bits_per_pixel;
if (bpp == 16 && info->var.green.length == 5)
bpp = 15;
width = info->var.xres_virtual;
hDisplaySize = info->var.xres;
hDisplay = (hDisplaySize / 8) - 1;
hStart = (hDisplaySize + info->var.right_margin) / 8 - 1;
hEnd = (hDisplaySize + info->var.right_margin +
info->var.hsync_len) / 8 - 1;
hTotal = (hDisplaySize + info->var.right_margin +
info->var.hsync_len + info->var.left_margin) / 8 - 5;
hBlankStart = hDisplay;
hBlankEnd = hTotal + 4;
height = info->var.yres_virtual;
vDisplay = info->var.yres - 1;
vStart = info->var.yres + info->var.lower_margin - 1;
vEnd = info->var.yres + info->var.lower_margin +
info->var.vsync_len - 1;
vTotal = info->var.yres + info->var.lower_margin +
info->var.vsync_len + info->var.upper_margin + 2;
vBlankStart = vDisplay;
vBlankEnd = vTotal + 1;
dotClock = 1000000000 / info->var.pixclock;
memcpy(&newmode, &reg_template, sizeof(struct riva_regs));
if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED)
vTotal |= 1;
if (par->FlatPanel) {
vStart = vTotal - 3;
vEnd = vTotal - 2;
vBlankStart = vStart;
hStart = hTotal - 3;
hEnd = hTotal - 2;
hBlankEnd = hTotal + 4;
}
newmode.crtc[0x0] = Set8Bits (hTotal);
newmode.crtc[0x1] = Set8Bits (hDisplay);
newmode.crtc[0x2] = Set8Bits (hBlankStart);
newmode.crtc[0x3] = SetBitField (hBlankEnd, 4: 0, 4:0) | SetBit (7);
newmode.crtc[0x4] = Set8Bits (hStart);
newmode.crtc[0x5] = SetBitField (hBlankEnd, 5: 5, 7:7)
| SetBitField (hEnd, 4: 0, 4:0);
newmode.crtc[0x6] = SetBitField (vTotal, 7: 0, 7:0);
newmode.crtc[0x7] = SetBitField (vTotal, 8: 8, 0:0)
| SetBitField (vDisplay, 8: 8, 1:1)
| SetBitField (vStart, 8: 8, 2:2)
| SetBitField (vBlankStart, 8: 8, 3:3)
| SetBit (4)
| SetBitField (vTotal, 9: 9, 5:5)
| SetBitField (vDisplay, 9: 9, 6:6)
| SetBitField (vStart, 9: 9, 7:7);
newmode.crtc[0x9] = SetBitField (vBlankStart, 9: 9, 5:5)
| SetBit (6);
newmode.crtc[0x10] = Set8Bits (vStart);
newmode.crtc[0x11] = SetBitField (vEnd, 3: 0, 3:0)
| SetBit (5);
newmode.crtc[0x12] = Set8Bits (vDisplay);
newmode.crtc[0x13] = (width / 8) * ((bpp + 1) / 8);
newmode.crtc[0x15] = Set8Bits (vBlankStart);
newmode.crtc[0x16] = Set8Bits (vBlankEnd);
newmode.ext.screen = SetBitField(hBlankEnd,6:6,4:4)
| SetBitField(vBlankStart,10:10,3:3)
| SetBitField(vStart,10:10,2:2)
| SetBitField(vDisplay,10:10,1:1)
| SetBitField(vTotal,10:10,0:0);
newmode.ext.horiz = SetBitField(hTotal,8:8,0:0)
| SetBitField(hDisplay,8:8,1:1)
| SetBitField(hBlankStart,8:8,2:2)
| SetBitField(hStart,8:8,3:3);
newmode.ext.extra = SetBitField(vTotal,11:11,0:0)
| SetBitField(vDisplay,11:11,2:2)
| SetBitField(vStart,11:11,4:4)
| SetBitField(vBlankStart,11:11,6:6);
if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) {
int tmp = (hTotal >> 1) & ~1;
newmode.ext.interlace = Set8Bits(tmp);
newmode.ext.horiz |= SetBitField(tmp, 8:8,4:4);
} else
newmode.ext.interlace = 0xff; /* interlace off */
if (par->riva.Architecture >= NV_ARCH_10)
par->riva.CURSOR = (U032 *)(info->screen_base + par->riva.CursorStart);
if (info->var.sync & FB_SYNC_HOR_HIGH_ACT)
newmode.misc_output &= ~0x40;
else
newmode.misc_output |= 0x40;
if (info->var.sync & FB_SYNC_VERT_HIGH_ACT)
newmode.misc_output &= ~0x80;
else
newmode.misc_output |= 0x80;
par->riva.CalcStateExt(&par->riva, &newmode.ext, bpp, width,
hDisplaySize, height, dotClock);
newmode.ext.scale = par->riva.PRAMDAC[0x00000848/4] & 0xfff000ff;
if (par->FlatPanel == 1) {
newmode.ext.pixel |= (1 << 7);
newmode.ext.scale |= (1 << 8);
}
if (par->SecondCRTC) {
newmode.ext.head = par->riva.PCRTC0[0x00000860/4] & ~0x00001000;
newmode.ext.head2 = par->riva.PCRTC0[0x00002860/4] | 0x00001000;
newmode.ext.crtcOwner = 3;
newmode.ext.pllsel |= 0x20000800;
newmode.ext.vpll2 = newmode.ext.vpll;
} else if (par->riva.twoHeads) {
newmode.ext.head = par->riva.PCRTC0[0x00000860/4] | 0x00001000;
newmode.ext.head2 = par->riva.PCRTC0[0x00002860/4] & ~0x00001000;
newmode.ext.crtcOwner = 0;
newmode.ext.vpll2 = par->riva.PRAMDAC0[0x00000520/4];
}
if (par->FlatPanel == 1) {
newmode.ext.pixel |= (1 << 7);
newmode.ext.scale |= (1 << 8);
}
newmode.ext.cursorConfig = 0x02000100;
par->current_state = newmode;
riva_load_state(par, &par->current_state);
par->riva.LockUnlock(&par->riva, 0); /* important for HW cursor */
rivafb_blank(0, info);
}
/**
* rivafb_do_maximize -
* @info: pointer to fb_info object containing info for current riva board
* @var:
* @nom:
* @den:
*
* DESCRIPTION:
* .
*
* RETURNS:
* -EINVAL on failure, 0 on success
*
*
* CALLED FROM:
* rivafb_check_var()
*/
static int rivafb_do_maximize(struct fb_info *info,
struct fb_var_screeninfo *var,
int nom, int den)
{
static struct {
int xres, yres;
} modes[] = {
{1600, 1280},
{1280, 1024},
{1024, 768},
{800, 600},
{640, 480},
{-1, -1}
};
int i;
/* use highest possible virtual resolution */
if (var->xres_virtual == -1 && var->yres_virtual == -1) {
printk(KERN_WARNING PFX
"using maximum available virtual resolution\n");
for (i = 0; modes[i].xres != -1; i++) {
if (modes[i].xres * nom / den * modes[i].yres <
info->fix.smem_len / 2)
break;
}
if (modes[i].xres == -1) {
printk(KERN_ERR PFX
"could not find a virtual resolution that fits into video memory!!\n");
DPRINTK("EXIT - EINVAL error\n");
return -EINVAL;
}
var->xres_virtual = modes[i].xres;
var->yres_virtual = modes[i].yres;
printk(KERN_INFO PFX
"virtual resolution set to maximum of %dx%d\n",
var->xres_virtual, var->yres_virtual);
} else if (var->xres_virtual == -1) {
var->xres_virtual = (info->fix.smem_len * den /
(nom * var->yres_virtual * 2)) & ~15;
printk(KERN_WARNING PFX
"setting virtual X resolution to %d\n", var->xres_virtual);
} else if (var->yres_virtual == -1) {
var->xres_virtual = (var->xres_virtual + 15) & ~15;
var->yres_virtual = info->fix.smem_len * den /
(nom * var->xres_virtual * 2);
printk(KERN_WARNING PFX
"setting virtual Y resolution to %d\n", var->yres_virtual);
} else {
var->xres_virtual = (var->xres_virtual + 15) & ~15;
if (var->xres_virtual * nom / den * var->yres_virtual > info->fix.smem_len) {
printk(KERN_ERR PFX
"mode %dx%dx%d rejected...resolution too high to fit into video memory!\n",
var->xres, var->yres, var->bits_per_pixel);
DPRINTK("EXIT - EINVAL error\n");
return -EINVAL;
}
}
if (var->xres_virtual * nom / den >= 8192) {
printk(KERN_WARNING PFX
"virtual X resolution (%d) is too high, lowering to %d\n",
var->xres_virtual, 8192 * den / nom - 16);
var->xres_virtual = 8192 * den / nom - 16;
}
if (var->xres_virtual < var->xres) {
printk(KERN_ERR PFX
"virtual X resolution (%d) is smaller than real\n", var->xres_virtual);
return -EINVAL;
}
if (var->yres_virtual < var->yres) {
printk(KERN_ERR PFX
"virtual Y resolution (%d) is smaller than real\n", var->yres_virtual);
return -EINVAL;
}
return 0;
}
/* acceleration routines */
inline void wait_for_idle(struct riva_par *par)
{
while (par->riva.Busy(&par->riva));
}
/* set copy ROP, no mask */
static void riva_setup_ROP(struct riva_par *par)
{
RIVA_FIFO_FREE(par->riva, Patt, 5);
par->riva.Patt->Shape = 0;
par->riva.Patt->Color0 = 0xffffffff;
par->riva.Patt->Color1 = 0xffffffff;
par->riva.Patt->Monochrome[0] = 0xffffffff;
par->riva.Patt->Monochrome[1] = 0xffffffff;
RIVA_FIFO_FREE(par->riva, Rop, 1);
par->riva.Rop->Rop3 = 0xCC;
}
void riva_setup_accel(struct riva_par *par)
{
RIVA_FIFO_FREE(par->riva, Clip, 2);
par->riva.Clip->TopLeft = 0x0;
par->riva.Clip->WidthHeight = 0x80008000;
riva_setup_ROP(par);
wait_for_idle(par);
}
/**
* riva_get_cmap_len - query current color map length
* @var: standard kernel fb changeable data
*
* DESCRIPTION:
* Get current color map length.
*
* RETURNS:
* Length of color map
*
* CALLED FROM:
* rivafb_setcolreg()
*/
static int riva_get_cmap_len(const struct fb_var_screeninfo *var)
{
int rc = 256; /* reasonable default */
switch (var->green.length) {
case 8:
rc = 256; /* 256 entries (2^8), 8 bpp and RGB8888 */
break;
case 5:
rc = 32; /* 32 entries (2^5), 16 bpp, RGB555 */
break;
case 6:
rc = 64; /* 64 entries (2^6), 16 bpp, RGB565 */
break;
default:
/* should not occur */
break;
}
return rc;
}
/* ------------------------------------------------------------------------- *
*
* framebuffer operations
*
* ------------------------------------------------------------------------- */
static int rivafb_open(struct fb_info *info, int user)
{
struct riva_par *par = (struct riva_par *) info->par;
int cnt = atomic_read(&par->ref_count);
if (!cnt) {
memset(&par->state, 0, sizeof(struct vgastate));
par->state.flags = VGA_SAVE_MODE | VGA_SAVE_FONTS;
/* save the DAC for Riva128 */
if (par->riva.Architecture == NV_ARCH_03)
par->state.flags |= VGA_SAVE_CMAP;
save_vga(&par->state);
RivaGetConfig(&par->riva, par->Chipset);
/* vgaHWunlock() + riva unlock (0x7F) */
CRTCout(par, 0x11, 0xFF);
par->riva.LockUnlock(&par->riva, 0);
riva_save_state(par, &par->initial_state);
}
atomic_inc(&par->ref_count);
return 0;
}
static int rivafb_release(struct fb_info *info, int user)
{
struct riva_par *par = (struct riva_par *) info->par;
int cnt = atomic_read(&par->ref_count);
if (!cnt)
return -EINVAL;
if (cnt == 1) {
par->riva.LockUnlock(&par->riva, 0);
par->riva.LoadStateExt(&par->riva, &par->initial_state.ext);
riva_load_state(par, &par->initial_state);
restore_vga(&par->state);
par->riva.LockUnlock(&par->riva, 1);
}
atomic_dec(&par->ref_count);
return 0;
}
static int rivafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
{
int nom, den; /* translating from pixels->bytes */
switch (var->bits_per_pixel) {
case 1 ... 8:
var->red.offset = var->green.offset = var->blue.offset = 0;
var->red.length = var->green.length = var->blue.length = 8;
var->bits_per_pixel = 8;
nom = den = 1;
break;
case 9 ... 15:
var->green.length = 5;
/* fall through */
case 16:
var->bits_per_pixel = 16;
if (var->green.length == 5) {
/* 0rrrrrgg gggbbbbb */
var->red.offset = 10;
var->green.offset = 5;
var->blue.offset = 0;
var->red.length = 5;
var->green.length = 5;
var->blue.length = 5;
} else {
/* rrrrrggg gggbbbbb */
var->red.offset = 11;
var->green.offset = 5;
var->blue.offset = 0;
var->red.length = 5;
var->green.length = 6;
var->blue.length = 5;
}
nom = 2;
den = 1;
break;
case 17 ... 32:
var->red.length = var->green.length = var->blue.length = 8;
var->bits_per_pixel = 32;
var->red.offset = 16;
var->green.offset = 8;
var->blue.offset = 0;
nom = 4;
den = 1;
break;
default:
printk(KERN_ERR PFX
"mode %dx%dx%d rejected...color depth not supported.\n",
var->xres, var->yres, var->bits_per_pixel);
DPRINTK("EXIT, returning -EINVAL\n");
return -EINVAL;
}
if (rivafb_do_maximize(info, var, nom, den) < 0)
return -EINVAL;
if (var->xoffset < 0)
var->xoffset = 0;
if (var->yoffset < 0)
var->yoffset = 0;
/* truncate xoffset and yoffset to maximum if too high */
if (var->xoffset > var->xres_virtual - var->xres)
var->xoffset = var->xres_virtual - var->xres - 1;
if (var->yoffset > var->yres_virtual - var->yres)
var->yoffset = var->yres_virtual - var->yres - 1;
var->red.msb_right =
var->green.msb_right =
var->blue.msb_right =
var->transp.offset = var->transp.length = var->transp.msb_right = 0;
return 0;
}
static int rivafb_set_par(struct fb_info *info)
{
struct riva_par *par = (struct riva_par *) info->par;
riva_load_video_mode(info);
riva_setup_accel(par);
info->fix.line_length = (info->var.xres_virtual * (info->var.bits_per_pixel >> 3));
info->fix.visual = (info->var.bits_per_pixel == 8) ?
FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
return 0;
}
/**
* rivafb_pan_display
* @var: standard kernel fb changeable data
* @con: TODO
* @info: pointer to fb_info object containing info for current riva board
*
* DESCRIPTION:
* Pan (or wrap, depending on the `vmode' field) the display using the
* `xoffset' and `yoffset' fields of the `var' structure.
* If the values don't fit, return -EINVAL.
*
* This call looks only at xoffset, yoffset and the FB_VMODE_YWRAP flag
*/
static int rivafb_pan_display(struct fb_var_screeninfo *var,
struct fb_info *info)
{
struct riva_par *par = (struct riva_par *)info->par;
unsigned int base;
if (var->xoffset > (var->xres_virtual - var->xres))
return -EINVAL;
if (var->yoffset > (var->yres_virtual - var->yres))
return -EINVAL;
if (var->vmode & FB_VMODE_YWRAP) {
if (var->yoffset < 0
|| var->yoffset >= info->var.yres_virtual
|| var->xoffset) return -EINVAL;
} else {
if (var->xoffset + info->var.xres > info->var.xres_virtual ||
var->yoffset + info->var.yres > info->var.yres_virtual)
return -EINVAL;
}
base = var->yoffset * info->fix.line_length + var->xoffset;
par->riva.SetStartAddress(&par->riva, base);
info->var.xoffset = var->xoffset;
info->var.yoffset = var->yoffset;
if (var->vmode & FB_VMODE_YWRAP)
info->var.vmode |= FB_VMODE_YWRAP;
else
info->var.vmode &= ~FB_VMODE_YWRAP;
return 0;
}
static int rivafb_blank(int blank, struct fb_info *info)
{
struct riva_par *par= (struct riva_par *)info->par;
unsigned char tmp, vesa;
tmp = SEQin(par, 0x01) & ~0x20; /* screen on/off */
vesa = CRTCin(par, 0x1a) & ~0xc0; /* sync on/off */
if (blank) {
tmp |= 0x20;
switch (blank - 1) {
case VESA_NO_BLANKING:
break;
case VESA_VSYNC_SUSPEND:
vesa |= 0x80;
break;
case VESA_HSYNC_SUSPEND:
vesa |= 0x40;
break;
case VESA_POWERDOWN:
vesa |= 0xc0;
break;
}
}
SEQout(par, 0x01, tmp);
CRTCout(par, 0x1a, vesa);
return 0;
}
/**
* rivafb_setcolreg
* @regno: register index
* @red: red component
* @green: green component
* @blue: blue component
* @transp: transparency
* @info: pointer to fb_info object containing info for current riva board
*
* DESCRIPTION:
* Set a single color register. The values supplied have a 16 bit
* magnitude.
*
* RETURNS:
* Return != 0 for invalid regno.
*
* CALLED FROM:
* fbcmap.c:fb_set_cmap()
*/
static int rivafb_setcolreg(unsigned regno, unsigned red, unsigned green,
unsigned blue, unsigned transp,
struct fb_info *info)
{
struct riva_par *par = (struct riva_par *)info->par;
RIVA_HW_INST *chip = &par->riva;
int i;
if (regno >= riva_get_cmap_len(&info->var))
return -EINVAL;
if (info->var.grayscale) {
/* gray = 0.30*R + 0.59*G + 0.11*B */
red = green = blue =
(red * 77 + green * 151 + blue * 28) >> 8;
}
switch (info->var.bits_per_pixel) {
case 8:
/* "transparent" stuff is completely ignored. */
riva_wclut(chip, regno, red >> 8, green >> 8, blue >> 8);
break;
case 16:
if (info->var.green.length == 5) {
if (regno < 16) {
/* 0rrrrrgg gggbbbbb */
((u32 *)info->pseudo_palette)[regno] =
((red & 0xf800) >> 1) |
((green & 0xf800) >> 6) |
((blue & 0xf800) >> 11);
}
for (i = 0; i < 8; i++)
riva_wclut(chip, regno*8+i, red >> 8,
green >> 8, blue >> 8);
} else {
u8 r, g, b;
if (regno < 16) {
/* rrrrrggg gggbbbbb */
((u32 *)info->pseudo_palette)[regno] =
((red & 0xf800) >> 0) |
((green & 0xf800) >> 5) |
((blue & 0xf800) >> 11);
}
if (regno < 32) {
for (i = 0; i < 8; i++) {
riva_wclut(chip, regno*8+i, red >> 8,
green >> 8, blue >> 8);
}
}
for (i = 0; i < 4; i++) {
riva_rclut(chip, regno*2+i, &r, &g, &b);
riva_wclut(chip, regno*4+i, r, green >> 8, b);
}
}
break;
case 32:
if (regno < 16) {
((u32 *)info->pseudo_palette)[regno] =
((red & 0xff00) << 8) |
((green & 0xff00)) | ((blue & 0xff00) >> 8);
}
riva_wclut(chip, regno, red >> 8, green >> 8, blue >> 8);
break;
default:
/* do nothing */
break;
}
return 0;
}
/**
* rivafb_fillrect - hardware accelerated color fill function
* @info: pointer to fb_info structure
* @rect: pointer to fb_fillrect structure
*
* DESCRIPTION:
* This function fills up a region of framebuffer memory with a solid
* color with a choice of two different ROP's, copy or invert.
*
* CALLED FROM:
* framebuffer hook
*/
static void rivafb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
{
struct riva_par *par = (struct riva_par *) info->par;
u_int color, rop = 0;
if (info->var.bits_per_pixel == 8)
color = rect->color;
else
color = ((u32 *)info->pseudo_palette)[rect->color];
switch (rect->rop) {
case ROP_XOR:
rop = 0x66;
break;
case ROP_COPY:
default:
rop = 0xCC;
break;
}
RIVA_FIFO_FREE(par->riva, Rop, 1);
par->riva.Rop->Rop3 = rop;
RIVA_FIFO_FREE(par->riva, Bitmap, 1);
par->riva.Bitmap->Color1A = color;
RIVA_FIFO_FREE(par->riva, Bitmap, 2);
par->riva.Bitmap->UnclippedRectangle[0].TopLeft =
(rect->dx << 16) | rect->dy;
par->riva.Bitmap->UnclippedRectangle[0].WidthHeight =
(rect->width << 16) | rect->height;
RIVA_FIFO_FREE(par->riva, Rop, 1);
par->riva.Rop->Rop3 = 0xCC; // back to COPY
}
/**
* rivafb_copyarea - hardware accelerated blit function
* @info: pointer to fb_info structure
* @region: pointer to fb_copyarea structure
*
* DESCRIPTION:
* This copies an area of pixels from one location to another
*
* CALLED FROM:
* framebuffer hook
*/
static void rivafb_copyarea(struct fb_info *info, const struct fb_copyarea *region)
{
struct riva_par *par = (struct riva_par *) info->par;
RIVA_FIFO_FREE(par->riva, Blt, 3);
par->riva.Blt->TopLeftSrc = (region->sy << 16) | region->sx;
par->riva.Blt->TopLeftDst = (region->dy << 16) | region->dx;
par->riva.Blt->WidthHeight = (region->height << 16) | region->width;
wait_for_idle(par);
}
static inline void convert_bgcolor_16(u32 *col)
{
*col = ((*col & 0x00007C00) << 9)
| ((*col & 0x000003E0) << 6)
| ((*col & 0x0000001F) << 3)
| 0xFF000000;
}
/**
* rivafb_imageblit: hardware accelerated color expand function
* @info: pointer to fb_info structure
* @image: pointer to fb_image structure
*
* DESCRIPTION:
* If the source is a monochrome bitmap, the function fills up a a region
* of framebuffer memory with pixels whose color is determined by the bit
* setting of the bitmap, 1 - foreground, 0 - background.
*
* If the source is not a monochrome bitmap, color expansion is not done.
* In this case, it is channeled to a software function.
*
* CALLED FROM:
* framebuffer hook
*/
static void rivafb_imageblit(struct fb_info *info,
const struct fb_image *image)
{
struct riva_par *par = (struct riva_par *) info->par;
u32 fgx = 0, bgx = 0, width, tmp;
u8 *cdat = (u8 *) image->data;
volatile u32 *d;
int i, size;
if (image->depth != 1) {
cfb_imageblit(info, image);
return;
}
switch (info->var.bits_per_pixel) {
case 8:
fgx = image->fg_color;
bgx = image->bg_color;
break;
case 16:
fgx = ((u32 *)info->pseudo_palette)[image->fg_color];
bgx = ((u32 *)info->pseudo_palette)[image->bg_color];
if (info->var.green.length == 6)
convert_bgcolor_16(&bgx);
break;
case 32:
fgx = ((u32 *)info->pseudo_palette)[image->fg_color];
bgx = ((u32 *)info->pseudo_palette)[image->bg_color];
break;
}
RIVA_FIFO_FREE(par->riva, Bitmap, 7);
par->riva.Bitmap->ClipE.TopLeft =
(image->dy << 16) | (image->dx & 0xFFFF);
par->riva.Bitmap->ClipE.BottomRight =
(((image->dy + image->height) << 16) |
((image->dx + image->width) & 0xffff));
par->riva.Bitmap->Color0E = bgx;
par->riva.Bitmap->Color1E = fgx;
par->riva.Bitmap->WidthHeightInE =
(image->height << 16) | ((image->width + 31) & ~31);
par->riva.Bitmap->WidthHeightOutE =
(image->height << 16) | ((image->width + 31) & ~31);
par->riva.Bitmap->PointE =
(image->dy << 16) | (image->dx & 0xFFFF);
d = &par->riva.Bitmap->MonochromeData01E;
width = (image->width + 31)/32;
size = width * image->height;
while (size >= 16) {
RIVA_FIFO_FREE(par->riva, Bitmap, 16);
for (i = 0; i < 16; i++) {
tmp = *((u32 *)cdat)++;
reverse_order(&tmp);
d[i] = tmp;
}
size -= 16;
}
if (size) {
RIVA_FIFO_FREE(par->riva, Bitmap, size);
for (i = 0; i < size; i++) {
tmp = *((u32 *) cdat)++;
reverse_order(&tmp);
d[i] = tmp;
}
}
}
/**
* rivafb_cursor - hardware cursor function
* @info: pointer to info structure
* @cursor: pointer to fbcursor structure
*
* DESCRIPTION:
* A cursor function that supports displaying a cursor image via hardware.
* Within the kernel, copy and invert rops are supported. If exported
* to user space, only the copy rop will be supported.
*
* CALLED FROM
* framebuffer hook
*/
static int rivafb_cursor(struct fb_info *info, struct fb_cursor *cursor)
{
struct riva_par *par = (struct riva_par *) info->par;
u8 data[MAX_CURS * MAX_CURS/8];
u8 mask[MAX_CURS * MAX_CURS/8];
u16 fg, bg;
int i;
par->riva.ShowHideCursor(&par->riva, 0);
if (cursor->set & FB_CUR_SETPOS) {
u32 xx, yy, temp;
info->cursor.image.dx = cursor->image.dx;
info->cursor.image.dy = cursor->image.dy;
yy = cursor->image.dy - info->var.yoffset;
xx = cursor->image.dx - info->var.xoffset;
temp = xx & 0xFFFF;
temp |= yy << 16;
par->riva.PRAMDAC[0x0000300/4] = temp;
}
if (cursor->set & FB_CUR_SETSIZE) {
info->cursor.image.height = cursor->image.height;
info->cursor.image.width = cursor->image.width;
memset_io(par->riva.CURSOR, 0, MAX_CURS * MAX_CURS * 2);
}
if (cursor->set & FB_CUR_SETCMAP) {
info->cursor.image.bg_color = cursor->image.bg_color;
info->cursor.image.fg_color = cursor->image.fg_color;
}
if (cursor->set & (FB_CUR_SETSHAPE | FB_CUR_SETCMAP)) {
u32 bg_idx = info->cursor.image.bg_color;
u32 fg_idx = info->cursor.image.fg_color;
u32 s_pitch = (info->cursor.image.width+7) >> 3;
u32 d_pitch = MAX_CURS/8;
u8 *dat = (u8 *) cursor->image.data;
u8 *msk = (u8 *) info->cursor.mask;
u8 src[64];
switch (info->cursor.rop) {
case ROP_XOR:
for (i = 0; i < s_pitch * info->cursor.image.height; i++)
src[i] = dat[i] ^ msk[i];
break;
case ROP_COPY:
default:
for (i = 0; i < s_pitch * info->cursor.image.height; i++)
src[i] = dat[i] & msk[i];
break;
}
move_buf_aligned(info, data, src, d_pitch, s_pitch, info->cursor.image.height);
move_buf_aligned(info, mask, msk, d_pitch, s_pitch, info->cursor.image.height);
bg = ((info->cmap.red[bg_idx] & 0xf8) << 7) |
((info->cmap.green[bg_idx] & 0xf8) << 2) |
((info->cmap.blue[bg_idx] & 0xf8) >> 3);
fg = ((info->cmap.red[fg_idx] & 0xf8) << 7) |
((info->cmap.green[fg_idx] & 0xf8) << 2) |
((info->cmap.blue[fg_idx] & 0xf8) >> 3);
par->riva.LockUnlock(&par->riva, 0);
rivafb_load_cursor_image(par, data, mask, bg, fg,
info->cursor.image.width,
info->cursor.image.height);
}
if (info->cursor.enable)
par->riva.ShowHideCursor(&par->riva, 1);
return 0;
}
static int rivafb_sync(struct fb_info *info)
{
struct riva_par *par = (struct riva_par *)info->par;
wait_for_idle(par);
return 0;
}
/* ------------------------------------------------------------------------- *
*
* initialization helper functions
*
* ------------------------------------------------------------------------- */
/* kernel interface */
static struct fb_ops riva_fb_ops = {
.owner = THIS_MODULE,
.fb_open = rivafb_open,
.fb_release = rivafb_release,
.fb_check_var = rivafb_check_var,
.fb_set_par = rivafb_set_par,
.fb_setcolreg = rivafb_setcolreg,
.fb_pan_display = rivafb_pan_display,
.fb_blank = rivafb_blank,
.fb_fillrect = rivafb_fillrect,
.fb_copyarea = rivafb_copyarea,
.fb_imageblit = rivafb_imageblit,
.fb_cursor = rivafb_cursor,
.fb_sync = rivafb_sync,
};
static int __devinit riva_set_fbinfo(struct fb_info *info)
{
struct riva_par *par = (struct riva_par *) info->par;
unsigned int cmap_len;
info->flags = FBINFO_FLAG_DEFAULT;
info->var = rivafb_default_var;
info->fix = rivafb_fix;
info->fbops = &riva_fb_ops;
info->pseudo_palette = pseudo_palette;
#ifndef MODULE
if (mode_option)
fb_find_mode(&info->var, info, mode_option,
NULL, 0, NULL, 8);
#endif
if (par->use_default_var)
/* We will use the modified default var */
info->var = rivafb_default_var;
cmap_len = riva_get_cmap_len(&info->var);
fb_alloc_cmap(&info->cmap, cmap_len, 0);
info->pixmap.size = 64 * 1024;
info->pixmap.buf_align = 4;
info->pixmap.scan_align = 4;
info->pixmap.flags = FB_PIXMAP_SYSTEM;
return 0;
}
#ifdef CONFIG_PPC_OF
static int riva_get_EDID_OF(struct riva_par *par, struct pci_dev *pd)
{
struct device_node *dp;
unsigned char *pedid = NULL;
dp = pci_device_to_OF_node(pd);
pedid = (unsigned char *)get_property(dp, "EDID,B", 0);
if (pedid) {
par->EDID = pedid;
return 1;
} else
return 0;
}
#endif /* CONFIG_PPC_OF */
static int riva_dfp_parse_EDID(struct riva_par *par)
{
unsigned char *block = par->EDID;
if (!block)
return 0;
/* jump to detailed timing block section */
block += 54;
par->clock = (block[0] + (block[1] << 8));
par->panel_xres = (block[2] + ((block[4] & 0xf0) << 4));
par->hblank = (block[3] + ((block[4] & 0x0f) << 8));
par->panel_yres = (block[5] + ((block[7] & 0xf0) << 4));
par->vblank = (block[6] + ((block[7] & 0x0f) << 8));
par->hOver_plus = (block[8] + ((block[11] & 0xc0) << 2));
par->hSync_width = (block[9] + ((block[11] & 0x30) << 4));
par->vOver_plus = ((block[10] >> 4) + ((block[11] & 0x0c) << 2));
par->vSync_width = ((block[10] & 0x0f) + ((block[11] & 0x03) << 4));
par->interlaced = ((block[17] & 0x80) >> 7);
par->synct = ((block[17] & 0x18) >> 3);
par->misc = ((block[17] & 0x06) >> 1);
par->hAct_high = par->vAct_high = 0;
if (par->synct == 3) {
if (par->misc & 2)
par->hAct_high = 1;
if (par->misc & 1)
par->vAct_high = 1;
}
printk(KERN_INFO PFX
"detected DFP panel size from EDID: %dx%d\n",
par->panel_xres, par->panel_yres);
par->got_dfpinfo = 1;
return 1;
}
static void riva_update_default_var(struct fb_info *info)
{
struct fb_var_screeninfo *var = &rivafb_default_var;
struct riva_par *par = (struct riva_par *) info->par;
var->xres = par->panel_xres;
var->yres = par->panel_yres;
var->xres_virtual = par->panel_xres;
var->yres_virtual = par->panel_yres;
var->xoffset = var->yoffset = 0;
var->bits_per_pixel = 8;
var->pixclock = 100000000 / par->clock;
var->left_margin = (par->hblank - par->hOver_plus - par->hSync_width);
var->right_margin = par->hOver_plus;
var->upper_margin = (par->vblank - par->vOver_plus - par->vSync_width);
var->lower_margin = par->vOver_plus;
var->hsync_len = par->hSync_width;
var->vsync_len = par->vSync_width;
var->sync = 0;
if (par->synct == 3) {
if (par->hAct_high)
var->sync |= FB_SYNC_HOR_HIGH_ACT;
if (par->vAct_high)
var->sync |= FB_SYNC_VERT_HIGH_ACT;
}
var->vmode = 0;
if (par->interlaced)
var->vmode |= FB_VMODE_INTERLACED;
var->accel_flags |= FB_ACCELF_TEXT;
par->use_default_var = 1;
}
static void riva_get_EDID(struct fb_info *info, struct pci_dev *pdev)
{
#ifdef CONFIG_PPC_OF
if (!riva_get_EDID_OF(info, pdev))
printk("rivafb: could not retrieve EDID from OF\n");
#else
/* XXX use other methods later */
#endif
}
static void riva_get_dfpinfo(struct fb_info *info)
{
struct riva_par *par = (struct riva_par *) info->par;
if (riva_dfp_parse_EDID(par))
riva_update_default_var(info);
/* if user specified flatpanel, we respect that */
if (par->got_dfpinfo == 1)
par->FlatPanel = 1;
}
/* ------------------------------------------------------------------------- *
*
* PCI bus
*
* ------------------------------------------------------------------------- */
static int __devinit rivafb_probe(struct pci_dev *pd,
const struct pci_device_id *ent)
{
struct riva_chip_info *rci = &riva_chip_info[ent->driver_data];
struct riva_par *default_par;
struct fb_info *info;
assert(pd != NULL);
assert(rci != NULL);
info = kmalloc(sizeof(struct fb_info), GFP_KERNEL);
if (!info)
goto err_out;
default_par = kmalloc(sizeof(struct riva_par), GFP_KERNEL);
if (!default_par)
goto err_out_kfree;
memset(info, 0, sizeof(struct fb_info));
memset(default_par, 0, sizeof(struct riva_par));
info->pixmap.addr = kmalloc(64 * 1024, GFP_KERNEL);
if (info->pixmap.addr == NULL)
goto err_out_kfree1;
memset(info->pixmap.addr, 0, 64 * 1024);
strcat(rivafb_fix.id, rci->name);
default_par->riva.Architecture = rci->arch_rev;
default_par->Chipset = (pd->vendor << 16) | pd->device;
printk(KERN_INFO PFX "nVidia device/chipset %X\n",default_par->Chipset);
default_par->FlatPanel = flatpanel;
if (flatpanel == 1)
printk(KERN_INFO PFX "flatpanel support enabled\n");
default_par->forceCRTC = forceCRTC;
rivafb_fix.mmio_len = pci_resource_len(pd, 0);
rivafb_fix.smem_len = pci_resource_len(pd, 1);
{
/* enable IO and mem if not already done */
unsigned short cmd;
pci_read_config_word(pd, PCI_COMMAND, &cmd);
cmd |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
pci_write_config_word(pd, PCI_COMMAND, cmd);
}
rivafb_fix.mmio_start = pci_resource_start(pd, 0);
rivafb_fix.smem_start = pci_resource_start(pd, 1);
if (!request_mem_region(rivafb_fix.mmio_start,
rivafb_fix.mmio_len, "rivafb")) {
printk(KERN_ERR PFX "cannot reserve MMIO region\n");
goto err_out_kfree2;
}
default_par->ctrl_base = ioremap(rivafb_fix.mmio_start,
rivafb_fix.mmio_len);
if (!default_par->ctrl_base) {
printk(KERN_ERR PFX "cannot ioremap MMIO base\n");
goto err_out_free_base0;
}
info->par = default_par;
riva_get_EDID(info, pd);
riva_get_dfpinfo(info);
switch (default_par->riva.Architecture) {
case NV_ARCH_03:
/* Riva128's PRAMIN is in the "framebuffer" space
* Since these cards were never made with more than 8 megabytes
* we can safely allocate this separately.
*/
if (!request_mem_region(rivafb_fix.smem_start + 0x00C00000,
0x00008000, "rivafb")) {
printk(KERN_ERR PFX "cannot reserve PRAMIN region\n");
goto err_out_iounmap_ctrl;
}
default_par->riva.PRAMIN = ioremap(rivafb_fix.smem_start + 0x00C00000, 0x00008000);
if (!default_par->riva.PRAMIN) {
printk(KERN_ERR PFX "cannot ioremap PRAMIN region\n");
goto err_out_free_nv3_pramin;
}
rivafb_fix.accel = FB_ACCEL_NV3;
break;
case NV_ARCH_04:
case NV_ARCH_10:
case NV_ARCH_20:
default_par->riva.PCRTC0 = (unsigned *)(default_par->ctrl_base + 0x00600000);
default_par->riva.PRAMIN = (unsigned *)(default_par->ctrl_base + 0x00710000);
rivafb_fix.accel = FB_ACCEL_NV4;
break;
}
riva_common_setup(default_par);
if (default_par->riva.Architecture == NV_ARCH_03) {
default_par->riva.PCRTC = default_par->riva.PCRTC0 = default_par->riva.PGRAPH;
}
rivafb_fix.smem_len = riva_get_memlen(default_par) * 1024;
default_par->dclk_max = riva_get_maxdclk(default_par) * 1000;
if (!request_mem_region(rivafb_fix.smem_start,
rivafb_fix.smem_len, "rivafb")) {
printk(KERN_ERR PFX "cannot reserve FB region\n");
goto err_out_iounmap_nv3_pramin;
}
info->screen_base = ioremap(rivafb_fix.smem_start,
rivafb_fix.smem_len);
if (!info->screen_base) {
printk(KERN_ERR PFX "cannot ioremap FB base\n");
goto err_out_free_base1;
}
#ifdef CONFIG_MTRR
if (!nomtrr) {
default_par->mtrr.vram = mtrr_add(rivafb_fix.smem_start,
rivafb_fix.smem_len,
MTRR_TYPE_WRCOMB, 1);
if (default_par->mtrr.vram < 0) {
printk(KERN_ERR PFX "unable to setup MTRR\n");
} else {
default_par->mtrr.vram_valid = 1;
/* let there be speed */
printk(KERN_INFO PFX "RIVA MTRR set to ON\n");
}
}
#endif /* CONFIG_MTRR */
if (riva_set_fbinfo(info) < 0) {
printk(KERN_ERR PFX "error setting initial video mode\n");
goto err_out_iounmap_fb;
}
if (register_framebuffer(info) < 0) {
printk(KERN_ERR PFX
"error registering riva framebuffer\n");
goto err_out_iounmap_fb;
}
pci_set_drvdata(pd, info);
printk(KERN_INFO PFX
"PCI nVidia NV%x framebuffer ver %s (%s, %dMB @ 0x%lX)\n",
default_par->riva.Architecture,
RIVAFB_VERSION,
info->fix.id,
info->fix.smem_len / (1024 * 1024),
info->fix.smem_start);
return 0;
err_out_iounmap_fb:
iounmap(info->screen_base);
err_out_free_base1:
release_mem_region(rivafb_fix.smem_start, rivafb_fix.smem_len);
err_out_iounmap_nv3_pramin:
if (default_par->riva.Architecture == NV_ARCH_03)
iounmap((caddr_t)default_par->riva.PRAMIN);
err_out_free_nv3_pramin:
if (default_par->riva.Architecture == NV_ARCH_03)
release_mem_region(rivafb_fix.smem_start + 0x00C00000, 0x00008000);
err_out_iounmap_ctrl:
iounmap(default_par->ctrl_base);
err_out_free_base0:
release_mem_region(rivafb_fix.mmio_start, rivafb_fix.mmio_len);
err_out_kfree2:
kfree(info->pixmap.addr);
err_out_kfree1:
kfree(default_par);
err_out_kfree:
kfree(info);
err_out:
return -ENODEV;
}
static void __exit rivafb_remove(struct pci_dev *pd)
{
struct fb_info *info = pci_get_drvdata(pd);
struct riva_par *par = (struct riva_par *) info->par;
if (!info)
return;
unregister_framebuffer(info);
#ifdef CONFIG_MTRR
if (par->mtrr.vram_valid)
mtrr_del(par->mtrr.vram, info->fix.smem_start,
info->fix.smem_len);
#endif /* CONFIG_MTRR */
iounmap(par->ctrl_base);
iounmap(info->screen_base);
release_mem_region(info->fix.mmio_start,
info->fix.mmio_len);
release_mem_region(info->fix.smem_start,
info->fix.smem_len);
if (par->riva.Architecture == NV_ARCH_03) {
iounmap((caddr_t)par->riva.PRAMIN);
release_mem_region(info->fix.smem_start + 0x00C00000, 0x00008000);
}
kfree(info->pixmap.addr);
kfree(par);
kfree(info);
pci_set_drvdata(pd, NULL);
}
/* ------------------------------------------------------------------------- *
*
* initialization
*
* ------------------------------------------------------------------------- */
#ifndef MODULE
int __init rivafb_setup(char *options)
{
char *this_opt;
if (!options || !*options)
return 0;
while ((this_opt = strsep(&options, ",")) != NULL) {
if (!strncmp(this_opt, "forceCRTC", 9)) {
char *p;
p = this_opt + 9;
if (!*p || !*(++p)) continue;
forceCRTC = *p - '0';
if (forceCRTC < 0 || forceCRTC > 1)
forceCRTC = -1;
} else if (!strncmp(this_opt, "flatpanel", 9)) {
flatpanel = 1;
#ifdef CONFIG_MTRR
} else if (!strncmp(this_opt, "nomtrr", 6)) {
nomtrr = 1;
#endif
} else
mode_option = this_opt;
}
return 0;
}
#endif /* !MODULE */
static struct pci_driver rivafb_driver = {
.name = "rivafb",
.id_table = rivafb_pci_tbl,
.probe = rivafb_probe,
.remove = __exit_p(rivafb_remove),
};
/* ------------------------------------------------------------------------- *
*
* modularization
*
* ------------------------------------------------------------------------- */
int __init rivafb_init(void)
{
if (pci_register_driver(&rivafb_driver) > 0)
return 0;
pci_unregister_driver(&rivafb_driver);
return -ENODEV;
}
#ifdef MODULE
static void __exit rivafb_exit(void)
{
pci_unregister_driver(&rivafb_driver);
}
module_init(rivafb_init);
module_exit(rivafb_exit);
MODULE_PARM(flatpanel, "i");
MODULE_PARM_DESC(flatpanel, "Enables experimental flat panel support for some chipsets. (0 or 1=enabled) (default=0)");
MODULE_PARM(forceCRTC, "i");
MODULE_PARM_DESC(forceCRTC, "Forces usage of a particular CRTC in case autodetection fails. (0 or 1) (default=autodetect)");
#ifdef CONFIG_MTRR
MODULE_PARM(nomtrr, "i");
MODULE_PARM_DESC(nomtrr, "Disables MTRR support (0 or 1=disabled) (default=0)");
#endif
#endif /* MODULE */
MODULE_AUTHOR("Ani Joshi, maintainer");
MODULE_DESCRIPTION("Framebuffer driver for nVidia Riva 128, TNT, TNT2, and the GeForce series");
MODULE_LICENSE("GPL");

/shark/trunk/drivers/fb/riva/nvreg.h
0,0 → 1,188
/* $XConsortium: nvreg.h /main/2 1996/10/28 05:13:41 kaleb $ */
/*
* Copyright 1996-1997 David J. McKay
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* DAVID J. MCKAY BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
/* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/nv/nvreg.h,v 3.2.2.1 1998/01/18 10:35:36 hohndel Exp $ */
#ifndef __NVREG_H_
#define __NVREG_H_
/* Little macro to construct bitmask for contiguous ranges of bits */
#define BITMASK(t,b) (((unsigned)(1U << (((t)-(b)+1)))-1) << (b))
#define MASKEXPAND(mask) BITMASK(1?mask,0?mask)
/* Macro to set specific bitfields (mask has to be a macro x:y) ! */
#define SetBF(mask,value) ((value) << (0?mask))
#define GetBF(var,mask) (((unsigned)((var) & MASKEXPAND(mask))) >> (0?mask) )
#define MaskAndSetBF(var,mask,value) (var)=(((var)&(~MASKEXPAND(mask)) \
| SetBF(mask,value)))
#define DEVICE_BASE(device) (0?NV##_##device)
#define DEVICE_SIZE(device) ((1?NV##_##device) - DEVICE_BASE(device)+1)
/* This is where we will have to have conditional compilation */
#define DEVICE_ACCESS(device,reg) \
nvCONTROL[(NV_##device##_##reg)/4]
#define DEVICE_WRITE(device,reg,value) DEVICE_ACCESS(device,reg)=(value)
#define DEVICE_READ(device,reg) DEVICE_ACCESS(device,reg)
#define DEVICE_PRINT(device,reg) \
ErrorF("NV_"#device"_"#reg"=#%08lx\n",DEVICE_ACCESS(device,reg))
#define DEVICE_DEF(device,mask,value) \
SetBF(NV_##device##_##mask,NV_##device##_##mask##_##value)
#define DEVICE_VALUE(device,mask,value) SetBF(NV_##device##_##mask,value)
#define DEVICE_MASK(device,mask) MASKEXPAND(NV_##device##_##mask)
#define PDAC_Write(reg,value) DEVICE_WRITE(PDAC,reg,value)
#define PDAC_Read(reg) DEVICE_READ(PDAC,reg)
#define PDAC_Print(reg) DEVICE_PRINT(PDAC,reg)
#define PDAC_Def(mask,value) DEVICE_DEF(PDAC,mask,value)
#define PDAC_Val(mask,value) DEVICE_VALUE(PDAC,mask,value)
#define PDAC_Mask(mask) DEVICE_MASK(PDAC,mask)
#define PFB_Write(reg,value) DEVICE_WRITE(PFB,reg,value)
#define PFB_Read(reg) DEVICE_READ(PFB,reg)
#define PFB_Print(reg) DEVICE_PRINT(PFB,reg)
#define PFB_Def(mask,value) DEVICE_DEF(PFB,mask,value)
#define PFB_Val(mask,value) DEVICE_VALUE(PFB,mask,value)
#define PFB_Mask(mask) DEVICE_MASK(PFB,mask)
#define PRM_Write(reg,value) DEVICE_WRITE(PRM,reg,value)
#define PRM_Read(reg) DEVICE_READ(PRM,reg)
#define PRM_Print(reg) DEVICE_PRINT(PRM,reg)
#define PRM_Def(mask,value) DEVICE_DEF(PRM,mask,value)
#define PRM_Val(mask,value) DEVICE_VALUE(PRM,mask,value)
#define PRM_Mask(mask) DEVICE_MASK(PRM,mask)
#define PGRAPH_Write(reg,value) DEVICE_WRITE(PGRAPH,reg,value)
#define PGRAPH_Read(reg) DEVICE_READ(PGRAPH,reg)
#define PGRAPH_Print(reg) DEVICE_PRINT(PGRAPH,reg)
#define PGRAPH_Def(mask,value) DEVICE_DEF(PGRAPH,mask,value)
#define PGRAPH_Val(mask,value) DEVICE_VALUE(PGRAPH,mask,value)
#define PGRAPH_Mask(mask) DEVICE_MASK(PGRAPH,mask)
#define PDMA_Write(reg,value) DEVICE_WRITE(PDMA,reg,value)
#define PDMA_Read(reg) DEVICE_READ(PDMA,reg)
#define PDMA_Print(reg) DEVICE_PRINT(PDMA,reg)
#define PDMA_Def(mask,value) DEVICE_DEF(PDMA,mask,value)
#define PDMA_Val(mask,value) DEVICE_VALUE(PDMA,mask,value)
#define PDMA_Mask(mask) DEVICE_MASK(PDMA,mask)
#define PTIMER_Write(reg,value) DEVICE_WRITE(PTIMER,reg,value)
#define PTIMER_Read(reg) DEVICE_READ(PTIMER,reg)
#define PTIMER_Print(reg) DEVICE_PRINT(PTIMER,reg)
#define PTIMER_Def(mask,value) DEVICE_DEF(PTIMER,mask,value)
#define PTIMER_Val(mask,value) DEVICE_VALUE(PTIEMR,mask,value)
#define PTIMER_Mask(mask) DEVICE_MASK(PTIMER,mask)
#define PEXTDEV_Write(reg,value) DEVICE_WRITE(PEXTDEV,reg,value)
#define PEXTDEV_Read(reg) DEVICE_READ(PEXTDEV,reg)
#define PEXTDEV_Print(reg) DEVICE_PRINT(PEXTDEV,reg)
#define PEXTDEV_Def(mask,value) DEVICE_DEF(PEXTDEV,mask,value)
#define PEXTDEV_Val(mask,value) DEVICE_VALUE(PEXTDEV,mask,value)
#define PEXTDEV_Mask(mask) DEVICE_MASK(PEXTDEV,mask)
#define PFIFO_Write(reg,value) DEVICE_WRITE(PFIFO,reg,value)
#define PFIFO_Read(reg) DEVICE_READ(PFIFO,reg)
#define PFIFO_Print(reg) DEVICE_PRINT(PFIFO,reg)
#define PFIFO_Def(mask,value) DEVICE_DEF(PFIFO,mask,value)
#define PFIFO_Val(mask,value) DEVICE_VALUE(PFIFO,mask,value)
#define PFIFO_Mask(mask) DEVICE_MASK(PFIFO,mask)
#define PRAM_Write(reg,value) DEVICE_WRITE(PRAM,reg,value)
#define PRAM_Read(reg) DEVICE_READ(PRAM,reg)
#define PRAM_Print(reg) DEVICE_PRINT(PRAM,reg)
#define PRAM_Def(mask,value) DEVICE_DEF(PRAM,mask,value)
#define PRAM_Val(mask,value) DEVICE_VALUE(PRAM,mask,value)
#define PRAM_Mask(mask) DEVICE_MASK(PRAM,mask)
#define PRAMFC_Write(reg,value) DEVICE_WRITE(PRAMFC,reg,value)
#define PRAMFC_Read(reg) DEVICE_READ(PRAMFC,reg)
#define PRAMFC_Print(reg) DEVICE_PRINT(PRAMFC,reg)
#define PRAMFC_Def(mask,value) DEVICE_DEF(PRAMFC,mask,value)
#define PRAMFC_Val(mask,value) DEVICE_VALUE(PRAMFC,mask,value)
#define PRAMFC_Mask(mask) DEVICE_MASK(PRAMFC,mask)
#define PMC_Write(reg,value) DEVICE_WRITE(PMC,reg,value)
#define PMC_Read(reg) DEVICE_READ(PMC,reg)
#define PMC_Print(reg) DEVICE_PRINT(PMC,reg)
#define PMC_Def(mask,value) DEVICE_DEF(PMC,mask,value)
#define PMC_Val(mask,value) DEVICE_VALUE(PMC,mask,value)
#define PMC_Mask(mask) DEVICE_MASK(PMC,mask)
#define PMC_Write(reg,value) DEVICE_WRITE(PMC,reg,value)
#define PMC_Read(reg) DEVICE_READ(PMC,reg)
#define PMC_Print(reg) DEVICE_PRINT(PMC,reg)
#define PMC_Def(mask,value) DEVICE_DEF(PMC,mask,value)
#define PMC_Val(mask,value) DEVICE_VALUE(PMC,mask,value)
#define PMC_Mask(mask) DEVICE_MASK(PMC,mask)
#define PBUS_Write(reg,value) DEVICE_WRITE(PBUS,reg,value)
#define PBUS_Read(reg) DEVICE_READ(PBUS,reg)
#define PBUS_Print(reg) DEVICE_PRINT(PBUS,reg)
#define PBUS_Def(mask,value) DEVICE_DEF(PBUS,mask,value)
#define PBUS_Val(mask,value) DEVICE_VALUE(PBUS,mask,value)
#define PBUS_Mask(mask) DEVICE_MASK(PBUS,mask)
#define PRAMDAC_Write(reg,value) DEVICE_WRITE(PRAMDAC,reg,value)
#define PRAMDAC_Read(reg) DEVICE_READ(PRAMDAC,reg)
#define PRAMDAC_Print(reg) DEVICE_PRINT(PRAMDAC,reg)
#define PRAMDAC_Def(mask,value) DEVICE_DEF(PRAMDAC,mask,value)
#define PRAMDAC_Val(mask,value) DEVICE_VALUE(PRAMDAC,mask,value)
#define PRAMDAC_Mask(mask) DEVICE_MASK(PRAMDAC,mask)
#define PDAC_ReadExt(reg) \
((PDAC_Write(INDEX_LO,(NV_PDAC_EXT_##reg) & 0xff)),\
(PDAC_Write(INDEX_HI,((NV_PDAC_EXT_##reg) >> 8) & 0xff)),\
(PDAC_Read(INDEX_DATA)))
#define PDAC_WriteExt(reg,value)\
((PDAC_Write(INDEX_LO,(NV_PDAC_EXT_##reg) & 0xff)),\
(PDAC_Write(INDEX_HI,((NV_PDAC_EXT_##reg) >> 8) & 0xff)),\
(PDAC_Write(INDEX_DATA,(value))))
#define CRTC_Write(index,value) outb((index), 0x3d4); outb(value, 0x3d5)
#define CRTC_Read(index) (outb(index, 0x3d4),inb(0x3d5))
#define PCRTC_Write(index,value) CRTC_Write(NV_PCRTC_##index,value)
#define PCRTC_Read(index) CRTC_Read(NV_PCRTC_##index)
#define PCRTC_Def(mask,value) DEVICE_DEF(PCRTC,mask,value)
#define PCRTC_Val(mask,value) DEVICE_VALUE(PCRTC,mask,value)
#define PCRTC_Mask(mask) DEVICE_MASK(PCRTC,mask)
#define SR_Write(index,value) outb(0x3c4,(index));outb(0x3c5,value)
#define SR_Read(index) (outb(0x3c4,index),inb(0x3c5))
extern volatile unsigned *nvCONTROL;
typedef enum {NV1,NV3,NV4,NumNVChips} NVChipType;
NVChipType GetChipType(void);
#endif

/shark/trunk/drivers/fb/riva/riva_tbl.h
0,0 → 1,1008
/***************************************************************************\
|* *|
|* Copyright 1993-1999 NVIDIA, Corporation. All rights reserved. *|
|* *|
|* NOTICE TO USER: The source code is copyrighted under U.S. and *|
|* international laws. Users and possessors of this source code are *|
|* hereby granted a nonexclusive, royalty-free copyright license to *|
|* use this code in individual and commercial software. *|
|* *|
|* Any use of this source code must include, in the user documenta- *|
|* tion and internal comments to the code, notices to the end user *|
|* as follows: *|
|* *|
|* Copyright 1993-1999 NVIDIA, Corporation. All rights reserved. *|
|* *|
|* NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY *|
|* OF THIS SOURCE CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" *|
|* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *|
|* ATION DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOURCE CODE, *|
|* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *|
|* MENT, AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL *|
|* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *|
|* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *|
|* SULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION *|
|* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF *|
|* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE. *|
|* *|
|* U.S. Government End Users. This source code is a "commercial *|
|* item," as that term is defined at 48 C.F.R. 2.101 (OCT 1995), *|
|* consisting of "commercial computer software" and "commercial *|
|* computer software documentation," as such terms are used in *|
|* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *|
|* ment only as a commercial end item. Consistent with 48 C.F.R. *|
|* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *|
|* all U.S. Government End Users acquire the source code with only *|
|* those rights set forth herein. *|
|* *|
\***************************************************************************/
/*
* GPL licensing note -- nVidia is allowing a liberal interpretation of
* the documentation restriction above, to merely say that this nVidia's
* copyright and disclaimer should be included with all code derived
* from this source. -- Jeff Garzik <jgarzik@pobox.com>, 01/Nov/99
*/
/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/riva_tbl.h,v 1.9 2002/01/30 01:35:03 mvojkovi Exp $ */
/*
* RIVA Fixed Functionality Init Tables.
*/
static unsigned RivaTablePMC[][2] =
{
{0x00000050, 0x00000000},
{0x00000080, 0xFFFF00FF},
{0x00000080, 0xFFFFFFFF}
};
static unsigned RivaTablePTIMER[][2] =
{
{0x00000080, 0x00000008},
{0x00000084, 0x00000003},
{0x00000050, 0x00000000},
{0x00000040, 0xFFFFFFFF}
};
static unsigned RivaTableFIFO[][2] =
{
{0x00000000, 0x80000000},
{0x00000800, 0x80000001},
{0x00001000, 0x80000002},
{0x00001800, 0x80000010},
{0x00002000, 0x80000011},
{0x00002800, 0x80000012},
{0x00003000, 0x80000016},
{0x00003800, 0x80000013}
};
static unsigned nv3TablePFIFO[][2] =
{
{0x00000140, 0x00000000},
{0x00000480, 0x00000000},
{0x00000490, 0x00000000},
{0x00000494, 0x00000000},
{0x00000481, 0x00000000},
{0x00000084, 0x00000000},
{0x00000086, 0x00002000},
{0x00000085, 0x00002200},
{0x00000484, 0x00000000},
{0x0000049C, 0x00000000},
{0x00000104, 0x00000000},
{0x00000108, 0x00000000},
{0x00000100, 0x00000000},
{0x000004A0, 0x00000000},
{0x000004A4, 0x00000000},
{0x000004A8, 0x00000000},
{0x000004AC, 0x00000000},
{0x000004B0, 0x00000000},
{0x000004B4, 0x00000000},
{0x000004B8, 0x00000000},
{0x000004BC, 0x00000000},
{0x00000050, 0x00000000},
{0x00000040, 0xFFFFFFFF},
{0x00000480, 0x00000001},
{0x00000490, 0x00000001},
{0x00000140, 0x00000001}
};
static unsigned nv3TablePGRAPH[][2] =
{
{0x00000020, 0x1230001F},
{0x00000021, 0x10113000},
{0x00000022, 0x1131F101},
{0x00000023, 0x0100F531},
{0x00000060, 0x00000000},
{0x00000065, 0x00000000},
{0x00000068, 0x00000000},
{0x00000069, 0x00000000},
{0x0000006A, 0x00000000},
{0x0000006B, 0x00000000},
{0x0000006C, 0x00000000},
{0x0000006D, 0x00000000},
{0x0000006E, 0x00000000},
{0x0000006F, 0x00000000},
{0x000001A8, 0x00000000},
{0x00000440, 0xFFFFFFFF},
{0x00000480, 0x00000001},
{0x000001A0, 0x00000000},
{0x000001A2, 0x00000000},
{0x0000018A, 0xFFFFFFFF},
{0x00000190, 0x00000000},
{0x00000142, 0x00000000},
{0x00000154, 0x00000000},
{0x00000155, 0xFFFFFFFF},
{0x00000156, 0x00000000},
{0x00000157, 0xFFFFFFFF},
{0x00000064, 0x10010002},
{0x00000050, 0x00000000},
{0x00000051, 0x00000000},
{0x00000040, 0xFFFFFFFF},
{0x00000041, 0xFFFFFFFF},
{0x00000440, 0xFFFFFFFF},
{0x000001A9, 0x00000001}
};
static unsigned nv3TablePGRAPH_8BPP[][2] =
{
{0x000001AA, 0x00001111}
};
static unsigned nv3TablePGRAPH_15BPP[][2] =
{
{0x000001AA, 0x00002222}
};
static unsigned nv3TablePGRAPH_32BPP[][2] =
{
{0x000001AA, 0x00003333}
};
static unsigned nv3TablePRAMIN[][2] =
{
{0x00000500, 0x00010000},
{0x00000501, 0x007FFFFF},
{0x00000200, 0x80000000},
{0x00000201, 0x00C20341},
{0x00000204, 0x80000001},
{0x00000205, 0x00C50342},
{0x00000208, 0x80000002},
{0x00000209, 0x00C60343},
{0x0000020C, 0x80000003},
{0x0000020D, 0x00DC0348},
{0x00000210, 0x80000004},
{0x00000211, 0x00DC0349},
{0x00000214, 0x80000005},
{0x00000215, 0x00DC034A},
{0x00000218, 0x80000006},
{0x00000219, 0x00DC034B},
{0x00000240, 0x80000010},
{0x00000241, 0x00D10344},
{0x00000244, 0x80000011},
{0x00000245, 0x00D00345},
{0x00000248, 0x80000012},
{0x00000249, 0x00CC0346},
{0x0000024C, 0x80000013},
{0x0000024D, 0x00D70347},
{0x00000258, 0x80000016},
{0x00000259, 0x00CA034C},
{0x00000D05, 0x00000000},
{0x00000D06, 0x00000000},
{0x00000D07, 0x00000000},
{0x00000D09, 0x00000000},
{0x00000D0A, 0x00000000},
{0x00000D0B, 0x00000000},
{0x00000D0D, 0x00000000},
{0x00000D0E, 0x00000000},
{0x00000D0F, 0x00000000},
{0x00000D11, 0x00000000},
{0x00000D12, 0x00000000},
{0x00000D13, 0x00000000},
{0x00000D15, 0x00000000},
{0x00000D16, 0x00000000},
{0x00000D17, 0x00000000},
{0x00000D19, 0x00000000},
{0x00000D1A, 0x00000000},
{0x00000D1B, 0x00000000},
{0x00000D1D, 0x00000140},
{0x00000D1E, 0x00000000},
{0x00000D1F, 0x00000000},
{0x00000D20, 0x10100200},
{0x00000D21, 0x00000000},
{0x00000D22, 0x00000000},
{0x00000D23, 0x00000000},
{0x00000D24, 0x10210200},
{0x00000D25, 0x00000000},
{0x00000D26, 0x00000000},
{0x00000D27, 0x00000000},
{0x00000D28, 0x10420200},
{0x00000D29, 0x00000000},
{0x00000D2A, 0x00000000},
{0x00000D2B, 0x00000000},
{0x00000D2C, 0x10830200},
{0x00000D2D, 0x00000000},
{0x00000D2E, 0x00000000},
{0x00000D2F, 0x00000000},
{0x00000D31, 0x00000000},
{0x00000D32, 0x00000000},
{0x00000D33, 0x00000000}
};
static unsigned nv3TablePRAMIN_8BPP[][2] =
{
/* 0xXXXXX3XX For MSB mono format */
/* 0xXXXXX2XX For LSB mono format */
{0x00000D04, 0x10110203},
{0x00000D08, 0x10110203},
{0x00000D0C, 0x1011020B},
{0x00000D10, 0x10118203},
{0x00000D14, 0x10110203},
{0x00000D18, 0x10110203},
{0x00000D1C, 0x10419208},
{0x00000D30, 0x10118203}
};
static unsigned nv3TablePRAMIN_15BPP[][2] =
{
/* 0xXXXXX2XX For MSB mono format */
/* 0xXXXXX3XX For LSB mono format */
{0x00000D04, 0x10110200},
{0x00000D08, 0x10110200},
{0x00000D0C, 0x10110208},
{0x00000D10, 0x10118200},
{0x00000D14, 0x10110200},
{0x00000D18, 0x10110200},
{0x00000D1C, 0x10419208},
{0x00000D30, 0x10118200}
};
static unsigned nv3TablePRAMIN_32BPP[][2] =
{
/* 0xXXXXX3XX For MSB mono format */
/* 0xXXXXX2XX For LSB mono format */
{0x00000D04, 0x10110201},
{0x00000D08, 0x10110201},
{0x00000D0C, 0x10110209},
{0x00000D10, 0x10118201},
{0x00000D14, 0x10110201},
{0x00000D18, 0x10110201},
{0x00000D1C, 0x10419208},
{0x00000D30, 0x10118201}
};
static unsigned nv4TableFIFO[][2] =
{
{0x00003800, 0x80000014}
};
static unsigned nv4TablePFIFO[][2] =
{
{0x00000140, 0x00000000},
{0x00000480, 0x00000000},
{0x00000494, 0x00000000},
{0x00000481, 0x00000000},
{0x0000048B, 0x00000000},
{0x00000400, 0x00000000},
{0x00000414, 0x00000000},
{0x00000084, 0x03000100},
{0x00000085, 0x00000110},
{0x00000086, 0x00000112},
{0x00000143, 0x0000FFFF},
{0x00000496, 0x0000FFFF},
{0x00000050, 0x00000000},
{0x00000040, 0xFFFFFFFF},
{0x00000415, 0x00000001},
{0x00000480, 0x00000001},
{0x00000494, 0x00000001},
{0x00000495, 0x00000001},
{0x00000140, 0x00000001}
};
static unsigned nv4TablePGRAPH[][2] =
{
{0x00000020, 0x1231C001},
{0x00000021, 0x72111101},
{0x00000022, 0x11D5F071},
{0x00000023, 0x10D4FF31},
{0x00000060, 0x00000000},
{0x00000068, 0x00000000},
{0x00000070, 0x00000000},
{0x00000078, 0x00000000},
{0x00000061, 0x00000000},
{0x00000069, 0x00000000},
{0x00000071, 0x00000000},
{0x00000079, 0x00000000},
{0x00000062, 0x00000000},
{0x0000006A, 0x00000000},
{0x00000072, 0x00000000},
{0x0000007A, 0x00000000},
{0x00000063, 0x00000000},
{0x0000006B, 0x00000000},
{0x00000073, 0x00000000},
{0x0000007B, 0x00000000},
{0x00000064, 0x00000000},
{0x0000006C, 0x00000000},
{0x00000074, 0x00000000},
{0x0000007C, 0x00000000},
{0x00000065, 0x00000000},
{0x0000006D, 0x00000000},
{0x00000075, 0x00000000},
{0x0000007D, 0x00000000},
{0x00000066, 0x00000000},
{0x0000006E, 0x00000000},
{0x00000076, 0x00000000},
{0x0000007E, 0x00000000},
{0x00000067, 0x00000000},
{0x0000006F, 0x00000000},
{0x00000077, 0x00000000},
{0x0000007F, 0x00000000},
{0x00000058, 0x00000000},
{0x00000059, 0x00000000},
{0x0000005A, 0x00000000},
{0x0000005B, 0x00000000},
{0x00000196, 0x00000000},
{0x000001A1, 0x01FFFFFF},
{0x00000197, 0x00000000},
{0x000001A2, 0x01FFFFFF},
{0x00000198, 0x00000000},
{0x000001A3, 0x01FFFFFF},
{0x00000199, 0x00000000},
{0x000001A4, 0x01FFFFFF},
{0x00000050, 0x00000000},
{0x00000040, 0xFFFFFFFF},
{0x0000005C, 0x10010100},
{0x000001C4, 0xFFFFFFFF},
{0x000001C8, 0x00000001},
{0x00000204, 0x00000000},
{0x000001C3, 0x00000001}
};
static unsigned nv4TablePGRAPH_8BPP[][2] =
{
{0x000001C9, 0x00111111},
{0x00000186, 0x00001010},
{0x0000020C, 0x03020202}
};
static unsigned nv4TablePGRAPH_15BPP[][2] =
{
{0x000001C9, 0x00226222},
{0x00000186, 0x00002071},
{0x0000020C, 0x09080808}
};
static unsigned nv4TablePGRAPH_16BPP[][2] =
{
{0x000001C9, 0x00556555},
{0x00000186, 0x000050C2},
{0x0000020C, 0x0C0B0B0B}
};
static unsigned nv4TablePGRAPH_32BPP[][2] =
{
{0x000001C9, 0x0077D777},
{0x00000186, 0x000070E5},
{0x0000020C, 0x0E0D0D0D}
};
static unsigned nv4TablePRAMIN[][2] =
{
{0x00000000, 0x80000010},
{0x00000001, 0x80011145},
{0x00000002, 0x80000011},
{0x00000003, 0x80011146},
{0x00000004, 0x80000012},
{0x00000005, 0x80011147},
{0x00000006, 0x80000013},
{0x00000007, 0x80011148},
{0x00000008, 0x80000014},
{0x00000009, 0x80011149},
{0x0000000A, 0x80000015},
{0x0000000B, 0x8001114A},
{0x0000000C, 0x80000016},
{0x0000000D, 0x8001114F},
{0x00000020, 0x80000000},
{0x00000021, 0x80011142},
{0x00000022, 0x80000001},
{0x00000023, 0x80011143},
{0x00000024, 0x80000002},
{0x00000025, 0x80011144},
{0x00000026, 0x80000003},
{0x00000027, 0x8001114B},
{0x00000028, 0x80000004},
{0x00000029, 0x8001114C},
{0x0000002A, 0x80000005},
{0x0000002B, 0x8001114D},
{0x0000002C, 0x80000006},
{0x0000002D, 0x8001114E},
{0x00000500, 0x00003000},
{0x00000501, 0x01FFFFFF},
{0x00000502, 0x00000002},
{0x00000503, 0x00000002},
{0x00000508, 0x01008043},
{0x0000050A, 0x00000000},
{0x0000050B, 0x00000000},
{0x0000050C, 0x01008019},
{0x0000050E, 0x00000000},
{0x0000050F, 0x00000000},
#if 1
{0x00000510, 0x01008018},
#else
{0x00000510, 0x01008044},
#endif
{0x00000512, 0x00000000},
{0x00000513, 0x00000000},
{0x00000514, 0x01008021},
{0x00000516, 0x00000000},
{0x00000517, 0x00000000},
{0x00000518, 0x0100805F},
{0x0000051A, 0x00000000},
{0x0000051B, 0x00000000},
#if 1
{0x0000051C, 0x0100804B},
#else
{0x0000051C, 0x0100804A},
#endif
{0x0000051E, 0x00000000},
{0x0000051F, 0x00000000},
{0x00000520, 0x0100A048},
{0x00000521, 0x00000D01},
{0x00000522, 0x11401140},
{0x00000523, 0x00000000},
{0x00000524, 0x0300A054},
{0x00000525, 0x00000D01},
{0x00000526, 0x11401140},
{0x00000527, 0x00000000},
{0x00000528, 0x0300A055},
{0x00000529, 0x00000D01},
{0x0000052A, 0x11401140},
{0x0000052B, 0x00000000},
{0x0000052C, 0x00000058},
{0x0000052E, 0x11401140},
{0x0000052F, 0x00000000},
{0x00000530, 0x00000059},
{0x00000532, 0x11401140},
{0x00000533, 0x00000000},
{0x00000534, 0x0000005A},
{0x00000536, 0x11401140},
{0x00000537, 0x00000000},
{0x00000538, 0x0000005B},
{0x0000053A, 0x11401140},
{0x0000053B, 0x00000000},
{0x0000053C, 0x0300A01C},
{0x0000053E, 0x11401140},
{0x0000053F, 0x00000000}
};
static unsigned nv4TablePRAMIN_8BPP[][2] =
{
/* 0xXXXXXX01 For MSB mono format */
/* 0xXXXXXX02 For LSB mono format */
{0x00000509, 0x00000302},
{0x0000050D, 0x00000302},
{0x00000511, 0x00000202},
{0x00000515, 0x00000302},
{0x00000519, 0x00000302},
{0x0000051D, 0x00000302},
{0x0000052D, 0x00000302},
{0x0000052E, 0x00000302},
{0x00000535, 0x00000000},
{0x00000539, 0x00000000},
{0x0000053D, 0x00000302}
};
static unsigned nv4TablePRAMIN_15BPP[][2] =
{
/* 0xXXXXXX01 For MSB mono format */
/* 0xXXXXXX02 For LSB mono format */
{0x00000509, 0x00000902},
{0x0000050D, 0x00000902},
{0x00000511, 0x00000802},
{0x00000515, 0x00000902},
{0x00000519, 0x00000902},
{0x0000051D, 0x00000902},
{0x0000052D, 0x00000902},
{0x0000052E, 0x00000902},
{0x00000535, 0x00000702},
{0x00000539, 0x00000702},
{0x0000053D, 0x00000902}
};
static unsigned nv4TablePRAMIN_16BPP[][2] =
{
/* 0xXXXXXX01 For MSB mono format */
/* 0xXXXXXX02 For LSB mono format */
{0x00000509, 0x00000C02},
{0x0000050D, 0x00000C02},
{0x00000511, 0x00000B02},
{0x00000515, 0x00000C02},
{0x00000519, 0x00000C02},
{0x0000051D, 0x00000C02},
{0x0000052D, 0x00000C02},
{0x0000052E, 0x00000C02},
{0x00000535, 0x00000702},
{0x00000539, 0x00000702},
{0x0000053D, 0x00000C02}
};
static unsigned nv4TablePRAMIN_32BPP[][2] =
{
/* 0xXXXXXX01 For MSB mono format */
/* 0xXXXXXX02 For LSB mono format */
{0x00000509, 0x00000E02},
{0x0000050D, 0x00000E02},
{0x00000511, 0x00000D02},
{0x00000515, 0x00000E02},
{0x00000519, 0x00000E02},
{0x0000051D, 0x00000E02},
{0x0000052D, 0x00000E02},
{0x0000052E, 0x00000E02},
{0x00000535, 0x00000E02},
{0x00000539, 0x00000E02},
{0x0000053D, 0x00000E02}
};
static unsigned nv10TableFIFO[][2] =
{
{0x00003800, 0x80000014}
};
static unsigned nv10TablePFIFO[][2] =
{
{0x00000140, 0x00000000},
{0x00000480, 0x00000000},
{0x00000494, 0x00000000},
{0x00000481, 0x00000000},
{0x0000048B, 0x00000000},
{0x00000400, 0x00000000},
{0x00000414, 0x00000000},
{0x00000084, 0x03000100},
{0x00000085, 0x00000110},
{0x00000086, 0x00000112},
{0x00000143, 0x0000FFFF},
{0x00000496, 0x0000FFFF},
{0x00000050, 0x00000000},
{0x00000040, 0xFFFFFFFF},
{0x00000415, 0x00000001},
{0x00000480, 0x00000001},
{0x00000494, 0x00000001},
{0x00000495, 0x00000001},
{0x00000140, 0x00000001}
};
static unsigned nv10TablePGRAPH[][2] =
{
{0x00000020, 0x0003FFFF},
{0x00000021, 0x00118701},
{0x00000022, 0x24F82AD9},
{0x00000023, 0x55DE0030},
{0x00000020, 0x00000000},
{0x00000024, 0x00000000},
{0x00000058, 0x00000000},
{0x00000060, 0x00000000},
{0x00000068, 0x00000000},
{0x00000070, 0x00000000},
{0x00000078, 0x00000000},
{0x00000059, 0x00000000},
{0x00000061, 0x00000000},
{0x00000069, 0x00000000},
{0x00000071, 0x00000000},
{0x00000079, 0x00000000},
{0x0000005A, 0x00000000},
{0x00000062, 0x00000000},
{0x0000006A, 0x00000000},
{0x00000072, 0x00000000},
{0x0000007A, 0x00000000},
{0x0000005B, 0x00000000},
{0x00000063, 0x00000000},
{0x0000006B, 0x00000000},
{0x00000073, 0x00000000},
{0x0000007B, 0x00000000},
{0x0000005C, 0x00000000},
{0x00000064, 0x00000000},
{0x0000006C, 0x00000000},
{0x00000074, 0x00000000},
{0x0000007C, 0x00000000},
{0x0000005D, 0x00000000},
{0x00000065, 0x00000000},
{0x0000006D, 0x00000000},
{0x00000075, 0x00000000},
{0x0000007D, 0x00000000},
{0x0000005E, 0x00000000},
{0x00000066, 0x00000000},
{0x0000006E, 0x00000000},
{0x00000076, 0x00000000},
{0x0000007E, 0x00000000},
{0x0000005F, 0x00000000},
{0x00000067, 0x00000000},
{0x0000006F, 0x00000000},
{0x00000077, 0x00000000},
{0x0000007F, 0x00000000},
{0x00000053, 0x00000000},
{0x00000054, 0x00000000},
{0x00000055, 0x00000000},
{0x00000056, 0x00000000},
{0x00000057, 0x00000000},
{0x00000196, 0x00000000},
{0x000001A1, 0x01FFFFFF},
{0x00000197, 0x00000000},
{0x000001A2, 0x01FFFFFF},
{0x00000198, 0x00000000},
{0x000001A3, 0x01FFFFFF},
{0x00000199, 0x00000000},
{0x000001A4, 0x01FFFFFF},
{0x0000019A, 0x00000000},
{0x000001A5, 0x01FFFFFF},
{0x0000019B, 0x00000000},
{0x000001A6, 0x01FFFFFF},
{0x00000050, 0x01111111},
{0x00000040, 0xFFFFFFFF},
{0x00000051, 0x10010100},
{0x000001C5, 0xFFFFFFFF},
{0x000001C8, 0x00000001},
{0x00000204, 0x00000000},
{0x000001C4, 0x00000001}
};
static unsigned nv10TablePGRAPH_8BPP[][2] =
{
{0x000001C9, 0x00111111},
{0x00000186, 0x00001010},
{0x0000020C, 0x03020202}
};
static unsigned nv10TablePGRAPH_15BPP[][2] =
{
{0x000001C9, 0x00226222},
{0x00000186, 0x00002071},
{0x0000020C, 0x09080808}
};
static unsigned nv10TablePGRAPH_16BPP[][2] =
{
{0x000001C9, 0x00556555},
{0x00000186, 0x000050C2},
{0x0000020C, 0x000B0B0C}
};
static unsigned nv10TablePGRAPH_32BPP[][2] =
{
{0x000001C9, 0x0077D777},
{0x00000186, 0x000070E5},
{0x0000020C, 0x0E0D0D0D}
};
static unsigned nv10tri05TablePGRAPH[][2] =
{
{(0x00000E00/4), 0x00000000},
{(0x00000E04/4), 0x00000000},
{(0x00000E08/4), 0x00000000},
{(0x00000E0C/4), 0x00000000},
{(0x00000E10/4), 0x00001000},
{(0x00000E14/4), 0x00001000},
{(0x00000E18/4), 0x4003ff80},
{(0x00000E1C/4), 0x00000000},
{(0x00000E20/4), 0x00000000},
{(0x00000E24/4), 0x00000000},
{(0x00000E28/4), 0x00000000},
{(0x00000E2C/4), 0x00000000},
{(0x00000E30/4), 0x00080008},
{(0x00000E34/4), 0x00080008},
{(0x00000E38/4), 0x00000000},
{(0x00000E3C/4), 0x00000000},
{(0x00000E40/4), 0x00000000},
{(0x00000E44/4), 0x00000000},
{(0x00000E48/4), 0x00000000},
{(0x00000E4C/4), 0x00000000},
{(0x00000E50/4), 0x00000000},
{(0x00000E54/4), 0x00000000},
{(0x00000E58/4), 0x00000000},
{(0x00000E5C/4), 0x00000000},
{(0x00000E60/4), 0x00000000},
{(0x00000E64/4), 0x10000000},
{(0x00000E68/4), 0x00000000},
{(0x00000E6C/4), 0x00000000},
{(0x00000E70/4), 0x00000000},
{(0x00000E74/4), 0x00000000},
{(0x00000E78/4), 0x00000000},
{(0x00000E7C/4), 0x00000000},
{(0x00000E80/4), 0x00000000},
{(0x00000E84/4), 0x00000000},
{(0x00000E88/4), 0x08000000},
{(0x00000E8C/4), 0x00000000},
{(0x00000E90/4), 0x00000000},
{(0x00000E94/4), 0x00000000},
{(0x00000E98/4), 0x00000000},
{(0x00000E9C/4), 0x4B7FFFFF},
{(0x00000EA0/4), 0x00000000},
{(0x00000EA4/4), 0x00000000},
{(0x00000EA8/4), 0x00000000},
{(0x00000F00/4), 0x07FF0800},
{(0x00000F04/4), 0x07FF0800},
{(0x00000F08/4), 0x07FF0800},
{(0x00000F0C/4), 0x07FF0800},
{(0x00000F10/4), 0x07FF0800},
{(0x00000F14/4), 0x07FF0800},
{(0x00000F18/4), 0x07FF0800},
{(0x00000F1C/4), 0x07FF0800},
{(0x00000F20/4), 0x07FF0800},
{(0x00000F24/4), 0x07FF0800},
{(0x00000F28/4), 0x07FF0800},
{(0x00000F2C/4), 0x07FF0800},
{(0x00000F30/4), 0x07FF0800},
{(0x00000F34/4), 0x07FF0800},
{(0x00000F38/4), 0x07FF0800},
{(0x00000F3C/4), 0x07FF0800},
{(0x00000F40/4), 0x10000000},
{(0x00000F44/4), 0x00000000},
{(0x00000F50/4), 0x00006740},
{(0x00000F54/4), 0x00000000},
{(0x00000F54/4), 0x00000000},
{(0x00000F54/4), 0x00000000},
{(0x00000F54/4), 0x3F800000},
{(0x00000F50/4), 0x00006750},
{(0x00000F54/4), 0x40000000},
{(0x00000F54/4), 0x40000000},
{(0x00000F54/4), 0x40000000},
{(0x00000F54/4), 0x40000000},
{(0x00000F50/4), 0x00006760},
{(0x00000F54/4), 0x00000000},
{(0x00000F54/4), 0x00000000},
{(0x00000F54/4), 0x3F800000},
{(0x00000F54/4), 0x00000000},
{(0x00000F50/4), 0x00006770},
{(0x00000F54/4), 0xC5000000},
{(0x00000F54/4), 0xC5000000},
{(0x00000F54/4), 0x00000000},
{(0x00000F54/4), 0x00000000},
{(0x00000F50/4), 0x00006780},
{(0x00000F54/4), 0x00000000},
{(0x00000F54/4), 0x00000000},
{(0x00000F54/4), 0x3F800000},
{(0x00000F54/4), 0x00000000},
{(0x00000F50/4), 0x000067A0},
{(0x00000F54/4), 0x3F800000},
{(0x00000F54/4), 0x3F800000},
{(0x00000F54/4), 0x3F800000},
{(0x00000F54/4), 0x3F800000},
{(0x00000F50/4), 0x00006AB0},
{(0x00000F54/4), 0x3F800000},
{(0x00000F54/4), 0x3F800000},
{(0x00000F54/4), 0x3F800000},
{(0x00000F50/4), 0x00006AC0},
{(0x00000F54/4), 0x00000000},
{(0x00000F54/4), 0x00000000},
{(0x00000F54/4), 0x00000000},
{(0x00000F50/4), 0x00006C10},
{(0x00000F54/4), 0xBF800000},
{(0x00000F50/4), 0x00007030},
{(0x00000F54/4), 0x7149F2CA},
{(0x00000F50/4), 0x00007040},
{(0x00000F54/4), 0x7149F2CA},
{(0x00000F50/4), 0x00007050},
{(0x00000F54/4), 0x7149F2CA},
{(0x00000F50/4), 0x00007060},
{(0x00000F54/4), 0x7149F2CA},
{(0x00000F50/4), 0x00007070},
{(0x00000F54/4), 0x7149F2CA},
{(0x00000F50/4), 0x00007080},
{(0x00000F54/4), 0x7149F2CA},
{(0x00000F50/4), 0x00007090},
{(0x00000F54/4), 0x7149F2CA},
{(0x00000F50/4), 0x000070A0},
{(0x00000F54/4), 0x7149F2CA},
{(0x00000F50/4), 0x00006A80},
{(0x00000F54/4), 0x00000000},
{(0x00000F54/4), 0x00000000},
{(0x00000F54/4), 0x3F800000},
{(0x00000F50/4), 0x00006AA0},
{(0x00000F54/4), 0x00000000},
{(0x00000F54/4), 0x00000000},
{(0x00000F54/4), 0x00000000},
{(0x00000F50/4), 0x00000040},
{(0x00000F54/4), 0x00000005},
{(0x00000F50/4), 0x00006400},
{(0x00000F54/4), 0x3F800000},
{(0x00000F54/4), 0x3F800000},
{(0x00000F54/4), 0x4B7FFFFF},
{(0x00000F54/4), 0x00000000},
{(0x00000F50/4), 0x00006410},
{(0x00000F54/4), 0xC5000000},
{(0x00000F54/4), 0xC5000000},
{(0x00000F54/4), 0x00000000},
{(0x00000F54/4), 0x00000000},
{(0x00000F50/4), 0x00006420},
{(0x00000F54/4), 0x00000000},
{(0x00000F54/4), 0x00000000},
{(0x00000F54/4), 0x00000000},
{(0x00000F54/4), 0x00000000},
{(0x00000F50/4), 0x00006430},
{(0x00000F54/4), 0x00000000},
{(0x00000F54/4), 0x00000000},
{(0x00000F54/4), 0x00000000},
{(0x00000F54/4), 0x00000000},
{(0x00000F50/4), 0x000064C0},
{(0x00000F54/4), 0x3F800000},
{(0x00000F54/4), 0x3F800000},
{(0x00000F54/4), 0x477FFFFF},
{(0x00000F54/4), 0x3F800000},
{(0x00000F50/4), 0x000064D0},
{(0x00000F54/4), 0xC5000000},
{(0x00000F54/4), 0xC5000000},
{(0x00000F54/4), 0x00000000},
{(0x00000F54/4), 0x00000000},
{(0x00000F50/4), 0x000064E0},
{(0x00000F54/4), 0xC4FFF000},
{(0x00000F54/4), 0xC4FFF000},
{(0x00000F54/4), 0x00000000},
{(0x00000F54/4), 0x00000000},
{(0x00000F50/4), 0x000064F0},
{(0x00000F54/4), 0x00000000},
{(0x00000F54/4), 0x00000000},
{(0x00000F54/4), 0x00000000},
{(0x00000F54/4), 0x00000000},
{(0x00000F40/4), 0x30000000},
{(0x00000F44/4), 0x00000004},
{(0x00000F48/4), 0x10000000},
{(0x00000F4C/4), 0x00000000}
};
static unsigned nv10TablePRAMIN[][2] =
{
{0x00000000, 0x80000010},
{0x00000001, 0x80011145},
{0x00000002, 0x80000011},
{0x00000003, 0x80011146},
{0x00000004, 0x80000012},
{0x00000005, 0x80011147},
{0x00000006, 0x80000013},
{0x00000007, 0x80011148},
{0x00000008, 0x80000014},
{0x00000009, 0x80011149},
{0x0000000A, 0x80000015},
{0x0000000B, 0x8001114A},
{0x0000000C, 0x80000016},
{0x0000000D, 0x80011150},
{0x00000020, 0x80000000},
{0x00000021, 0x80011142},
{0x00000022, 0x80000001},
{0x00000023, 0x80011143},
{0x00000024, 0x80000002},
{0x00000025, 0x80011144},
{0x00000026, 0x80000003},
{0x00000027, 0x8001114B},
{0x00000028, 0x80000004},
{0x00000029, 0x8001114C},
{0x0000002A, 0x80000005},
{0x0000002B, 0x8001114D},
{0x0000002C, 0x80000006},
{0x0000002D, 0x8001114E},
{0x0000002E, 0x80000007},
{0x0000002F, 0x8001114F},
{0x00000500, 0x00003000},
{0x00000501, 0x01FFFFFF},
{0x00000502, 0x00000002},
{0x00000503, 0x00000002},
#ifdef __BIG_ENDIAN
{0x00000508, 0x01088043},
#else
{0x00000508, 0x01008043},
#endif
{0x0000050A, 0x00000000},
{0x0000050B, 0x00000000},
#ifdef __BIG_ENDIAN
{0x0000050C, 0x01088019},
#else
{0x0000050C, 0x01008019},
#endif
{0x0000050E, 0x00000000},
{0x0000050F, 0x00000000},
#ifdef __BIG_ENDIAN
{0x00000510, 0x01088018},
#else
{0x00000510, 0x01008018},
#endif
{0x00000512, 0x00000000},
{0x00000513, 0x00000000},
#ifdef __BIG_ENDIAN
{0x00000514, 0x01088021},
#else
{0x00000514, 0x01008021},
#endif
{0x00000516, 0x00000000},
{0x00000517, 0x00000000},
#ifdef __BIG_ENDIAN
{0x00000518, 0x0108805F},
#else
{0x00000518, 0x0100805F},
#endif
{0x0000051A, 0x00000000},
{0x0000051B, 0x00000000},
#ifdef __BIG_ENDIAN
{0x0000051C, 0x0108804B},
#else
{0x0000051C, 0x0100804B},
#endif
{0x0000051E, 0x00000000},
{0x0000051F, 0x00000000},
{0x00000520, 0x0100A048},
{0x00000521, 0x00000D01},
{0x00000522, 0x11401140},
{0x00000523, 0x00000000},
{0x00000524, 0x0300A094},
{0x00000525, 0x00000D01},
{0x00000526, 0x11401140},
{0x00000527, 0x00000000},
{0x00000528, 0x0300A095},
{0x00000529, 0x00000D01},
{0x0000052A, 0x11401140},
{0x0000052B, 0x00000000},
#ifdef __BIG_ENDIAN
{0x0000052C, 0x00080058},
#else
{0x0000052C, 0x00000058},
#endif
{0x0000052E, 0x11401140},
{0x0000052F, 0x00000000},
#ifdef __BIG_ENDIAN
{0x00000530, 0x00080059},
#else
{0x00000530, 0x00000059},
#endif
{0x00000532, 0x11401140},
{0x00000533, 0x00000000},
{0x00000534, 0x0000005A},
{0x00000536, 0x11401140},
{0x00000537, 0x00000000},
{0x00000538, 0x0000005B},
{0x0000053A, 0x11401140},
{0x0000053B, 0x00000000},
{0x0000053C, 0x00000093},
{0x0000053E, 0x11401140},
{0x0000053F, 0x00000000},
#ifdef __BIG_ENDIAN
{0x00000540, 0x0308A01C},
#else
{0x00000540, 0x0300A01C},
#endif
{0x00000542, 0x11401140},
{0x00000543, 0x00000000}
};
static unsigned nv10TablePRAMIN_8BPP[][2] =
{
/* 0xXXXXXX01 For MSB mono format */
/* 0xXXXXXX02 For LSB mono format */
{0x00000509, 0x00000302},
{0x0000050D, 0x00000302},
{0x00000511, 0x00000202},
{0x00000515, 0x00000302},
{0x00000519, 0x00000302},
{0x0000051D, 0x00000302},
{0x0000052D, 0x00000302},
{0x0000052E, 0x00000302},
{0x00000535, 0x00000000},
{0x00000539, 0x00000000},
{0x0000053D, 0x00000000},
{0x00000541, 0x00000302}
};
static unsigned nv10TablePRAMIN_15BPP[][2] =
{
/* 0xXXXXXX01 For MSB mono format */
/* 0xXXXXXX02 For LSB mono format */
{0x00000509, 0x00000902},
{0x0000050D, 0x00000902},
{0x00000511, 0x00000802},
{0x00000515, 0x00000902},
{0x00000519, 0x00000902},
{0x0000051D, 0x00000902},
{0x0000052D, 0x00000902},
{0x0000052E, 0x00000902},
{0x00000535, 0x00000902},
{0x00000539, 0x00000902},
{0x0000053D, 0x00000902},
{0x00000541, 0x00000902}
};
static unsigned nv10TablePRAMIN_16BPP[][2] =
{
/* 0xXXXXXX01 For MSB mono format */
/* 0xXXXXXX02 For LSB mono format */
{0x00000509, 0x00000C02},
{0x0000050D, 0x00000C02},
{0x00000511, 0x00000B02},
{0x00000515, 0x00000C02},
{0x00000519, 0x00000C02},
{0x0000051D, 0x00000C02},
{0x0000052D, 0x00000C02},
{0x0000052E, 0x00000C02},
{0x00000535, 0x00000C02},
{0x00000539, 0x00000C02},
{0x0000053D, 0x00000C02},
{0x00000541, 0x00000C02}
};
static unsigned nv10TablePRAMIN_32BPP[][2] =
{
/* 0xXXXXXX01 For MSB mono format */
/* 0xXXXXXX02 For LSB mono format */
{0x00000509, 0x00000E02},
{0x0000050D, 0x00000E02},
{0x00000511, 0x00000D02},
{0x00000515, 0x00000E02},
{0x00000519, 0x00000E02},
{0x0000051D, 0x00000E02},
{0x0000052D, 0x00000E02},
{0x0000052E, 0x00000E02},
{0x00000535, 0x00000E02},
{0x00000539, 0x00000E02},
{0x0000053D, 0x00000E02},
{0x00000541, 0x00000E02}
};

/shark/trunk/drivers/fb/riva/nv4ref.h
0,0 → 1,2445
/***************************************************************************\
|* *|
|* Copyright 1993-1998 NVIDIA, Corporation. All rights reserved. *|
|* *|
|* NOTICE TO USER: The source code is copyrighted under U.S. and *|
|* international laws. Users and possessors of this source code are *|
|* hereby granted a nonexclusive, royalty-free copyright license to *|
|* use this code in individual and commercial software. *|
|* *|
|* Any use of this source code must include, in the user documenta- *|
|* tion and internal comments to the code, notices to the end user *|
|* as follows: *|
|* *|
|* Copyright 1993-1998 NVIDIA, Corporation. All rights reserved. *|
|* *|
|* NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY *|
|* OF THIS SOURCE CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" *|
|* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *|
|* ATION DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOURCE CODE, *|
|* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *|
|* MENT, AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL *|
|* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *|
|* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *|
|* SULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION *|
|* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF *|
|* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE. *|
|* *|
|* U.S. Government End Users. This source code is a "commercial *|
|* item," as that term is defined at 48 C.F.R. 2.101 (OCT 1995), *|
|* consisting of "commercial computer software" and "commercial *|
|* computer software documentation," as such terms are used in *|
|* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *|
|* ment only as a commercial end item. Consistent with 48 C.F.R. *|
|* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *|
|* all U.S. Government End Users acquire the source code with only *|
|* those rights set forth herein. *|
|* *|
\***************************************************************************/
/*
* GPL licensing note -- nVidia is allowing a liberal interpretation of
* the documentation restriction above, to merely say that this nVidia's
* copyright and disclaimer should be included with all code derived
* from this source. -- Jeff Garzik <jgarzik@pobox.com>, 01/Nov/99
*/
/***************************************************************************\
|* Modified 1999 by Fredrik Reite (fredrik@reite.com) *|
\***************************************************************************/
#ifndef __NV4REF_H__
#define __NV4REF_H__
/* Magic values to lock/unlock extended regs */
#define NV_CIO_SR_LOCK_INDEX 0x0000001F /* */
#define NV_CIO_SR_UNLOCK_RW_VALUE 0x00000057 /* */
#define NV_CIO_SR_UNLOCK_RO_VALUE 0x00000075 /* */
#define NV_CIO_SR_LOCK_VALUE 0x00000099 /* */
#define UNLOCK_EXT_MAGIC 0x57
#define LOCK_EXT_MAGIC 0x99 /* Any value other than 0x57 will do */
#define LOCK_EXT_INDEX 0x6
#define NV_PCRTC_HORIZ_TOTAL 0x00
#define NV_PCRTC_HORIZ_DISPLAY_END 0x01
#define NV_PCRTC_HORIZ_BLANK_START 0x02
#define NV_PCRTC_HORIZ_BLANK_END 0x03
#define NV_PCRTC_HORIZ_BLANK_END_EVRA 7:7
#define NV_PCRTC_HORIZ_BLANK_END_DISPLAY_END_SKEW 6:5
#define NV_PCRTC_HORIZ_BLANK_END_HORIZ_BLANK_END 4:0
#define NV_PCRTC_HORIZ_RETRACE_START 0x04
#define NV_PCRTC_HORIZ_RETRACE_END 0x05
#define NV_PCRTC_HORIZ_RETRACE_END_HORIZ_BLANK_END_5 7:7
#define NV_PCRTC_HORIZ_RETRACE_END_HORIZ_RETRACE_SKEW 6:5
#define NV_PCRTC_HORIZ_RETRACE_END_HORIZ_RETRACE_END 4:0
#define NV_PCRTC_VERT_TOTAL 0x06
#define NV_PCRTC_OVERFLOW 0x07
#define NV_PCRTC_OVERFLOW_VERT_RETRACE_START_9 7:7
#define NV_PCRTC_OVERFLOW_VERT_DISPLAY_END_9 6:6
#define NV_PCRTC_OVERFLOW_VERT_TOTAL_9 5:5
#define NV_PCRTC_OVERFLOW_LINE_COMPARE_8 4:4
#define NV_PCRTC_OVERFLOW_VERT_BLANK_START_8 3:3
#define NV_PCRTC_OVERFLOW_VERT_RETRACE_START_8 2:2
#define NV_PCRTC_OVERFLOW_VERT_DISPLAY_END_8 1:1
#define NV_PCRTC_OVERFLOW_VERT_TOTAL_8 0:0
#define NV_PCRTC_PRESET_ROW_SCAN 0x08
#define NV_PCRTC_MAX_SCAN_LINE 0x09
#define NV_PCRTC_MAX_SCAN_LINE_DOUBLE_SCAN 7:7
#define NV_PCRTC_MAX_SCAN_LINE_LINE_COMPARE_9 6:6
#define NV_PCRTC_MAX_SCAN_LINE_VERT_BLANK_START_9 5:5
#define NV_PCRTC_MAX_SCAN_LINE_MAX_SCAN_LINE 4:0
#define NV_PCRTC_CURSOR_START 0x0A
#define NV_PCRTC_CURSOR_END 0x0B
#define NV_PCRTC_START_ADDR_HIGH 0x0C
#define NV_PCRTC_START_ADDR_LOW 0x0D
#define NV_PCRTC_CURSOR_LOCATION_HIGH 0x0E
#define NV_PCRTC_CURSOR_LOCATION_LOW 0x0F
#define NV_PCRTC_VERT_RETRACE_START 0x10
#define NV_PCRTC_VERT_RETRACE_END 0x11
#define NV_PCRTC_VERT_DISPLAY_END 0x12
#define NV_PCRTC_OFFSET 0x13
#define NV_PCRTC_UNDERLINE_LOCATION 0x14
#define NV_PCRTC_VERT_BLANK_START 0x15
#define NV_PCRTC_VERT_BLANK_END 0x16
#define NV_PCRTC_MODE_CONTROL 0x17
#define NV_PCRTC_LINE_COMPARE 0x18
/* Extended offset and start address */
#define NV_PCRTC_REPAINT0 0x19
#define NV_PCRTC_REPAINT0_OFFSET_10_8 7:5
#define NV_PCRTC_REPAINT0_START_ADDR_20_16 4:0
/* Horizonal extended bits */
#define NV_PCRTC_HORIZ_EXTRA 0x2d
#define NV_PCRTC_HORIZ_EXTRA_INTER_HALF_START_8 4:4
#define NV_PCRTC_HORIZ_EXTRA_HORIZ_RETRACE_START_8 3:3
#define NV_PCRTC_HORIZ_EXTRA_HORIZ_BLANK_START_8 2:2
#define NV_PCRTC_HORIZ_EXTRA_DISPLAY_END_8 1:1
#define NV_PCRTC_HORIZ_EXTRA_DISPLAY_TOTAL_8 0:0
/* Assorted extra bits */
#define NV_PCRTC_EXTRA 0x25
#define NV_PCRTC_EXTRA_OFFSET_11 5:5
#define NV_PCRTC_EXTRA_HORIZ_BLANK_END_6 4:4
#define NV_PCRTC_EXTRA_VERT_BLANK_START_10 3:3
#define NV_PCRTC_EXTRA_VERT_RETRACE_START_10 2:2
#define NV_PCRTC_EXTRA_VERT_DISPLAY_END_10 1:1
#define NV_PCRTC_EXTRA_VERT_TOTAL_10 0:0
/* Controls how much data the refresh fifo requests */
#define NV_PCRTC_FIFO_CONTROL 0x1b
#define NV_PCRTC_FIFO_CONTROL_UNDERFLOW_WARN 7:7
#define NV_PCRTC_FIFO_CONTROL_BURST_LENGTH 2:0
#define NV_PCRTC_FIFO_CONTROL_BURST_LENGTH_8 0x0
#define NV_PCRTC_FIFO_CONTROL_BURST_LENGTH_32 0x1
#define NV_PCRTC_FIFO_CONTROL_BURST_LENGTH_64 0x2
#define NV_PCRTC_FIFO_CONTROL_BURST_LENGTH_128 0x3
#define NV_PCRTC_FIFO_CONTROL_BURST_LENGTH_256 0x4
/* When the fifo occupancy falls below *twice* the watermark,
* the refresh fifo will start to be refilled. If this value is
* too low, you will get junk on the screen. Too high, and performance
* will suffer. Watermark in units of 8 bytes
*/
#define NV_PCRTC_FIFO 0x20
#define NV_PCRTC_FIFO_RESET 7:7
#define NV_PCRTC_FIFO_WATERMARK 5:0
/* Various flags */
#define NV_PCRTC_REPAINT1 0x1a
#define NV_PCRTC_REPAINT1_HSYNC 7:7
#define NV_PCRTC_REPAINT1_HYSNC_DISABLE 0x01
#define NV_PCRTC_REPAINT1_HYSNC_ENABLE 0x00
#define NV_PCRTC_REPAINT1_VSYNC 6:6
#define NV_PCRTC_REPAINT1_VYSNC_DISABLE 0x01
#define NV_PCRTC_REPAINT1_VYSNC_ENABLE 0x00
#define NV_PCRTC_REPAINT1_COMPATIBLE_TEXT 4:4
#define NV_PCRTC_REPAINT1_COMPATIBLE_TEXT_ENABLE 0x01
#define NV_PCRTC_REPAINT1_COMPATIBLE_TEXT_DISABLE 0x00
#define NV_PCRTC_REPAINT1_LARGE_SCREEN 2:2
#define NV_PCRTC_REPAINT1_LARGE_SCREEN_DISABLE 0x01
#define NV_PCRTC_REPAINT1_LARGE_SCREEN_ENABLE 0x00 /* >=1280 */
#define NV_PCRTC_REPAINT1_PALETTE_WIDTH 1:1
#define NV_PCRTC_REPAINT1_PALETTE_WIDTH_8BITS 0x00
#define NV_PCRTC_REPAINT1_PALETTE_WIDTH_6BITS 0x01
#define NV_PCRTC_GRCURSOR0 0x30
#define NV_PCRTC_GRCURSOR0_START_ADDR_21_16 5:0
#define NV_PCRTC_GRCURSOR1 0x31
#define NV_PCRTC_GRCURSOR1_START_ADDR_15_11 7:3
#define NV_PCRTC_GRCURSOR1_SCAN_DBL 1:1
#define NV_PCRTC_GRCURSOR1_SCAN_DBL_DISABLE 0
#define NV_PCRTC_GRCURSOR1_SCAN_DBL_ENABLE 1
#define NV_PCRTC_GRCURSOR1_CURSOR 0:0
#define NV_PCRTC_GRCURSOR1_CURSOR_DISABLE 0
#define NV_PCRTC_GRCURSOR1_CURSOR_ENABLE 1
/* Controls what the format of the framebuffer is */
#define NV_PCRTC_PIXEL 0x28
#define NV_PCRTC_PIXEL_MODE 7:7
#define NV_PCRTC_PIXEL_MODE_TV 0x01
#define NV_PCRTC_PIXEL_MODE_VGA 0x00
#define NV_PCRTC_PIXEL_TV_MODE 6:6
#define NV_PCRTC_PIXEL_TV_MODE_NTSC 0x00
#define NV_PCRTC_PIXEL_TV_MODE_PAL 0x01
#define NV_PCRTC_PIXEL_TV_HORIZ_ADJUST 5:3
#define NV_PCRTC_PIXEL_FORMAT 1:0
#define NV_PCRTC_PIXEL_FORMAT_VGA 0x00
#define NV_PCRTC_PIXEL_FORMAT_8BPP 0x01
#define NV_PCRTC_PIXEL_FORMAT_16BPP 0x02
#define NV_PCRTC_PIXEL_FORMAT_32BPP 0x03
/* RAMDAC registers and fields */
#define NV_PRAMDAC 0x00680FFF:0x00680000 /* RW--D */
#define NV_PRAMDAC_GRCURSOR_START_POS 0x00680300 /* RW-4R */
#define NV_PRAMDAC_GRCURSOR_START_POS_X 11:0 /* RWXSF */
#define NV_PRAMDAC_GRCURSOR_START_POS_Y 27:16 /* RWXSF */
#define NV_PRAMDAC_NVPLL_COEFF 0x00680500 /* RW-4R */
#define NV_PRAMDAC_NVPLL_COEFF_MDIV 7:0 /* RWIUF */
#define NV_PRAMDAC_NVPLL_COEFF_NDIV 15:8 /* RWIUF */
#define NV_PRAMDAC_NVPLL_COEFF_PDIV 18:16 /* RWIVF */
#define NV_PRAMDAC_MPLL_COEFF 0x00680504 /* RW-4R */
#define NV_PRAMDAC_MPLL_COEFF_MDIV 7:0 /* RWIUF */
#define NV_PRAMDAC_MPLL_COEFF_NDIV 15:8 /* RWIUF */
#define NV_PRAMDAC_MPLL_COEFF_PDIV 18:16 /* RWIVF */
#define NV_PRAMDAC_VPLL_COEFF 0x00680508 /* RW-4R */
#define NV_PRAMDAC_VPLL_COEFF_MDIV 7:0 /* RWIUF */
#define NV_PRAMDAC_VPLL_COEFF_NDIV 15:8 /* RWIUF */
#define NV_PRAMDAC_VPLL_COEFF_PDIV 18:16 /* RWIVF */
#define NV_PRAMDAC_PLL_COEFF_SELECT 0x0068050C /* RW-4R */
#define NV_PRAMDAC_PLL_COEFF_SELECT_DLL_BYPASS 4:4 /* RWIVF */
#define NV_PRAMDAC_PLL_COEFF_SELECT_DLL_BYPASS_FALSE 0x00000000 /* RWI-V */
#define NV_PRAMDAC_PLL_COEFF_SELECT_DLL_BYPASS_TRUE 0x00000001 /* RW--V */
#define NV_PRAMDAC_PLL_COEFF_SELECT_MPLL_SOURCE 8:8 /* RWIVF */
#define NV_PRAMDAC_PLL_COEFF_SELECT_MPLL_SOURCE_DEFAULT 0x00000000 /* RWI-V */
#define NV_PRAMDAC_PLL_COEFF_SELECT_MPLL_SOURCE_PROG 0x00000001 /* RW--V */
#define NV_PRAMDAC_PLL_COEFF_SELECT_MPLL_BYPASS 12:12 /* RWIVF */
#define NV_PRAMDAC_PLL_COEFF_SELECT_MPLL_BYPASS_FALSE 0x00000000 /* RWI-V */
#define NV_PRAMDAC_PLL_COEFF_SELECT_MPLL_BYPASS_TRUE 0x00000001 /* RW--V */
#define NV_PRAMDAC_PLL_COEFF_SELECT_VPLL_SOURCE 16:16 /* RWIVF */
#define NV_PRAMDAC_PLL_COEFF_SELECT_VPLL_SOURCE_DEFAULT 0x00000000 /* RWI-V */
#define NV_PRAMDAC_PLL_COEFF_SELECT_VPLL_SOURCE_PROG 0x00000001 /* RW--V */
#define NV_PRAMDAC_PLL_COEFF_SELECT_VPLL_BYPASS 20:20 /* RWIVF */
#define NV_PRAMDAC_PLL_COEFF_SELECT_VPLL_BYPASS_FALSE 0x00000000 /* RWI-V */
#define NV_PRAMDAC_PLL_COEFF_SELECT_VPLL_BYPASS_TRUE 0x00000001 /* RW--V */
#define NV_PRAMDAC_PLL_COEFF_SELECT_PCLK_SOURCE 25:24 /* RWIVF */
#define NV_PRAMDAC_PLL_COEFF_SELECT_PCLK_SOURCE_VPLL 0x00000000 /* RWI-V */
#define NV_PRAMDAC_PLL_COEFF_SELECT_PCLK_SOURCE_VIP 0x00000001 /* RW--V */
#define NV_PRAMDAC_PLL_COEFF_SELECT_PCLK_SOURCE_XTALOSC 0x00000002 /* RW--V */
#define NV_PRAMDAC_PLL_COEFF_SELECT_VCLK_RATIO 28:28 /* RWIVF */
#define NV_PRAMDAC_PLL_COEFF_SELECT_VCLK_RATIO_DB1 0x00000000 /* RWI-V */
#define NV_PRAMDAC_PLL_COEFF_SELECT_VCLK_RATIO_DB2 0x00000001 /* RW--V */
#define NV_PRAMDAC_GENERAL_CONTROL 0x00680600 /* RW-4R */
#define NV_PRAMDAC_GENERAL_CONTROL_FF_COEFF 1:0 /* RWIVF */
#define NV_PRAMDAC_GENERAL_CONTROL_FF_COEFF_DEF 0x00000000 /* RWI-V */
#define NV_PRAMDAC_GENERAL_CONTROL_IDC_MODE 4:4 /* RWIVF */
#define NV_PRAMDAC_GENERAL_CONTROL_IDC_MODE_GAMMA 0x00000000 /* RWI-V */
#define NV_PRAMDAC_GENERAL_CONTROL_IDC_MODE_INDEX 0x00000001 /* RW--V */
#define NV_PRAMDAC_GENERAL_CONTROL_VGA_STATE 8:8 /* RWIVF */
#define NV_PRAMDAC_GENERAL_CONTROL_VGA_STATE_NOTSE 0x00000000 /* RWI-V */
#define NV_PRAMDAC_GENERAL_CONTROL_VGA_STATE_SEL 0x00000001 /* RW--V */
#define NV_PRAMDAC_GENERAL_CONTROL_565_MODE 12:12 /* RWIVF */
#define NV_PRAMDAC_GENERAL_CONTROL_565_MODE_NOTSEL 0x00000000 /* RWI-V */
#define NV_PRAMDAC_GENERAL_CONTROL_565_MODE_SEL 0x00000001 /* RW--V */
#define NV_PRAMDAC_GENERAL_CONTROL_BLK_PEDSTL 16:16 /* RWIVF */
#define NV_PRAMDAC_GENERAL_CONTROL_BLK_PEDSTL_OFF 0x00000000 /* RWI-V */
#define NV_PRAMDAC_GENERAL_CONTROL_BLK_PEDSTL_ON 0x00000001 /* RW--V */
#define NV_PRAMDAC_GENERAL_CONTROL_TERMINATION 17:17 /* RWIVF */
#define NV_PRAMDAC_GENERAL_CONTROL_TERMINATION_37OHM 0x00000000 /* RWI-V */
#define NV_PRAMDAC_GENERAL_CONTROL_TERMINATION_75OHM 0x00000001 /* RW--V */
#define NV_PRAMDAC_GENERAL_CONTROL_BPC 20:20 /* RWIVF */
#define NV_PRAMDAC_GENERAL_CONTROL_BPC_6BITS 0x00000000 /* RWI-V */
#define NV_PRAMDAC_GENERAL_CONTROL_BPC_8BITS 0x00000001 /* RW--V */
#define NV_PRAMDAC_GENERAL_CONTROL_DAC_SLEEP 24:24 /* RWIVF */
#define NV_PRAMDAC_GENERAL_CONTROL_DAC_SLEEP_DIS 0x00000000 /* RWI-V */
#define NV_PRAMDAC_GENERAL_CONTROL_DAC_SLEEP_EN 0x00000001 /* RW--V */
#define NV_PRAMDAC_GENERAL_CONTROL_PALETTE_CLK 28:28 /* RWIVF */
#define NV_PRAMDAC_GENERAL_CONTROL_PALETTE_CLK_EN 0x00000000 /* RWI-V */
#define NV_PRAMDAC_GENERAL_CONTROL_PALETTE_CLK_DIS 0x00000001 /* RW--V */
/* Master Control */
#define NV_PMC 0x00000FFF:0x00000000 /* RW--D */
#define NV_PMC_BOOT_0 0x00000000 /* R--4R */
#define NV_PMC_BOOT_0_MINOR_REVISION 3:0 /* C--VF */
#define NV_PMC_BOOT_0_MINOR_REVISION_0 0x00000000 /* C---V */
#define NV_PMC_BOOT_0_MAJOR_REVISION 7:4 /* C--VF */
#define NV_PMC_BOOT_0_MAJOR_REVISION_A 0x00000000 /* C---V */
#define NV_PMC_BOOT_0_MAJOR_REVISION_B 0x00000001 /* ----V */
#define NV_PMC_BOOT_0_IMPLEMENTATION 11:8 /* C--VF */
#define NV_PMC_BOOT_0_IMPLEMENTATION_NV4_0 0x00000000 /* C---V */
#define NV_PMC_BOOT_0_ARCHITECTURE 15:12 /* C--VF */
#define NV_PMC_BOOT_0_ARCHITECTURE_NV0 0x00000000 /* ----V */
#define NV_PMC_BOOT_0_ARCHITECTURE_NV1 0x00000001 /* ----V */
#define NV_PMC_BOOT_0_ARCHITECTURE_NV2 0x00000002 /* ----V */
#define NV_PMC_BOOT_0_ARCHITECTURE_NV3 0x00000003 /* ----V */
#define NV_PMC_BOOT_0_ARCHITECTURE_NV4 0x00000004 /* C---V */
#define NV_PMC_BOOT_0_FIB_REVISION 19:16 /* C--VF */
#define NV_PMC_BOOT_0_FIB_REVISION_0 0x00000000 /* C---V */
#define NV_PMC_BOOT_0_MASK_REVISION 23:20 /* C--VF */
#define NV_PMC_BOOT_0_MASK_REVISION_A 0x00000000 /* C---V */
#define NV_PMC_BOOT_0_MASK_REVISION_B 0x00000001 /* ----V */
#define NV_PMC_BOOT_0_MANUFACTURER 27:24 /* C--UF */
#define NV_PMC_BOOT_0_MANUFACTURER_NVIDIA 0x00000000 /* C---V */
#define NV_PMC_BOOT_0_FOUNDRY 31:28 /* C--VF */
#define NV_PMC_BOOT_0_FOUNDRY_SGS 0x00000000 /* ----V */
#define NV_PMC_BOOT_0_FOUNDRY_HELIOS 0x00000001 /* ----V */
#define NV_PMC_BOOT_0_FOUNDRY_TSMC 0x00000002 /* C---V */
#define NV_PMC_INTR_0 0x00000100 /* RW-4R */
#define NV_PMC_INTR_0_PMEDIA 4:4 /* R--VF */
#define NV_PMC_INTR_0_PMEDIA_NOT_PENDING 0x00000000 /* R---V */
#define NV_PMC_INTR_0_PMEDIA_PENDING 0x00000001 /* R---V */
#define NV_PMC_INTR_0_PFIFO 8:8 /* R--VF */
#define NV_PMC_INTR_0_PFIFO_NOT_PENDING 0x00000000 /* R---V */
#define NV_PMC_INTR_0_PFIFO_PENDING 0x00000001 /* R---V */
#define NV_PMC_INTR_0_PGRAPH 12:12 /* R--VF */
#define NV_PMC_INTR_0_PGRAPH_NOT_PENDING 0x00000000 /* R---V */
#define NV_PMC_INTR_0_PGRAPH_PENDING 0x00000001 /* R---V */
#define NV_PMC_INTR_0_PVIDEO 16:16 /* R--VF */
#define NV_PMC_INTR_0_PVIDEO_NOT_PENDING 0x00000000 /* R---V */
#define NV_PMC_INTR_0_PVIDEO_PENDING 0x00000001 /* R---V */
#define NV_PMC_INTR_0_PTIMER 20:20 /* R--VF */
#define NV_PMC_INTR_0_PTIMER_NOT_PENDING 0x00000000 /* R---V */
#define NV_PMC_INTR_0_PTIMER_PENDING 0x00000001 /* R---V */
#define NV_PMC_INTR_0_PCRTC 24:24 /* R--VF */
#define NV_PMC_INTR_0_PCRTC_NOT_PENDING 0x00000000 /* R---V */
#define NV_PMC_INTR_0_PCRTC_PENDING 0x00000001 /* R---V */
#define NV_PMC_INTR_0_PBUS 28:28 /* R--VF */
#define NV_PMC_INTR_0_PBUS_NOT_PENDING 0x00000000 /* R---V */
#define NV_PMC_INTR_0_PBUS_PENDING 0x00000001 /* R---V */
#define NV_PMC_INTR_0_SOFTWARE 31:31 /* RWIVF */
#define NV_PMC_INTR_0_SOFTWARE_NOT_PENDING 0x00000000 /* RWI-V */
#define NV_PMC_INTR_0_SOFTWARE_PENDING 0x00000001 /* RW--V */
#define NV_PMC_INTR_EN_0 0x00000140 /* RW-4R */
#define NV_PMC_INTR_EN_0_INTA 1:0 /* RWIVF */
#define NV_PMC_INTR_EN_0_INTA_DISABLED 0x00000000 /* RWI-V */
#define NV_PMC_INTR_EN_0_INTA_HARDWARE 0x00000001 /* RW--V */
#define NV_PMC_INTR_EN_0_INTA_SOFTWARE 0x00000002 /* RW--V */
#define NV_PMC_INTR_READ_0 0x00000160 /* R--4R */
#define NV_PMC_INTR_READ_0_INTA 0:0 /* R--VF */
#define NV_PMC_INTR_READ_0_INTA_LOW 0x00000000 /* R---V */
#define NV_PMC_INTR_READ_0_INTA_HIGH 0x00000001 /* R---V */
#define NV_PMC_ENABLE 0x00000200 /* RW-4R */
#define NV_PMC_ENABLE_PMEDIA 4:4 /* RWIVF */
#define NV_PMC_ENABLE_PMEDIA_DISABLED 0x00000000 /* RWI-V */
#define NV_PMC_ENABLE_PMEDIA_ENABLED 0x00000001 /* RW--V */
#define NV_PMC_ENABLE_PFIFO 8:8 /* RWIVF */
#define NV_PMC_ENABLE_PFIFO_DISABLED 0x00000000 /* RWI-V */
#define NV_PMC_ENABLE_PFIFO_ENABLED 0x00000001 /* RW--V */
#define NV_PMC_ENABLE_PGRAPH 12:12 /* RWIVF */
#define NV_PMC_ENABLE_PGRAPH_DISABLED 0x00000000 /* RWI-V */
#define NV_PMC_ENABLE_PGRAPH_ENABLED 0x00000001 /* RW--V */
#define NV_PMC_ENABLE_PPMI 16:16 /* RWIVF */
#define NV_PMC_ENABLE_PPMI_DISABLED 0x00000000 /* RWI-V */
#define NV_PMC_ENABLE_PPMI_ENABLED 0x00000001 /* RW--V */
#define NV_PMC_ENABLE_PFB 20:20 /* RWIVF */
#define NV_PMC_ENABLE_PFB_DISABLED 0x00000000 /* RW--V */
#define NV_PMC_ENABLE_PFB_ENABLED 0x00000001 /* RWI-V */
#define NV_PMC_ENABLE_PCRTC 24:24 /* RWIVF */
#define NV_PMC_ENABLE_PCRTC_DISABLED 0x00000000 /* RW--V */
#define NV_PMC_ENABLE_PCRTC_ENABLED 0x00000001 /* RWI-V */
#define NV_PMC_ENABLE_PVIDEO 28:28 /* RWIVF */
#define NV_PMC_ENABLE_PVIDEO_DISABLED 0x00000000 /* RWI-V */
#define NV_PMC_ENABLE_PVIDEO_ENABLED 0x00000001 /* RW--V */
/* dev_timer.ref */
#define NV_PTIMER 0x00009FFF:0x00009000 /* RW--D */
#define NV_PTIMER_INTR_0 0x00009100 /* RW-4R */
#define NV_PTIMER_INTR_0_ALARM 0:0 /* RWXVF */
#define NV_PTIMER_INTR_0_ALARM_NOT_PENDING 0x00000000 /* R---V */
#define NV_PTIMER_INTR_0_ALARM_PENDING 0x00000001 /* R---V */
#define NV_PTIMER_INTR_0_ALARM_RESET 0x00000001 /* -W--V */
#define NV_PTIMER_INTR_EN_0 0x00009140 /* RW-4R */
#define NV_PTIMER_INTR_EN_0_ALARM 0:0 /* RWIVF */
#define NV_PTIMER_INTR_EN_0_ALARM_DISABLED 0x00000000 /* RWI-V */
#define NV_PTIMER_INTR_EN_0_ALARM_ENABLED 0x00000001 /* RW--V */
#define NV_PTIMER_NUMERATOR 0x00009200 /* RW-4R */
#define NV_PTIMER_NUMERATOR_VALUE 15:0 /* RWIUF */
#define NV_PTIMER_NUMERATOR_VALUE_0 0x00000000 /* RWI-V */
#define NV_PTIMER_DENOMINATOR 0x00009210 /* RW-4R */
#define NV_PTIMER_DENOMINATOR_VALUE 15:0 /* RWIUF */
#define NV_PTIMER_DENOMINATOR_VALUE_0 0x00000000 /* RWI-V */
#define NV_PTIMER_TIME_0 0x00009400 /* RW-4R */
#define NV_PTIMER_TIME_0_NSEC 31:5 /* RWXUF */
#define NV_PTIMER_TIME_1 0x00009410 /* RW-4R */
#define NV_PTIMER_TIME_1_NSEC 28:0 /* RWXUF */
#define NV_PTIMER_ALARM_0 0x00009420 /* RW-4R */
#define NV_PTIMER_ALARM_0_NSEC 31:5 /* RWXUF */
/* dev_fifo.ref */
#define NV_PFIFO 0x00003FFF:0x00002000 /* RW--D */
#define NV_PFIFO_DELAY_0 0x00002040 /* RW-4R */
#define NV_PFIFO_DELAY_0_WAIT_RETRY 9:0 /* RWIUF */
#define NV_PFIFO_DELAY_0_WAIT_RETRY_0 0x00000000 /* RWI-V */
#define NV_PFIFO_DMA_TIMESLICE 0x00002044 /* RW-4R */
#define NV_PFIFO_DMA_TIMESLICE_SELECT 16:0 /* RWIUF */
#define NV_PFIFO_DMA_TIMESLICE_SELECT_1 0x00000000 /* RWI-V */
#define NV_PFIFO_DMA_TIMESLICE_SELECT_16K 0x00003fff /* RW--V */
#define NV_PFIFO_DMA_TIMESLICE_SELECT_32K 0x00007fff /* RW--V */
#define NV_PFIFO_DMA_TIMESLICE_SELECT_64K 0x0000ffff /* RW--V */
#define NV_PFIFO_DMA_TIMESLICE_SELECT_128K 0x0001ffff /* RW--V */
#define NV_PFIFO_DMA_TIMESLICE_TIMEOUT 24:24 /* RWIUF */
#define NV_PFIFO_DMA_TIMESLICE_TIMEOUT_DISABLED 0x00000000 /* RW--V */
#define NV_PFIFO_DMA_TIMESLICE_TIMEOUT_ENABLED 0x00000001 /* RWI-V */
#define NV_PFIFO_PIO_TIMESLICE 0x00002048 /* RW-4R */
#define NV_PFIFO_PIO_TIMESLICE_SELECT 16:0 /* RWIUF */
#define NV_PFIFO_PIO_TIMESLICE_SELECT_1 0x00000000 /* RWI-V */
#define NV_PFIFO_PIO_TIMESLICE_SELECT_16K 0x00003fff /* RW--V */
#define NV_PFIFO_PIO_TIMESLICE_SELECT_32K 0x00007fff /* RW--V */
#define NV_PFIFO_PIO_TIMESLICE_SELECT_64K 0x0000ffff /* RW--V */
#define NV_PFIFO_PIO_TIMESLICE_SELECT_128K 0x0001ffff /* RW--V */
#define NV_PFIFO_PIO_TIMESLICE_TIMEOUT 24:24 /* RWIUF */
#define NV_PFIFO_PIO_TIMESLICE_TIMEOUT_DISABLED 0x00000000 /* RW--V */
#define NV_PFIFO_PIO_TIMESLICE_TIMEOUT_ENABLED 0x00000001 /* RWI-V */
#define NV_PFIFO_TIMESLICE 0x0000204C /* RW-4R */
#define NV_PFIFO_TIMESLICE_TIMER 17:0 /* RWIUF */
#define NV_PFIFO_TIMESLICE_TIMER_EXPIRED 0x0003FFFF /* RWI-V */
#define NV_PFIFO_NEXT_CHANNEL 0x00002050 /* RW-4R */
#define NV_PFIFO_NEXT_CHANNEL_CHID 3:0 /* RWXUF */
#define NV_PFIFO_NEXT_CHANNEL_MODE 8:8 /* RWXVF */
#define NV_PFIFO_NEXT_CHANNEL_MODE_PIO 0x00000000 /* RW--V */
#define NV_PFIFO_NEXT_CHANNEL_MODE_DMA 0x00000001 /* RW--V */
#define NV_PFIFO_NEXT_CHANNEL_SWITCH 12:12 /* RWIVF */
#define NV_PFIFO_NEXT_CHANNEL_SWITCH_NOT_PENDING 0x00000000 /* RWI-V */
#define NV_PFIFO_NEXT_CHANNEL_SWITCH_PENDING 0x00000001 /* RW--V */
#define NV_PFIFO_DEBUG_0 0x00002080 /* R--4R */
#define NV_PFIFO_DEBUG_0_CACHE_ERROR0 0:0 /* R-XVF */
#define NV_PFIFO_DEBUG_0_CACHE_ERROR0_NOT_PENDING 0x00000000 /* R---V */
#define NV_PFIFO_DEBUG_0_CACHE_ERROR0_PENDING 0x00000001 /* R---V */
#define NV_PFIFO_DEBUG_0_CACHE_ERROR1 4:4 /* R-XVF */
#define NV_PFIFO_DEBUG_0_CACHE_ERROR1_NOT_PENDING 0x00000000 /* R---V */
#define NV_PFIFO_DEBUG_0_CACHE_ERROR1_PENDING 0x00000001 /* R---V */
#define NV_PFIFO_INTR_0 0x00002100 /* RW-4R */
#define NV_PFIFO_INTR_0_CACHE_ERROR 0:0 /* RWXVF */
#define NV_PFIFO_INTR_0_CACHE_ERROR_NOT_PENDING 0x00000000 /* R---V */
#define NV_PFIFO_INTR_0_CACHE_ERROR_PENDING 0x00000001 /* R---V */
#define NV_PFIFO_INTR_0_CACHE_ERROR_RESET 0x00000001 /* -W--V */
#define NV_PFIFO_INTR_0_RUNOUT 4:4 /* RWXVF */
#define NV_PFIFO_INTR_0_RUNOUT_NOT_PENDING 0x00000000 /* R---V */
#define NV_PFIFO_INTR_0_RUNOUT_PENDING 0x00000001 /* R---V */
#define NV_PFIFO_INTR_0_RUNOUT_RESET 0x00000001 /* -W--V */
#define NV_PFIFO_INTR_0_RUNOUT_OVERFLOW 8:8 /* RWXVF */
#define NV_PFIFO_INTR_0_RUNOUT_OVERFLOW_NOT_PENDING 0x00000000 /* R---V */
#define NV_PFIFO_INTR_0_RUNOUT_OVERFLOW_PENDING 0x00000001 /* R---V */
#define NV_PFIFO_INTR_0_RUNOUT_OVERFLOW_RESET 0x00000001 /* -W--V */
#define NV_PFIFO_INTR_0_DMA_PUSHER 12:12 /* RWXVF */
#define NV_PFIFO_INTR_0_DMA_PUSHER_NOT_PENDING 0x00000000 /* R---V */
#define NV_PFIFO_INTR_0_DMA_PUSHER_PENDING 0x00000001 /* R---V */
#define NV_PFIFO_INTR_0_DMA_PUSHER_RESET 0x00000001 /* -W--V */
#define NV_PFIFO_INTR_0_DMA_PT 16:16 /* RWXVF */
#define NV_PFIFO_INTR_0_DMA_PT_NOT_PENDING 0x00000000 /* R---V */
#define NV_PFIFO_INTR_0_DMA_PT_PENDING 0x00000001 /* R---V */
#define NV_PFIFO_INTR_0_DMA_PT_RESET 0x00000001 /* -W--V */
#define NV_PFIFO_INTR_EN_0 0x00002140 /* RW-4R */
#define NV_PFIFO_INTR_EN_0_CACHE_ERROR 0:0 /* RWIVF */
#define NV_PFIFO_INTR_EN_0_CACHE_ERROR_DISABLED 0x00000000 /* RWI-V */
#define NV_PFIFO_INTR_EN_0_CACHE_ERROR_ENABLED 0x00000001 /* RW--V */
#define NV_PFIFO_INTR_EN_0_RUNOUT 4:4 /* RWIVF */
#define NV_PFIFO_INTR_EN_0_RUNOUT_DISABLED 0x00000000 /* RWI-V */
#define NV_PFIFO_INTR_EN_0_RUNOUT_ENABLED 0x00000001 /* RW--V */
#define NV_PFIFO_INTR_EN_0_RUNOUT_OVERFLOW 8:8 /* RWIVF */
#define NV_PFIFO_INTR_EN_0_RUNOUT_OVERFLOW_DISABLED 0x00000000 /* RWI-V */
#define NV_PFIFO_INTR_EN_0_RUNOUT_OVERFLOW_ENABLED 0x00000001 /* RW--V */
#define NV_PFIFO_INTR_EN_0_DMA_PUSHER 12:12 /* RWIVF */
#define NV_PFIFO_INTR_EN_0_DMA_PUSHER_DISABLED 0x00000000 /* RWI-V */
#define NV_PFIFO_INTR_EN_0_DMA_PUSHER_ENABLED 0x00000001 /* RW--V */
#define NV_PFIFO_INTR_EN_0_DMA_PT 16:16 /* RWIVF */
#define NV_PFIFO_INTR_EN_0_DMA_PT_DISABLED 0x00000000 /* RWI-V */
#define NV_PFIFO_INTR_EN_0_DMA_PT_ENABLED 0x00000001 /* RW--V */
#define NV_PFIFO_RAMHT 0x00002210 /* RW-4R */
#define NV_PFIFO_RAMHT_BASE_ADDRESS 8:4 /* RWIUF */
#define NV_PFIFO_RAMHT_BASE_ADDRESS_10000 0x00000010 /* RWI-V */
#define NV_PFIFO_RAMHT_SIZE 17:16 /* RWIUF */
#define NV_PFIFO_RAMHT_SIZE_4K 0x00000000 /* RWI-V */
#define NV_PFIFO_RAMHT_SIZE_8K 0x00000001 /* RW--V */
#define NV_PFIFO_RAMHT_SIZE_16K 0x00000002 /* RW--V */
#define NV_PFIFO_RAMHT_SIZE_32K 0x00000003 /* RW--V */
#define NV_PFIFO_RAMHT_SEARCH 25:24 /* RWIUF */
#define NV_PFIFO_RAMHT_SEARCH_16 0x00000000 /* RWI-V */
#define NV_PFIFO_RAMHT_SEARCH_32 0x00000001 /* RW--V */
#define NV_PFIFO_RAMHT_SEARCH_64 0x00000002 /* RW--V */
#define NV_PFIFO_RAMHT_SEARCH_128 0x00000003 /* RW--V */
#define NV_PFIFO_RAMFC 0x00002214 /* RW-4R */
#define NV_PFIFO_RAMFC_BASE_ADDRESS 8:1 /* RWIUF */
#define NV_PFIFO_RAMFC_BASE_ADDRESS_11000 0x00000088 /* RWI-V */
#define NV_PFIFO_RAMRO 0x00002218 /* RW-4R */
#define NV_PFIFO_RAMRO_BASE_ADDRESS 8:1 /* RWIUF */
#define NV_PFIFO_RAMRO_BASE_ADDRESS_11200 0x00000089 /* RWI-V */
#define NV_PFIFO_RAMRO_BASE_ADDRESS_12000 0x00000090 /* RW--V */
#define NV_PFIFO_RAMRO_SIZE 16:16 /* RWIVF */
#define NV_PFIFO_RAMRO_SIZE_512 0x00000000 /* RWI-V */
#define NV_PFIFO_RAMRO_SIZE_8K 0x00000001 /* RW--V */
#define NV_PFIFO_CACHES 0x00002500 /* RW-4R */
#define NV_PFIFO_CACHES_REASSIGN 0:0 /* RWIVF */
#define NV_PFIFO_CACHES_REASSIGN_DISABLED 0x00000000 /* RWI-V */
#define NV_PFIFO_CACHES_REASSIGN_ENABLED 0x00000001 /* RW--V */
#define NV_PFIFO_CACHES_DMA_SUSPEND 4:4 /* R--VF */
#define NV_PFIFO_CACHES_DMA_SUSPEND_IDLE 0x00000000 /* R---V */
#define NV_PFIFO_CACHES_DMA_SUSPEND_BUSY 0x00000001 /* R---V */
#define NV_PFIFO_MODE 0x00002504 /* RW-4R */
#define NV_PFIFO_MODE_CHANNEL_0 0:0 /* RWIVF */
#define NV_PFIFO_MODE_CHANNEL_0_PIO 0x00000000 /* RWI-V */
#define NV_PFIFO_MODE_CHANNEL_0_DMA 0x00000001 /* RW--V */
#define NV_PFIFO_MODE_CHANNEL_1 1:1 /* RWIVF */
#define NV_PFIFO_MODE_CHANNEL_1_PIO 0x00000000 /* RWI-V */
#define NV_PFIFO_MODE_CHANNEL_1_DMA 0x00000001 /* RW--V */
#define NV_PFIFO_MODE_CHANNEL_2 2:2 /* RWIVF */
#define NV_PFIFO_MODE_CHANNEL_2_PIO 0x00000000 /* RWI-V */
#define NV_PFIFO_MODE_CHANNEL_2_DMA 0x00000001 /* RW--V */
#define NV_PFIFO_MODE_CHANNEL_3 3:3 /* RWIVF */
#define NV_PFIFO_MODE_CHANNEL_3_PIO 0x00000000 /* RWI-V */
#define NV_PFIFO_MODE_CHANNEL_3_DMA 0x00000001 /* RW--V */
#define NV_PFIFO_MODE_CHANNEL_4 4:4 /* RWIVF */
#define NV_PFIFO_MODE_CHANNEL_4_PIO 0x00000000 /* RWI-V */
#define NV_PFIFO_MODE_CHANNEL_4_DMA 0x00000001 /* RW--V */
#define NV_PFIFO_MODE_CHANNEL_5 5:5 /* RWIVF */
#define NV_PFIFO_MODE_CHANNEL_5_PIO 0x00000000 /* RWI-V */
#define NV_PFIFO_MODE_CHANNEL_5_DMA 0x00000001 /* RW--V */
#define NV_PFIFO_MODE_CHANNEL_6 6:6 /* RWIVF */
#define NV_PFIFO_MODE_CHANNEL_6_PIO 0x00000000 /* RWI-V */
#define NV_PFIFO_MODE_CHANNEL_6_DMA 0x00000001 /* RW--V */
#define NV_PFIFO_MODE_CHANNEL_7 7:7 /* RWIVF */
#define NV_PFIFO_MODE_CHANNEL_7_PIO 0x00000000 /* RWI-V */
#define NV_PFIFO_MODE_CHANNEL_7_DMA 0x00000001 /* RW--V */
#define NV_PFIFO_MODE_CHANNEL_8 8:8 /* RWIVF */
#define NV_PFIFO_MODE_CHANNEL_8_PIO 0x00000000 /* RWI-V */
#define NV_PFIFO_MODE_CHANNEL_8_DMA 0x00000001 /* RW--V */
#define NV_PFIFO_MODE_CHANNEL_9 9:9 /* RWIVF */
#define NV_PFIFO_MODE_CHANNEL_9_PIO 0x00000000 /* RWI-V */
#define NV_PFIFO_MODE_CHANNEL_9_DMA 0x00000001 /* RW--V */
#define NV_PFIFO_MODE_CHANNEL_10 10:10 /* RWIVF */
#define NV_PFIFO_MODE_CHANNEL_10_PIO 0x00000000 /* RWI-V */
#define NV_PFIFO_MODE_CHANNEL_10_DMA 0x00000001 /* RW--V */
#define NV_PFIFO_MODE_CHANNEL_11 11:11 /* RWIVF */
#define NV_PFIFO_MODE_CHANNEL_11_PIO 0x00000000 /* RWI-V */
#define NV_PFIFO_MODE_CHANNEL_11_DMA 0x00000001 /* RW--V */
#define NV_PFIFO_MODE_CHANNEL_12 12:12 /* RWIVF */
#define NV_PFIFO_MODE_CHANNEL_12_PIO 0x00000000 /* RWI-V */
#define NV_PFIFO_MODE_CHANNEL_12_DMA 0x00000001 /* RW--V */
#define NV_PFIFO_MODE_CHANNEL_13 13:13 /* RWIVF */
#define NV_PFIFO_MODE_CHANNEL_13_PIO 0x00000000 /* RWI-V */
#define NV_PFIFO_MODE_CHANNEL_13_DMA 0x00000001 /* RW--V */
#define NV_PFIFO_MODE_CHANNEL_14 14:14 /* RWIVF */
#define NV_PFIFO_MODE_CHANNEL_14_PIO 0x00000000 /* RWI-V */
#define NV_PFIFO_MODE_CHANNEL_14_DMA 0x00000001 /* RW--V */
#define NV_PFIFO_MODE_CHANNEL_15 15:15 /* RWIVF */
#define NV_PFIFO_MODE_CHANNEL_15_PIO 0x00000000 /* RWI-V */
#define NV_PFIFO_MODE_CHANNEL_15_DMA 0x00000001 /* RW--V */
#define NV_PFIFO_DMA 0x00002508 /* RW-4R */
#define NV_PFIFO_DMA_CHANNEL_0 0:0 /* RWIVF */
#define NV_PFIFO_DMA_CHANNEL_0_NOT_PENDING 0x00000000 /* RWI-V */
#define NV_PFIFO_DMA_CHANNEL_0_PENDING 0x00000001 /* RW--V */
#define NV_PFIFO_DMA_CHANNEL_1 1:1 /* RWIVF */
#define NV_PFIFO_DMA_CHANNEL_1_NOT_PENDING 0x00000000 /* RWI-V */
#define NV_PFIFO_DMA_CHANNEL_1_PENDING 0x00000001 /* RW--V */
#define NV_PFIFO_DMA_CHANNEL_2 2:2 /* RWIVF */
#define NV_PFIFO_DMA_CHANNEL_2_NOT_PENDING 0x00000000 /* RWI-V */
#define NV_PFIFO_DMA_CHANNEL_2_PENDING 0x00000001 /* RW--V */
#define NV_PFIFO_DMA_CHANNEL_3 3:3 /* RWIVF */
#define NV_PFIFO_DMA_CHANNEL_3_NOT_PENDING 0x00000000 /* RWI-V */
#define NV_PFIFO_DMA_CHANNEL_3_PENDING 0x00000001 /* RW--V */
#define NV_PFIFO_DMA_CHANNEL_4 4:4 /* RWIVF */
#define NV_PFIFO_DMA_CHANNEL_4_NOT_PENDING 0x00000000 /* RWI-V */
#define NV_PFIFO_DMA_CHANNEL_4_PENDING 0x00000001 /* RW--V */
#define NV_PFIFO_DMA_CHANNEL_5 5:5 /* RWIVF */
#define NV_PFIFO_DMA_CHANNEL_5_NOT_PENDING 0x00000000 /* RWI-V */
#define NV_PFIFO_DMA_CHANNEL_5_PENDING 0x00000001 /* RW--V */
#define NV_PFIFO_DMA_CHANNEL_6 6:6 /* RWIVF */
#define NV_PFIFO_DMA_CHANNEL_6_NOT_PENDING 0x00000000 /* RWI-V */
#define NV_PFIFO_DMA_CHANNEL_6_PENDING 0x00000001 /* RW--V */
#define NV_PFIFO_DMA_CHANNEL_7 7:7 /* RWIVF */
#define NV_PFIFO_DMA_CHANNEL_7_NOT_PENDING 0x00000000 /* RWI-V */
#define NV_PFIFO_DMA_CHANNEL_7_PENDING 0x00000001 /* RW--V */
#define NV_PFIFO_DMA_CHANNEL_8 8:8 /* RWIVF */
#define NV_PFIFO_DMA_CHANNEL_8_NOT_PENDING 0x00000000 /* RWI-V */
#define NV_PFIFO_DMA_CHANNEL_8_PENDING 0x00000001 /* RW--V */
#define NV_PFIFO_DMA_CHANNEL_9 9:9 /* RWIVF */
#define NV_PFIFO_DMA_CHANNEL_9_NOT_PENDING 0x00000000 /* RWI-V */
#define NV_PFIFO_DMA_CHANNEL_9_PENDING 0x00000001 /* RW--V */
#define NV_PFIFO_DMA_CHANNEL_10 10:10 /* RWIVF */
#define NV_PFIFO_DMA_CHANNEL_10_NOT_PENDING 0x00000000 /* RWI-V */
#define NV_PFIFO_DMA_CHANNEL_10_PENDING 0x00000001 /* RW--V */
#define NV_PFIFO_DMA_CHANNEL_11 11:11 /* RWIVF */
#define NV_PFIFO_DMA_CHANNEL_11_NOT_PENDING 0x00000000 /* RWI-V */
#define NV_PFIFO_DMA_CHANNEL_11_PENDING 0x00000001 /* RW--V */
#define NV_PFIFO_DMA_CHANNEL_12 12:12 /* RWIVF */
#define NV_PFIFO_DMA_CHANNEL_12_NOT_PENDING 0x00000000 /* RWI-V */
#define NV_PFIFO_DMA_CHANNEL_12_PENDING 0x00000001 /* RW--V */
#define NV_PFIFO_DMA_CHANNEL_13 13:13 /* RWIVF */
#define NV_PFIFO_DMA_CHANNEL_13_NOT_PENDING 0x00000000 /* RWI-V */
#define NV_PFIFO_DMA_CHANNEL_13_PENDING 0x00000001 /* RW--V */
#define NV_PFIFO_DMA_CHANNEL_14 14:14 /* RWIVF */
#define NV_PFIFO_DMA_CHANNEL_14_NOT_PENDING 0x00000000 /* RWI-V */
#define NV_PFIFO_DMA_CHANNEL_14_PENDING 0x00000001 /* RW--V */
#define NV_PFIFO_DMA_CHANNEL_15 15:15 /* RWIVF */
#define NV_PFIFO_DMA_CHANNEL_15_NOT_PENDING 0x00000000 /* RWI-V */
#define NV_PFIFO_DMA_CHANNEL_15_PENDING 0x00000001 /* RW--V */
#define NV_PFIFO_SIZE 0x0000250C /* RW-4R */
#define NV_PFIFO_SIZE_CHANNEL_0 0:0 /* RWIVF */
#define NV_PFIFO_SIZE_CHANNEL_0_124_BYTES 0x00000000 /* RWI-V */
#define NV_PFIFO_SIZE_CHANNEL_0_512_BYTES 0x00000001 /* RW--V */
#define NV_PFIFO_SIZE_CHANNEL_1 1:1 /* RWIVF */
#define NV_PFIFO_SIZE_CHANNEL_1_124_BYTES 0x00000000 /* RWI-V */
#define NV_PFIFO_SIZE_CHANNEL_1_512_BYTES 0x00000001 /* RW--V */
#define NV_PFIFO_SIZE_CHANNEL_2 2:2 /* RWIVF */
#define NV_PFIFO_SIZE_CHANNEL_2_124_BYTES 0x00000000 /* RWI-V */
#define NV_PFIFO_SIZE_CHANNEL_2_512_BYTES 0x00000001 /* RW--V */
#define NV_PFIFO_SIZE_CHANNEL_3 3:3 /* RWIVF */
#define NV_PFIFO_SIZE_CHANNEL_3_124_BYTES 0x00000000 /* RWI-V */
#define NV_PFIFO_SIZE_CHANNEL_3_512_BYTES 0x00000001 /* RW--V */
#define NV_PFIFO_SIZE_CHANNEL_4 4:4 /* RWIVF */
#define NV_PFIFO_SIZE_CHANNEL_4_124_BYTES 0x00000000 /* RWI-V */
#define NV_PFIFO_SIZE_CHANNEL_4_512_BYTES 0x00000001 /* RW--V */
#define NV_PFIFO_SIZE_CHANNEL_5 5:5 /* RWIVF */
#define NV_PFIFO_SIZE_CHANNEL_5_124_BYTES 0x00000000 /* RWI-V */
#define NV_PFIFO_SIZE_CHANNEL_5_512_BYTES 0x00000001 /* RW--V */
#define NV_PFIFO_SIZE_CHANNEL_6 6:6 /* RWIVF */
#define NV_PFIFO_SIZE_CHANNEL_6_124_BYTES 0x00000000 /* RWI-V */
#define NV_PFIFO_SIZE_CHANNEL_6_512_BYTES 0x00000001 /* RW--V */
#define NV_PFIFO_SIZE_CHANNEL_7 7:7 /* RWIVF */
#define NV_PFIFO_SIZE_CHANNEL_7_124_BYTES 0x00000000 /* RWI-V */
#define NV_PFIFO_SIZE_CHANNEL_7_512_BYTES 0x00000001 /* RW--V */
#define NV_PFIFO_SIZE_CHANNEL_8 8:8 /* RWIVF */
#define NV_PFIFO_SIZE_CHANNEL_8_124_BYTES 0x00000000 /* RWI-V */
#define NV_PFIFO_SIZE_CHANNEL_8_512_BYTES 0x00000001 /* RW--V */
#define NV_PFIFO_SIZE_CHANNEL_9 9:9 /* RWIVF */
#define NV_PFIFO_SIZE_CHANNEL_9_124_BYTES 0x00000000 /* RWI-V */
#define NV_PFIFO_SIZE_CHANNEL_9_512_BYTES 0x00000001 /* RW--V */
#define NV_PFIFO_SIZE_CHANNEL_10 10:10 /* RWIVF */
#define NV_PFIFO_SIZE_CHANNEL_10_124_BYTES 0x00000000 /* RWI-V */
#define NV_PFIFO_SIZE_CHANNEL_10_512_BYTES 0x00000001 /* RW--V */
#define NV_PFIFO_SIZE_CHANNEL_11 11:11 /* RWIVF */
#define NV_PFIFO_SIZE_CHANNEL_11_124_BYTES 0x00000000 /* RWI-V */
#define NV_PFIFO_SIZE_CHANNEL_11_512_BYTES 0x00000001 /* RW--V */
#define NV_PFIFO_SIZE_CHANNEL_12 12:12 /* RWIVF */
#define NV_PFIFO_SIZE_CHANNEL_12_124_BYTES 0x00000000 /* RWI-V */
#define NV_PFIFO_SIZE_CHANNEL_12_512_BYTES 0x00000001 /* RW--V */
#define NV_PFIFO_SIZE_CHANNEL_13 13:13 /* RWIVF */
#define NV_PFIFO_SIZE_CHANNEL_13_124_BYTES 0x00000000 /* RWI-V */
#define NV_PFIFO_SIZE_CHANNEL_13_512_BYTES 0x00000001 /* RW--V */
#define NV_PFIFO_SIZE_CHANNEL_14 14:14 /* RWIVF */
#define NV_PFIFO_SIZE_CHANNEL_14_124_BYTES 0x00000000 /* RWI-V */
#define NV_PFIFO_SIZE_CHANNEL_14_512_BYTES 0x00000001 /* RW--V */
#define NV_PFIFO_SIZE_CHANNEL_15 15:15 /* RWIVF */
#define NV_PFIFO_SIZE_CHANNEL_15_124_BYTES 0x00000000 /* RWI-V */
#define NV_PFIFO_SIZE_CHANNEL_15_512_BYTES 0x00000001 /* RW--V */
#define NV_PFIFO_CACHE0_PUSH0 0x00003000 /* RW-4R */
#define NV_PFIFO_CACHE0_PUSH0_ACCESS 0:0 /* RWIVF */
#define NV_PFIFO_CACHE0_PUSH0_ACCESS_DISABLED 0x00000000 /* RWI-V */
#define NV_PFIFO_CACHE0_PUSH0_ACCESS_ENABLED 0x00000001 /* RW--V */
#define NV_PFIFO_CACHE1_PUSH0 0x00003200 /* RW-4R */
#define NV_PFIFO_CACHE1_PUSH0_ACCESS 0:0 /* RWIVF */
#define NV_PFIFO_CACHE1_PUSH0_ACCESS_DISABLED 0x00000000 /* RWI-V */
#define NV_PFIFO_CACHE1_PUSH0_ACCESS_ENABLED 0x00000001 /* RW--V */
#define NV_PFIFO_CACHE0_PUSH1 0x00003004 /* RW-4R */
#define NV_PFIFO_CACHE0_PUSH1_CHID 3:0 /* RWXUF */
#define NV_PFIFO_CACHE1_PUSH1 0x00003204 /* RW-4R */
#define NV_PFIFO_CACHE1_PUSH1_CHID 3:0 /* RWXUF */
#define NV_PFIFO_CACHE1_PUSH1_MODE 8:8 /* RWIVF */
#define NV_PFIFO_CACHE1_PUSH1_MODE_PIO 0x00000000 /* RWI-V */
#define NV_PFIFO_CACHE1_PUSH1_MODE_DMA 0x00000001 /* RW--V */
#define NV_PFIFO_CACHE1_DMA_PUSH 0x00003220 /* RW-4R */
#define NV_PFIFO_CACHE1_DMA_PUSH_ACCESS 0:0 /* RWIVF */
#define NV_PFIFO_CACHE1_DMA_PUSH_ACCESS_DISABLED 0x00000000 /* RWI-V */
#define NV_PFIFO_CACHE1_DMA_PUSH_ACCESS_ENABLED 0x00000001 /* RW--V */
#define NV_PFIFO_CACHE1_DMA_PUSH_STATE 4:4 /* R--VF */
#define NV_PFIFO_CACHE1_DMA_PUSH_STATE_IDLE 0x00000000 /* R---V */
#define NV_PFIFO_CACHE1_DMA_PUSH_STATE_BUSY 0x00000001 /* R---V */
#define NV_PFIFO_CACHE1_DMA_PUSH_BUFFER 8:8 /* R--VF */
#define NV_PFIFO_CACHE1_DMA_PUSH_BUFFER_NOT_EMPTY 0x00000000 /* R---V */
#define NV_PFIFO_CACHE1_DMA_PUSH_BUFFER_EMPTY 0x00000001 /* R---V */
#define NV_PFIFO_CACHE1_DMA_PUSH_STATUS 12:12 /* RWIVF */
#define NV_PFIFO_CACHE1_DMA_PUSH_STATUS_RUNNING 0x00000000 /* RWI-V */
#define NV_PFIFO_CACHE1_DMA_PUSH_STATUS_SUSPENDED 0x00000001 /* RW--V */
#define NV_PFIFO_CACHE1_DMA_FETCH 0x00003224 /* RW-4R */
#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG 7:3 /* RWIUF */
#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_8_BYTES 0x00000000 /* RW--V */
#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_16_BYTES 0x00000001 /* RW--V */
#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_24_BYTES 0x00000002 /* RW--V */
#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_32_BYTES 0x00000003 /* RW--V */
#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_40_BYTES 0x00000004 /* RW--V */
#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_48_BYTES 0x00000005 /* RW--V */
#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_56_BYTES 0x00000006 /* RW--V */
#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_64_BYTES 0x00000007 /* RW--V */
#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_72_BYTES 0x00000008 /* RW--V */
#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_80_BYTES 0x00000009 /* RW--V */
#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_88_BYTES 0x0000000A /* RW--V */
#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_96_BYTES 0x0000000B /* RW--V */
#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_104_BYTES 0x0000000C /* RW--V */
#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_112_BYTES 0x0000000D /* RW--V */
#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_120_BYTES 0x0000000E /* RW--V */
#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES 0x0000000F /* RWI-V */
#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_136_BYTES 0x00000010 /* RW--V */
#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_144_BYTES 0x00000011 /* RW--V */
#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_152_BYTES 0x00000012 /* RW--V */
#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_160_BYTES 0x00000013 /* RW--V */
#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_168_BYTES 0x00000014 /* RW--V */
#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_176_BYTES 0x00000015 /* RW--V */
#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_184_BYTES 0x00000016 /* RW--V */
#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_192_BYTES 0x00000017 /* RW--V */
#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_200_BYTES 0x00000018 /* RW--V */
#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_208_BYTES 0x00000019 /* RW--V */
#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_216_BYTES 0x0000001A /* RW--V */
#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_224_BYTES 0x0000001B /* RW--V */
#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_232_BYTES 0x0000001C /* RW--V */
#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_240_BYTES 0x0000001D /* RW--V */
#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_248_BYTES 0x0000001E /* RW--V */
#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_256_BYTES 0x0000001F /* RW--V */
#define NV_PFIFO_CACHE1_DMA_FETCH_SIZE 15:13 /* RWIUF */
#define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_32_BYTES 0x00000000 /* RW--V */
#define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_64_BYTES 0x00000001 /* RW--V */
#define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_96_BYTES 0x00000002 /* RW--V */
#define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES 0x00000003 /* RWI-V */
#define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_160_BYTES 0x00000004 /* RW--V */
#define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_192_BYTES 0x00000005 /* RW--V */
#define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_224_BYTES 0x00000006 /* RW--V */
#define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_256_BYTES 0x00000007 /* RW--V */
#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS 19:16 /* RWIUF */
#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_0 0x00000000 /* RWI-V */
#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_1 0x00000001 /* RW--V */
#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_2 0x00000002 /* RW--V */
#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_3 0x00000003 /* RW--V */
#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_4 0x00000004 /* RW--V */
#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_5 0x00000005 /* RW--V */
#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_6 0x00000006 /* RW--V */
#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_7 0x00000007 /* RW--V */
#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8 0x00000008 /* RW--V */
#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_9 0x00000009 /* RW--V */
#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_10 0x0000000A /* RW--V */
#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_11 0x0000000B /* RW--V */
#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_12 0x0000000C /* RW--V */
#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_13 0x0000000D /* RW--V */
#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_14 0x0000000E /* RW--V */
#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_15 0x0000000F /* RW--V */
#define NV_PFIFO_CACHE1_DMA_PUT 0x00003240 /* RW-4R */
#define NV_PFIFO_CACHE1_DMA_PUT_OFFSET 28:2 /* RWXUF */
#define NV_PFIFO_CACHE1_DMA_GET 0x00003244 /* RW-4R */
#define NV_PFIFO_CACHE1_DMA_GET_OFFSET 28:2 /* RWXUF */
#define NV_PFIFO_CACHE1_DMA_STATE 0x00003228 /* RW-4R */
#define NV_PFIFO_CACHE1_DMA_STATE_METHOD 12:2 /* RWXUF */
#define NV_PFIFO_CACHE1_DMA_STATE_SUBCHANNEL 15:13 /* RWXUF */
#define NV_PFIFO_CACHE1_DMA_STATE_METHOD_COUNT 28:18 /* RWIUF */
#define NV_PFIFO_CACHE1_DMA_STATE_METHOD_COUNT_0 0x00000000 /* RWI-V */
#define NV_PFIFO_CACHE1_DMA_STATE_ERROR 31:30 /* RWXUF */
#define NV_PFIFO_CACHE1_DMA_STATE_ERROR_NONE 0x00000000 /* RW--V */
#define NV_PFIFO_CACHE1_DMA_STATE_ERROR_NON_CACHE 0x00000001 /* RW--V */
#define NV_PFIFO_CACHE1_DMA_STATE_ERROR_RESERVED_CMD 0x00000002 /* RW--V */
#define NV_PFIFO_CACHE1_DMA_STATE_ERROR_PROTECTION 0x00000003 /* RW--V */
#define NV_PFIFO_CACHE1_DMA_INSTANCE 0x0000322C /* RW-4R */
#define NV_PFIFO_CACHE1_DMA_INSTANCE_ADDRESS 15:0 /* RWXUF */
#define NV_PFIFO_CACHE1_DMA_CTL 0x00003230 /* RW-4R */
#define NV_PFIFO_CACHE1_DMA_CTL_ADJUST 11:2 /* RWXUF */
#define NV_PFIFO_CACHE1_DMA_CTL_PAGE_TABLE 12:12 /* RWXUF */
#define NV_PFIFO_CACHE1_DMA_CTL_PAGE_TABLE_NOT_PRESENT 0x00000000 /* RW--V */
#define NV_PFIFO_CACHE1_DMA_CTL_PAGE_TABLE_PRESENT 0x00000001 /* RW--V */
#define NV_PFIFO_CACHE1_DMA_CTL_PAGE_ENTRY 13:13 /* RWXUF */
#define NV_PFIFO_CACHE1_DMA_CTL_PAGE_ENTRY_NOT_LINEAR 0x00000000 /* RW--V */
#define NV_PFIFO_CACHE1_DMA_CTL_PAGE_ENTRY_LINEAR 0x00000001 /* RW--V */
#define NV_PFIFO_CACHE1_DMA_CTL_TARGET_NODE 17:16 /* RWXUF */
#define NV_PFIFO_CACHE1_DMA_CTL_TARGET_NODE_PCI 0x00000002 /* RW--V */
#define NV_PFIFO_CACHE1_DMA_CTL_TARGET_NODE_AGP 0x00000003 /* RW--V */
#define NV_PFIFO_CACHE1_DMA_CTL_AT_INFO 31:31 /* RWIUF */
#define NV_PFIFO_CACHE1_DMA_CTL_AT_INFO_INVALID 0x00000000 /* RW--V */
#define NV_PFIFO_CACHE1_DMA_CTL_AT_INFO_VALID 0x00000001 /* RWI-V */
#define NV_PFIFO_CACHE1_DMA_LIMIT 0x00003234 /* RW-4R */
#define NV_PFIFO_CACHE1_DMA_LIMIT_OFFSET 28:2 /* RWXUF */
#define NV_PFIFO_CACHE1_DMA_TLB_TAG 0x00003238 /* RW-4R */
#define NV_PFIFO_CACHE1_DMA_TLB_TAG_ADDRESS 28:12 /* RWXUF */
#define NV_PFIFO_CACHE1_DMA_TLB_TAG_STATE 0:0 /* RWIUF */
#define NV_PFIFO_CACHE1_DMA_TLB_TAG_STATE_INVALID 0x00000000 /* RWI-V */
#define NV_PFIFO_CACHE1_DMA_TLB_TAG_STATE_VALID 0x00000001 /* RW--V */
#define NV_PFIFO_CACHE1_DMA_TLB_PTE 0x0000323C /* RW-4R */
#define NV_PFIFO_CACHE1_DMA_TLB_PTE_FRAME_ADDRESS 31:12 /* RWXUF */
#define NV_PFIFO_CACHE0_PULL0 0x00003050 /* RW-4R */
#define NV_PFIFO_CACHE0_PULL0_ACCESS 0:0 /* RWIVF */
#define NV_PFIFO_CACHE0_PULL0_ACCESS_DISABLED 0x00000000 /* RWI-V */
#define NV_PFIFO_CACHE0_PULL0_ACCESS_ENABLED 0x00000001 /* RW--V */
#define NV_PFIFO_CACHE0_PULL0_HASH 4:4 /* R-XVF */
#define NV_PFIFO_CACHE0_PULL0_HASH_SUCCEEDED 0x00000000 /* R---V */
#define NV_PFIFO_CACHE0_PULL0_HASH_FAILED 0x00000001 /* R---V */
#define NV_PFIFO_CACHE0_PULL0_DEVICE 8:8 /* R-XVF */
#define NV_PFIFO_CACHE0_PULL0_DEVICE_HARDWARE 0x00000000 /* R---V */
#define NV_PFIFO_CACHE0_PULL0_DEVICE_SOFTWARE 0x00000001 /* R---V */
#define NV_PFIFO_CACHE0_PULL0_HASH_STATE 12:12 /* R-XVF */
#define NV_PFIFO_CACHE0_PULL0_HASH_STATE_IDLE 0x00000000 /* R---V */
#define NV_PFIFO_CACHE0_PULL0_HASH_STATE_BUSY 0x00000001 /* R---V */
#define NV_PFIFO_CACHE1_PULL0 0x00003250 /* RW-4R */
#define NV_PFIFO_CACHE1_PULL0_ACCESS 0:0 /* RWIVF */
#define NV_PFIFO_CACHE1_PULL0_ACCESS_DISABLED 0x00000000 /* RWI-V */
#define NV_PFIFO_CACHE1_PULL0_ACCESS_ENABLED 0x00000001 /* RW--V */
#define NV_PFIFO_CACHE1_PULL0_HASH 4:4 /* R-XVF */
#define NV_PFIFO_CACHE1_PULL0_HASH_SUCCEEDED 0x00000000 /* R---V */
#define NV_PFIFO_CACHE1_PULL0_HASH_FAILED 0x00000001 /* R---V */
#define NV_PFIFO_CACHE1_PULL0_DEVICE 8:8 /* R-XVF */
#define NV_PFIFO_CACHE1_PULL0_DEVICE_HARDWARE 0x00000000 /* R---V */
#define NV_PFIFO_CACHE1_PULL0_DEVICE_SOFTWARE 0x00000001 /* R---V */
#define NV_PFIFO_CACHE1_PULL0_HASH_STATE 12:12 /* R-XVF */
#define NV_PFIFO_CACHE1_PULL0_HASH_STATE_IDLE 0x00000000 /* R---V */
#define NV_PFIFO_CACHE1_PULL0_HASH_STATE_BUSY 0x00000001 /* R---V */
#define NV_PFIFO_CACHE0_PULL1 0x00003054 /* RW-4R */
#define NV_PFIFO_CACHE0_PULL1_ENGINE 1:0 /* RWXUF */
#define NV_PFIFO_CACHE0_PULL1_ENGINE_SW 0x00000000 /* RW--V */
#define NV_PFIFO_CACHE0_PULL1_ENGINE_GRAPHICS 0x00000001 /* RW--V */
#define NV_PFIFO_CACHE0_PULL1_ENGINE_DVD 0x00000002 /* RW--V */
#define NV_PFIFO_CACHE1_PULL1 0x00003254 /* RW-4R */
#define NV_PFIFO_CACHE1_PULL1_ENGINE 1:0 /* RWXUF */
#define NV_PFIFO_CACHE1_PULL1_ENGINE_SW 0x00000000 /* RW--V */
#define NV_PFIFO_CACHE1_PULL1_ENGINE_GRAPHICS 0x00000001 /* RW--V */
#define NV_PFIFO_CACHE1_PULL1_ENGINE_DVD 0x00000002 /* RW--V */
#define NV_PFIFO_CACHE0_HASH 0x00003058 /* RW-4R */
#define NV_PFIFO_CACHE0_HASH_INSTANCE 15:0 /* RWXUF */
#define NV_PFIFO_CACHE0_HASH_VALID 16:16 /* RWXVF */
#define NV_PFIFO_CACHE1_HASH 0x00003258 /* RW-4R */
#define NV_PFIFO_CACHE1_HASH_INSTANCE 15:0 /* RWXUF */
#define NV_PFIFO_CACHE1_HASH_VALID 16:16 /* RWXVF */
#define NV_PFIFO_CACHE0_STATUS 0x00003014 /* R--4R */
#define NV_PFIFO_CACHE0_STATUS_LOW_MARK 4:4 /* R--VF */
#define NV_PFIFO_CACHE0_STATUS_LOW_MARK_NOT_EMPTY 0x00000000 /* R---V */
#define NV_PFIFO_CACHE0_STATUS_LOW_MARK_EMPTY 0x00000001 /* R---V */
#define NV_PFIFO_CACHE0_STATUS_HIGH_MARK 8:8 /* R--VF */
#define NV_PFIFO_CACHE0_STATUS_HIGH_MARK_NOT_FULL 0x00000000 /* R---V */
#define NV_PFIFO_CACHE0_STATUS_HIGH_MARK_FULL 0x00000001 /* R---V */
#define NV_PFIFO_CACHE1_STATUS 0x00003214 /* R--4R */
#define NV_PFIFO_CACHE1_STATUS_LOW_MARK 4:4 /* R--VF */
#define NV_PFIFO_CACHE1_STATUS_LOW_MARK_NOT_EMPTY 0x00000000 /* R---V */
#define NV_PFIFO_CACHE1_STATUS_LOW_MARK_EMPTY 0x00000001 /* R---V */
#define NV_PFIFO_CACHE1_STATUS_HIGH_MARK 8:8 /* R--VF */
#define NV_PFIFO_CACHE1_STATUS_HIGH_MARK_NOT_FULL 0x00000000 /* R---V */
#define NV_PFIFO_CACHE1_STATUS_HIGH_MARK_FULL 0x00000001 /* R---V */
#define NV_PFIFO_CACHE1_STATUS1 0x00003218 /* R--4R */
#define NV_PFIFO_CACHE1_STATUS1_RANOUT 0:0 /* R-XVF */
#define NV_PFIFO_CACHE1_STATUS1_RANOUT_FALSE 0x00000000 /* R---V */
#define NV_PFIFO_CACHE1_STATUS1_RANOUT_TRUE 0x00000001 /* R---V */
#define NV_PFIFO_CACHE0_PUT 0x00003010 /* RW-4R */
#define NV_PFIFO_CACHE0_PUT_ADDRESS 2:2 /* RWXUF */
#define NV_PFIFO_CACHE1_PUT 0x00003210 /* RW-4R */
#define NV_PFIFO_CACHE1_PUT_ADDRESS 9:2 /* RWXUF */
#define NV_PFIFO_CACHE0_GET 0x00003070 /* RW-4R */
#define NV_PFIFO_CACHE0_GET_ADDRESS 2:2 /* RWXUF */
#define NV_PFIFO_CACHE1_GET 0x00003270 /* RW-4R */
#define NV_PFIFO_CACHE1_GET_ADDRESS 9:2 /* RWXUF */
#define NV_PFIFO_CACHE0_ENGINE 0x00003080 /* RW-4R */
#define NV_PFIFO_CACHE0_ENGINE_0 1:0 /* RWXUF */
#define NV_PFIFO_CACHE0_ENGINE_0_SW 0x00000000 /* RW--V */
#define NV_PFIFO_CACHE0_ENGINE_0_GRAPHICS 0x00000001 /* RW--V */
#define NV_PFIFO_CACHE0_ENGINE_0_DVD 0x00000002 /* RW--V */
#define NV_PFIFO_CACHE0_ENGINE_1 5:4 /* RWXUF */
#define NV_PFIFO_CACHE0_ENGINE_1_SW 0x00000000 /* RW--V */
#define NV_PFIFO_CACHE0_ENGINE_1_GRAPHICS 0x00000001 /* RW--V */
#define NV_PFIFO_CACHE0_ENGINE_1_DVD 0x00000002 /* RW--V */
#define NV_PFIFO_CACHE0_ENGINE_2 9:8 /* RWXUF */
#define NV_PFIFO_CACHE0_ENGINE_2_SW 0x00000000 /* RW--V */
#define NV_PFIFO_CACHE0_ENGINE_2_GRAPHICS 0x00000001 /* RW--V */
#define NV_PFIFO_CACHE0_ENGINE_2_DVD 0x00000002 /* RW--V */
#define NV_PFIFO_CACHE0_ENGINE_3 13:12 /* RWXUF */
#define NV_PFIFO_CACHE0_ENGINE_3_SW 0x00000000 /* RW--V */
#define NV_PFIFO_CACHE0_ENGINE_3_GRAPHICS 0x00000001 /* RW--V */
#define NV_PFIFO_CACHE0_ENGINE_3_DVD 0x00000002 /* RW--V */
#define NV_PFIFO_CACHE0_ENGINE_4 17:16 /* RWXUF */
#define NV_PFIFO_CACHE0_ENGINE_4_SW 0x00000000 /* RW--V */
#define NV_PFIFO_CACHE0_ENGINE_4_GRAPHICS 0x00000001 /* RW--V */
#define NV_PFIFO_CACHE0_ENGINE_4_DVD 0x00000002 /* RW--V */
#define NV_PFIFO_CACHE0_ENGINE_5 21:20 /* RWXUF */
#define NV_PFIFO_CACHE0_ENGINE_5_SW 0x00000000 /* RW--V */
#define NV_PFIFO_CACHE0_ENGINE_5_GRAPHICS 0x00000001 /* RW--V */
#define NV_PFIFO_CACHE0_ENGINE_5_DVD 0x00000002 /* RW--V */
#define NV_PFIFO_CACHE0_ENGINE_6 25:24 /* RWXUF */
#define NV_PFIFO_CACHE0_ENGINE_6_SW 0x00000000 /* RW--V */
#define NV_PFIFO_CACHE0_ENGINE_6_GRAPHICS 0x00000001 /* RW--V */
#define NV_PFIFO_CACHE0_ENGINE_6_DVD 0x00000002 /* RW--V */
#define NV_PFIFO_CACHE0_ENGINE_7 29:28 /* RWXUF */
#define NV_PFIFO_CACHE0_ENGINE_7_SW 0x00000000 /* RW--V */
#define NV_PFIFO_CACHE0_ENGINE_7_GRAPHICS 0x00000001 /* RW--V */
#define NV_PFIFO_CACHE0_ENGINE_7_DVD 0x00000002 /* RW--V */
#define NV_PFIFO_CACHE1_ENGINE 0x00003280 /* RW-4R */
#define NV_PFIFO_CACHE1_ENGINE_0 1:0 /* RWXUF */
#define NV_PFIFO_CACHE1_ENGINE_0_SW 0x00000000 /* RW--V */
#define NV_PFIFO_CACHE1_ENGINE_0_GRAPHICS 0x00000001 /* RW--V */
#define NV_PFIFO_CACHE1_ENGINE_0_DVD 0x00000002 /* RW--V */
#define NV_PFIFO_CACHE1_ENGINE_1 5:4 /* RWXUF */
#define NV_PFIFO_CACHE1_ENGINE_1_SW 0x00000000 /* RW--V */
#define NV_PFIFO_CACHE1_ENGINE_1_GRAPHICS 0x00000001 /* RW--V */
#define NV_PFIFO_CACHE1_ENGINE_1_DVD 0x00000002 /* RW--V */
#define NV_PFIFO_CACHE1_ENGINE_2 9:8 /* RWXUF */
#define NV_PFIFO_CACHE1_ENGINE_2_SW 0x00000000 /* RW--V */
#define NV_PFIFO_CACHE1_ENGINE_2_GRAPHICS 0x00000001 /* RW--V */
#define NV_PFIFO_CACHE1_ENGINE_2_DVD 0x00000002 /* RW--V */
#define NV_PFIFO_CACHE1_ENGINE_3 13:12 /* RWXUF */
#define NV_PFIFO_CACHE1_ENGINE_3_SW 0x00000000 /* RW--V */
#define NV_PFIFO_CACHE1_ENGINE_3_GRAPHICS 0x00000001 /* RW--V */
#define NV_PFIFO_CACHE1_ENGINE_3_DVD 0x00000002 /* RW--V */
#define NV_PFIFO_CACHE1_ENGINE_4 17:16 /* RWXUF */
#define NV_PFIFO_CACHE1_ENGINE_4_SW 0x00000000 /* RW--V */
#define NV_PFIFO_CACHE1_ENGINE_4_GRAPHICS 0x00000001 /* RW--V */
#define NV_PFIFO_CACHE1_ENGINE_4_DVD 0x00000002 /* RW--V */
#define NV_PFIFO_CACHE1_ENGINE_5 21:20 /* RWXUF */
#define NV_PFIFO_CACHE1_ENGINE_5_SW 0x00000000 /* RW--V */
#define NV_PFIFO_CACHE1_ENGINE_5_GRAPHICS 0x00000001 /* RW--V */
#define NV_PFIFO_CACHE1_ENGINE_5_DVD 0x00000002 /* RW--V */
#define NV_PFIFO_CACHE1_ENGINE_6 25:24 /* RWXUF */
#define NV_PFIFO_CACHE1_ENGINE_6_SW 0x00000000 /* RW--V */
#define NV_PFIFO_CACHE1_ENGINE_6_GRAPHICS 0x00000001 /* RW--V */
#define NV_PFIFO_CACHE1_ENGINE_6_DVD 0x00000002 /* RW--V */
#define NV_PFIFO_CACHE1_ENGINE_7 29:28 /* RWXUF */
#define NV_PFIFO_CACHE1_ENGINE_7_SW 0x00000000 /* RW--V */
#define NV_PFIFO_CACHE1_ENGINE_7_GRAPHICS 0x00000001 /* RW--V */
#define NV_PFIFO_CACHE1_ENGINE_7_DVD 0x00000002 /* RW--V */
#define NV_PFIFO_CACHE0_METHOD(i) (0x00003100+(i)*8) /* RW-4A */
#define NV_PFIFO_CACHE0_METHOD__SIZE_1 1 /* */
#define NV_PFIFO_CACHE0_METHOD_ADDRESS 12:2 /* RWXUF */
#define NV_PFIFO_CACHE0_METHOD_SUBCHANNEL 15:13 /* RWXUF */
#define NV_PFIFO_CACHE1_METHOD(i) (0x00003800+(i)*8) /* RW-4A */
#define NV_PFIFO_CACHE1_METHOD__SIZE_1 128 /* */
#define NV_PFIFO_CACHE1_METHOD_ADDRESS 12:2 /* RWXUF */
#define NV_PFIFO_CACHE1_METHOD_SUBCHANNEL 15:13 /* RWXUF */
#define NV_PFIFO_CACHE1_METHOD_ALIAS(i) (0x00003C00+(i)*8) /* RW-4A */
#define NV_PFIFO_CACHE1_METHOD_ALIAS__SIZE_1 128 /* */
#define NV_PFIFO_CACHE0_DATA(i) (0x00003104+(i)*8) /* RW-4A */
#define NV_PFIFO_CACHE0_DATA__SIZE_1 1 /* */
#define NV_PFIFO_CACHE0_DATA_VALUE 31:0 /* RWXVF */
#define NV_PFIFO_CACHE1_DATA(i) (0x00003804+(i)*8) /* RW-4A */
#define NV_PFIFO_CACHE1_DATA__SIZE_1 128 /* */
#define NV_PFIFO_CACHE1_DATA_VALUE 31:0 /* RWXVF */
#define NV_PFIFO_CACHE1_DATA_ALIAS(i) (0x00003C04+(i)*8) /* RW-4A */
#define NV_PFIFO_CACHE1_DATA_ALIAS__SIZE_1 128 /* */
#define NV_PFIFO_DEVICE(i) (0x00002800+(i)*4) /* R--4A */
#define NV_PFIFO_DEVICE__SIZE_1 128 /* */
#define NV_PFIFO_DEVICE_CHID 3:0 /* R--UF */
#define NV_PFIFO_DEVICE_SWITCH 24:24 /* R--VF */
#define NV_PFIFO_DEVICE_SWITCH_UNAVAILABLE 0x00000000 /* R---V */
#define NV_PFIFO_DEVICE_SWITCH_AVAILABLE 0x00000001 /* R---V */
#define NV_PFIFO_RUNOUT_STATUS 0x00002400 /* R--4R */
#define NV_PFIFO_RUNOUT_STATUS_RANOUT 0:0 /* R--VF */
#define NV_PFIFO_RUNOUT_STATUS_RANOUT_FALSE 0x00000000 /* R---V */
#define NV_PFIFO_RUNOUT_STATUS_RANOUT_TRUE 0x00000001 /* R---V */
#define NV_PFIFO_RUNOUT_STATUS_LOW_MARK 4:4 /* R--VF */
#define NV_PFIFO_RUNOUT_STATUS_LOW_MARK_NOT_EMPTY 0x00000000 /* R---V */
#define NV_PFIFO_RUNOUT_STATUS_LOW_MARK_EMPTY 0x00000001 /* R---V */
#define NV_PFIFO_RUNOUT_STATUS_HIGH_MARK 8:8 /* R--VF */
#define NV_PFIFO_RUNOUT_STATUS_HIGH_MARK_NOT_FULL 0x00000000 /* R---V */
#define NV_PFIFO_RUNOUT_STATUS_HIGH_MARK_FULL 0x00000001 /* R---V */
#define NV_PFIFO_RUNOUT_PUT 0x00002410 /* RW-4R */
#define NV_PFIFO_RUNOUT_PUT_ADDRESS 12:3 /* RWXUF */
#define NV_PFIFO_RUNOUT_PUT_ADDRESS__SIZE_0 8:3 /* RWXUF */
#define NV_PFIFO_RUNOUT_PUT_ADDRESS__SIZE_1 12:3 /* RWXUF */
#define NV_PFIFO_RUNOUT_GET 0x00002420 /* RW-4R */
#define NV_PFIFO_RUNOUT_GET_ADDRESS 13:3 /* RWXUF */
/* dev_graphics.ref */
#define NV_PGRAPH 0x00401FFF:0x00400000 /* RW--D */
#define NV_PGRAPH_DEBUG_0 0x00400080 /* RW-4R */
#define NV_PGRAPH_DEBUG_1 0x00400084 /* RW-4R */
#define NV_PGRAPH_DEBUG_2 0x00400088 /* RW-4R */
#define NV_PGRAPH_DEBUG_3 0x0040008C /* RW-4R */
#define NV_PGRAPH_INTR 0x00400100 /* RW-4R */
#define NV_PGRAPH_INTR_NOTIFY 0:0 /* RWIVF */
#define NV_PGRAPH_INTR_NOTIFY_NOT_PENDING 0x00000000 /* R-I-V */
#define NV_PGRAPH_INTR_NOTIFY_PENDING 0x00000001 /* R---V */
#define NV_PGRAPH_INTR_NOTIFY_RESET 0x00000001 /* -W--C */
#define NV_PGRAPH_INTR_MISSING_HW 4:4 /* RWIVF */
#define NV_PGRAPH_INTR_MISSING_HW_NOT_PENDING 0x00000000 /* R-I-V */
#define NV_PGRAPH_INTR_MISSING_HW_PENDING 0x00000001 /* R---V */
#define NV_PGRAPH_INTR_MISSING_HW_RESET 0x00000001 /* -W--C */
#define NV_PGRAPH_INTR_TLB_PRESENT_A 8:8 /* RWIVF */
#define NV_PGRAPH_INTR_TLB_PRESENT_A_NOT_PENDING 0x00000000 /* R-I-V */
#define NV_PGRAPH_INTR_TLB_PRESENT_A_PENDING 0x00000001 /* R---V */
#define NV_PGRAPH_INTR_TLB_PRESENT_A_RESET 0x00000001 /* -W--C */
#define NV_PGRAPH_INTR_TLB_PRESENT_B 9:9 /* RWIVF */
#define NV_PGRAPH_INTR_TLB_PRESENT_B_NOT_PENDING 0x00000000 /* R-I-V */
#define NV_PGRAPH_INTR_TLB_PRESENT_B_PENDING 0x00000001 /* R---V */
#define NV_PGRAPH_INTR_TLB_PRESENT_B_RESET 0x00000001 /* -W--C */
#define NV_PGRAPH_INTR_CONTEXT_SWITCH 12:12 /* RWIVF */
#define NV_PGRAPH_INTR_CONTEXT_SWITCH_NOT_PENDING 0x00000000 /* R-I-V */
#define NV_PGRAPH_INTR_CONTEXT_SWITCH_PENDING 0x00000001 /* R---V */
#define NV_PGRAPH_INTR_CONTEXT_SWITCH_RESET 0x00000001 /* -W--C */
#define NV_PGRAPH_INTR_BUFFER_NOTIFY 16:16 /* RWIVF */
#define NV_PGRAPH_INTR_BUFFER_NOTIFY_NOT_PENDING 0x00000000 /* R-I-V */
#define NV_PGRAPH_INTR_BUFFER_NOTIFY_PENDING 0x00000001 /* R---V */
#define NV_PGRAPH_INTR_BUFFER_NOTIFY_RESET 0x00000001 /* -W--C */
#define NV_PGRAPH_NSTATUS 0x00400104 /* RW-4R */
#define NV_PGRAPH_NSTATUS_STATE_IN_USE 11:11 /* RWIVF */
#define NV_PGRAPH_NSTATUS_STATE_IN_USE_NOT_PENDING 0x00000000 /* RWI-V */
#define NV_PGRAPH_NSTATUS_STATE_IN_USE_PENDING 0x00000001 /* RW--V */
#define NV_PGRAPH_NSTATUS_INVALID_STATE 12:12 /* RWIVF */
#define NV_PGRAPH_NSTATUS_INVALID_STATE_NOT_PENDING 0x00000000 /* RWI-V */
#define NV_PGRAPH_NSTATUS_INVALID_STATE_PENDING 0x00000001 /* RW--V */
#define NV_PGRAPH_NSTATUS_BAD_ARGUMENT 13:13 /* RWIVF */
#define NV_PGRAPH_NSTATUS_BAD_ARGUMENT_NOT_PENDING 0x00000000 /* RWI-V */
#define NV_PGRAPH_NSTATUS_BAD_ARGUMENT_PENDING 0x00000001 /* RW--V */
#define NV_PGRAPH_NSTATUS_PROTECTION_FAULT 14:14 /* RWIVF */
#define NV_PGRAPH_NSTATUS_PROTECTION_FAULT_NOT_PENDING 0x00000000 /* RWI-V */
#define NV_PGRAPH_NSTATUS_PROTECTION_FAULT_PENDING 0x00000001 /* RW--V */
#define NV_PGRAPH_NSOURCE 0x00400108 /* R--4R */
#define NV_PGRAPH_NSOURCE_NOTIFICATION 0:0 /* R-IVF */
#define NV_PGRAPH_NSOURCE_NOTIFICATION_NOT_PENDING 0x00000000 /* R-I-V */
#define NV_PGRAPH_NSOURCE_NOTIFICATION_PENDING 0x00000001 /* R---V */
#define NV_PGRAPH_NSOURCE_DATA_ERROR 1:1 /* R-IVF */
#define NV_PGRAPH_NSOURCE_DATA_ERROR_NOT_PENDING 0x00000000 /* R-I-V */
#define NV_PGRAPH_NSOURCE_DATA_ERROR_PENDING 0x00000001 /* R---V */
#define NV_PGRAPH_NSOURCE_PROTECTION_ERROR 2:2 /* R-IVF */
#define NV_PGRAPH_NSOURCE_PROTECTION_ERROR_NOT_PENDING 0x00000000 /* R-I-V */
#define NV_PGRAPH_NSOURCE_PROTECTION_ERROR_PENDING 0x00000001 /* R---V */
#define NV_PGRAPH_NSOURCE_RANGE_EXCEPTION 3:3 /* R-IVF */
#define NV_PGRAPH_NSOURCE_RANGE_EXCEPTION_NOT_PENDING 0x00000000 /* R-I-V */
#define NV_PGRAPH_NSOURCE_RANGE_EXCEPTION_PENDING 0x00000001 /* R---V */
#define NV_PGRAPH_NSOURCE_LIMIT_COLOR 4:4 /* R-IVF */
#define NV_PGRAPH_NSOURCE_LIMIT_COLOR_NOT_PENDING 0x00000000 /* R-I-V */
#define NV_PGRAPH_NSOURCE_LIMIT_COLOR_PENDING 0x00000001 /* R---V */
#define NV_PGRAPH_NSOURCE_LIMIT_ZETA_ 5:5 /* R-IVF */
#define NV_PGRAPH_NSOURCE_LIMIT_ZETA_NOT_PENDING 0x00000000 /* R-I-V */
#define NV_PGRAPH_NSOURCE_LIMIT_ZETA_PENDING 0x00000001 /* R---V */
#define NV_PGRAPH_NSOURCE_ILLEGAL_MTHD 6:6 /* R-IVF */
#define NV_PGRAPH_NSOURCE_ILLEGAL_MTHD_NOT_PENDING 0x00000000 /* R-I-V */
#define NV_PGRAPH_NSOURCE_ILLEGAL_MTHD_PENDING 0x00000001 /* R---V */
#define NV_PGRAPH_NSOURCE_DMA_R_PROTECTION 7:7 /* R-IVF */
#define NV_PGRAPH_NSOURCE_DMA_R_PROTECTION_NOT_PENDING 0x00000000 /* R-I-V */
#define NV_PGRAPH_NSOURCE_DMA_R_PROTECTION_PENDING 0x00000001 /* R---V */
#define NV_PGRAPH_NSOURCE_DMA_W_PROTECTION 8:8 /* R-IVF */
#define NV_PGRAPH_NSOURCE_DMA_W_PROTECTION_NOT_PENDING 0x00000000 /* R-I-V */
#define NV_PGRAPH_NSOURCE_DMA_W_PROTECTION_PENDING 0x00000001 /* R---V */
#define NV_PGRAPH_NSOURCE_FORMAT_EXCEPTION 9:9 /* R-IVF */
#define NV_PGRAPH_NSOURCE_FORMAT_EXCEPTION_NOT_PENDING 0x00000000 /* R-I-V */
#define NV_PGRAPH_NSOURCE_FORMAT_EXCEPTION_PENDING 0x00000001 /* R---V */
#define NV_PGRAPH_NSOURCE_PATCH_EXCEPTION 10:10 /* R-IVF */
#define NV_PGRAPH_NSOURCE_PATCH_EXCEPTION_NOT_PENDING 0x00000000 /* R-I-V */
#define NV_PGRAPH_NSOURCE_PATCH_EXCEPTION_PENDING 0x00000001 /* R---V */
#define NV_PGRAPH_NSOURCE_STATE_INVALID 11:11 /* R-IVF */
#define NV_PGRAPH_NSOURCE_STATE_INVALID_NOT_PENDING 0x00000000 /* R-I-V */
#define NV_PGRAPH_NSOURCE_STATE_INVALID_PENDING 0x00000001 /* R---V */
#define NV_PGRAPH_NSOURCE_DOUBLE_NOTIFY 12:12 /* R-IVF */
#define NV_PGRAPH_NSOURCE_DOUBLE_NOTIFY_NOT_PENDING 0x00000000 /* R-I-V */
#define NV_PGRAPH_NSOURCE_DOUBLE_NOTIFY_PENDING 0x00000001 /* R---V */
#define NV_PGRAPH_NSOURCE_NOTIFY_IN_USE 13:13 /* R-IVF */
#define NV_PGRAPH_NSOURCE_NOTIFY_IN_USE_NOT_PENDING 0x00000000 /* R-I-V */
#define NV_PGRAPH_NSOURCE_NOTIFY_IN_USE_PENDING 0x00000001 /* R---V */
#define NV_PGRAPH_NSOURCE_METHOD_CNT 14:14 /* R-IVF */
#define NV_PGRAPH_NSOURCE_METHOD_CNT_NOT_PENDING 0x00000000 /* R-I-V */
#define NV_PGRAPH_NSOURCE_METHOD_CNT_PENDING 0x00000001 /* R---V */
#define NV_PGRAPH_NSOURCE_BFR_NOTIFICATION 15:15 /* R-IVF */
#define NV_PGRAPH_NSOURCE_BFR_NOTIFICATION_NOT_PENDING 0x00000000 /* R-I-V */
#define NV_PGRAPH_NSOURCE_BFR_NOTIFICATION_PENDING 0x00000001 /* R---V */
#define NV_PGRAPH_INTR_EN 0x00400140 /* RW-4R */
#define NV_PGRAPH_INTR_EN_NOTIFY 0:0 /* RWIVF */
#define NV_PGRAPH_INTR_EN_NOTIFY_DISABLED 0x00000000 /* RWI-V */
#define NV_PGRAPH_INTR_EN_NOTIFY_ENABLED 0x00000001 /* RW--V */
#define NV_PGRAPH_INTR_EN_MISSING_HW 4:4 /* RWIVF */
#define NV_PGRAPH_INTR_EN_MISSING_HW_DISABLED 0x00000000 /* RWI-V */
#define NV_PGRAPH_INTR_EN_MISSING_HW_ENABLED 0x00000001 /* RW--V */
#define NV_PGRAPH_INTR_EN_TLB_PRESENT_A 8:8 /* RWIVF */
#define NV_PGRAPH_INTR_EN_TLB_PRESENT_A_DISABLED 0x00000000 /* RWI-V */
#define NV_PGRAPH_INTR_EN_TLB_PRESENT_A_ENABLED 0x00000001 /* RW--V */
#define NV_PGRAPH_INTR_EN_TLB_PRESENT_B 9:9 /* RWIVF */
#define NV_PGRAPH_INTR_EN_TLB_PRESENT_B_DISABLED 0x00000000 /* RWI-V */
#define NV_PGRAPH_INTR_EN_TLB_PRESENT_B_ENABLED 0x00000001 /* RW--V */
#define NV_PGRAPH_INTR_EN_CONTEXT_SWITCH 12:12 /* RWIVF */
#define NV_PGRAPH_INTR_EN_CONTEXT_SWITCH_DISABLED 0x00000000 /* RWI-V */
#define NV_PGRAPH_INTR_EN_CONTEXT_SWITCH_ENABLED 0x00000001 /* RW--V */
#define NV_PGRAPH_INTR_EN_BUFFER_NOTIFY 16:16 /* RWIVF */
#define NV_PGRAPH_INTR_EN_BUFFER_NOTIFY_DISABLED 0x00000000 /* RWI-V */
#define NV_PGRAPH_INTR_EN_BUFFER_NOTIFY_ENABLED 0x00000001 /* RW--V */
#define NV_PGRAPH_CTX_SWITCH1 0x00400160 /* RW-4R */
#define NV_PGRAPH_CTX_SWITCH1_GRCLASS 7:0 /* RWXVF */
#define NV_PGRAPH_CTX_SWITCH1_CHROMA_KEY 12:12 /* RWXUF */
#define NV_PGRAPH_CTX_SWITCH1_CHROMA_KEY_DISABLE 0x00000000 /* RW--V */
#define NV_PGRAPH_CTX_SWITCH1_CHROMA_KEY_ENABLE 0x00000001 /* RW--V */
#define NV_PGRAPH_CTX_SWITCH1_USER_CLIP 13:13 /* RWXUF */
#define NV_PGRAPH_CTX_SWITCH1_USER_CLIP_DISABLE 0x00000000 /* RW--V */
#define NV_PGRAPH_CTX_SWITCH1_USER_CLIP_ENABLE 0x00000001 /* RW--V */
#define NV_PGRAPH_CTX_SWITCH1_SWIZZLE 14:14 /* RWXUF */
#define NV_PGRAPH_CTX_SWITCH1_SWIZZLE_DISABLE 0x00000000 /* RW--V */
#define NV_PGRAPH_CTX_SWITCH1_SWIZZLE_ENABLE 0x00000001 /* RW--V */
#define NV_PGRAPH_CTX_SWITCH1_PATCH_CONFIG 17:15 /* RWXUF */
#define NV_PGRAPH_CTX_SWITCH1_PATCH_CONFIG_SRCCOPY_AND 0x00000000 /* RW--V */
#define NV_PGRAPH_CTX_SWITCH1_PATCH_CONFIG_ROP_AND 0x00000001 /* RW--V */
#define NV_PGRAPH_CTX_SWITCH1_PATCH_CONFIG_BLEND_AND 0x00000002 /* RW--V */
#define NV_PGRAPH_CTX_SWITCH1_PATCH_CONFIG_SRCCOPY 0x00000003 /* RW--V */
#define NV_PGRAPH_CTX_SWITCH1_PATCH_CONFIG_SRCCOPY_PRE 0x00000004 /* RW--V */
#define NV_PGRAPH_CTX_SWITCH1_PATCH_CONFIG_BLEND_PRE 0x00000005 /* RW--V */
#define NV_PGRAPH_CTX_SWITCH1_PATCH_STATUS 24:24 /* RWXUF */
#define NV_PGRAPH_CTX_SWITCH1_PATCH_STATUS_INVALID 0x00000000 /* RW--V */
#define NV_PGRAPH_CTX_SWITCH1_PATCH_STATUS_VALID 0x00000001 /* RW--V */
#define NV_PGRAPH_CTX_SWITCH1_CONTEXT_SURFACE 25:25 /* RWXUF */
#define NV_PGRAPH_CTX_SWITCH1_CONTEXT_SURFACE_INVALID 0x00000000 /* RW--V */
#define NV_PGRAPH_CTX_SWITCH1_CONTEXT_SURFACE_VALID 0x00000001 /* RW--V */
#define NV_PGRAPH_CTX_SWITCH1_VOLATILE_RESET 31:31 /* CWIVF */
#define NV_PGRAPH_CTX_SWITCH1_VOLATILE_RESET_IGNORE 0x00000000 /* CWI-V */
#define NV_PGRAPH_CTX_SWITCH1_VOLATILE_RESET_ENABLED 0x00000001 /* -W--T */
#define NV_PGRAPH_CTX_SWITCH2 0x00400164 /* RW-4R */
#define NV_PGRAPH_CTX_SWITCH2_MONO_FORMAT 1:0 /* RWXUF */
#define NV_PGRAPH_CTX_SWITCH2_MONO_FORMAT_INVALID 0x00 /* RW--V */
#define NV_PGRAPH_CTX_SWITCH2_MONO_FORMAT_CGA6_M1 0x01 /* RW--V */
#define NV_PGRAPH_CTX_SWITCH2_MONO_FORMAT_LE_M1 0x02 /* RW--V */
#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT 13:8 /* RWXUF */
#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_INVALID 0x00 /* RW--V */
#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_Y8 0x01 /* RW--V */
#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_X16A8Y8 0x02 /* RW--V */
#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_X24Y8 0x03 /* RW--V */
#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_A1R5G5B5 0x06 /* RW--V */
#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_X1R5G5B5 0x07 /* RW--V */
#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_X16A1R5G5B5 0x08 /* RW--V */
#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_X17R5G5B5 0x09 /* RW--V */
#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_R5G6B5 0x0A /* RW--V */
#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_A16R5G6B5 0x0B /* RW--V */
#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_X16R5G6B5 0x0C /* RW--V */
#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_A8R8G8B8 0x0D /* RW--V */
#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_X8R8G8B8 0x0E /* RW--V */
#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_Y16 0x0F /* RW--V */
#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_A16Y16 0x10 /* RW--V */
#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_X16Y16 0x11 /* RW--V */
#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_V8YB8U8YA8 0x12 /* RW--V */
#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_YB8V8YA8U8 0x13 /* RW--V */
#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_Y32 0x14 /* RW--V */
#define NV_PGRAPH_CTX_SWITCH2_NOTIFY_INSTANCE 31:16 /* RWXUF */
#define NV_PGRAPH_CTX_SWITCH2_NOTIFY_INSTANCE_INVALID 0x0000 /* RW--V */
#define NV_PGRAPH_CTX_SWITCH3 0x00400168 /* RW-4R */
#define NV_PGRAPH_CTX_SWITCH3_DMA_INSTANCE_0 15:0 /* RWXUF */
#define NV_PGRAPH_CTX_SWITCH3_DMA_INSTANCE_0_INVALID 0x0000 /* RW--V */
#define NV_PGRAPH_CTX_SWITCH3_DMA_INSTANCE_1 31:16 /* RWXUF */
#define NV_PGRAPH_CTX_SWITCH3_DMA_INSTANCE_1_INVALID 0x0000 /* RW--V */
#define NV_PGRAPH_CTX_SWITCH4 0x0040016C /* RW-4R */
#define NV_PGRAPH_CTX_SWITCH4_USER_INSTANCE 15:0 /* RWXUF */
#define NV_PGRAPH_CTX_SWITCH4_USER_INSTANCE_INVALID 0x0000 /* RW--V */
#define NV_PGRAPH_CTX_CACHE1(i) (0x00400180+(i)*4) /* RW-4A */
#define NV_PGRAPH_CTX_CACHE1__SIZE_1 8 /* */
#define NV_PGRAPH_CTX_CACHE1_GRCLASS 7:0 /* RWXVF */
#define NV_PGRAPH_CTX_CACHE1_CHROMA_KEY 12:12 /* RWXVF */
#define NV_PGRAPH_CTX_CACHE1_USER_CLIP 13:13 /* RWXVF */
#define NV_PGRAPH_CTX_CACHE1_SWIZZLE 14:14 /* RWXVF */
#define NV_PGRAPH_CTX_CACHE1_PATCH_CONFIG 19:15 /* RWXVF */
#define NV_PGRAPH_CTX_CACHE1_SPARE1 20:20 /* RWXVF */
#define NV_PGRAPH_CTX_CACHE1_PATCH_STATUS 24:24 /* RWXVF */
#define NV_PGRAPH_CTX_CACHE1_CONTEXT_SURFACE 25:25 /* RWXVF */
#define NV_PGRAPH_CTX_CACHE2(i) (0x004001a0+(i)*4) /* RW-4A */
#define NV_PGRAPH_CTX_CACHE2__SIZE_1 8 /* */
#define NV_PGRAPH_CTX_CACHE2_MONO_FORMAT 1:0 /* RWXVF */
#define NV_PGRAPH_CTX_CACHE2_COLOR_FORMAT 13:8 /* RWXVF */
#define NV_PGRAPH_CTX_CACHE2_NOTIFY_INSTANCE 31:16 /* RWXVF */
#define NV_PGRAPH_CTX_CACHE3(i) (0x004001c0+(i)*4) /* RW-4A */
#define NV_PGRAPH_CTX_CACHE3__SIZE_1 8 /* */
#define NV_PGRAPH_CTX_CACHE3_DMA_INSTANCE_0 15:0 /* RWXVF */
#define NV_PGRAPH_CTX_CACHE3_DMA_INSTANCE_1 31:16 /* RWXVF */
#define NV_PGRAPH_CTX_CACHE4(i) (0x004001e0+(i)*4) /* RW-4A */
#define NV_PGRAPH_CTX_CACHE4__SIZE_1 8 /* */
#define NV_PGRAPH_CTX_CACHE4_USER_INSTANCE 15:0 /* RWXVF */
#define NV_PGRAPH_CTX_CONTROL 0x00400170 /* RW-4R */
#define NV_PGRAPH_CTX_CONTROL_MINIMUM_TIME 1:0 /* RWIVF */
#define NV_PGRAPH_CTX_CONTROL_MINIMUM_TIME_33US 0x00000000 /* RWI-V */
#define NV_PGRAPH_CTX_CONTROL_MINIMUM_TIME_262US 0x00000001 /* RW--V */
#define NV_PGRAPH_CTX_CONTROL_MINIMUM_TIME_2MS 0x00000002 /* RW--V */
#define NV_PGRAPH_CTX_CONTROL_MINIMUM_TIME_17MS 0x00000003 /* RW--V */
#define NV_PGRAPH_CTX_CONTROL_TIME 8:8 /* RWIVF */
#define NV_PGRAPH_CTX_CONTROL_TIME_EXPIRED 0x00000000 /* RWI-V */
#define NV_PGRAPH_CTX_CONTROL_TIME_NOT_EXPIRED 0x00000001 /* RW--V */
#define NV_PGRAPH_CTX_CONTROL_CHID 16:16 /* RWIVF */
#define NV_PGRAPH_CTX_CONTROL_CHID_INVALID 0x00000000 /* RWI-V */
#define NV_PGRAPH_CTX_CONTROL_CHID_VALID 0x00000001 /* RW--V */
#define NV_PGRAPH_CTX_CONTROL_CHANGE 20:20 /* R--VF */
#define NV_PGRAPH_CTX_CONTROL_CHANGE_UNAVAILABLE 0x00000000 /* R---V */
#define NV_PGRAPH_CTX_CONTROL_CHANGE_AVAILABLE 0x00000001 /* R---V */
#define NV_PGRAPH_CTX_CONTROL_SWITCHING 24:24 /* RWIVF */
#define NV_PGRAPH_CTX_CONTROL_SWITCHING_IDLE 0x00000000 /* RWI-V */
#define NV_PGRAPH_CTX_CONTROL_SWITCHING_BUSY 0x00000001 /* RW--V */
#define NV_PGRAPH_CTX_CONTROL_DEVICE 28:28 /* RWIVF */
#define NV_PGRAPH_CTX_CONTROL_DEVICE_DISABLED 0x00000000 /* RWI-V */
#define NV_PGRAPH_CTX_CONTROL_DEVICE_ENABLED 0x00000001 /* RW--V */
#define NV_PGRAPH_CTX_USER 0x00400174 /* RW-4R */
#define NV_PGRAPH_CTX_USER_SUBCH 15:13 /* RWIVF */
#define NV_PGRAPH_CTX_USER_SUBCH_0 0x00000000 /* RWI-V */
#define NV_PGRAPH_CTX_USER_CHID 27:24 /* RWIVF */
#define NV_PGRAPH_CTX_USER_CHID_0 0x00000000 /* RWI-V */
#define NV_PGRAPH_FIFO 0x00400720 /* RW-4R */
#define NV_PGRAPH_FIFO_ACCESS 0:0 /* RWIVF */
#define NV_PGRAPH_FIFO_ACCESS_DISABLED 0x00000000 /* RW--V */
#define NV_PGRAPH_FIFO_ACCESS_ENABLED 0x00000001 /* RWI-V */
#define NV_PGRAPH_FFINTFC_FIFO_0(i) (0x00400730+(i)*4) /* RW-4A */
#define NV_PGRAPH_FFINTFC_FIFO_0__SIZE_1 4 /* */
#define NV_PGRAPH_FFINTFC_FIFO_0_TAG 0:0 /* RWXVF */
#define NV_PGRAPH_FFINTFC_FIFO_0_TAG_MTHD 0x00000000 /* RW--V */
#define NV_PGRAPH_FFINTFC_FIFO_0_TAG_CHSW 0x00000001 /* RW--V */
#define NV_PGRAPH_FFINTFC_FIFO_0_SUBCH 3:1 /* RWXVF */
#define NV_PGRAPH_FFINTFC_FIFO_0_SUBCH_0 0x00000000 /* RW--V */
#define NV_PGRAPH_FFINTFC_FIFO_0_SUBCH_1 0x00000001 /* RW--V */
#define NV_PGRAPH_FFINTFC_FIFO_0_SUBCH_2 0x00000002 /* RW--V */
#define NV_PGRAPH_FFINTFC_FIFO_0_SUBCH_3 0x00000003 /* RW--V */
#define NV_PGRAPH_FFINTFC_FIFO_0_SUBCH_4 0x00000004 /* RW--V */
#define NV_PGRAPH_FFINTFC_FIFO_0_SUBCH_5 0x00000005 /* RW--V */
#define NV_PGRAPH_FFINTFC_FIFO_0_SUBCH_6 0x00000006 /* RW--V */
#define NV_PGRAPH_FFINTFC_FIFO_0_SUBCH_7 0x00000007 /* RW--V */
#define NV_PGRAPH_FFINTFC_FIFO_0_MTHD 14:4 /* RWXVF */
#define NV_PGRAPH_FFINTFC_FIFO_0_MTHD_CTX_SWITCH 0x00000000 /* RW--V */
#define NV_PGRAPH_FFINTFC_FIFO_1(i) (0x00400740+(i)*4) /* RW-4A */
#define NV_PGRAPH_FFINTFC_FIFO_1__SIZE_1 4 /* */
#define NV_PGRAPH_FFINTFC_FIFO_1_ARGUMENT 31:0 /* RWXVF */
#define NV_PGRAPH_FFINTFC_FIFO_PTR 0x00400750 /* RW-4R */
#define NV_PGRAPH_FFINTFC_FIFO_PTR_WRITE 2:0 /* RWIVF */
#define NV_PGRAPH_FFINTFC_FIFO_PTR_WRITE_0 0x00000000 /* RWI-V */
#define NV_PGRAPH_FFINTFC_FIFO_PTR_READ 6:4 /* RWIVF */
#define NV_PGRAPH_FFINTFC_FIFO_PTR_READ_0 0x00000000 /* RWI-V */
#define NV_PGRAPH_FFINTFC_ST2 0x00400754 /* RW-4R */
#define NV_PGRAPH_FFINTFC_ST2_STATUS 0:0 /* RWIVF */
#define NV_PGRAPH_FFINTFC_ST2_STATUS_INVALID 0x00000000 /* RWI-V */
#define NV_PGRAPH_FFINTFC_ST2_STATUS_VALID 0x00000001 /* RW--V */
#define NV_PGRAPH_FFINTFC_ST2_MTHD 11:1 /* RWIVF */
#define NV_PGRAPH_FFINTFC_ST2_MTHD_CTX_SWITCH 0x00000000 /* RWI-V */
#define NV_PGRAPH_FFINTFC_ST2_SUBCH 14:12 /* RWIVF */
#define NV_PGRAPH_FFINTFC_ST2_SUBCH_0 0x00000000 /* RWI-V */
#define NV_PGRAPH_FFINTFC_ST2_SUBCH_1 0x00000001 /* RW--V */
#define NV_PGRAPH_FFINTFC_ST2_SUBCH_2 0x00000002 /* RW--V */
#define NV_PGRAPH_FFINTFC_ST2_SUBCH_3 0x00000003 /* RW--V */
#define NV_PGRAPH_FFINTFC_ST2_SUBCH_4 0x00000004 /* RW--V */
#define NV_PGRAPH_FFINTFC_ST2_SUBCH_5 0x00000005 /* RW--V */
#define NV_PGRAPH_FFINTFC_ST2_SUBCH_6 0x00000006 /* RW--V */
#define NV_PGRAPH_FFINTFC_ST2_SUBCH_7 0x00000007 /* RW--V */
#define NV_PGRAPH_FFINTFC_ST2_CHID 18:15 /* RWIVF */
#define NV_PGRAPH_FFINTFC_ST2_CHID_0 0x00000000 /* RWI-V */
#define NV_PGRAPH_FFINTFC_ST2_CHID_1 0x00000001 /* RW--V */
#define NV_PGRAPH_FFINTFC_ST2_CHID_2 0x00000002 /* RW--V */
#define NV_PGRAPH_FFINTFC_ST2_CHID_3 0x00000003 /* RW--V */
#define NV_PGRAPH_FFINTFC_ST2_CHID_4 0x00000004 /* RW--V */
#define NV_PGRAPH_FFINTFC_ST2_CHID_5 0x00000005 /* RW--V */
#define NV_PGRAPH_FFINTFC_ST2_CHID_6 0x00000006 /* RW--V */
#define NV_PGRAPH_FFINTFC_ST2_CHID_7 0x00000007 /* RW--V */
#define NV_PGRAPH_FFINTFC_ST2_CHID_8 0x00000008 /* RW--V */
#define NV_PGRAPH_FFINTFC_ST2_CHID_9 0x00000009 /* RW--V */
#define NV_PGRAPH_FFINTFC_ST2_CHID_10 0x0000000A /* RW--V */
#define NV_PGRAPH_FFINTFC_ST2_CHID_11 0x0000000B /* RW--V */
#define NV_PGRAPH_FFINTFC_ST2_CHID_12 0x0000000C /* RW--V */
#define NV_PGRAPH_FFINTFC_ST2_CHID_13 0x0000000D /* RW--V */
#define NV_PGRAPH_FFINTFC_ST2_CHID_14 0x0000000E /* RW--V */
#define NV_PGRAPH_FFINTFC_ST2_CHID_15 0x0000000F /* RW--V */
#define NV_PGRAPH_FFINTFC_ST2_CHID_STATUS 19:19 /* RWIVF */
#define NV_PGRAPH_FFINTFC_ST2_CHID_STATUS_INVALID 0x00000000 /* RWI-V */
#define NV_PGRAPH_FFINTFC_ST2_CHID_STATUS_VALID 0x00000001 /* RW--V */
#define NV_PGRAPH_FFINTFC_ST2_D 0x00400758 /* RW-4R */
#define NV_PGRAPH_FFINTFC_ST2_D_ARGUMENT 31:0 /* RWIVF */
#define NV_PGRAPH_FFINTFC_ST2_D_ARGUMENT_0 0x00000000 /* RWI-V */
#define NV_PGRAPH_STATUS 0x00400700 /* R--4R */
#define NV_PGRAPH_STATUS_STATE 0:0 /* R-IVF */
#define NV_PGRAPH_STATUS_STATE_IDLE 0x00000000 /* R-I-V */
#define NV_PGRAPH_STATUS_STATE_BUSY 0x00000001 /* R---V */
#define NV_PGRAPH_STATUS_XY_LOGIC 4:4 /* R-IVF */
#define NV_PGRAPH_STATUS_XY_LOGIC_IDLE 0x00000000 /* R-I-V */
#define NV_PGRAPH_STATUS_XY_LOGIC_BUSY 0x00000001 /* R---V */
#define NV_PGRAPH_STATUS_FE 5:5 /* R-IVF */
#define NV_PGRAPH_STATUS_FE_IDLE 0x00000000 /* R-I-V */
#define NV_PGRAPH_STATUS_FE_BUSY 0x00000001 /* R---V */
#define NV_PGRAPH_STATUS_RASTERIZER 6:6 /* R-IVF */
#define NV_PGRAPH_STATUS_RASTERIZER_IDLE 0x00000000 /* R-I-V */
#define NV_PGRAPH_STATUS_RASTERIZER_BUSY 0x00000001 /* R---V */
#define NV_PGRAPH_STATUS_PORT_NOTIFY 8:8 /* R-IVF */
#define NV_PGRAPH_STATUS_PORT_NOTIFY_IDLE 0x00000000 /* R-I-V */
#define NV_PGRAPH_STATUS_PORT_NOTIFY_BUSY 0x00000001 /* R---V */
#define NV_PGRAPH_STATUS_PORT_REGISTER 12:12 /* R-IVF */
#define NV_PGRAPH_STATUS_PORT_REGISTER_IDLE 0x00000000 /* R-I-V */
#define NV_PGRAPH_STATUS_PORT_REGISTER_BUSY 0x00000001 /* R---V */
#define NV_PGRAPH_STATUS_PORT_DMA 16:16 /* R-IVF */
#define NV_PGRAPH_STATUS_PORT_DMA_IDLE 0x00000000 /* R-I-V */
#define NV_PGRAPH_STATUS_PORT_DMA_BUSY 0x00000001 /* R---V */
#define NV_PGRAPH_STATUS_DMA_ENGINE 17:17 /* R-IVF */
#define NV_PGRAPH_STATUS_DMA_ENGINE_IDLE 0x00000000 /* R-I-V */
#define NV_PGRAPH_STATUS_DMA_ENGINE_BUSY 0x00000001 /* R---V */
#define NV_PGRAPH_STATUS_DMA_NOTIFY 20:20 /* R-IVF */
#define NV_PGRAPH_STATUS_DMA_NOTIFY_IDLE 0x00000000 /* R-I-V */
#define NV_PGRAPH_STATUS_DMA_NOTIFY_BUSY 0x00000001 /* R---V */
#define NV_PGRAPH_STATUS_DMA_BUFFER_NOTIFY 21:21 /* R-IVF */
#define NV_PGRAPH_STATUS_DMA_BUFFER_NOTIFY_IDLE 0x00000000 /* R-I-V */
#define NV_PGRAPH_STATUS_DMA_BUFFER_NOTIFY_BUSY 0x00000001 /* R---V */
#define NV_PGRAPH_STATUS_D3D 24:24 /* R-IVF */
#define NV_PGRAPH_STATUS_D3D_IDLE 0x00000000 /* R-I-V */
#define NV_PGRAPH_STATUS_D3D_BUSY 0x00000001 /* R---V */
#define NV_PGRAPH_STATUS_CACHE 25:25 /* R-IVF */
#define NV_PGRAPH_STATUS_CACHE_IDLE 0x00000000 /* R-I-V */
#define NV_PGRAPH_STATUS_CACHE_BUSY 0x00000001 /* R---V */
#define NV_PGRAPH_STATUS_LIGHTING 26:26 /* R-IVF */
#define NV_PGRAPH_STATUS_LIGHTING_IDLE 0x00000000 /* R-I-V */
#define NV_PGRAPH_STATUS_LIGHTING_BUSY 0x00000001 /* R---V */
#define NV_PGRAPH_STATUS_PREROP 27:27 /* R-IVF */
#define NV_PGRAPH_STATUS_PREROP_IDLE 0x00000000 /* R-I-V */
#define NV_PGRAPH_STATUS_PREROP_BUSY 0x00000001 /* R---V */
#define NV_PGRAPH_STATUS_ROP 28:28 /* R-IVF */
#define NV_PGRAPH_STATUS_ROP_IDLE 0x00000000 /* R-I-V */
#define NV_PGRAPH_STATUS_ROP_BUSY 0x00000001 /* R---V */
#define NV_PGRAPH_STATUS_PORT_USER 29:29 /* R-IVF */
#define NV_PGRAPH_STATUS_PORT_USER_IDLE 0x00000000 /* R-I-V */
#define NV_PGRAPH_STATUS_PORT_USER_BUSY 0x00000001 /* R---V */
#define NV_PGRAPH_TRAPPED_ADDR 0x00400704 /* R--4R */
#define NV_PGRAPH_TRAPPED_ADDR_MTHD 12:2 /* R-XUF */
#define NV_PGRAPH_TRAPPED_ADDR_SUBCH 15:13 /* R-XUF */
#define NV_PGRAPH_TRAPPED_ADDR_CHID 27:24 /* R-XUF */
#define NV_PGRAPH_TRAPPED_DATA 0x00400708 /* R--4R */
#define NV_PGRAPH_TRAPPED_DATA_VALUE 31:0 /* R-XVF */
#define NV_PGRAPH_SURFACE 0x0040070C /* RW-4R */
#define NV_PGRAPH_SURFACE_TYPE 1:0 /* RWIVF */
#define NV_PGRAPH_SURFACE_TYPE_INVALID 0x00000000 /* RWI-V */
#define NV_PGRAPH_SURFACE_TYPE_NON_SWIZZLE 0x00000001 /* RW--V */
#define NV_PGRAPH_SURFACE_TYPE_SWIZZLE 0x00000002 /* RW--V */
#define NV_PGRAPH_NOTIFY 0x00400714 /* RW-4R */
#define NV_PGRAPH_NOTIFY_BUFFER_REQ 0:0 /* RWIVF */
#define NV_PGRAPH_NOTIFY_BUFFER_REQ_NOT_PENDING 0x00000000 /* RWI-V */
#define NV_PGRAPH_NOTIFY_BUFFER_REQ_PENDING 0x00000001 /* RW--V */
#define NV_PGRAPH_NOTIFY_BUFFER_STYLE 8:8 /* RWIVF */
#define NV_PGRAPH_NOTIFY_BUFFER_STYLE_WRITE_ONLY 0x00000000 /* RWI-V */
#define NV_PGRAPH_NOTIFY_BUFFER_STYLE_WRITE_THEN_AWAKEN 0x00000001 /* RW--V */
#define NV_PGRAPH_NOTIFY_REQ 16:16 /* RWIVF */
#define NV_PGRAPH_NOTIFY_REQ_NOT_PENDING 0x00000000 /* RWI-V */
#define NV_PGRAPH_NOTIFY_REQ_PENDING 0x00000001 /* RW--V */
#define NV_PGRAPH_NOTIFY_STYLE 20:20 /* RWIVF */
#define NV_PGRAPH_NOTIFY_STYLE_WRITE_ONLY 0x00000000 /* RWI-V */
#define NV_PGRAPH_NOTIFY_STYLE_WRITE_THEN_AWAKEN 0x00000001 /* RW--V */
#define NV_PGRAPH_BOFFSET(i) (0x00400640+(i)*4) /* RW-4A */
#define NV_PGRAPH_BOFFSET__SIZE_1 6 /* */
#define NV_PGRAPH_BOFFSET_LINADRS 23:0 /* RWIUF */
#define NV_PGRAPH_BOFFSET_LINADRS_0 0x00000000 /* RWI-V */
#define NV_PGRAPH_BOFFSET0 0x00400640 /* RW-4R */
#define NV_PGRAPH_BOFFSET0__ALIAS_1 NV_PGRAPH_BOFFSET(0) /* */
#define NV_PGRAPH_BOFFSET0_LINADRS 23:0 /* RWIUF */
#define NV_PGRAPH_BOFFSET0_LINADRS_0 0x00000000 /* RWI-V */
#define NV_PGRAPH_BOFFSET1 0x00400644 /* RW-4R */
#define NV_PGRAPH_BOFFSET1__ALIAS_1 NV_PGRAPH_BOFFSET(1) /* */
#define NV_PGRAPH_BOFFSET1_LINADRS 23:0 /* RWIUF */
#define NV_PGRAPH_BOFFSET1_LINADRS_0 0x00000000 /* RWI-V */
#define NV_PGRAPH_BOFFSET2 0x00400648 /* RW-4R */
#define NV_PGRAPH_BOFFSET2__ALIAS_1 NV_PGRAPH_BOFFSET(2) /* */
#define NV_PGRAPH_BOFFSET2_LINADRS 23:0 /* RWIUF */
#define NV_PGRAPH_BOFFSET2_LINADRS_0 0x00000000 /* RWI-V */
#define NV_PGRAPH_BOFFSET3 0x0040064C /* RW-4R */
#define NV_PGRAPH_BOFFSET3__ALIAS_1 NV_PGRAPH_BOFFSET(3) /* */
#define NV_PGRAPH_BOFFSET3_LINADRS 23:0 /* RWIUF */
#define NV_PGRAPH_BOFFSET3_LINADRS_0 0x00000000 /* RWI-V */
#define NV_PGRAPH_BOFFSET4 0x00400650 /* RW-4R */
#define NV_PGRAPH_BOFFSET4__ALIAS_1 NV_PGRAPH_BOFFSET(4) /* */
#define NV_PGRAPH_BOFFSET4_LINADRS 23:0 /* RWIUF */
#define NV_PGRAPH_BOFFSET4_LINADRS_0 0x00000000 /* RWI-V */
#define NV_PGRAPH_BOFFSET5 0x00400654 /* RW-4R */
#define NV_PGRAPH_BOFFSET5__ALIAS_1 NV_PGRAPH_BOFFSET(5) /* */
#define NV_PGRAPH_BOFFSET5_LINADRS 23:0 /* RWIUF */
#define NV_PGRAPH_BOFFSET5_LINADRS_0 0x00000000 /* RWI-V */
#define NV_PGRAPH_BBASE(i) (0x00400658+(i)*4) /* RW-4A */
#define NV_PGRAPH_BBASE__SIZE_1 6 /* */
#define NV_PGRAPH_BBASE_LINADRS 23:0 /* RWIUF */
#define NV_PGRAPH_BBASE_LINADRS_0 0x00000000 /* RWI-V */
#define NV_PGRAPH_BBASE0 0x00400658 /* RW-4R */
#define NV_PGRAPH_BBASE0__ALIAS_1 NV_PGRAPH_BBASE(0) /* */
#define NV_PGRAPH_BBASE0_LINADRS 23:0 /* RWIUF */
#define NV_PGRAPH_BBASE0_LINADRS_0 0x00000000 /* RWI-V */
#define NV_PGRAPH_BBASE1 0x0040065c /* RW-4R */
#define NV_PGRAPH_BBASE1__ALIAS_1 NV_PGRAPH_BBASE(1) /* */
#define NV_PGRAPH_BBASE1_LINADRS 23:0 /* RWIUF */
#define NV_PGRAPH_BBASE1_LINADRS_0 0x00000000 /* RWI-V */
#define NV_PGRAPH_BBASE2 0x00400660 /* RW-4R */
#define NV_PGRAPH_BBASE2__ALIAS_1 NV_PGRAPH_BBASE(2) /* */
#define NV_PGRAPH_BBASE2_LINADRS 23:0 /* RWIUF */
#define NV_PGRAPH_BBASE2_LINADRS_0 0x00000000 /* RWI-V */
#define NV_PGRAPH_BBASE3 0x00400664 /* RW-4R */
#define NV_PGRAPH_BBASE3__ALIAS_1 NV_PGRAPH_BBASE(3) /* */
#define NV_PGRAPH_BBASE3_LINADRS 23:0 /* RWIUF */
#define NV_PGRAPH_BBASE3_LINADRS_0 0x00000000 /* RWI-V */
#define NV_PGRAPH_BBASE4 0x00400668 /* RW-4R */
#define NV_PGRAPH_BBASE4__ALIAS_1 NV_PGRAPH_BBASE(4) /* */
#define NV_PGRAPH_BBASE4_LINADRS 23:0 /* RWIUF */
#define NV_PGRAPH_BBASE4_LINADRS_0 0x00000000 /* RWI-V */
#define NV_PGRAPH_BBASE5 0x0040066C /* RW-4R */
#define NV_PGRAPH_BBASE5__ALIAS_1 NV_PGRAPH_BBASE(5) /* */
#define NV_PGRAPH_BBASE5_LINADRS 23:0 /* RWIUF */
#define NV_PGRAPH_BBASE5_LINADRS_0 0x00000000 /* RWI-V */
#define NV_PGRAPH_BPITCH(i) (0x00400670+(i)*4) /* RW-4A */
#define NV_PGRAPH_BPITCH__SIZE_1 5 /* */
#define NV_PGRAPH_BPITCH_VALUE 12:0 /* RWIUF */
#define NV_PGRAPH_BPITCH_VALUE_0 0x00000000 /* RWI-V */
#define NV_PGRAPH_BPITCH0 0x00400670 /* RW-4R */
#define NV_PGRAPH_BPITCH0__ALIAS_1 NV_PGRAPH_BPITCH(0) /* */
#define NV_PGRAPH_BPITCH0_VALUE 12:0 /* RWIUF */
#define NV_PGRAPH_BPITCH0_VALUE_0 0x00000000 /* RWI-V */
#define NV_PGRAPH_BPITCH1 0x00400674 /* RW-4R */
#define NV_PGRAPH_BPITCH1__ALIAS_1 NV_PGRAPH_BPITCH(1) /* */
#define NV_PGRAPH_BPITCH1_VALUE 12:0 /* RWIUF */
#define NV_PGRAPH_BPITCH1_VALUE_0 0x00000000 /* RWI-V */
#define NV_PGRAPH_BPITCH2 0x00400678 /* RW-4R */
#define NV_PGRAPH_BPITCH2__ALIAS_1 NV_PGRAPH_BPITCH(2) /* */
#define NV_PGRAPH_BPITCH2_VALUE 12:0 /* RWIUF */
#define NV_PGRAPH_BPITCH2_VALUE_0 0x00000000 /* RWI-V */
#define NV_PGRAPH_BPITCH3 0x0040067C /* RW-4R */
#define NV_PGRAPH_BPITCH3__ALIAS_1 NV_PGRAPH_BPITCH(3) /* */
#define NV_PGRAPH_BPITCH3_VALUE 12:0 /* RWIUF */
#define NV_PGRAPH_BPITCH3_VALUE_0 0x00000000 /* RWI-V */
#define NV_PGRAPH_BPITCH4 0x00400680 /* RW-4R */
#define NV_PGRAPH_BPITCH4__ALIAS_1 NV_PGRAPH_BPITCH(4) /* */
#define NV_PGRAPH_BPITCH4_VALUE 12:0 /* RWIUF */
#define NV_PGRAPH_BPITCH4_VALUE_0 0x00000000 /* RWI-V */
#define NV_PGRAPH_BLIMIT(i) (0x00400684+(i)*4) /* RW-4A */
#define NV_PGRAPH_BLIMIT__SIZE_1 6 /* */
#define NV_PGRAPH_BLIMIT_VALUE 23:0 /* RWXUF */
#define NV_PGRAPH_BLIMIT_TYPE 31:31 /* RWIVF */
#define NV_PGRAPH_BLIMIT_TYPE_IN_MEMORY 0x00000000 /* RW--V */
#define NV_PGRAPH_BLIMIT_TYPE_NULL 0x00000001 /* RWI-V */
#define NV_PGRAPH_BLIMIT0 0x00400684 /* RW-4R */
#define NV_PGRAPH_BLIMIT0__ALIAS_1 NV_PGRAPH_BLIMIT(0) /* */
#define NV_PGRAPH_BLIMIT0_VALUE 23:0 /* RWXUF */
#define NV_PGRAPH_BLIMIT0_TYPE 31:31 /* RWIVF */
#define NV_PGRAPH_BLIMIT0_TYPE_IN_MEMORY 0x00000000 /* RW--V */
#define NV_PGRAPH_BLIMIT0_TYPE_NULL 0x00000001 /* RWI-V */
#define NV_PGRAPH_BLIMIT1 0x00400688 /* RW-4R */
#define NV_PGRAPH_BLIMIT1__ALIAS_1 NV_PGRAPH_BLIMIT(1) /* */
#define NV_PGRAPH_BLIMIT1_VALUE 23:0 /* RWXUF */
#define NV_PGRAPH_BLIMIT1_TYPE 31:31 /* RWIVF */
#define NV_PGRAPH_BLIMIT1_TYPE_IN_MEMORY 0x00000000 /* RW--V */
#define NV_PGRAPH_BLIMIT1_TYPE_NULL 0x00000001 /* RWI-V */
#define NV_PGRAPH_BLIMIT2 0x0040068c /* RW-4R */
#define NV_PGRAPH_BLIMIT2__ALIAS_1 NV_PGRAPH_BLIMIT(2) /* */
#define NV_PGRAPH_BLIMIT2_VALUE 23:0 /* RWXUF */
#define NV_PGRAPH_BLIMIT2_TYPE 31:31 /* RWIVF */
#define NV_PGRAPH_BLIMIT2_TYPE_IN_MEMORY 0x00000000 /* RW--V */
#define NV_PGRAPH_BLIMIT2_TYPE_NULL 0x00000001 /* RWI-V */
#define NV_PGRAPH_BLIMIT3 0x00400690 /* RW-4R */
#define NV_PGRAPH_BLIMIT3__ALIAS_1 NV_PGRAPH_BLIMIT(3) /* */
#define NV_PGRAPH_BLIMIT3_VALUE 23:0 /* RWXUF */
#define NV_PGRAPH_BLIMIT3_TYPE 31:31 /* RWIVF */
#define NV_PGRAPH_BLIMIT3_TYPE_IN_MEMORY 0x00000000 /* RW--V */
#define NV_PGRAPH_BLIMIT3_TYPE_NULL 0x00000001 /* RWI-V */
#define NV_PGRAPH_BLIMIT4 0x00400694 /* RW-4R */
#define NV_PGRAPH_BLIMIT4__ALIAS_1 NV_PGRAPH_BLIMIT(4) /* */
#define NV_PGRAPH_BLIMIT4_VALUE 23:0 /* RWXUF */
#define NV_PGRAPH_BLIMIT4_TYPE 31:31 /* RWIVF */
#define NV_PGRAPH_BLIMIT4_TYPE_IN_MEMORY 0x00000000 /* RW--V */
#define NV_PGRAPH_BLIMIT4_TYPE_NULL 0x00000001 /* RWI-V */
#define NV_PGRAPH_BLIMIT5 0x00400698 /* RW-4R */
#define NV_PGRAPH_BLIMIT5__ALIAS_1 NV_PGRAPH_BLIMIT(5) /* */
#define NV_PGRAPH_BLIMIT5_VALUE 23:0 /* RWXUF */
#define NV_PGRAPH_BLIMIT5_TYPE 31:31 /* RWIVF */
#define NV_PGRAPH_BLIMIT5_TYPE_IN_MEMORY 0x00000000 /* RW--V */
#define NV_PGRAPH_BLIMIT5_TYPE_NULL 0x00000001 /* RWI-V */
#define NV_PGRAPH_BSWIZZLE2 0x0040069c /* RW-4R */
#define NV_PGRAPH_BSWIZZLE2_WIDTH 19:16 /* RWIUF */
#define NV_PGRAPH_BSWIZZLE2_WIDTH_0 0x00000000 /* RWI-V */
#define NV_PGRAPH_BSWIZZLE2_HEIGHT 27:24 /* RWIUF */
#define NV_PGRAPH_BSWIZZLE2_HEIGHT_0 0x00000000 /* RWI-V */
#define NV_PGRAPH_BSWIZZLE5 0x004006a0 /* RW-4R */
#define NV_PGRAPH_BSWIZZLE5_WIDTH 19:16 /* RWIUF */
#define NV_PGRAPH_BSWIZZLE5_WIDTH_0 0x00000000 /* RWI-V */
#define NV_PGRAPH_BSWIZZLE5_HEIGHT 27:24 /* RWIUF */
#define NV_PGRAPH_BSWIZZLE5_HEIGHT_0 0x00000000 /* RWI-V */
#define NV_PGRAPH_BPIXEL 0x00400724 /* RW-4R */
#define NV_PGRAPH_BPIXEL_DEPTH0 3:0 /* RWIVF */
#define NV_PGRAPH_BPIXEL_DEPTH0_INVALID 0x00000000 /* RWI-V */
#define NV_PGRAPH_BPIXEL_DEPTH0_Y8 0x00000001 /* RW--V */
#define NV_PGRAPH_BPIXEL_DEPTH0_X1R5G5B5_Z1R5G5B5 0x00000002 /* RW--V */
#define NV_PGRAPH_BPIXEL_DEPTH0_X1R5G5B5_O1R5G5B5 0x00000003 /* RW--V */
#define NV_PGRAPH_BPIXEL_DEPTH0_A1R5G5B5 0x00000004 /* RW--V */
#define NV_PGRAPH_BPIXEL_DEPTH0_R5G6B5 0x00000005 /* RW--V */
#define NV_PGRAPH_BPIXEL_DEPTH0_Y16 0x00000006 /* RW--V */
#define NV_PGRAPH_BPIXEL_DEPTH0_X8R8G8B8_Z8R8G8B8 0x00000007 /* RW--V */
#define NV_PGRAPH_BPIXEL_DEPTH0_X8R8G8B8_O1Z7R8G8B8 0x00000008 /* RW--V */
#define NV_PGRAPH_BPIXEL_DEPTH0_X1A7R8G8B8_Z1A7R8G8B8 0x00000009 /* RW--V */
#define NV_PGRAPH_BPIXEL_DEPTH0_X1A7R8G8B8_O1A7R8G8B8 0x0000000a /* RW--V */
#define NV_PGRAPH_BPIXEL_DEPTH0_X8R8G8B8_O8R8G8B8 0x0000000b /* RW--V */
#define NV_PGRAPH_BPIXEL_DEPTH0_A8R8G8B8 0x0000000c /* RW--V */
#define NV_PGRAPH_BPIXEL_DEPTH0_Y32 0x0000000d /* RW--V */
#define NV_PGRAPH_BPIXEL_DEPTH0_V8YB8U8YA8 0x0000000e /* RW--V */
#define NV_PGRAPH_BPIXEL_DEPTH0_YB8V8YA8U8 0x0000000f /* RW--V */
#define NV_PGRAPH_BPIXEL_DEPTH1 7:4 /* RWIVF */
#define NV_PGRAPH_BPIXEL_DEPTH1_INVALID 0x00000000 /* RWI-V */
#define NV_PGRAPH_BPIXEL_DEPTH1_Y8 0x00000001 /* RW--V */
#define NV_PGRAPH_BPIXEL_DEPTH1_X1R5G5B5_Z1R5G5B5 0x00000002 /* RW--V */
#define NV_PGRAPH_BPIXEL_DEPTH1_X1R5G5B5_O1R5G5B5 0x00000003 /* RW--V */
#define NV_PGRAPH_BPIXEL_DEPTH1_A1R5G5B5 0x00000004 /* RW--V */
#define NV_PGRAPH_BPIXEL_DEPTH1_R5G6B5 0x00000005 /* RW--V */
#define NV_PGRAPH_BPIXEL_DEPTH1_Y16 0x00000006 /* RW--V */
#define NV_PGRAPH_BPIXEL_DEPTH1_X8R8G8B8_Z8R8G8B8 0x00000007 /* RW--V */
#define NV_PGRAPH_BPIXEL_DEPTH1_X8R8G8B8_O1Z7R8G8B8 0x00000008 /* RW--V */
#define NV_PGRAPH_BPIXEL_DEPTH1_X1A7R8G8B8_Z1A7R8G8B8 0x00000009 /* RW--V */
#define NV_PGRAPH_BPIXEL_DEPTH1_X1A7R8G8B8_O1A7R8G8B8 0x0000000a /* RW--V */
#define NV_PGRAPH_BPIXEL_DEPTH1_X8R8G8B8_O8R8G8B8 0x0000000b /* RW--V */
#define NV_PGRAPH_BPIXEL_DEPTH1_A8R8G8B8 0x0000000c /* RW--V */
#define NV_PGRAPH_BPIXEL_DEPTH1_Y32 0x0000000d /* RW--V */
#define NV_PGRAPH_BPIXEL_DEPTH1_V8YB8U8YA8 0x0000000e /* RW--V */
#define NV_PGRAPH_BPIXEL_DEPTH1_YB8V8YA8U8 0x0000000f /* RW--V */
#define NV_PGRAPH_BPIXEL_DEPTH2 11:8 /* RWIVF */
#define NV_PGRAPH_BPIXEL_DEPTH2_INVALID 0x00000000 /* RWI-V */
#define NV_PGRAPH_BPIXEL_DEPTH2_Y8 0x00000001 /* RW--V */
#define NV_PGRAPH_BPIXEL_DEPTH2_X1R5G5B5_Z1R5G5B5 0x00000002 /* RW--V */
#define NV_PGRAPH_BPIXEL_DEPTH2_X1R5G5B5_O1R5G5B5 0x00000003 /* RW--V */
#define NV_PGRAPH_BPIXEL_DEPTH2_A1R5G5B5 0x00000004 /* RW--V */
#define NV_PGRAPH_BPIXEL_DEPTH2_R5G6B5 0x00000005 /* RW--V */
#define NV_PGRAPH_BPIXEL_DEPTH2_Y16 0x00000006 /* RW--V */
#define NV_PGRAPH_BPIXEL_DEPTH2_X8R8G8B8_Z8R8G8B8 0x00000007 /* RW--V */
#define NV_PGRAPH_BPIXEL_DEPTH2_X8R8G8B8_O1Z7R8G8B8 0x00000008 /* RW--V */
#define NV_PGRAPH_BPIXEL_DEPTH2_X1A7R8G8B8_Z1A7R8G8B8 0x00000009 /* RW--V */
#define NV_PGRAPH_BPIXEL_DEPTH2_X1A7R8G8B8_O1A7R8G8B8 0x0000000a /* RW--V */
#define NV_PGRAPH_BPIXEL_DEPTH2_X8R8G8B8_O8R8G8B8 0x0000000b /* RW--V */
#define NV_PGRAPH_BPIXEL_DEPTH2_A8R8G8B8 0x0000000c /* RW--V */
#define NV_PGRAPH_BPIXEL_DEPTH2_Y32 0x0000000d /* RW--V */
#define NV_PGRAPH_BPIXEL_DEPTH2_V8YB8U8YA8 0x0000000e /* RW--V */
#define NV_PGRAPH_BPIXEL_DEPTH2_YB8V8YA8U8 0x0000000f /* RW--V */
#define NV_PGRAPH_BPIXEL_DEPTH3 15:12 /* RWIVF */
#define NV_PGRAPH_BPIXEL_DEPTH3_INVALID 0x00000000 /* RWI-V */
#define NV_PGRAPH_BPIXEL_DEPTH3_Y8 0x00000001 /* RW--V */
#define NV_PGRAPH_BPIXEL_DEPTH3_X1R5G5B5_Z1R5G5B5 0x00000002 /* RW--V */
#define NV_PGRAPH_BPIXEL_DEPTH3_X1R5G5B5_O1R5G5B5 0x00000003 /* RW--V */
#define NV_PGRAPH_BPIXEL_DEPTH3_A1R5G5B5 0x00000004 /* RW--V */
#define NV_PGRAPH_BPIXEL_DEPTH3_R5G6B5 0x00000005 /* RW--V */
#define NV_PGRAPH_BPIXEL_DEPTH3_Y16 0x00000006 /* RW--V */
#define NV_PGRAPH_BPIXEL_DEPTH3_X8R8G8B8_Z8R8G8B8 0x00000007 /* RW--V */
#define NV_PGRAPH_BPIXEL_DEPTH3_X8R8G8B8_O1Z7R8G8B8 0x00000008 /* RW--V */
#define NV_PGRAPH_BPIXEL_DEPTH3_X1A7R8G8B8_Z1A7R8G8B8 0x00000009 /* RW--V */
#define NV_PGRAPH_BPIXEL_DEPTH3_X1A7R8G8B8_O1A7R8G8B8 0x0000000a /* RW--V */
#define NV_PGRAPH_BPIXEL_DEPTH3_X8R8G8B8_O8R8G8B8 0x0000000b /* RW--V */
#define NV_PGRAPH_BPIXEL_DEPTH3_A8R8G8B8 0x0000000c /* RW--V */
#define NV_PGRAPH_BPIXEL_DEPTH3_Y32 0x0000000d /* RW--V */
#define NV_PGRAPH_BPIXEL_DEPTH3_V8YB8U8YA8 0x0000000e /* RW--V */
#define NV_PGRAPH_BPIXEL_DEPTH3_YB8V8YA8U8 0x0000000f /* RW--V */
#define NV_PGRAPH_BPIXEL_DEPTH4 19:16 /* RWIVF */
#define NV_PGRAPH_BPIXEL_DEPTH4_INVALID 0x00000000 /* RWI-V */
#define NV_PGRAPH_BPIXEL_DEPTH4_Y8 0x00000001 /* RW--V */
#define NV_PGRAPH_BPIXEL_DEPTH4_X1R5G5B5_Z1R5G5B5 0x00000002 /* RW--V */
#define NV_PGRAPH_BPIXEL_DEPTH4_X1R5G5B5_O1R5G5B5 0x00000003 /* RW--V */
#define NV_PGRAPH_BPIXEL_DEPTH4_A1R5G5B5 0x00000004 /* RW--V */
#define NV_PGRAPH_BPIXEL_DEPTH4_R5G6B5 0x00000005 /* RW--V */
#define NV_PGRAPH_BPIXEL_DEPTH4_Y16 0x00000006 /* RW--V */
#define NV_PGRAPH_BPIXEL_DEPTH4_X8R8G8B8_Z8R8G8B8 0x00000007 /* RW--V */
#define NV_PGRAPH_BPIXEL_DEPTH4_X8R8G8B8_O1Z7R8G8B8 0x00000008 /* RW--V */
#define NV_PGRAPH_BPIXEL_DEPTH4_X1A7R8G8B8_Z1A7R8G8B8 0x00000009 /* RW--V */
#define NV_PGRAPH_BPIXEL_DEPTH4_X1A7R8G8B8_O1A7R8G8B8 0x0000000a /* RW--V */
#define NV_PGRAPH_BPIXEL_DEPTH4_X8R8G8B8_O8R8G8B8 0x0000000b /* RW--V */
#define NV_PGRAPH_BPIXEL_DEPTH4_A8R8G8B8 0x0000000c /* RW--V */
#define NV_PGRAPH_BPIXEL_DEPTH4_Y32 0x0000000d /* RW--V */
#define NV_PGRAPH_BPIXEL_DEPTH4_V8YB8U8YA8 0x0000000e /* RW--V */
#define NV_PGRAPH_BPIXEL_DEPTH4_YB8V8YA8U8 0x0000000f /* RW--V */
#define NV_PGRAPH_BPIXEL_DEPTH5 23:20 /* RWIVF */
#define NV_PGRAPH_BPIXEL_DEPTH5_INVALID 0x00000000 /* RWI-V */
#define NV_PGRAPH_BPIXEL_DEPTH5_Y8 0x00000001 /* RW--V */
#define NV_PGRAPH_BPIXEL_DEPTH5_X1R5G5B5_Z1R5G5B5 0x00000002 /* RW--V */
#define NV_PGRAPH_BPIXEL_DEPTH5_X1R5G5B5_O1R5G5B5 0x00000003 /* RW--V */
#define NV_PGRAPH_BPIXEL_DEPTH5_A1R5G5B5 0x00000004 /* RW--V */
#define NV_PGRAPH_BPIXEL_DEPTH5_R5G6B5 0x00000005 /* RW--V */
#define NV_PGRAPH_BPIXEL_DEPTH5_Y16 0x00000006 /* RW--V */
#define NV_PGRAPH_BPIXEL_DEPTH5_X8R8G8B8_Z8R8G8B8 0x00000007 /* RW--V */
#define NV_PGRAPH_BPIXEL_DEPTH5_X8R8G8B8_O1Z7R8G8B8 0x00000008 /* RW--V */
#define NV_PGRAPH_BPIXEL_DEPTH5_X1A7R8G8B8_Z1A7R8G8B8 0x00000009 /* RW--V */
#define NV_PGRAPH_BPIXEL_DEPTH5_X1A7R8G8B8_O1A7R8G8B8 0x0000000a /* RW--V */
#define NV_PGRAPH_BPIXEL_DEPTH5_X8R8G8B8_O8R8G8B8 0x0000000b /* RW--V */
#define NV_PGRAPH_BPIXEL_DEPTH5_A8R8G8B8 0x0000000c /* RW--V */
#define NV_PGRAPH_BPIXEL_DEPTH5_Y32 0x0000000d /* RW--V */
#define NV_PGRAPH_BPIXEL_DEPTH5_V8YB8U8YA8 0x0000000e /* RW--V */
#define NV_PGRAPH_BPIXEL_DEPTH5_YB8V8YA8U8 0x0000000f /* RW--V */
#define NV_PGRAPH_LIMIT_VIOL_PIX 0x00400610 /* RW-4R */
#define NV_PGRAPH_LIMIT_VIOL_PIX_ADRS 23:0 /* RWIVF */
#define NV_PGRAPH_LIMIT_VIOL_PIX_ADRS_0 0x00000000 /* RWI-V */
#define NV_PGRAPH_LIMIT_VIOL_PIX_BLIT 29:29 /* RWIVF */
#define NV_PGRAPH_LIMIT_VIOL_PIX_BLIT_NO_VIOL 0x00000000 /* RWI-V */
#define NV_PGRAPH_LIMIT_VIOL_PIX_BLIT_VIOL 0x00000001 /* RW--V */
#define NV_PGRAPH_LIMIT_VIOL_PIX_LIMIT 30:30 /* RWIVF */
#define NV_PGRAPH_LIMIT_VIOL_PIX_LIMIT_NO_VIOL 0x00000000 /* RWI-V */
#define NV_PGRAPH_LIMIT_VIOL_PIX_LIMIT_VIOL 0x00000001 /* RW--V */
#define NV_PGRAPH_LIMIT_VIOL_PIX_OVRFLW 31:31 /* RWIVF */
#define NV_PGRAPH_LIMIT_VIOL_PIX_OVRFLW_NO_VIOL 0x00000000 /* RWI-V */
#define NV_PGRAPH_LIMIT_VIOL_PIX_OVRFLW_VIOL 0x00000001 /* RW--V */
#define NV_PGRAPH_LIMIT_VIOL_Z 0x00400614 /* RW-4R */
#define NV_PGRAPH_LIMIT_VIOL_Z_ADRS 23:0 /* RWIVF */
#define NV_PGRAPH_LIMIT_VIOL_Z_ADRS_0 0x00000000 /* RWI-V */
#define NV_PGRAPH_LIMIT_VIOL_Z_LIMIT 30:30 /* RWIVF */
#define NV_PGRAPH_LIMIT_VIOL_Z_LIMIT_NO_VIOL 0x00000000 /* RWI-V */
#define NV_PGRAPH_LIMIT_VIOL_Z_LIMIT_VIOL 0x00000001 /* RW--V */
#define NV_PGRAPH_LIMIT_VIOL_Z_OVRFLW 31:31 /* RWIVF */
#define NV_PGRAPH_LIMIT_VIOL_Z_OVRFLW_NO_VIOL 0x00000000 /* RWI-V */
#define NV_PGRAPH_LIMIT_VIOL_Z_OVRFLW_VIOL 0x00000001 /* RW--V */
#define NV_PGRAPH_STATE 0x00400710 /* RW-4R */
#define NV_PGRAPH_STATE_BUFFER_0 0:0 /* RWIVF */
#define NV_PGRAPH_STATE_BUFFER_0_INVALID 0x00000000 /* RWI-V */
#define NV_PGRAPH_STATE_BUFFER_0_VALID 0x00000001 /* RW--V */
#define NV_PGRAPH_STATE_BUFFER_1 1:1 /* RWIVF */
#define NV_PGRAPH_STATE_BUFFER_1_INVALID 0x00000000 /* RWI-V */
#define NV_PGRAPH_STATE_BUFFER_1_VALID 0x00000001 /* RW--V */
#define NV_PGRAPH_STATE_BUFFER_2 2:2 /* RWIVF */
#define NV_PGRAPH_STATE_BUFFER_2_INVALID 0x00000000 /* RWI-V */
#define NV_PGRAPH_STATE_BUFFER_2_VALID 0x00000001 /* RW--V */
#define NV_PGRAPH_STATE_BUFFER_3 3:3 /* RWIVF */
#define NV_PGRAPH_STATE_BUFFER_3_INVALID 0x00000000 /* RWI-V */
#define NV_PGRAPH_STATE_BUFFER_3_VALID 0x00000001 /* RW--V */
#define NV_PGRAPH_STATE_BUFFER_4 4:4 /* RWIVF */
#define NV_PGRAPH_STATE_BUFFER_4_INVALID 0x00000000 /* RWI-V */
#define NV_PGRAPH_STATE_BUFFER_4_VALID 0x00000001 /* RW--V */
#define NV_PGRAPH_STATE_BUFFER_5 5:5 /* RWIVF */
#define NV_PGRAPH_STATE_BUFFER_5_INVALID 0x00000000 /* RWI-V */
#define NV_PGRAPH_STATE_BUFFER_5_VALID 0x00000001 /* RW--V */
#define NV_PGRAPH_STATE_PITCH_0 8:8 /* RWIVF */
#define NV_PGRAPH_STATE_PITCH_0_INVALID 0x00000000 /* RWI-V */
#define NV_PGRAPH_STATE_PITCH_0_VALID 0x00000001 /* RW--V */
#define NV_PGRAPH_STATE_PITCH_1 9:9 /* RWIVF */
#define NV_PGRAPH_STATE_PITCH_1_INVALID 0x00000000 /* RWI-V */
#define NV_PGRAPH_STATE_PITCH_1_VALID 0x00000001 /* RW--V */
#define NV_PGRAPH_STATE_PITCH_2 10:10 /* RWIVF */
#define NV_PGRAPH_STATE_PITCH_2_INVALID 0x00000000 /* RWI-V */
#define NV_PGRAPH_STATE_PITCH_2_VALID 0x00000001 /* RW--V */
#define NV_PGRAPH_STATE_PITCH_3 11:11 /* RWIVF */
#define NV_PGRAPH_STATE_PITCH_3_INVALID 0x00000000 /* RWI-V */
#define NV_PGRAPH_STATE_PITCH_3_VALID 0x00000001 /* RW--V */
#define NV_PGRAPH_STATE_PITCH_4 12:12 /* RWIVF */
#define NV_PGRAPH_STATE_PITCH_4_INVALID 0x00000000 /* RWI-V */
#define NV_PGRAPH_STATE_PITCH_4_VALID 0x00000001 /* RW--V */
#define NV_PGRAPH_STATE_CHROMA_COLOR 16:16 /* RWIVF */
#define NV_PGRAPH_STATE_CHROMA_COLOR_INVALID 0x00000000 /* RWI-V */
#define NV_PGRAPH_STATE_CHROMA_COLOR_VALID 0x00000001 /* RW--V */
#define NV_PGRAPH_STATE_CHROMA_COLORFMT 17:17 /* RWIVF */
#define NV_PGRAPH_STATE_CHROMA_COLORFMT_INVALID 0x00000000 /* RWI-V */
#define NV_PGRAPH_STATE_CHROMA_COLORFMT_VALID 0x00000001 /* RW--V */
#define NV_PGRAPH_STATE_CPATTERN_COLORFMT 20:20 /* RWIVF */
#define NV_PGRAPH_STATE_CPATTERN_COLORFMT_INVALID 0x00000000 /* RWI-V */
#define NV_PGRAPH_STATE_CPATTERN_COLORFMT_VALID 0x00000001 /* RW--V */
#define NV_PGRAPH_STATE_CPATTERN_MONOFMT 21:21 /* RWIVF */
#define NV_PGRAPH_STATE_CPATTERN_MONOFMT_INVALID 0x00000000 /* RWI-V */
#define NV_PGRAPH_STATE_CPATTERN_MONOFMT_VALID 0x00000001 /* RW--V */
#define NV_PGRAPH_STATE_CPATTERN_SELECT 22:22 /* RWIVF */
#define NV_PGRAPH_STATE_CPATTERN_SELECT_INVALID 0x00000000 /* RWI-V */
#define NV_PGRAPH_STATE_CPATTERN_SELECT_VALID 0x00000001 /* RW--V */
#define NV_PGRAPH_STATE_PATTERN_COLOR0 24:24 /* RWIVF */
#define NV_PGRAPH_STATE_PATTERN_COLOR0_INVALID 0x00000000 /* RWI-V */
#define NV_PGRAPH_STATE_PATTERN_COLOR0_VALID 0x00000001 /* RW--V */
#define NV_PGRAPH_STATE_PATTERN_COLOR1 25:25 /* RWIVF */
#define NV_PGRAPH_STATE_PATTERN_COLOR1_INVALID 0x00000000 /* RWI-V */
#define NV_PGRAPH_STATE_PATTERN_COLOR1_VALID 0x00000001 /* RW--V */
#define NV_PGRAPH_STATE_PATTERN_PATT0 26:26 /* RWIVF */
#define NV_PGRAPH_STATE_PATTERN_PATT0_INVALID 0x00000000 /* RWI-V */
#define NV_PGRAPH_STATE_PATTERN_PATT0_VALID 0x00000001 /* RW--V */
#define NV_PGRAPH_STATE_PATTERN_PATT1 27:27 /* RWIVF */
#define NV_PGRAPH_STATE_PATTERN_PATT1_INVALID 0x00000000 /* RWI-V */
#define NV_PGRAPH_STATE_PATTERN_PATT1_VALID 0x00000001 /* RW--V */
#define NV_PGRAPH_CACHE_INDEX 0x00400728 /* RW-4R */
#define NV_PGRAPH_CACHE_INDEX_BANK 2:2 /* RWXVF */
#define NV_PGRAPH_CACHE_INDEX_BANK_10 0x00000000 /* RW--V */
#define NV_PGRAPH_CACHE_INDEX_BANK_32 0x00000001 /* RW--V */
#define NV_PGRAPH_CACHE_INDEX_ADRS 12:3 /* RWXVF */
#define NV_PGRAPH_CACHE_INDEX_ADRS_0 0x00000000 /* RW--V */
#define NV_PGRAPH_CACHE_INDEX_ADRS_1024 0x00000400 /* RW--V */
#define NV_PGRAPH_CACHE_INDEX_OP 14:13 /* RWXVF */
#define NV_PGRAPH_CACHE_INDEX_OP_WR_CACHE 0x00000000 /* RW--V */
#define NV_PGRAPH_CACHE_INDEX_OP_RD_CACHE 0x00000001 /* RW--V */
#define NV_PGRAPH_CACHE_INDEX_OP_RD_INDEX 0x00000002 /* RW--V */
#define NV_PGRAPH_CACHE_RAM 0x0040072c /* RW-4R */
#define NV_PGRAPH_CACHE_RAM_VALUE 31:0 /* RWXVF */
#define NV_PGRAPH_DMA_PITCH 0x00400760 /* RW-4R */
#define NV_PGRAPH_DMA_PITCH_S0 15:0 /* RWXSF */
#define NV_PGRAPH_DMA_PITCH_S1 31:16 /* RWXSF */
#define NV_PGRAPH_DVD_COLORFMT 0x00400764 /* RW-4R */
#define NV_PGRAPH_DVD_COLORFMT_IMAGE 5:0 /* RWNVF */
#define NV_PGRAPH_DVD_COLORFMT_IMAGE_FORMAT_INVALID 0x00 /* RWN-V */
#define NV_PGRAPH_DVD_COLORFMT_IMAGE_FORMAT_LE_V8YB8U8YA8 0x12 /* RW--V */
#define NV_PGRAPH_DVD_COLORFMT_IMAGE_FORMAT_LE_YB8V8YA8U8 0x13 /* RW--V */
#define NV_PGRAPH_DVD_COLORFMT_OVLY 9:8 /* RWNVF */
#define NV_PGRAPH_DVD_COLORFMT_OVLY_FORMAT_INVALID 0x00 /* RWN-V */
#define NV_PGRAPH_DVD_COLORFMT_OVLY_FORMAT_LE_A8Y8U8V8 0x01 /* RW--V */
#define NV_PGRAPH_DVD_COLORFMT_OVLY_FORMAT_LE_A4V6YB6A4U6YA6 0x02 /* RW--V */
#define NV_PGRAPH_DVD_COLORFMT_OVLY_FORMAT_TRANSPARENT 0x03 /* RW--V */
#define NV_PGRAPH_SCALED_FORMAT 0x00400768 /* RW-4R */
#define NV_PGRAPH_SCALED_FORMAT_ORIGIN 17:16 /* RWIVF */
#define NV_PGRAPH_SCALED_FORMAT_ORIGIN_INVALID 0x00000000 /* RWI-V */
#define NV_PGRAPH_SCALED_FORMAT_ORIGIN_CENTER 0x00000001 /* RW--V */
#define NV_PGRAPH_SCALED_FORMAT_ORIGIN_CORNER 0x00000002 /* RW--V */
#define NV_PGRAPH_SCALED_FORMAT_INTERPOLATOR 24:24 /* RWIVF */
#define NV_PGRAPH_SCALED_FORMAT_INTERPOLATOR_ZOH 0x00000000 /* RWI-V */
#define NV_PGRAPH_SCALED_FORMAT_INTERPOLATOR_FOH 0x00000001 /* RW--V */
#define NV_PGRAPH_PATT_COLOR0 0x00400800 /* RW-4R */
#define NV_PGRAPH_PATT_COLOR0_VALUE 31:0 /* RWXUF */
#define NV_PGRAPH_PATT_COLOR1 0x00400804 /* RW-4R */
#define NV_PGRAPH_PATT_COLOR1_VALUE 31:0 /* RWXUF */
#define NV_PGRAPH_PATT_COLORRAM(i) (0x00400900+(i)*4) /* R--4A */
#define NV_PGRAPH_PATT_COLORRAM__SIZE_1 64 /* */
#define NV_PGRAPH_PATT_COLORRAM_VALUE 23:0 /* R--UF */
#define NV_PGRAPH_PATTERN(i) (0x00400808+(i)*4) /* RW-4A */
#define NV_PGRAPH_PATTERN__SIZE_1 2 /* */
#define NV_PGRAPH_PATTERN_BITMAP 31:0 /* RWXVF */
#define NV_PGRAPH_PATTERN_SHAPE 0x00400810 /* RW-4R */
#define NV_PGRAPH_PATTERN_SHAPE_VALUE 1:0 /* RWXVF */
#define NV_PGRAPH_PATTERN_SHAPE_VALUE_8X_8Y 0x00000000 /* RW--V */
#define NV_PGRAPH_PATTERN_SHAPE_VALUE_64X_1Y 0x00000001 /* RW--V */
#define NV_PGRAPH_PATTERN_SHAPE_VALUE_1X_64Y 0x00000002 /* RW--V */
#define NV_PGRAPH_PATTERN_SHAPE_SELECT 4:4 /* RWXVF */
#define NV_PGRAPH_PATTERN_SHAPE_SELECT_2COLOR 0x00000000 /* RW--V */
#define NV_PGRAPH_PATTERN_SHAPE_SELECT_FULLCOLOR 0x00000001 /* RW--V */
#define NV_PGRAPH_MONO_COLOR0 0x00400600 /* RW-4R */
#define NV_PGRAPH_MONO_COLOR0_VALUE 31:0 /* RWXUF */
#define NV_PGRAPH_ROP3 0x00400604 /* RW-4R */
#define NV_PGRAPH_ROP3_VALUE 7:0 /* RWXVF */
#define NV_PGRAPH_CHROMA 0x00400814 /* RW-4R */
#define NV_PGRAPH_CHROMA_VALUE 31:0 /* RWXUF */
#define NV_PGRAPH_BETA_AND 0x00400608 /* RW-4R */
#define NV_PGRAPH_BETA_AND_VALUE_FRACTION 30:23 /* RWXUF */
#define NV_PGRAPH_BETA_PREMULT 0x0040060c /* RW-4R */
#define NV_PGRAPH_BETA_PREMULT_VALUE 31:0 /* RWXUF */
#define NV_PGRAPH_CONTROL0 0x00400818 /* RW-4R */
#define NV_PGRAPH_CONTROL1 0x0040081c /* RW-4R */
#define NV_PGRAPH_CONTROL2 0x00400820 /* RW-4R */
#define NV_PGRAPH_BLEND 0x00400824 /* RW-4R */
#define NV_PGRAPH_DPRAM_INDEX 0x00400828 /* RW-4R */
#define NV_PGRAPH_DPRAM_INDEX_ADRS 6:0 /* RWIVF */
#define NV_PGRAPH_DPRAM_INDEX_ADRS_0 0x00000000 /* RWI-V */
#define NV_PGRAPH_DPRAM_INDEX_SELECT 10:8 /* RWIVF */
#define NV_PGRAPH_DPRAM_INDEX_SELECT_ADRS_0 0x00000000 /* RWI-V */
#define NV_PGRAPH_DPRAM_INDEX_SELECT_ADRS_1 0x00000001 /* RW--V */
#define NV_PGRAPH_DPRAM_INDEX_SELECT_DATA_0 0x00000002 /* RW--V */
#define NV_PGRAPH_DPRAM_INDEX_SELECT_DATA_1 0x00000003 /* RW--V */
#define NV_PGRAPH_DPRAM_INDEX_SELECT_WE_0 0x00000004 /* RW--V */
#define NV_PGRAPH_DPRAM_INDEX_SELECT_WE_1 0x00000005 /* RW--V */
#define NV_PGRAPH_DPRAM_INDEX_SELECT_ALPHA_0 0x00000006 /* RW--V */
#define NV_PGRAPH_DPRAM_INDEX_SELECT_ALPHA_1 0x00000007 /* RW--V */
#define NV_PGRAPH_DPRAM_DATA 0x0040082c /* RW-4R */
#define NV_PGRAPH_DPRAM_DATA_VALUE 31:0 /* RWXVF */
#define NV_PGRAPH_DPRAM_ADRS_0 0x0040082c /* RW-4R */
#define NV_PGRAPH_DPRAM_ADRS_0__ALIAS_1 NV_PGRAPH_DPRAM_DATA /* */
#define NV_PGRAPH_DPRAM_ADRS_0_VALUE 19:0 /* RWXVF */
#define NV_PGRAPH_DPRAM_ADRS_1 0x0040082c /* RW-4R */
#define NV_PGRAPH_DPRAM_ADRS_1__ALIAS_1 NV_PGRAPH_DPRAM_DATA /* */
#define NV_PGRAPH_DPRAM_ADRS_1_VALUE 19:0 /* RWXVF */
#define NV_PGRAPH_DPRAM_DATA_0 0x0040082c /* RW-4R */
#define NV_PGRAPH_DPRAM_DATA_0__ALIAS_1 NV_PGRAPH_DPRAM_DATA /* */
#define NV_PGRAPH_DPRAM_DATA_0_VALUE 31:0 /* RWXVF */
#define NV_PGRAPH_DPRAM_DATA_1 0x0040082c /* RW-4R */
#define NV_PGRAPH_DPRAM_DATA_1__ALIAS_1 NV_PGRAPH_DPRAM_DATA /* */
#define NV_PGRAPH_DPRAM_DATA_1_VALUE 31:0 /* RWXVF */
#define NV_PGRAPH_DPRAM_WE_0 0x0040082c /* RW-4R */
#define NV_PGRAPH_DPRAM_WE_0__ALIAS_1 NV_PGRAPH_DPRAM_DATA /* */
#define NV_PGRAPH_DPRAM_WE_0_VALUE 23:0 /* RWXVF */
#define NV_PGRAPH_DPRAM_WE_1 0x0040082c /* RW-4R */
#define NV_PGRAPH_DPRAM_WE_1__ALIAS_1 NV_PGRAPH_DPRAM_DATA /* */
#define NV_PGRAPH_DPRAM_WE_1_VALUE 23:0 /* RWXVF */
#define NV_PGRAPH_DPRAM_ALPHA_0 0x0040082c /* RW-4R */
#define NV_PGRAPH_DPRAM_ALPHA_0__ALIAS_1 NV_PGRAPH_DPRAM_DATA /* */
#define NV_PGRAPH_DPRAM_ALPHA_0_VALUE 31:0 /* RWXVF */
#define NV_PGRAPH_DPRAM_ALPHA_1 0x0040082c /* RW-4R */
#define NV_PGRAPH_DPRAM_ALPHA_1__ALIAS_1 NV_PGRAPH_DPRAM_DATA /* */
#define NV_PGRAPH_DPRAM_ALPHA_1_VALUE 31:0 /* RWXVF */
#define NV_PGRAPH_STORED_FMT 0x00400830 /* RW-4R */
#define NV_PGRAPH_STORED_FMT_MONO0 5:0 /* RWXVF */
#define NV_PGRAPH_STORED_FMT_PATT0 13:8 /* RWXVF */
#define NV_PGRAPH_STORED_FMT_PATT1 21:16 /* RWXVF */
#define NV_PGRAPH_STORED_FMT_CHROMA 29:24 /* RWXVF */
#define NV_PGRAPH_FORMATS 0x00400618 /* RW-4R */
#define NV_PGRAPH_FORMATS_ROP 2:0 /* R-XVF */
#define NV_PGRAPH_FORMATS_ROP_Y8 0x00000000 /* -W--V */
#define NV_PGRAPH_FORMATS_ROP_RGB15 0x00000001 /* -W--V */
#define NV_PGRAPH_FORMATS_ROP_RGB16 0x00000002 /* -W--V */
#define NV_PGRAPH_FORMATS_ROP_Y16 0x00000003 /* -W--V */
#define NV_PGRAPH_FORMATS_ROP_INVALID 0x00000004 /* -W--V */
#define NV_PGRAPH_FORMATS_ROP_RGB24 0x00000005 /* -W--V */
#define NV_PGRAPH_FORMATS_ROP_RGB30 0x00000006 /* -W--V */
#define NV_PGRAPH_FORMATS_ROP_Y32 0x00000007 /* -W--V */
#define NV_PGRAPH_FORMATS_SRC 9:4 /* R-XVF */
#define NV_PGRAPH_FORMATS_SRC_INVALID 0x00000000 /* RW--V */
#define NV_PGRAPH_FORMATS_SRC_LE_Y8 0x00000001 /* RW--V */
#define NV_PGRAPH_FORMATS_SRC_LE_X16A8Y8 0x00000002 /* RW--V */
#define NV_PGRAPH_FORMATS_SRC_LE_X24Y8 0x00000003 /* RW--V */
#define NV_PGRAPH_FORMATS_SRC_LE_A1R5G5B5 0x00000006 /* RW--V */
#define NV_PGRAPH_FORMATS_SRC_LE_X1R5G5B5 0x00000007 /* RW--V */
#define NV_PGRAPH_FORMATS_SRC_LE_X16A1R5G5B5 0x00000008 /* RW--V */
#define NV_PGRAPH_FORMATS_SRC_LE_X17R5G5B5 0x00000009 /* RW--V */
#define NV_PGRAPH_FORMATS_SRC_LE_R5G6B5 0x0000000A /* RW--V */
#define NV_PGRAPH_FORMATS_SRC_LE_A16R5G6B5 0x0000000B /* RW--V */
#define NV_PGRAPH_FORMATS_SRC_LE_X16R5G6B5 0x0000000C /* RW--V */
#define NV_PGRAPH_FORMATS_SRC_LE_A8R8G8B8 0x0000000D /* RW--V */
#define NV_PGRAPH_FORMATS_SRC_LE_X8R8G8B8 0x0000000E /* RW--V */
#define NV_PGRAPH_FORMATS_SRC_LE_Y16 0x0000000F /* RW--V */
#define NV_PGRAPH_FORMATS_SRC_LE_A16Y16 0x00000010 /* RW--V */
#define NV_PGRAPH_FORMATS_SRC_LE_X16Y16 0x00000011 /* RW--V */
#define NV_PGRAPH_FORMATS_SRC_LE_V8YB8U8YA8 0x00000012 /* RW--V */
#define NV_PGRAPH_FORMATS_SRC_LE_YB8V8YA8U8 0x00000013 /* RW--V */
#define NV_PGRAPH_FORMATS_SRC_LE_Y32 0x00000014 /* RW--V */
#define NV_PGRAPH_FORMATS_FB 15:12 /* R-XVF */
#define NV_PGRAPH_FORMATS_FB_INVALID 0x00000000 /* RWI-V */
#define NV_PGRAPH_FORMATS_FB_Y8 0x00000001 /* RW--V */
#define NV_PGRAPH_FORMATS_FB_X1R5G5B5_Z1R5G5B5 0x00000002 /* RW--V */
#define NV_PGRAPH_FORMATS_FB_X1R5G5B5_O1R5G5B5 0x00000003 /* RW--V */
#define NV_PGRAPH_FORMATS_FB_A1R5G5B5 0x00000004 /* RW--V */
#define NV_PGRAPH_FORMATS_FB_R5G6B5 0x00000005 /* RW--V */
#define NV_PGRAPH_FORMATS_FB_Y16 0x00000006 /* RW--V */
#define NV_PGRAPH_FORMATS_FB_X8R8G8B8_Z8R8G8B8 0x00000007 /* RW--V */
#define NV_PGRAPH_FORMATS_FB_X8R8G8B8_O1Z7R8G8B8 0x00000008 /* RW--V */
#define NV_PGRAPH_FORMATS_FB_X1A7R8G8B8_Z1A7R8G8B8 0x00000009 /* RW--V */
#define NV_PGRAPH_FORMATS_FB_X1A7R8G8B8_O1A7R8G8B8 0x0000000a /* RW--V */
#define NV_PGRAPH_FORMATS_FB_X8R8G8B8_O8R8G8B8 0x0000000b /* RW--V */
#define NV_PGRAPH_FORMATS_FB_A8R8G8B8 0x0000000c /* RW--V */
#define NV_PGRAPH_FORMATS_FB_Y32 0x0000000d /* RW--V */
#define NV_PGRAPH_FORMATS_FB_V8YB8U8YA8 0x0000000e /* RW--V */
#define NV_PGRAPH_FORMATS_FB_YB8V8YA8U8 0x0000000f /* RW--V */
#define NV_PGRAPH_ABS_X_RAM(i) (0x00400400+(i)*4) /* RW-4A */
#define NV_PGRAPH_ABS_X_RAM__SIZE_1 32 /* */
#define NV_PGRAPH_ABS_X_RAM_VALUE 31:0 /* RWXUF */
#define NV_PGRAPH_X_RAM_BPORT(i) (0x00400c00+(i)*4) /* R--4A */
#define NV_PGRAPH_X_RAM_BPORT__SIZE_1 32 /* */
#define NV_PGRAPH_X_RAM_BPORT_VALUE 31:0 /* R--UF */
#define NV_PGRAPH_ABS_Y_RAM(i) (0x00400480+(i)*4) /* RW-4A */
#define NV_PGRAPH_ABS_Y_RAM__SIZE_1 32 /* */
#define NV_PGRAPH_ABS_Y_RAM_VALUE 31:0 /* RWXUF */
#define NV_PGRAPH_Y_RAM_BPORT(i) (0x00400c80+(i)*4) /* R--4A */
#define NV_PGRAPH_Y_RAM_BPORT__SIZE_1 32 /* */
#define NV_PGRAPH_Y_RAM_BPORT_VALUE 31:0 /* R--UF */
#define NV_PGRAPH_XY_LOGIC_MISC0 0x00400514 /* RW-4R */
#define NV_PGRAPH_XY_LOGIC_MISC0_COUNTER 17:0 /* RWBUF */
#define NV_PGRAPH_XY_LOGIC_MISC0_COUNTER_0 0x00000000 /* RWB-V */
#define NV_PGRAPH_XY_LOGIC_MISC0_DIMENSION 20:20 /* RWVVF */
#define NV_PGRAPH_XY_LOGIC_MISC0_DIMENSION_NONZERO 0x00000000 /* RWV-V */
#define NV_PGRAPH_XY_LOGIC_MISC0_DIMENSION_ZERO 0x00000001 /* RW--V */
#define NV_PGRAPH_XY_LOGIC_MISC0_INDEX 31:28 /* RWBUF */
#define NV_PGRAPH_XY_LOGIC_MISC0_INDEX_0 0x00000000 /* RWB-V */
#define NV_PGRAPH_XY_LOGIC_MISC1 0x00400518 /* RW-4R */
#define NV_PGRAPH_XY_LOGIC_MISC1_INITIAL 0:0 /* RWNVF */
#define NV_PGRAPH_XY_LOGIC_MISC1_INITIAL_NEEDED 0x00000000 /* RWN-V */
#define NV_PGRAPH_XY_LOGIC_MISC1_INITIAL_DONE 0x00000001 /* RW--V */
#define NV_PGRAPH_XY_LOGIC_MISC1_XTRACLIPX 4:4 /* RWIVF */
#define NV_PGRAPH_XY_LOGIC_MISC1_XTRACLIPX_NOTNULL 0x00000000 /* RWI-V */
#define NV_PGRAPH_XY_LOGIC_MISC1_XTRACLIPX_NULL 0x00000001 /* RW--V */
#define NV_PGRAPH_XY_LOGIC_MISC1_XTRACLIPY 5:5 /* RWIVF */
#define NV_PGRAPH_XY_LOGIC_MISC1_XTRACLIPY_NOTNULL 0x00000000 /* RWI-V */
#define NV_PGRAPH_XY_LOGIC_MISC1_XTRACLIPY_NULL 0x00000001 /* RW--V */
#define NV_PGRAPH_XY_LOGIC_MISC1_SEL_XIMAX 12:12 /* RWIVF */
#define NV_PGRAPH_XY_LOGIC_MISC1_SEL_XIMAX_UUMAX 0x00000000 /* RWI-V */
#define NV_PGRAPH_XY_LOGIC_MISC1_SEL_XIMAX_IMAGEMAX 0x00000001 /* RW--V */
#define NV_PGRAPH_XY_LOGIC_MISC1_SEL_YIMAX 16:16 /* RWIVF */
#define NV_PGRAPH_XY_LOGIC_MISC1_SEL_YIMAX_UUMAX 0x00000000 /* RWI-V */
#define NV_PGRAPH_XY_LOGIC_MISC1_SEL_YIMAX_IMAGEMAX 0x00000001 /* RW--V */
#define NV_PGRAPH_XY_LOGIC_MISC1_SEL_XXTRA 20:20 /* RWIVF */
#define NV_PGRAPH_XY_LOGIC_MISC1_SEL_XXTRA_CLIPMAX 0x00000000 /* RWI-V */
#define NV_PGRAPH_XY_LOGIC_MISC1_SEL_XXTRA_IMAGEMAX 0x00000001 /* RW--V */
#define NV_PGRAPH_XY_LOGIC_MISC2 0x0040051C /* RW-4R */
#define NV_PGRAPH_XY_LOGIC_MISC2_HANDOFF 0:0 /* RWIVF */
#define NV_PGRAPH_XY_LOGIC_MISC2_HANDOFF_DISABLE 0x00000000 /* RWI-V */
#define NV_PGRAPH_XY_LOGIC_MISC2_HANDOFF_ENABLE 0x00000001 /* RW--V */
#define NV_PGRAPH_XY_LOGIC_MISC2_XTRACLIPX 4:4 /* RWIVF */
#define NV_PGRAPH_XY_LOGIC_MISC2_XTRACLIPX_NOTNULL 0x00000000 /* RWI-V */
#define NV_PGRAPH_XY_LOGIC_MISC2_XTRACLIPX_NULL 0x00000001 /* RW--V */
#define NV_PGRAPH_XY_LOGIC_MISC2_XTRACLIPY 5:5 /* RWIVF */
#define NV_PGRAPH_XY_LOGIC_MISC2_XTRACLIPY_NOTNULL 0x00000000 /* RWI-V */
#define NV_PGRAPH_XY_LOGIC_MISC2_XTRACLIPY_NULL 0x00000001 /* RW--V */
#define NV_PGRAPH_XY_LOGIC_MISC2_SEL_XIMAX 12:12 /* RWIVF */
#define NV_PGRAPH_XY_LOGIC_MISC2_SEL_XIMAX_UCMAX 0x00000000 /* RWI-V */
#define NV_PGRAPH_XY_LOGIC_MISC2_SEL_XIMAX_IMAGEMAX 0x00000001 /* RW--V */
#define NV_PGRAPH_XY_LOGIC_MISC2_SEL_YIMAX 16:16 /* RWIVF */
#define NV_PGRAPH_XY_LOGIC_MISC2_SEL_YIMAX_UCMAX 0x00000000 /* RWI-V */
#define NV_PGRAPH_XY_LOGIC_MISC2_SEL_YIMAX_IMAGEMAX 0x00000001 /* RW--V */
#define NV_PGRAPH_XY_LOGIC_MISC2_SEL_XXTRA 20:20 /* RWIVF */
#define NV_PGRAPH_XY_LOGIC_MISC2_SEL_XXTRA_CLIPMAX 0x00000000 /* RWI-V */
#define NV_PGRAPH_XY_LOGIC_MISC2_SEL_XXTRA_IMAGEMAX 0x00000001 /* RW--V */
#define NV_PGRAPH_XY_LOGIC_MISC3 0x00400520 /* RW-4R */
#define NV_PGRAPH_XY_LOGIC_MISC3_WDIMY_EQ_0 0:0 /* RWXVF */
#define NV_PGRAPH_XY_LOGIC_MISC3_WDIMY_EQ_0_NULL 0x00000000 /* RW--V */
#define NV_PGRAPH_XY_LOGIC_MISC3_WDIMY_EQ_0_TRUE 0x00000001 /* RW--V */
#define NV_PGRAPH_XY_LOGIC_MISC3_RELOAD_WDIMY 4:4 /* RWXVF */
#define NV_PGRAPH_XY_LOGIC_MISC3_RELOAD_WDIMY_NULL 0x00000000 /* RW--V */
#define NV_PGRAPH_XY_LOGIC_MISC3_RELOAD_WDIMY_TRUE 0x00000001 /* RW--V */
#define NV_PGRAPH_XY_LOGIC_MISC3_RELOAD_WX 8:8 /* RWIVF */
#define NV_PGRAPH_XY_LOGIC_MISC3_RELOAD_WX_NULL 0x00000000 /* RWI-V */
#define NV_PGRAPH_XY_LOGIC_MISC3_RELOAD_WX_TRUE 0x00000001 /* RW--V */
#define NV_PGRAPH_XY_LOGIC_MISC3_TEXT_ALG 12:12 /* RWIVF */
#define NV_PGRAPH_XY_LOGIC_MISC3_TEXT_ALG_NULL 0x00000000 /* RWI-V */
#define NV_PGRAPH_XY_LOGIC_MISC3_TEXT_ALG_TRUE 0x00000001 /* RW--V */
#define NV_PGRAPH_XY_LOGIC_MISC3_TEXT_DIMX 22:16 /* RWXUF */
#define NV_PGRAPH_XY_LOGIC_MISC3_TEXT_DIMX_0 0x00000000 /* RW--V */
#define NV_PGRAPH_XY_LOGIC_MISC3_TEXT_WDIMX 30:24 /* RWXUF */
#define NV_PGRAPH_XY_LOGIC_MISC3_TEXT_WDIMX_0 0x00000000 /* RW--V */
#define NV_PGRAPH_X_MISC 0x00400500 /* RW-4R */
#define NV_PGRAPH_X_MISC_BIT33_0 0:0 /* RWNVF */
#define NV_PGRAPH_X_MISC_BIT33_0_0 0x00000000 /* RWN-V */
#define NV_PGRAPH_X_MISC_BIT33_1 1:1 /* RWNVF */
#define NV_PGRAPH_X_MISC_BIT33_1_0 0x00000000 /* RWN-V */
#define NV_PGRAPH_X_MISC_BIT33_2 2:2 /* RWNVF */
#define NV_PGRAPH_X_MISC_BIT33_2_0 0x00000000 /* RWN-V */
#define NV_PGRAPH_X_MISC_BIT33_3 3:3 /* RWNVF */
#define NV_PGRAPH_X_MISC_BIT33_3_0 0x00000000 /* RWN-V */
#define NV_PGRAPH_X_MISC_RANGE_0 4:4 /* RWNVF */
#define NV_PGRAPH_X_MISC_RANGE_0_0 0x00000000 /* RWN-V */
#define NV_PGRAPH_X_MISC_RANGE_1 5:5 /* RWNVF */
#define NV_PGRAPH_X_MISC_RANGE_1_0 0x00000000 /* RWN-V */
#define NV_PGRAPH_X_MISC_RANGE_2 6:6 /* RWNVF */
#define NV_PGRAPH_X_MISC_RANGE_2_0 0x00000000 /* RWN-V */
#define NV_PGRAPH_X_MISC_RANGE_3 7:7 /* RWNVF */
#define NV_PGRAPH_X_MISC_RANGE_3_0 0x00000000 /* RWN-V */
#define NV_PGRAPH_X_MISC_ADDER_OUTPUT 29:28 /* RWXVF */
#define NV_PGRAPH_X_MISC_ADDER_OUTPUT_EQ_0 0x00000000 /* RW--V */
#define NV_PGRAPH_X_MISC_ADDER_OUTPUT_LT_0 0x00000001 /* RW--V */
#define NV_PGRAPH_X_MISC_ADDER_OUTPUT_GT_0 0x00000002 /* RW--V */
#define NV_PGRAPH_Y_MISC 0x00400504 /* RW-4R */
#define NV_PGRAPH_Y_MISC_BIT33_0 0:0 /* RWNVF */
#define NV_PGRAPH_Y_MISC_BIT33_0_0 0x00000000 /* RWN-V */
#define NV_PGRAPH_Y_MISC_BIT33_1 1:1 /* RWNVF */
#define NV_PGRAPH_Y_MISC_BIT33_1_0 0x00000000 /* RWN-V */
#define NV_PGRAPH_Y_MISC_BIT33_2 2:2 /* RWNVF */
#define NV_PGRAPH_Y_MISC_BIT33_2_0 0x00000000 /* RWN-V */
#define NV_PGRAPH_Y_MISC_BIT33_3 3:3 /* RWNVF */
#define NV_PGRAPH_Y_MISC_BIT33_3_0 0x00000000 /* RWN-V */
#define NV_PGRAPH_Y_MISC_RANGE_0 4:4 /* RWNVF */
#define NV_PGRAPH_Y_MISC_RANGE_0_0 0x00000000 /* RWN-V */
#define NV_PGRAPH_Y_MISC_RANGE_1 5:5 /* RWNVF */
#define NV_PGRAPH_Y_MISC_RANGE_1_0 0x00000000 /* RWN-V */
#define NV_PGRAPH_Y_MISC_RANGE_2 6:6 /* RWNVF */
#define NV_PGRAPH_Y_MISC_RANGE_2_0 0x00000000 /* RWN-V */
#define NV_PGRAPH_Y_MISC_RANGE_3 7:7 /* RWNVF */
#define NV_PGRAPH_Y_MISC_RANGE_3_0 0x00000000 /* RWN-V */
#define NV_PGRAPH_Y_MISC_ADDER_OUTPUT 29:28 /* RWXVF */
#define NV_PGRAPH_Y_MISC_ADDER_OUTPUT_EQ_0 0x00000000 /* RW--V */
#define NV_PGRAPH_Y_MISC_ADDER_OUTPUT_LT_0 0x00000001 /* RW--V */
#define NV_PGRAPH_Y_MISC_ADDER_OUTPUT_GT_0 0x00000002 /* RW--V */
#define NV_PGRAPH_ABS_UCLIP_XMIN 0x0040053C /* RW-4R */
#define NV_PGRAPH_ABS_UCLIP_XMIN_VALUE 15:0 /* RWXSF */
#define NV_PGRAPH_ABS_UCLIP_XMAX 0x00400544 /* RW-4R */
#define NV_PGRAPH_ABS_UCLIP_XMAX_VALUE 17:0 /* RWXSF */
#define NV_PGRAPH_ABS_UCLIP_YMIN 0x00400540 /* RW-4R */
#define NV_PGRAPH_ABS_UCLIP_YMIN_VALUE 15:0 /* RWXSF */
#define NV_PGRAPH_ABS_UCLIP_YMAX 0x00400548 /* RW-4R */
#define NV_PGRAPH_ABS_UCLIP_YMAX_VALUE 17:0 /* RWXSF */
#define NV_PGRAPH_ABS_UCLIPA_XMIN 0x00400560 /* RW-4R */
#define NV_PGRAPH_ABS_UCLIPA_XMIN_VALUE 15:0 /* RWXSF */
#define NV_PGRAPH_ABS_UCLIPA_XMAX 0x00400568 /* RW-4R */
#define NV_PGRAPH_ABS_UCLIPA_XMAX_VALUE 17:0 /* RWXSF */
#define NV_PGRAPH_ABS_UCLIPA_YMIN 0x00400564 /* RW-4R */
#define NV_PGRAPH_ABS_UCLIPA_YMIN_VALUE 15:0 /* RWXSF */
#define NV_PGRAPH_ABS_UCLIPA_YMAX 0x0040056C /* RW-4R */
#define NV_PGRAPH_ABS_UCLIPA_YMAX_VALUE 17:0 /* RWXSF */
#define NV_PGRAPH_SOURCE_COLOR 0x0040050C /* RW-4R */
#define NV_PGRAPH_SOURCE_COLOR_VALUE 31:0 /* RWNVF */
#define NV_PGRAPH_SOURCE_COLOR_VALUE_0 0x00000000 /* RWN-V */
#define NV_PGRAPH_VALID1 0x00400508 /* RW-4R */
#define NV_PGRAPH_VALID1_VLD 22:0 /* RWNVF */
#define NV_PGRAPH_VALID1_VLD_0 0x00000000 /* RWN-V */
#define NV_PGRAPH_VALID1_CLIP_MIN 28:28 /* RWIVF */
#define NV_PGRAPH_VALID1_CLIP_MIN_NO_ERROR 0x00000000 /* RWI-V */
#define NV_PGRAPH_VALID1_CLIP_MIN_ONLY 0x00000001 /* RW--V */
#define NV_PGRAPH_VALID1_CLIPA_MIN 29:29 /* RWIVF */
#define NV_PGRAPH_VALID1_CLIPA_MIN_NO_ERROR 0x00000000 /* RWI-V */
#define NV_PGRAPH_VALID1_CLIPA_MIN_ONLY 0x00000001 /* RW--V */
#define NV_PGRAPH_VALID1_CLIP_MAX 30:30 /* RWIVF */
#define NV_PGRAPH_VALID1_CLIP_MAX_NO_ERROR 0x00000000 /* RWI-V */
#define NV_PGRAPH_VALID1_CLIP_MAX_ONLY 0x00000001 /* RW--V */
#define NV_PGRAPH_VALID1_CLIPA_MAX 31:31 /* RWIVF */
#define NV_PGRAPH_VALID1_CLIPA_MAX_NO_ERROR 0x00000000 /* RWI-V */
#define NV_PGRAPH_VALID1_CLIPA_MAX_ONLY 0x00000001 /* RW--V */
#define NV_PGRAPH_VALID2 0x00400578 /* RW-4R */
#define NV_PGRAPH_VALID2_VLD2 28:0 /* RWNVF */
#define NV_PGRAPH_VALID2_VLD2_0 0x00000000 /* RWN-V */
#define NV_PGRAPH_ABS_ICLIP_XMAX 0x00400534 /* RW-4R */
#define NV_PGRAPH_ABS_ICLIP_XMAX_VALUE 17:0 /* RWXSF */
#define NV_PGRAPH_ABS_ICLIP_YMAX 0x00400538 /* RW-4R */
#define NV_PGRAPH_ABS_ICLIP_YMAX_VALUE 17:0 /* RWXSF */
#define NV_PGRAPH_CLIPX_0 0x00400524 /* RW-4R */
#define NV_PGRAPH_CLIPX_0_CLIP0_MIN 1:0 /* RWNVF */
#define NV_PGRAPH_CLIPX_0_CLIP0_MIN_GT 0x00000000 /* RW--V */
#define NV_PGRAPH_CLIPX_0_CLIP0_MIN_LT 0x00000001 /* RWN-V */
#define NV_PGRAPH_CLIPX_0_CLIP0_MIN_EQ 0x00000002 /* RW--V */
#define NV_PGRAPH_CLIPX_0_CLIP0_MAX 3:2 /* RWNVF */
#define NV_PGRAPH_CLIPX_0_CLIP0_MAX_LT 0x00000000 /* RW--V */
#define NV_PGRAPH_CLIPX_0_CLIP0_MAX_GT 0x00000001 /* RWN-V */
#define NV_PGRAPH_CLIPX_0_CLIP0_MAX_EQ 0x00000002 /* RW--V */
#define NV_PGRAPH_CLIPX_0_CLIP1_MIN 5:4 /* RWNVF */
#define NV_PGRAPH_CLIPX_0_CLIP1_MIN_GT 0x00000000 /* RW--V */
#define NV_PGRAPH_CLIPX_0_CLIP1_MIN_LT 0x00000001 /* RWN-V */
#define NV_PGRAPH_CLIPX_0_CLIP1_MIN_EQ 0x00000002 /* RW--V */
#define NV_PGRAPH_CLIPX_0_CLIP1_MAX 7:6 /* RWNVF */
#define NV_PGRAPH_CLIPX_0_CLIP1_MAX_LT 0x00000000 /* RW--V */
#define NV_PGRAPH_CLIPX_0_CLIP1_MAX_GT 0x00000001 /* RWN-V */
#define NV_PGRAPH_CLIPX_0_CLIP1_MAX_EQ 0x00000002 /* RW--V */
#define NV_PGRAPH_CLIPX_0_CLIP2_MIN 9:8 /* RWNVF */
#define NV_PGRAPH_CLIPX_0_CLIP2_MIN_GT 0x00000000 /* RW--V */
#define NV_PGRAPH_CLIPX_0_CLIP2_MIN_LT 0x00000001 /* RWN-V */
#define NV_PGRAPH_CLIPX_0_CLIP2_MIN_EQ 0x00000002 /* RW--V */
#define NV_PGRAPH_CLIPX_0_CLIP2_MAX 11:10 /* RWNVF */
#define NV_PGRAPH_CLIPX_0_CLIP2_MAX_LT 0x00000000 /* RW--V */
#define NV_PGRAPH_CLIPX_0_CLIP2_MAX_GT 0x00000001 /* RWN-V */
#define NV_PGRAPH_CLIPX_0_CLIP2_MAX_EQ 0x00000002 /* RW--V */
#define NV_PGRAPH_CLIPX_0_CLIP3_MIN 13:12 /* RWNVF */
#define NV_PGRAPH_CLIPX_0_CLIP3_MIN_GT 0x00000000 /* RW--V */
#define NV_PGRAPH_CLIPX_0_CLIP3_MIN_LT 0x00000001 /* RWN-V */
#define NV_PGRAPH_CLIPX_0_CLIP3_MIN_EQ 0x00000002 /* RW--V */
#define NV_PGRAPH_CLIPX_0_CLIP3_MAX 15:14 /* RWNVF */
#define NV_PGRAPH_CLIPX_0_CLIP3_MAX_LT 0x00000000 /* RW--V */
#define NV_PGRAPH_CLIPX_0_CLIP3_MAX_GT 0x00000001 /* RWN-V */
#define NV_PGRAPH_CLIPX_0_CLIP3_MAX_EQ 0x00000002 /* RW--V */
#define NV_PGRAPH_CLIPX_0_CLIP4_MIN 17:16 /* RWNVF */
#define NV_PGRAPH_CLIPX_0_CLIP4_MIN_GT 0x00000000 /* RW--V */
#define NV_PGRAPH_CLIPX_0_CLIP4_MIN_LT 0x00000001 /* RWN-V */
#define NV_PGRAPH_CLIPX_0_CLIP4_MIN_EQ 0x00000002 /* RW--V */
#define NV_PGRAPH_CLIPX_0_CLIP4_MAX 19:18 /* RWNVF */
#define NV_PGRAPH_CLIPX_0_CLIP4_MAX_LT 0x00000000 /* RW--V */
#define NV_PGRAPH_CLIPX_0_CLIP4_MAX_GT 0x00000001 /* RWN-V */
#define NV_PGRAPH_CLIPX_0_CLIP4_MAX_EQ 0x00000002 /* RW--V */
#define NV_PGRAPH_CLIPX_0_CLIP5_MIN 21:20 /* RWNVF */
#define NV_PGRAPH_CLIPX_0_CLIP5_MIN_GT 0x00000000 /* RW--V */
#define NV_PGRAPH_CLIPX_0_CLIP5_MIN_LT 0x00000001 /* RWN-V */
#define NV_PGRAPH_CLIPX_0_CLIP5_MIN_EQ 0x00000002 /* RW--V */
#define NV_PGRAPH_CLIPX_0_CLIP5_MAX 23:22 /* RWNVF */
#define NV_PGRAPH_CLIPX_0_CLIP5_MAX_LT 0x00000000 /* RW--V */
#define NV_PGRAPH_CLIPX_0_CLIP5_MAX_GT 0x00000001 /* RWN-V */
#define NV_PGRAPH_CLIPX_0_CLIP5_MAX_EQ 0x00000002 /* RW--V */
#define NV_PGRAPH_CLIPX_0_CLIP6_MIN 25:24 /* RWNVF */
#define NV_PGRAPH_CLIPX_0_CLIP6_MIN_GT 0x00000000 /* RW--V */
#define NV_PGRAPH_CLIPX_0_CLIP6_MIN_LT 0x00000001 /* RWN-V */
#define NV_PGRAPH_CLIPX_0_CLIP6_MIN_EQ 0x00000002 /* RW--V */
#define NV_PGRAPH_CLIPX_0_CLIP6_MAX 27:26 /* RWNVF */
#define NV_PGRAPH_CLIPX_0_CLIP6_MAX_LT 0x00000000 /* RW--V */
#define NV_PGRAPH_CLIPX_0_CLIP6_MAX_GT 0x00000001 /* RWN-V */
#define NV_PGRAPH_CLIPX_0_CLIP6_MAX_EQ 0x00000002 /* RW--V */
#define NV_PGRAPH_CLIPX_0_CLIP7_MIN 29:28 /* RWNVF */
#define NV_PGRAPH_CLIPX_0_CLIP7_MIN_GT 0x00000000 /* RW--V */
#define NV_PGRAPH_CLIPX_0_CLIP7_MIN_LT 0x00000001 /* RWN-V */
#define NV_PGRAPH_CLIPX_0_CLIP7_MIN_EQ 0x00000002 /* RW--V */
#define NV_PGRAPH_CLIPX_0_CLIP7_MAX 31:30 /* RWNVF */
#define NV_PGRAPH_CLIPX_0_CLIP7_MAX_LT 0x00000000 /* RW--V */
#define NV_PGRAPH_CLIPX_0_CLIP7_MAX_GT 0x00000001 /* RWN-V */
#define NV_PGRAPH_CLIPX_0_CLIP7_MAX_EQ 0x00000002 /* RW--V */
#define NV_PGRAPH_CLIPX_1 0x00400528 /* RW-4R */
#define NV_PGRAPH_CLIPX_1_CLIP8_MIN 1:0 /* RWNVF */
#define NV_PGRAPH_CLIPX_1_CLIP8_MIN_GT 0x00000000 /* RW--V */
#define NV_PGRAPH_CLIPX_1_CLIP8_MIN_LT 0x00000001 /* RWN-V */
#define NV_PGRAPH_CLIPX_1_CLIP8_MIN_EQ 0x00000002 /* RW--V */
#define NV_PGRAPH_CLIPX_1_CLIP8_MAX 3:2 /* RWNVF */
#define NV_PGRAPH_CLIPX_1_CLIP8_MAX_LT 0x00000000 /* RW--V */
#define NV_PGRAPH_CLIPX_1_CLIP8_MAX_GT 0x00000001 /* RWN-V */
#define NV_PGRAPH_CLIPX_1_CLIP8_MAX_EQ 0x00000002 /* RW--V */
#define NV_PGRAPH_CLIPX_1_CLIP9_MIN 5:4 /* RWNVF */
#define NV_PGRAPH_CLIPX_1_CLIP9_MIN_GT 0x00000000 /* RW--V */
#define NV_PGRAPH_CLIPX_1_CLIP9_MIN_LT 0x00000001 /* RWN-V */
#define NV_PGRAPH_CLIPX_1_CLIP9_MIN_EQ 0x00000002 /* RW--V */
#define NV_PGRAPH_CLIPX_1_CLIP9_MAX 7:6 /* RWNVF */
#define NV_PGRAPH_CLIPX_1_CLIP9_MAX_LT 0x00000000 /* RW--V */
#define NV_PGRAPH_CLIPX_1_CLIP9_MAX_GT 0x00000001 /* RWN-V */
#define NV_PGRAPH_CLIPX_1_CLIP9_MAX_EQ 0x00000002 /* RW--V */
#define NV_PGRAPH_CLIPX_1_CLIP10_MIN 9:8 /* RWNVF */
#define NV_PGRAPH_CLIPX_1_CLIP10_MIN_GT 0x00000000 /* RW--V */
#define NV_PGRAPH_CLIPX_1_CLIP10_MIN_LT 0x00000001 /* RWN-V */
#define NV_PGRAPH_CLIPX_1_CLIP10_MIN_EQ 0x00000002 /* RW--V */
#define NV_PGRAPH_CLIPX_1_CLIP10_MAX 11:10 /* RWNVF */
#define NV_PGRAPH_CLIPX_1_CLIP10_MAX_LT 0x00000000 /* RW--V */
#define NV_PGRAPH_CLIPX_1_CLIP10_MAX_GT 0x00000001 /* RWN-V */
#define NV_PGRAPH_CLIPX_1_CLIP10_MAX_EQ 0x00000002 /* RW--V */
#define NV_PGRAPH_CLIPX_1_CLIP11_MIN 13:12 /* RWNVF */
#define NV_PGRAPH_CLIPX_1_CLIP11_MIN_GT 0x00000000 /* RW--V */
#define NV_PGRAPH_CLIPX_1_CLIP11_MIN_LT 0x00000001 /* RWN-V */
#define NV_PGRAPH_CLIPX_1_CLIP11MIN_EQ 0x00000002 /* RW--V */
#define NV_PGRAPH_CLIPX_1_CLIP11_MAX 15:14 /* RWNVF */
#define NV_PGRAPH_CLIPX_1_CLIP11_MAX_LT 0x00000000 /* RW--V */
#define NV_PGRAPH_CLIPX_1_CLIP11_MAX_GT 0x00000001 /* RWN-V */
#define NV_PGRAPH_CLIPX_1_CLIP11_MAX_EQ 0x00000002 /* RW--V */
#define NV_PGRAPH_CLIPX_1_CLIP12_MIN 17:16 /* RWNVF */
#define NV_PGRAPH_CLIPX_1_CLIP12_MIN_GT 0x00000000 /* RW--V */
#define NV_PGRAPH_CLIPX_1_CLIP12_MIN_LT 0x00000001 /* RWN-V */
#define NV_PGRAPH_CLIPX_1_CLIP12_MIN_EQ 0x00000002 /* RW--V */
#define NV_PGRAPH_CLIPX_1_CLIP12_MAX 19:18 /* RWNVF */
#define NV_PGRAPH_CLIPX_1_CLIP12_MAX_LT 0x00000000 /* RW--V */
#define NV_PGRAPH_CLIPX_1_CLIP12_MAX_GT 0x00000001 /* RWN-V */
#define NV_PGRAPH_CLIPX_1_CLIP12_MAX_EQ 0x00000002 /* RW--V */
#define NV_PGRAPH_CLIPX_1_CLIP13_MIN 21:20 /* RWNVF */
#define NV_PGRAPH_CLIPX_1_CLIP13_MIN_GT 0x00000000 /* RW--V */
#define NV_PGRAPH_CLIPX_1_CLIP13_MIN_LT 0x00000001 /* RWN-V */
#define NV_PGRAPH_CLIPX_1_CLIP13_MIN_EQ 0x00000002 /* RW--V */
#define NV_PGRAPH_CLIPX_1_CLIP13_MAX 23:22 /* RWNVF */
#define NV_PGRAPH_CLIPX_1_CLIP13_MAX_LT 0x00000000 /* RW--V */
#define NV_PGRAPH_CLIPX_1_CLIP13_MAX_GT 0x00000001 /* RWN-V */
#define NV_PGRAPH_CLIPX_1_CLIP13_MAX_EQ 0x00000002 /* RW--V */
#define NV_PGRAPH_CLIPX_1_CLIP14_MIN 25:24 /* RWNVF */
#define NV_PGRAPH_CLIPX_1_CLIP14_MIN_GT 0x00000000 /* RW--V */
#define NV_PGRAPH_CLIPX_1_CLIP14_MIN_LT 0x00000001 /* RWN-V */
#define NV_PGRAPH_CLIPX_1_CLIP14_MIN_EQ 0x00000002 /* RW--V */
#define NV_PGRAPH_CLIPX_1_CLIP14_MAX 27:26 /* RWNVF */
#define NV_PGRAPH_CLIPX_1_CLIP14_MAX_LT 0x00000000 /* RW--V */
#define NV_PGRAPH_CLIPX_1_CLIP14_MAX_GT 0x00000001 /* RWN-V */
#define NV_PGRAPH_CLIPX_1_CLIP14_MAX_EQ 0x00000002 /* RW--V */
#define NV_PGRAPH_CLIPX_1_CLIP15_MIN 29:28 /* RWNVF */
#define NV_PGRAPH_CLIPX_1_CLIP15_MIN_GT 0x00000000 /* RW--V */
#define NV_PGRAPH_CLIPX_1_CLIP15_MIN_LT 0x00000001 /* RWN-V */
#define NV_PGRAPH_CLIPX_1_CLIP15_MIN_EQ 0x00000002 /* RW--V */
#define NV_PGRAPH_CLIPX_1_CLIP15_MAX 31:30 /* RWNVF */
#define NV_PGRAPH_CLIPX_1_CLIP15_MAX_LT 0x00000000 /* RW--V */
#define NV_PGRAPH_CLIPX_1_CLIP15_MAX_GT 0x00000001 /* RWN-V */
#define NV_PGRAPH_CLIPX_1_CLIP15_MAX_EQ 0x00000002 /* RW--V */
#define NV_PGRAPH_CLIPY_0 0x0040052c /* RW-4R */
#define NV_PGRAPH_CLIPY_0_CLIP0_MIN 1:0 /* RWNVF */
#define NV_PGRAPH_CLIPY_0_CLIP0_MIN_GT 0x00000000 /* RW--V */
#define NV_PGRAPH_CLIPY_0_CLIP0_MIN_LT 0x00000001 /* RWN-V */
#define NV_PGRAPH_CLIPY_0_CLIP0_MIN_EQ 0x00000002 /* RW--V */
#define NV_PGRAPH_CLIPY_0_CLIP0_MAX 3:2 /* RWNVF */
#define NV_PGRAPH_CLIPY_0_CLIP0_MAX_LT 0x00000000 /* RW--V */
#define NV_PGRAPH_CLIPY_0_CLIP0_MAX_GT 0x00000001 /* RWN-V */
#define NV_PGRAPH_CLIPY_0_CLIP0_MAX_EQ 0x00000002 /* RW--V */
#define NV_PGRAPH_CLIPY_0_CLIP1_MIN 5:4 /* RWNVF */
#define NV_PGRAPH_CLIPY_0_CLIP1_MIN_GT 0x00000000 /* RW--V */
#define NV_PGRAPH_CLIPY_0_CLIP1_MIN_LT 0x00000001 /* RWN-V */
#define NV_PGRAPH_CLIPY_0_CLIP1_MIN_EQ 0x00000002 /* RW--V */
#define NV_PGRAPH_CLIPY_0_CLIP1_MAX 7:6 /* RWNVF */
#define NV_PGRAPH_CLIPY_0_CLIP1_MAX_LT 0x00000000 /* RW--V */
#define NV_PGRAPH_CLIPY_0_CLIP1_MAX_GT 0x00000001 /* RWN-V */
#define NV_PGRAPH_CLIPY_0_CLIP1_MAX_EQ 0x00000002 /* RW--V */
#define NV_PGRAPH_CLIPY_0_CLIP2_MIN 9:8 /* RWNVF */
#define NV_PGRAPH_CLIPY_0_CLIP2_MIN_GT 0x00000000 /* RW--V */
#define NV_PGRAPH_CLIPY_0_CLIP2_MIN_LT 0x00000001 /* RWN-V */
#define NV_PGRAPH_CLIPY_0_CLIP2_MIN_EQ 0x00000002 /* RW--V */
#define NV_PGRAPH_CLIPY_0_CLIP2_MAX 11:10 /* RWNVF */
#define NV_PGRAPH_CLIPY_0_CLIP2_MAX_LT 0x00000000 /* RW--V */
#define NV_PGRAPH_CLIPY_0_CLIP2_MAX_GT 0x00000001 /* RWN-V */
#define NV_PGRAPH_CLIPY_0_CLIP2_MAX_EQ 0x00000002 /* RW--V */
#define NV_PGRAPH_CLIPY_0_CLIP3_MIN 13:12 /* RWNVF */
#define NV_PGRAPH_CLIPY_0_CLIP3_MIN_GT 0x00000000 /* RW--V */
#define NV_PGRAPH_CLIPY_0_CLIP3_MIN_LT 0x00000001 /* RWN-V */
#define NV_PGRAPH_CLIPY_0_CLIP3_MIN_EQ 0x00000002 /* RW--V */
#define NV_PGRAPH_CLIPY_0_CLIP3_MAX 15:14 /* RWNVF */
#define NV_PGRAPH_CLIPY_0_CLIP3_MAX_LT 0x00000000 /* RW--V */
#define NV_PGRAPH_CLIPY_0_CLIP3_MAX_GT 0x00000001 /* RWN-V */
#define NV_PGRAPH_CLIPY_0_CLIP3_MAX_EQ 0x00000002 /* RW--V */
#define NV_PGRAPH_CLIPY_0_CLIP4_MIN 17:16 /* RWNVF */
#define NV_PGRAPH_CLIPY_0_CLIP4_MIN_GT 0x00000000 /* RW--V */
#define NV_PGRAPH_CLIPY_0_CLIP4_MIN_LT 0x00000001 /* RWN-V */
#define NV_PGRAPH_CLIPY_0_CLIP4_MIN_EQ 0x00000002 /* RW--V */
#define NV_PGRAPH_CLIPY_0_CLIP4_MAX 19:18 /* RWNVF */
#define NV_PGRAPH_CLIPY_0_CLIP4_MAX_LT 0x00000000 /* RW--V */
#define NV_PGRAPH_CLIPY_0_CLIP4_MAX_GT 0x00000001 /* RWN-V */
#define NV_PGRAPH_CLIPY_0_CLIP4_MAX_EQ 0x00000002 /* RW--V */
#define NV_PGRAPH_CLIPY_0_CLIP5_MIN 21:20 /* RWNVF */
#define NV_PGRAPH_CLIPY_0_CLIP5_MIN_GT 0x00000000 /* RW--V */
#define NV_PGRAPH_CLIPY_0_CLIP5_MIN_LT 0x00000001 /* RWN-V */
#define NV_PGRAPH_CLIPY_0_CLIP5_MIN_EQ 0x00000002 /* RW--V */
#define NV_PGRAPH_CLIPY_0_CLIP5_MAX 23:22 /* RWNVF */
#define NV_PGRAPH_CLIPY_0_CLIP5_MAX_LT 0x00000000 /* RW--V */
#define NV_PGRAPH_CLIPY_0_CLIP5_MAX_GT 0x00000001 /* RWN-V */
#define NV_PGRAPH_CLIPY_0_CLIP5_MAX_EQ 0x00000002 /* RW--V */
#define NV_PGRAPH_CLIPY_0_CLIP6_MIN 25:24 /* RWNVF */
#define NV_PGRAPH_CLIPY_0_CLIP6_MIN_GT 0x00000000 /* RW--V */
#define NV_PGRAPH_CLIPY_0_CLIP6_MIN_LT 0x00000001 /* RWN-V */
#define NV_PGRAPH_CLIPY_0_CLIP6_MIN_EQ 0x00000002 /* RW--V */
#define NV_PGRAPH_CLIPY_0_CLIP6_MAX 27:26 /* RWNVF */
#define NV_PGRAPH_CLIPY_0_CLIP6_MAX_LT 0x00000000 /* RW--V */
#define NV_PGRAPH_CLIPY_0_CLIP6_MAX_GT 0x00000001 /* RWN-V */
#define NV_PGRAPH_CLIPY_0_CLIP6_MAX_EQ 0x00000002 /* RW--V */
#define NV_PGRAPH_CLIPY_0_CLIP7_MIN 29:28 /* RWNVF */
#define NV_PGRAPH_CLIPY_0_CLIP7_MIN_GT 0x00000000 /* RW--V */
#define NV_PGRAPH_CLIPY_0_CLIP7_MIN_LT 0x00000001 /* RWN-V */
#define NV_PGRAPH_CLIPY_0_CLIP7_MIN_EQ 0x00000002 /* RW--V */
#define NV_PGRAPH_CLIPY_0_CLIP7_MAX 31:30 /* RWNVF */
#define NV_PGRAPH_CLIPY_0_CLIP7_MAX_LT 0x00000000 /* RW--V */
#define NV_PGRAPH_CLIPY_0_CLIP7_MAX_GT 0x00000001 /* RWN-V */
#define NV_PGRAPH_CLIPY_0_CLIP7_MAX_EQ 0x00000002 /* RW--V */
#define NV_PGRAPH_CLIPY_1 0x00400530 /* RW-4R */
#define NV_PGRAPH_CLIPY_1_CLIP8_MIN 1:0 /* RWNVF */
#define NV_PGRAPH_CLIPY_1_CLIP8_MIN_GT 0x00000000 /* RW--V */
#define NV_PGRAPH_CLIPY_1_CLIP8_MIN_LT 0x00000001 /* RWN-V */
#define NV_PGRAPH_CLIPY_1_CLIP8_MIN_EQ 0x00000002 /* RW--V */
#define NV_PGRAPH_CLIPY_1_CLIP8_MAX 3:2 /* RWNVF */
#define NV_PGRAPH_CLIPY_1_CLIP8_MAX_LT 0x00000000 /* RW--V */
#define NV_PGRAPH_CLIPY_1_CLIP8_MAX_GT 0x00000001 /* RWN-V */
#define NV_PGRAPH_CLIPY_1_CLIP8_MAX_EQ 0x00000002 /* RW--V */
#define NV_PGRAPH_CLIPY_1_CLIP9_MIN 5:4 /* RWNVF */
#define NV_PGRAPH_CLIPY_1_CLIP9_MIN_GT 0x00000000 /* RW--V */
#define NV_PGRAPH_CLIPY_1_CLIP9_MIN_LT 0x00000001 /* RWN-V */
#define NV_PGRAPH_CLIPY_1_CLIP9_MIN_EQ 0x00000002 /* RW--V */
#define NV_PGRAPH_CLIPY_1_CLIP9_MAX 7:6 /* RWNVF */
#define NV_PGRAPH_CLIPY_1_CLIP9_MAX_LT 0x00000000 /* RW--V */
#define NV_PGRAPH_CLIPY_1_CLIP9_MAX_GT 0x00000001 /* RWN-V */
#define NV_PGRAPH_CLIPY_1_CLIP9_MAX_EQ 0x00000002 /* RW--V */
#define NV_PGRAPH_CLIPY_1_CLIP10_MIN 9:8 /* RWNVF */
#define NV_PGRAPH_CLIPY_1_CLIP10_MIN_GT 0x00000000 /* RW--V */
#define NV_PGRAPH_CLIPY_1_CLIP10_MIN_LT 0x00000001 /* RWN-V */
#define NV_PGRAPH_CLIPY_1_CLIP10_MIN_EQ 0x00000002 /* RW--V */
#define NV_PGRAPH_CLIPY_1_CLIP10_MAX 11:10 /* RWNVF */
#define NV_PGRAPH_CLIPY_1_CLIP10_MAX_LT 0x00000000 /* RW--V */
#define NV_PGRAPH_CLIPY_1_CLIP10_MAX_GT 0x00000001 /* RWN-V */
#define NV_PGRAPH_CLIPY_1_CLIP10_MAX_EQ 0x00000002 /* RW--V */
#define NV_PGRAPH_CLIPY_1_CLIP11_MIN 13:12 /* RWNVF */
#define NV_PGRAPH_CLIPY_1_CLIP11_MIN_GT 0x00000000 /* RW--V */
#define NV_PGRAPH_CLIPY_1_CLIP11_MIN_LT 0x00000001 /* RWN-V */
#define NV_PGRAPH_CLIPY_1_CLIP11MIN_EQ 0x00000002 /* RW--V */
#define NV_PGRAPH_CLIPY_1_CLIP11_MAX 15:14 /* RWNVF */
#define NV_PGRAPH_CLIPY_1_CLIP11_MAX_LT 0x00000000 /* RW--V */
#define NV_PGRAPH_CLIPY_1_CLIP11_MAX_GT 0x00000001 /* RWN-V */
#define NV_PGRAPH_CLIPY_1_CLIP11_MAX_EQ 0x00000002 /* RW--V */
#define NV_PGRAPH_CLIPY_1_CLIP12_MIN 17:16 /* RWNVF */
#define NV_PGRAPH_CLIPY_1_CLIP12_MIN_GT 0x00000000 /* RW--V */
#define NV_PGRAPH_CLIPY_1_CLIP12_MIN_LT 0x00000001 /* RWN-V */
#define NV_PGRAPH_CLIPY_1_CLIP12_MIN_EQ 0x00000002 /* RW--V */
#define NV_PGRAPH_CLIPY_1_CLIP12_MAX 19:18 /* RWNVF */
#define NV_PGRAPH_CLIPY_1_CLIP12_MAX_LT 0x00000000 /* RW--V */
#define NV_PGRAPH_CLIPY_1_CLIP12_MAX_GT 0x00000001 /* RWN-V */
#define NV_PGRAPH_CLIPY_1_CLIP12_MAX_EQ 0x00000002 /* RW--V */
#define NV_PGRAPH_CLIPY_1_CLIP13_MIN 21:20 /* RWNVF */
#define NV_PGRAPH_CLIPY_1_CLIP13_MIN_GT 0x00000000 /* RW--V */
#define NV_PGRAPH_CLIPY_1_CLIP13_MIN_LT 0x00000001 /* RWN-V */
#define NV_PGRAPH_CLIPY_1_CLIP13_MIN_EQ 0x00000002 /* RW--V */
#define NV_PGRAPH_CLIPY_1_CLIP13_MAX 23:22 /* RWNVF */
#define NV_PGRAPH_CLIPY_1_CLIP13_MAX_LT 0x00000000 /* RW--V */
#define NV_PGRAPH_CLIPY_1_CLIP13_MAX_GT 0x00000001 /* RWN-V */
#define NV_PGRAPH_CLIPY_1_CLIP13_MAX_EQ 0x00000002 /* RW--V */
#define NV_PGRAPH_CLIPY_1_CLIP14_MIN 25:24 /* RWNVF */
#define NV_PGRAPH_CLIPY_1_CLIP14_MIN_GT 0x00000000 /* RW--V */
#define NV_PGRAPH_CLIPY_1_CLIP14_MIN_LT 0x00000001 /* RWN-V */
#define NV_PGRAPH_CLIPY_1_CLIP14_MIN_EQ 0x00000002 /* RW--V */
#define NV_PGRAPH_CLIPY_1_CLIP14_MAX 27:26 /* RWNVF */
#define NV_PGRAPH_CLIPY_1_CLIP14_MAX_LT 0x00000000 /* RW--V */
#define NV_PGRAPH_CLIPY_1_CLIP14_MAX_GT 0x00000001 /* RWN-V */
#define NV_PGRAPH_CLIPY_1_CLIP14_MAX_EQ 0x00000002 /* RW--V */
#define NV_PGRAPH_CLIPY_1_CLIP15_MIN 29:28 /* RWNVF */
#define NV_PGRAPH_CLIPY_1_CLIP15_MIN_GT 0x00000000 /* RW--V */
#define NV_PGRAPH_CLIPY_1_CLIP15_MIN_LT 0x00000001 /* RWN-V */
#define NV_PGRAPH_CLIPY_1_CLIP15_MIN_EQ 0x00000002 /* RW--V */
#define NV_PGRAPH_CLIPY_1_CLIP15_MAX 31:30 /* RWNVF */
#define NV_PGRAPH_CLIPY_1_CLIP15_MAX_LT 0x00000000 /* RW--V */
#define NV_PGRAPH_CLIPY_1_CLIP15_MAX_GT 0x00000001 /* RWN-V */
#define NV_PGRAPH_CLIPY_1_CLIP15_MAX_EQ 0x00000002 /* RW--V */
#define NV_PGRAPH_MISC24_0 0x00400510 /* RW-4R */
#define NV_PGRAPH_MISC24_0_VALUE 23:0 /* RWXUF */
#define NV_PGRAPH_MISC24_1 0x00400570 /* RW-4R */
#define NV_PGRAPH_MISC24_1_VALUE 23:0 /* RWXUF */
#define NV_PGRAPH_MISC24_2 0x00400574 /* RW-4R */
#define NV_PGRAPH_MISC24_2_VALUE 23:0 /* RWXUF */
#define NV_PGRAPH_PASSTHRU_0 0x0040057C /* RW-4R */
#define NV_PGRAPH_PASSTHRU_0_VALUE 31:0 /* RWXUF */
#define NV_PGRAPH_PASSTHRU_1 0x00400580 /* RW-4R */
#define NV_PGRAPH_PASSTHRU_1_VALUE 31:0 /* RWXUF */
#define NV_PGRAPH_PASSTHRU_2 0x00400584 /* RW-4R */
#define NV_PGRAPH_PASSTHRU_2_VALUE 31:0 /* RWXUF */
#define NV_PGRAPH_U_RAM(i) (0x00400d00+(i)*4) /* RW-4A */
#define NV_PGRAPH_U_RAM__SIZE_1 16 /* */
#define NV_PGRAPH_U_RAM_VALUE 31:6 /* RWXFF */
#define NV_PGRAPH_V_RAM(i) (0x00400d40+(i)*4) /* RW-4A */
#define NV_PGRAPH_V_RAM__SIZE_1 16 /* */
#define NV_PGRAPH_V_RAM_VALUE 31:6 /* RWXFF */
#define NV_PGRAPH_M_RAM(i) (0x00400d80+(i)*4) /* RW-4A */
#define NV_PGRAPH_M_RAM__SIZE_1 16 /* */
#define NV_PGRAPH_M_RAM_VALUE 31:6 /* RWXFF */
#define NV_PGRAPH_DMA_START_0 0x00401000 /* RW-4R */
#define NV_PGRAPH_DMA_START_0_VALUE 31:0 /* RWXUF */
#define NV_PGRAPH_DMA_START_1 0x00401004 /* RW-4R */
#define NV_PGRAPH_DMA_START_1_VALUE 31:0 /* RWXUF */
#define NV_PGRAPH_DMA_LENGTH 0x00401008 /* RW-4R */
#define NV_PGRAPH_DMA_LENGTH_VALUE 21:0 /* RWXUF */
#define NV_PGRAPH_DMA_MISC 0x0040100C /* RW-4R */
#define NV_PGRAPH_DMA_MISC_COUNT 15:0 /* RWXUF */
#define NV_PGRAPH_DMA_MISC_FMT_SRC 18:16 /* RWXVF */
#define NV_PGRAPH_DMA_MISC_FMT_DST 22:20 /* RWXVF */
#define NV_PGRAPH_DMA_DATA_0 0x00401020 /* RW-4R */
#define NV_PGRAPH_DMA_DATA_0_VALUE 31:0 /* RWXUF */
#define NV_PGRAPH_DMA_DATA_1 0x00401024 /* RW-4R */
#define NV_PGRAPH_DMA_DATA_1_VALUE 31:0 /* RWXUF */
#define NV_PGRAPH_DMA_RM 0x00401030 /* RW-4R */
#define NV_PGRAPH_DMA_RM_ASSIST_A 0:0 /* RWIVF */
#define NV_PGRAPH_DMA_RM_ASSIST_A_NOT_PENDING 0x00000000 /* R-I-V */
#define NV_PGRAPH_DMA_RM_ASSIST_A_PENDING 0x00000001 /* R---V */
#define NV_PGRAPH_DMA_RM_ASSIST_A_RESET 0x00000001 /* -W--C */
#define NV_PGRAPH_DMA_RM_ASSIST_B 1:1 /* RWIVF */
#define NV_PGRAPH_DMA_RM_ASSIST_B_NOT_PENDING 0x00000000 /* R-I-V */
#define NV_PGRAPH_DMA_RM_ASSIST_B_PENDING 0x00000001 /* R---V */
#define NV_PGRAPH_DMA_RM_ASSIST_B_RESET 0x00000001 /* -W--C */
#define NV_PGRAPH_DMA_RM_WRITE_REQ 4:4 /* CWIVF */
#define NV_PGRAPH_DMA_RM_WRITE_REQ_NOT_PENDING 0x00000000 /* CWI-V */
#define NV_PGRAPH_DMA_RM_WRITE_REQ_PENDING 0x00000001 /* -W--T */
#define NV_PGRAPH_DMA_A_XLATE_INST 0x00401040 /* RW-4R */
#define NV_PGRAPH_DMA_A_XLATE_INST_VALUE 15:0 /* RWXUF */
#define NV_PGRAPH_DMA_A_CONTROL 0x00401044 /* RW-4R */
#define NV_PGRAPH_DMA_A_CONTROL_PAGE_TABLE 12:12 /* RWIVF */
#define NV_PGRAPH_DMA_A_CONTROL_PAGE_TABLE_NOT_PRESENT 0x00000000 /* RWI-V */
#define NV_PGRAPH_DMA_A_CONTROL_PAGE_TABLE_PRESENT 0x00000001 /* RW--V */
#define NV_PGRAPH_DMA_A_CONTROL_PAGE_ENTRY 13:13 /* RWXVF */
#define NV_PGRAPH_DMA_A_CONTROL_PAGE_ENTRY_NOT_LINEAR 0x00000000 /* RW--V */
#define NV_PGRAPH_DMA_A_CONTROL_PAGE_ENTRY_LINEAR 0x00000001 /* RW--V */
#define NV_PGRAPH_DMA_A_CONTROL_TARGET_NODE 17:16 /* RWXUF */
#define NV_PGRAPH_DMA_A_CONTROL_TARGET_NODE_NVM 0x00000000 /* RW--V */
#define NV_PGRAPH_DMA_A_CONTROL_TARGET_NODE_PCI 0x00000002 /* RW--V */
#define NV_PGRAPH_DMA_A_CONTROL_TARGET_NODE_AGP 0x00000003 /* RW--V */
#define NV_PGRAPH_DMA_A_CONTROL_ADJUST 31:20 /* RWXUF */
#define NV_PGRAPH_DMA_A_LIMIT 0x00401048 /* RW-4R */
#define NV_PGRAPH_DMA_A_LIMIT_OFFSET 31:0 /* RWXUF */
#define NV_PGRAPH_DMA_A_TLB_PTE 0x0040104C /* RW-4R */
#define NV_PGRAPH_DMA_A_TLB_PTE_ACCESS 1:1 /* RWXVF */
#define NV_PGRAPH_DMA_A_TLB_PTE_ACCESS_READ_ONLY 0x00000000 /* RW--V */
#define NV_PGRAPH_DMA_A_TLB_PTE_ACCESS_READ_WRITE 0x00000001 /* RW--V */
#define NV_PGRAPH_DMA_A_TLB_PTE_FRAME_ADDRESS 31:12 /* RWXUF */
#define NV_PGRAPH_DMA_A_TLB_TAG 0x00401050 /* RW-4R */
#define NV_PGRAPH_DMA_A_TLB_TAG_ADDRESS 31:12 /* RWXUF */
#define NV_PGRAPH_DMA_A_ADJ_OFFSET 0x00401054 /* RW-4R */
#define NV_PGRAPH_DMA_A_ADJ_OFFSET_VALUE 31:0 /* RWXUF */
#define NV_PGRAPH_DMA_A_OFFSET 0x00401058 /* RW-4R */
#define NV_PGRAPH_DMA_A_OFFSET_VALUE 31:0 /* RWXUF */
#define NV_PGRAPH_DMA_A_SIZE 0x0040105C /* RW-4R */
#define NV_PGRAPH_DMA_A_SIZE_VALUE 24:0 /* RWXUF */
#define NV_PGRAPH_DMA_A_Y_SIZE 0x00401060 /* RW-4R */
#define NV_PGRAPH_DMA_A_Y_SIZE_VALUE 10:0 /* RWXUF */
#define NV_PGRAPH_DMA_B_XLATE_INST 0x00401080 /* RW-4R */
#define NV_PGRAPH_DMA_B_XLATE_INST_VALUE 15:0 /* RWXUF */
#define NV_PGRAPH_DMA_B_CONTROL 0x00401084 /* RW-4R */
#define NV_PGRAPH_DMA_B_CONTROL_PAGE_TABLE 12:12 /* RWIVF */
#define NV_PGRAPH_DMA_B_CONTROL_PAGE_TABLE_NOT_PRESENT 0x00000000 /* RWI-V */
#define NV_PGRAPH_DMA_B_CONTROL_PAGE_TABLE_PRESENT 0x00000001 /* RW--V */
#define NV_PGRAPH_DMA_B_CONTROL_PAGE_ENTRY 13:13 /* RWXVF */
#define NV_PGRAPH_DMA_B_CONTROL_PAGE_ENTRY_NOT_LINEAR 0x00000000 /* RW--V */
#define NV_PGRAPH_DMA_B_CONTROL_PAGE_ENTRY_LINEAR 0x00000001 /* RW--V */
#define NV_PGRAPH_DMA_B_CONTROL_TARGET_NODE 17:16 /* RWXUF */
#define NV_PGRAPH_DMA_B_CONTROL_TARGET_NODE_NVM 0x00000000 /* RW--V */
#define NV_PGRAPH_DMA_B_CONTROL_TARGET_NODE_PCI 0x00000002 /* RW--V */
#define NV_PGRAPH_DMA_B_CONTROL_TARGET_NODE_AGP 0x00000003 /* RW--V */
#define NV_PGRAPH_DMA_B_CONTROL_ADJUST 31:20 /* RWXUF */
#define NV_PGRAPH_DMA_B_LIMIT 0x00401088 /* RW-4R */
#define NV_PGRAPH_DMA_B_LIMIT_OFFSET 31:0 /* RWXUF */
#define NV_PGRAPH_DMA_B_TLB_PTE 0x0040108C /* RW-4R */
#define NV_PGRAPH_DMA_B_TLB_PTE_ACCESS 1:1 /* RWXVF */
#define NV_PGRAPH_DMA_B_TLB_PTE_ACCESS_READ_ONLY 0x00000000 /* RW--V */
#define NV_PGRAPH_DMA_B_TLB_PTE_ACCESS_READ_WRITE 0x00000001 /* RW--V */
#define NV_PGRAPH_DMA_B_TLB_PTE_FRAME_ADDRESS 31:12 /* RWXUF */
#define NV_PGRAPH_DMA_B_TLB_TAG 0x00401090 /* RW-4R */
#define NV_PGRAPH_DMA_B_TLB_TAG_ADDRESS 31:12 /* RWXUF */
#define NV_PGRAPH_DMA_B_ADJ_OFFSET 0x00401094 /* RW-4R */
#define NV_PGRAPH_DMA_B_ADJ_OFFSET_VALUE 31:0 /* RWXUF */
#define NV_PGRAPH_DMA_B_OFFSET 0x00401098 /* RW-4R */
#define NV_PGRAPH_DMA_B_OFFSET_VALUE 31:0 /* RWXUF */
#define NV_PGRAPH_DMA_B_SIZE 0x0040109C /* RW-4R */
#define NV_PGRAPH_DMA_B_SIZE_VALUE 24:0 /* RWXUF */
#define NV_PGRAPH_DMA_B_Y_SIZE 0x004010A0 /* RW-4R */
#define NV_PGRAPH_DMA_B_Y_SIZE_VALUE 10:0 /* RWXUF */
/* Framebuffer registers */
#define NV_PFB 0x00100FFF:0x00100000 /* RW--D */
#define NV_PFB_BOOT_0 0x00100000 /* RW-4R */
#define NV_PFB_BOOT_0_RAM_AMOUNT 1:0 /* RW-VF */
#define NV_PFB_BOOT_0_RAM_AMOUNT_32MB 0x00000000 /* RW--V */
#define NV_PFB_BOOT_0_RAM_AMOUNT_4MB 0x00000001 /* RW--V */
#define NV_PFB_BOOT_0_RAM_AMOUNT_8MB 0x00000002 /* RW--V */
#define NV_PFB_BOOT_0_RAM_AMOUNT_16MB 0x00000003 /* RW--V */
#define NV_PFB_BOOT_0_RAM_WIDTH_128 2:2 /* RW-VF */
#define NV_PFB_BOOT_0_RAM_WIDTH_128_OFF 0x00000000 /* RW--V */
#define NV_PFB_BOOT_0_RAM_WIDTH_128_ON 0x00000001 /* RW--V */
#define NV_PFB_BOOT_0_RAM_TYPE 4:3 /* RW-VF */
#define NV_PFB_BOOT_0_RAM_TYPE_256K 0x00000000 /* RW--V */
#define NV_PFB_BOOT_0_RAM_TYPE_512K_2BANK 0x00000001 /* RW--V */
#define NV_PFB_BOOT_0_RAM_TYPE_512K_4BANK 0x00000002 /* RW--V */
#define NV_PFB_BOOT_0_RAM_TYPE_1024K_2BANK 0x00000003 /* RW--V */
#define NV_PFB_CONFIG_0 0x00100200 /* RW-4R */
#define NV_PFB_CONFIG_0_TYPE 14:0 /* RWIVF */
#define NV_PFB_CONFIG_0_TYPE_OLD1024_FIXED_8BPP 0x00000120 /* RW--V */
#define NV_PFB_CONFIG_0_TYPE_OLD1024_FIXED_16BPP 0x00000220 /* RW--V */
#define NV_PFB_CONFIG_0_TYPE_OLD1024_FIXED_32BPP 0x00000320 /* RW--V */
#define NV_PFB_CONFIG_0_TYPE_OLD1024_VAR_8BPP 0x00004120 /* RW--V */
#define NV_PFB_CONFIG_0_TYPE_OLD1024_VAR_16BPP 0x00004220 /* RW--V */
#define NV_PFB_CONFIG_0_TYPE_OLD1024_VAR_32BPP 0x00004320 /* RW--V */
#define NV_PFB_CONFIG_0_TYPE_TETRIS 0x00002000 /* RW--V */
#define NV_PFB_CONFIG_0_TYPE_NOTILING 0x00001114 /* RWI-V */
#define NV_PFB_CONFIG_0_TETRIS_MODE 17:15 /* RWI-F */
#define NV_PFB_CONFIG_0_TETRIS_MODE_PASS 0x00000000 /* RWI-V */
#define NV_PFB_CONFIG_0_TETRIS_MODE_1 0x00000001 /* RW--V */
#define NV_PFB_CONFIG_0_TETRIS_MODE_2 0x00000002 /* RW--V */
#define NV_PFB_CONFIG_0_TETRIS_MODE_3 0x00000003 /* RW--V */
#define NV_PFB_CONFIG_0_TETRIS_MODE_4 0x00000004 /* RW--V */
#define NV_PFB_CONFIG_0_TETRIS_MODE_5 0x00000005 /* RW--V */
#define NV_PFB_CONFIG_0_TETRIS_MODE_6 0x00000006 /* RW--V */
#define NV_PFB_CONFIG_0_TETRIS_MODE_7 0x00000007 /* RW--V */
#define NV_PFB_CONFIG_0_TETRIS_SHIFT 19:18 /* RWI-F */
#define NV_PFB_CONFIG_0_TETRIS_SHIFT_0 0x00000000 /* RWI-V */
#define NV_PFB_CONFIG_0_TETRIS_SHIFT_1 0x00000001 /* RW--V */
#define NV_PFB_CONFIG_0_TETRIS_SHIFT_2 0x00000002 /* RW--V */
#define NV_PFB_CONFIG_0_BANK_SWAP 22:20 /* RWI-F */
#define NV_PFB_CONFIG_0_BANK_SWAP_OFF 0x00000000 /* RWI-V */
#define NV_PFB_CONFIG_0_BANK_SWAP_1M 0x00000001 /* RW--V */
#define NV_PFB_CONFIG_0_BANK_SWAP_2M 0x00000005 /* RW--V */
#define NV_PFB_CONFIG_0_BANK_SWAP_4M 0x00000007 /* RW--V */
#define NV_PFB_CONFIG_0_UNUSED 23:23 /* RW-VF */
#define NV_PFB_CONFIG_0_SCRAMBLE_EN 29:29 /* RWIVF */
#define NV_PFB_CONFIG_0_SCRAMBLE_EN_INIT 0x00000000 /* RW--V */
#define NV_PFB_CONFIG_0_SCRAMBLE_ACTIVE 0x00000001 /* RW--V */
#define NV_PFB_CONFIG_0_PRAMIN_WR 28:28 /* RWIVF */
#define NV_PFB_CONFIG_0_PRAMIN_WR_INIT 0x00000000 /* RW--V */
#define NV_PFB_CONFIG_0_PRAMIN_WR_DISABLED 0x00000001 /* RW--V */
#define NV_PFB_CONFIG_0_PRAMIN_WR_MASK 27:24 /* RWIVF */
#define NV_PFB_CONFIG_0_PRAMIN_WR_MASK_INIT 0x00000000 /* RWI-V */
#define NV_PFB_CONFIG_0_PRAMIN_WR_MASK_CLEAR 0x0000000f /* RWI-V */
#define NV_PFB_CONFIG_1 0x00100204 /* RW-4R */
#define NV_PFB_RTL 0x00100300 /* RW-4R */
#define NV_PFB_RTL_H 0:0 /* RWIUF */
#define NV_PFB_RTL_H_DEFAULT 0x00000000 /* RWI-V */
#define NV_PFB_RTL_MC 1:1 /* RWIUF */
#define NV_PFB_RTL_MC_DEFAULT 0x00000000 /* RWI-V */
#define NV_PFB_RTL_V 2:2 /* RWIUF */
#define NV_PFB_RTL_V_DEFAULT 0x00000000 /* RWI-V */
#define NV_PFB_RTL_G 3:3 /* RWIUF */
#define NV_PFB_RTL_G_DEFAULT 0x00000000 /* RWI-V */
#define NV_PFB_RTL_GB 4:4 /* RWIUF */
#define NV_PFB_RTL_GB_DEFAULT 0x00000000 /* RWI-V */
#define NV_PFB_CONFIG_0_RESOLUTION 5:0 /* RWIVF */
#define NV_PFB_CONFIG_0_RESOLUTION_320_PIXELS 0x0000000a /* RW--V */
#define NV_PFB_CONFIG_0_RESOLUTION_400_PIXELS 0x0000000d /* RW--V */
#define NV_PFB_CONFIG_0_RESOLUTION_480_PIXELS 0x0000000f /* RW--V */
#define NV_PFB_CONFIG_0_RESOLUTION_512_PIXELS 0x00000010 /* RW--V */
#define NV_PFB_CONFIG_0_RESOLUTION_640_PIXELS 0x00000014 /* RW--V */
#define NV_PFB_CONFIG_0_RESOLUTION_800_PIXELS 0x00000019 /* RW--V */
#define NV_PFB_CONFIG_0_RESOLUTION_960_PIXELS 0x0000001e /* RW--V */
#define NV_PFB_CONFIG_0_RESOLUTION_1024_PIXELS 0x00000020 /* RW--V */
#define NV_PFB_CONFIG_0_RESOLUTION_1152_PIXELS 0x00000024 /* RW--V */
#define NV_PFB_CONFIG_0_RESOLUTION_1280_PIXELS 0x00000028 /* RW--V */
#define NV_PFB_CONFIG_0_RESOLUTION_1600_PIXELS 0x00000032 /* RW--V */
#define NV_PFB_CONFIG_0_RESOLUTION_DEFAULT 0x00000014 /* RWI-V */
#define NV_PFB_CONFIG_0_PIXEL_DEPTH 9:8 /* RWIVF */
#define NV_PFB_CONFIG_0_PIXEL_DEPTH_8_BITS 0x00000001 /* RW--V */
#define NV_PFB_CONFIG_0_PIXEL_DEPTH_16_BITS 0x00000002 /* RW--V */
#define NV_PFB_CONFIG_0_PIXEL_DEPTH_32_BITS 0x00000003 /* RW--V */
#define NV_PFB_CONFIG_0_PIXEL_DEPTH_DEFAULT 0x00000001 /* RWI-V */
#define NV_PFB_CONFIG_0_TILING 12:12 /* RWIVF */
#define NV_PFB_CONFIG_0_TILING_ENABLED 0x00000000 /* RW--V */
#define NV_PFB_CONFIG_0_TILING_DISABLED 0x00000001 /* RWI-V */
#define NV_PFB_CONFIG_1_SGRAM100 3:3 /* RWIVF */
#define NV_PFB_CONFIG_1_SGRAM100_ENABLED 0x00000000 /* RWI-V */
#define NV_PFB_CONFIG_1_SGRAM100_DISABLED 0x00000001 /* RW--V */
#define NV_PFB_DEBUG_0_CKE_ALWAYSON 29:29 /* RWIVF */
#define NV_PFB_DEBUG_0_CKE_ALWAYSON_OFF 0x00000000 /* RW--V */
#define NV_PFB_DEBUG_0_CKE_ALWAYSON_ON 0x00000001 /* RWI-V */
#define NV_PEXTDEV 0x00101FFF:0x00101000 /* RW--D */
#define NV_PEXTDEV_BOOT_0 0x00101000 /* R--4R */
#define NV_PEXTDEV_BOOT_0_STRAP_BUS_SPEED 0:0 /* R-XVF */
#define NV_PEXTDEV_BOOT_0_STRAP_BUS_SPEED_33MHZ 0x00000000 /* R---V */
#define NV_PEXTDEV_BOOT_0_STRAP_BUS_SPEED_66MHZ 0x00000001 /* R---V */
#define NV_PEXTDEV_BOOT_0_STRAP_SUB_VENDOR 1:1 /* R-XVF */
#define NV_PEXTDEV_BOOT_0_STRAP_SUB_VENDOR_NO_BIOS 0x00000000 /* R---V */
#define NV_PEXTDEV_BOOT_0_STRAP_SUB_VENDOR_BIOS 0x00000001 /* R---V */
#define NV_PEXTDEV_BOOT_0_STRAP_RAM_TYPE 3:2 /* R-XVF */
#define NV_PEXTDEV_BOOT_0_STRAP_RAM_TYPE_SGRAM_256K 0x00000000 /* R---V */
#define NV_PEXTDEV_BOOT_0_STRAP_RAM_TYPE_SGRAM_512K_2BANK 0x00000001 /* R---V */
#define NV_PEXTDEV_BOOT_0_STRAP_RAM_TYPE_SGRAM_512K_4BANK 0x00000002 /* R---V */
#define NV_PEXTDEV_BOOT_0_STRAP_RAM_TYPE_1024K_2BANK 0x00000003 /* R---V */
#define NV_PEXTDEV_BOOT_0_STRAP_RAM_WIDTH 4:4 /* R-XVF */
#define NV_PEXTDEV_BOOT_0_STRAP_RAM_WIDTH_64 0x00000000 /* R---V */
#define NV_PEXTDEV_BOOT_0_STRAP_RAM_WIDTH_128 0x00000001 /* R---V */
#define NV_PEXTDEV_BOOT_0_STRAP_BUS_TYPE 5:5 /* R-XVF */
#define NV_PEXTDEV_BOOT_0_STRAP_BUS_TYPE_PCI 0x00000000 /* R---V */
#define NV_PEXTDEV_BOOT_0_STRAP_BUS_TYPE_AGP 0x00000001 /* R---V */
#define NV_PEXTDEV_BOOT_0_STRAP_CRYSTAL 6:6 /* R-XVF */
#define NV_PEXTDEV_BOOT_0_STRAP_CRYSTAL_13500K 0x00000000 /* R---V */
#define NV_PEXTDEV_BOOT_0_STRAP_CRYSTAL_14318180 0x00000001 /* R---V */
#define NV_PEXTDEV_BOOT_0_STRAP_TVMODE 8:7 /* R-XVF */
#define NV_PEXTDEV_BOOT_0_STRAP_TVMODE_SECAM 0x00000000 /* R---V */
#define NV_PEXTDEV_BOOT_0_STRAP_TVMODE_NTSC 0x00000001 /* R---V */
#define NV_PEXTDEV_BOOT_0_STRAP_TVMODE_PAL 0x00000002 /* R---V */
#define NV_PEXTDEV_BOOT_0_STRAP_TVMODE_DISABLED 0x00000003 /* R---V */
#define NV_PEXTDEV_BOOT_0_STRAP_OVERWRITE 11:11 /* RWIVF */
#define NV_PEXTDEV_BOOT_0_STRAP_OVERWRITE_DISABLED 0x00000000 /* RWI-V */
#define NV_PEXTDEV_BOOT_0_STRAP_OVERWRITE_ENABLED 0x00000001 /* RW--V */
/* Extras */
#define NV_PRAMIN 0x007FFFFF:0x00700000 /* RW--M */
/*#define NV_PRAMIN 0x00FFFFFF:0x00C00000*/
#define NV_PNVM 0x01FFFFFF:0x01000000 /* RW--M */
/*#define NV_PNVM 0x00BFFFFF:0x00800000*/
#define NV_CHAN0 0x0080ffff:0x00800000
/* FIFO subchannels */
#define NV_UROP 0x43
#define NV_UCHROMA 0x57
#define NV_UCLIP 0x19
#define NV_UPATT 0x18
#define NV_ULIN 0x5C
#define NV_UTRI 0x5D
#define NV_URECT 0x5E
#define NV_UBLIT 0x5F
#define NV_UGLYPH 0x4B
#endif /*__NV4REF_H__*/

/shark/trunk/drivers/fb/riva/nv_type.h
0,0 → 1,58
/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/nv_type.h,v 1.35 2002/08/05 20:47:06 mvojkovi Exp $ */
#ifndef __NV_STRUCT_H__
#define __NV_STRUCT_H__
#define NV_CHIP_RIVA_128 ((PCI_VENDOR_ID_NVIDIA_SGS << 16)| PCI_DEVICE_ID_NVIDIA_RIVA128)
#define NV_CHIP_TNT ((PCI_VENDOR_ID_NVIDIA << 16)| PCI_DEVICE_ID_NVIDIA_TNT)
#define NV_CHIP_TNT2 ((PCI_VENDOR_ID_NVIDIA << 16)| PCI_DEVICE_ID_NVIDIA_TNT2)
#define NV_CHIP_UTNT2 ((PCI_VENDOR_ID_NVIDIA << 16)| PCI_DEVICE_ID_NVIDIA_UTNT2)
#define NV_CHIP_VTNT2 ((PCI_VENDOR_ID_NVIDIA << 16)| PCI_DEVICE_ID_NVIDIA_VTNT2)
#define NV_CHIP_UVTNT2 ((PCI_VENDOR_ID_NVIDIA << 16)| PCI_DEVICE_ID_NVIDIA_UVTNT2)
#define NV_CHIP_ITNT2 ((PCI_VENDOR_ID_NVIDIA << 16)| PCI_DEVICE_ID_NVIDIA_ITNT2)
#define NV_CHIP_GEFORCE_256 ((PCI_VENDOR_ID_NVIDIA << 16)| PCI_DEVICE_ID_NVIDIA_GEFORCE_256)
#define NV_CHIP_GEFORCE_DDR ((PCI_VENDOR_ID_NVIDIA << 16)| PCI_DEVICE_ID_NVIDIA_GEFORCE_DDR)
#define NV_CHIP_QUADRO ((PCI_VENDOR_ID_NVIDIA << 16)| PCI_DEVICE_ID_NVIDIA_QUADRO)
#define NV_CHIP_GEFORCE2_MX ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX)
#define NV_CHIP_GEFORCE2_MX_100 ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX_100)
#define NV_CHIP_QUADRO2_MXR ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_QUADRO2_MXR)
#define NV_CHIP_GEFORCE2_GO ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE2_GO)
#define NV_CHIP_GEFORCE2_GTS ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS)
#define NV_CHIP_GEFORCE2_TI ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE2_TI)
#define NV_CHIP_GEFORCE2_ULTRA ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE2_ULTRA)
#define NV_CHIP_QUADRO2_PRO ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_QUADRO2_PRO)
#define NV_CHIP_GEFORCE4_MX_460 ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_460)
#define NV_CHIP_GEFORCE4_MX_440 ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440)
#define NV_CHIP_GEFORCE4_MX_420 ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_420)
#define NV_CHIP_GEFORCE4_440_GO ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO)
#define NV_CHIP_GEFORCE4_420_GO ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO)
#define NV_CHIP_GEFORCE4_420_GO_M32 ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO_M32)
#define NV_CHIP_QUADRO4_500XGL ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_QUADRO4_500XGL)
#define NV_CHIP_GEFORCE4_440_GO_M64 ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO_M64)
#define NV_CHIP_QUADRO4_200 ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_QUADRO4_200)
#define NV_CHIP_QUADRO4_550XGL ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_QUADRO4_550XGL)
#define NV_CHIP_QUADRO4_500_GOGL ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_QUADRO4_500_GOGL)
#define NV_CHIP_0x0180 ((PCI_VENDOR_ID_NVIDIA << 16) | 0x0180)
#define NV_CHIP_0x0181 ((PCI_VENDOR_ID_NVIDIA << 16) | 0x0181)
#define NV_CHIP_0x0182 ((PCI_VENDOR_ID_NVIDIA << 16) | 0x0182)
#define NV_CHIP_0x0188 ((PCI_VENDOR_ID_NVIDIA << 16) | 0x0188)
#define NV_CHIP_0x018A ((PCI_VENDOR_ID_NVIDIA << 16) | 0x018A)
#define NV_CHIP_0x018B ((PCI_VENDOR_ID_NVIDIA << 16) | 0x018B)
#define NV_CHIP_IGEFORCE2 ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_IGEFORCE2)
#define NV_CHIP_0x01F0 ((PCI_VENDOR_ID_NVIDIA << 16) | 0x01F0)
#define NV_CHIP_GEFORCE3 ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE3)
#define NV_CHIP_GEFORCE3_TI_200 ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE3_TI_200)
#define NV_CHIP_GEFORCE3_TI_500 ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE3_TI_500)
#define NV_CHIP_QUADRO_DCC ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_QUADRO_DCC)
#define NV_CHIP_GEFORCE4_TI_4600 ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4600)
#define NV_CHIP_GEFORCE4_TI_4400 ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4400)
#define NV_CHIP_GEFORCE4_TI_4200 ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4200)
#define NV_CHIP_QUADRO4_900XGL ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_QUADRO4_900XGL)
#define NV_CHIP_QUADRO4_750XGL ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_QUADRO4_750XGL)
#define NV_CHIP_QUADRO4_700XGL ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_QUADRO4_700XGL)
#define NV_CHIP_0x0280 ((PCI_VENDOR_ID_NVIDIA << 16) | 0x0280)
#define NV_CHIP_0x0281 ((PCI_VENDOR_ID_NVIDIA << 16) | 0x0281)
#define NV_CHIP_0x0288 ((PCI_VENDOR_ID_NVIDIA << 16) | 0x0288)
#define NV_CHIP_0x0289 ((PCI_VENDOR_ID_NVIDIA << 16) | 0x0289)
#endif /* __NV_STRUCT_H__ */

/shark/trunk/drivers/fb/fbmem.c
962,7 → 962,7
return fb_set_cmap(&cmap, 1, info);
}
static int
int
fb_ioctl(struct inode *inode, struct file *file, unsigned int cmd,
unsigned long arg)
{
1325,7 → 1325,10
linuxcomp_setfd(i,num);
fb_open(i,NULL);
if (fb_open(i,NULL)) {
kfree(i);
return -1;
}
kfree(i);
1342,7 → 1345,10
linuxcomp_setfd(i,num);
fb_release(i,NULL);
if(fb_release(i,NULL)) {
kfree(i);
return -1;
}
kfree(i);
1350,6 → 1356,39
}
int fb_set_mode_inode(int num, int wx, int wy, int bpp) {
struct inode *i;
struct fb_var_screeninfo var;
i = (struct inode *)kmalloc(sizeof(struct inode),GFP_KERNEL);
linuxcomp_setfd(i,num);
if (fb_ioctl(i, NULL, FBIOGET_VSCREENINFO, (unsigned long)&var)) {
kfree(i);
return -1;
}
var.xres = wx;
var.yres = wy;
var.xres_virtual = wx;
var.yres_virtual = wy;
var.xoffset = 0;
var.yoffset = 0;
var.bits_per_pixel = bpp;
if (fb_ioctl(i, NULL, FBIOPUT_VSCREENINFO, (unsigned long)&var)) {
kfree(i);
return -1;
}
kfree(i);
return 0;
}
/**
* video_setup - process command line options
* @options: string of options

/shark/trunk/drivers/fb/shark_fb26.c
23,11 → 23,15
extern int fbmem_init(void);
extern int fb_open_inode(int num);
extern int fb_close_inode(int num);
extern int fb_set_mode_inode(int num, int wx, int wy, int bpp);
/* Init the Linux PCI 2.6 Driver */
int FB26_init() {
fbmem_init();
if (fbmem_init()) {
printk("FB ERROR: Cannot init the FrameBuffer driver\n");
return -1;
}
return 0;
35,16 → 39,33
int FB26_open(int num) {
fb_open_inode(num);
if (fb_open_inode(num)) {
printk("FB ERROR: Cannot open the FrameBuffer driver\n");
return -1;
}
return 0;
}
int FB26_set_mode(int num, int wx, int wy, int bpp) {
if (fb_set_mode_inode(num,wx,wy,bpp)) {
printk("FB ERROR: Cannot set mode for FrameBuffer driver\n");
return -1;
}
return 0;
}
int FB26_close(int num) {
fb_close_inode(num);
if (fb_close_inode(num)) {
printk("FB ERROR: Cannot close the FrameBuffer driver\n");
return -1;
}
return 0;
}

/shark/trunk/drivers/fb/modedb.c
0,0 → 1,541
/*
* linux/drivers/video/modedb.c -- Standard video mode database management
*
* Copyright (C) 1999 Geert Uytterhoeven
*
* 2001 - Documented with DocBook
* - Brad Douglas <brad@neruo.com>
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive for
* more details.
*/
#include <linuxcomp.h>
#include <linux/module.h>
#include <linux/tty.h>
#include <linux/fb.h>
#include <linux/sched.h>
#undef DEBUG
#define name_matches(v, s, l) \
((v).name && !strncmp((s), (v).name, (l)) && strlen((v).name) == (l))
#define res_matches(v, x, y) \
((v).xres == (x) && (v).yres == (y))
#ifdef DEBUG
#define DPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt, __FUNCTION__ , ## args)
#else
#define DPRINTK(fmt, args...)
#endif
const char *global_mode_option = NULL;
/*
* Standard video mode definitions (taken from XFree86)
*/
#define DEFAULT_MODEDB_INDEX 0
static const struct fb_videomode modedb[] __initdata = {
{
/* 640x400 @ 70 Hz, 31.5 kHz hsync */
NULL, 70, 640, 400, 39721, 40, 24, 39, 9, 96, 2,
0, FB_VMODE_NONINTERLACED
}, {
/* 640x480 @ 60 Hz, 31.5 kHz hsync */
NULL, 60, 640, 480, 39721, 40, 24, 32, 11, 96, 2,
0, FB_VMODE_NONINTERLACED
}, {
/* 800x600 @ 56 Hz, 35.15 kHz hsync */
NULL, 56, 800, 600, 27777, 128, 24, 22, 1, 72, 2,
0, FB_VMODE_NONINTERLACED
}, {
/* 1024x768 @ 87 Hz interlaced, 35.5 kHz hsync */
NULL, 87, 1024, 768, 22271, 56, 24, 33, 8, 160, 8,
0, FB_VMODE_INTERLACED
}, {
/* 640x400 @ 85 Hz, 37.86 kHz hsync */
NULL, 85, 640, 400, 31746, 96, 32, 41, 1, 64, 3,
FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED
}, {
/* 640x480 @ 72 Hz, 36.5 kHz hsync */
NULL, 72, 640, 480, 31746, 144, 40, 30, 8, 40, 3,
0, FB_VMODE_NONINTERLACED
}, {
/* 640x480 @ 75 Hz, 37.50 kHz hsync */
NULL, 75, 640, 480, 31746, 120, 16, 16, 1, 64, 3,
0, FB_VMODE_NONINTERLACED
}, {
/* 800x600 @ 60 Hz, 37.8 kHz hsync */
NULL, 60, 800, 600, 25000, 88, 40, 23, 1, 128, 4,
FB_SYNC_HOR_HIGH_ACT|FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED
}, {
/* 640x480 @ 85 Hz, 43.27 kHz hsync */
NULL, 85, 640, 480, 27777, 80, 56, 25, 1, 56, 3,
0, FB_VMODE_NONINTERLACED
}, {
/* 1152x864 @ 89 Hz interlaced, 44 kHz hsync */
NULL, 69, 1152, 864, 15384, 96, 16, 110, 1, 216, 10,
0, FB_VMODE_INTERLACED
}, {
/* 800x600 @ 72 Hz, 48.0 kHz hsync */
NULL, 72, 800, 600, 20000, 64, 56, 23, 37, 120, 6,
FB_SYNC_HOR_HIGH_ACT|FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED
}, {
/* 1024x768 @ 60 Hz, 48.4 kHz hsync */
NULL, 60, 1024, 768, 15384, 168, 8, 29, 3, 144, 6,
0, FB_VMODE_NONINTERLACED
}, {
/* 640x480 @ 100 Hz, 53.01 kHz hsync */
NULL, 100, 640, 480, 21834, 96, 32, 36, 8, 96, 6,
0, FB_VMODE_NONINTERLACED
}, {
/* 1152x864 @ 60 Hz, 53.5 kHz hsync */
NULL, 60, 1152, 864, 11123, 208, 64, 16, 4, 256, 8,
0, FB_VMODE_NONINTERLACED
}, {
/* 800x600 @ 85 Hz, 55.84 kHz hsync */
NULL, 85, 800, 600, 16460, 160, 64, 36, 16, 64, 5,
0, FB_VMODE_NONINTERLACED
}, {
/* 1024x768 @ 70 Hz, 56.5 kHz hsync */
NULL, 70, 1024, 768, 13333, 144, 24, 29, 3, 136, 6,
0, FB_VMODE_NONINTERLACED
}, {
/* 1280x1024 @ 87 Hz interlaced, 51 kHz hsync */
NULL, 87, 1280, 1024, 12500, 56, 16, 128, 1, 216, 12,
0, FB_VMODE_INTERLACED
}, {
/* 800x600 @ 100 Hz, 64.02 kHz hsync */
NULL, 100, 800, 600, 14357, 160, 64, 30, 4, 64, 6,
0, FB_VMODE_NONINTERLACED
}, {
/* 1024x768 @ 76 Hz, 62.5 kHz hsync */
NULL, 76, 1024, 768, 11764, 208, 8, 36, 16, 120, 3,
0, FB_VMODE_NONINTERLACED
}, {
/* 1152x864 @ 70 Hz, 62.4 kHz hsync */
NULL, 70, 1152, 864, 10869, 106, 56, 20, 1, 160, 10,
0, FB_VMODE_NONINTERLACED
}, {
/* 1280x1024 @ 61 Hz, 64.2 kHz hsync */
NULL, 61, 1280, 1024, 9090, 200, 48, 26, 1, 184, 3,
0, FB_VMODE_NONINTERLACED
}, {
/* 1400x1050 @ 60Hz, 63.9 kHz hsync */
NULL, 68, 1400, 1050, 9259, 136, 40, 13, 1, 112, 3,
0, FB_VMODE_NONINTERLACED
}, {
/* 1400x1050 @ 75,107 Hz, 82,392 kHz +hsync +vsync*/
"LCD_XGA_75", 75, 1400, 1050, 9271, 120, 56, 13, 0, 112, 3,
FB_SYNC_HOR_HIGH_ACT|FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED
}, {
/* 1400x1050 @ 60 Hz, ? kHz +hsync +vsync*/
"LCD_XGA_60", 60, 1400, 1050, 9259, 128, 40, 12, 0, 112, 3,
FB_SYNC_HOR_HIGH_ACT|FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED
}, {
/* 1024x768 @ 85 Hz, 70.24 kHz hsync */
NULL, 85, 1024, 768, 10111, 192, 32, 34, 14, 160, 6,
0, FB_VMODE_NONINTERLACED
}, {
/* 1152x864 @ 78 Hz, 70.8 kHz hsync */
NULL, 78, 1152, 864, 9090, 228, 88, 32, 0, 84, 12,
0, FB_VMODE_NONINTERLACED
}, {
/* 1280x1024 @ 70 Hz, 74.59 kHz hsync */
NULL, 70, 1280, 1024, 7905, 224, 32, 28, 8, 160, 8,
0, FB_VMODE_NONINTERLACED
}, {
/* 1600x1200 @ 60Hz, 75.00 kHz hsync */
NULL, 60, 1600, 1200, 6172, 304, 64, 46, 1, 192, 3,
FB_SYNC_HOR_HIGH_ACT|FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED
}, {
/* 1152x864 @ 84 Hz, 76.0 kHz hsync */
NULL, 84, 1152, 864, 7407, 184, 312, 32, 0, 128, 12,
0, FB_VMODE_NONINTERLACED
}, {
/* 1280x1024 @ 74 Hz, 78.85 kHz hsync */
NULL, 74, 1280, 1024, 7407, 256, 32, 34, 3, 144, 3,
0, FB_VMODE_NONINTERLACED
}, {
/* 1024x768 @ 100Hz, 80.21 kHz hsync */
NULL, 100, 1024, 768, 8658, 192, 32, 21, 3, 192, 10,
0, FB_VMODE_NONINTERLACED
}, {
/* 1280x1024 @ 76 Hz, 81.13 kHz hsync */
NULL, 76, 1280, 1024, 7407, 248, 32, 34, 3, 104, 3,
0, FB_VMODE_NONINTERLACED
}, {
/* 1600x1200 @ 70 Hz, 87.50 kHz hsync */
NULL, 70, 1600, 1200, 5291, 304, 64, 46, 1, 192, 3,
0, FB_VMODE_NONINTERLACED
}, {
/* 1152x864 @ 100 Hz, 89.62 kHz hsync */
NULL, 100, 1152, 864, 7264, 224, 32, 17, 2, 128, 19,
0, FB_VMODE_NONINTERLACED
}, {
/* 1280x1024 @ 85 Hz, 91.15 kHz hsync */
NULL, 85, 1280, 1024, 6349, 224, 64, 44, 1, 160, 3,
FB_SYNC_HOR_HIGH_ACT|FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED
}, {
/* 1600x1200 @ 75 Hz, 93.75 kHz hsync */
NULL, 75, 1600, 1200, 4938, 304, 64, 46, 1, 192, 3,
FB_SYNC_HOR_HIGH_ACT|FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED
}, {
/* 1600x1200 @ 85 Hz, 105.77 kHz hsync */
NULL, 85, 1600, 1200, 4545, 272, 16, 37, 4, 192, 3,
FB_SYNC_HOR_HIGH_ACT|FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED
}, {
/* 1280x1024 @ 100 Hz, 107.16 kHz hsync */
NULL, 100, 1280, 1024, 5502, 256, 32, 26, 7, 128, 15,
0, FB_VMODE_NONINTERLACED
}, {
/* 1800x1440 @ 64Hz, 96.15 kHz hsync */
NULL, 64, 1800, 1440, 4347, 304, 96, 46, 1, 192, 3,
FB_SYNC_HOR_HIGH_ACT|FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED
}, {
/* 1800x1440 @ 70Hz, 104.52 kHz hsync */
NULL, 70, 1800, 1440, 4000, 304, 96, 46, 1, 192, 3,
FB_SYNC_HOR_HIGH_ACT|FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED
}, {
/* 512x384 @ 78 Hz, 31.50 kHz hsync */
NULL, 78, 512, 384, 49603, 48, 16, 16, 1, 64, 3,
0, FB_VMODE_NONINTERLACED
}, {
/* 512x384 @ 85 Hz, 34.38 kHz hsync */
NULL, 85, 512, 384, 45454, 48, 16, 16, 1, 64, 3,
0, FB_VMODE_NONINTERLACED
}, {
/* 320x200 @ 70 Hz, 31.5 kHz hsync, 8:5 aspect ratio */
NULL, 70, 320, 200, 79440, 16, 16, 20, 4, 48, 1,
0, FB_VMODE_DOUBLE
}, {
/* 320x240 @ 60 Hz, 31.5 kHz hsync, 4:3 aspect ratio */
NULL, 60, 320, 240, 79440, 16, 16, 16, 5, 48, 1,
0, FB_VMODE_DOUBLE
}, {
/* 320x240 @ 72 Hz, 36.5 kHz hsync */
NULL, 72, 320, 240, 63492, 16, 16, 16, 4, 48, 2,
0, FB_VMODE_DOUBLE
}, {
/* 400x300 @ 56 Hz, 35.2 kHz hsync, 4:3 aspect ratio */
NULL, 56, 400, 300, 55555, 64, 16, 10, 1, 32, 1,
0, FB_VMODE_DOUBLE
}, {
/* 400x300 @ 60 Hz, 37.8 kHz hsync */
NULL, 60, 400, 300, 50000, 48, 16, 11, 1, 64, 2,
0, FB_VMODE_DOUBLE
}, {
/* 400x300 @ 72 Hz, 48.0 kHz hsync */
NULL, 72, 400, 300, 40000, 32, 24, 11, 19, 64, 3,
0, FB_VMODE_DOUBLE
}, {
/* 480x300 @ 56 Hz, 35.2 kHz hsync, 8:5 aspect ratio */
NULL, 56, 480, 300, 46176, 80, 16, 10, 1, 40, 1,
0, FB_VMODE_DOUBLE
}, {
/* 480x300 @ 60 Hz, 37.8 kHz hsync */
NULL, 60, 480, 300, 41858, 56, 16, 11, 1, 80, 2,
0, FB_VMODE_DOUBLE
}, {
/* 480x300 @ 63 Hz, 39.6 kHz hsync */
NULL, 63, 480, 300, 40000, 56, 16, 11, 1, 80, 2,
0, FB_VMODE_DOUBLE
}, {
/* 480x300 @ 72 Hz, 48.0 kHz hsync */
NULL, 72, 480, 300, 33386, 40, 24, 11, 19, 80, 3,
0, FB_VMODE_DOUBLE
},
};
const struct fb_videomode vesa_modes[] = {
/* 0 640x350-85 VESA */
{ NULL, 85, 640, 350, 31746, 96, 32, 60, 32, 64, 3,
FB_SYNC_HOR_HIGH_ACT, FB_VMODE_NONINTERLACED },
/* 1 640x400-85 VESA */
{ NULL, 85, 640, 400, 31746, 96, 32, 41, 01, 64, 3,
FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED },
/* 2 720x400-85 VESA */
{ NULL, 85, 721, 400, 28169, 108, 36, 42, 01, 72, 3,
FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED },
/* 3 640x480-60 VESA */
{ NULL, 60, 640, 480, 39682, 48, 16, 33, 10, 96, 2,
0, FB_VMODE_NONINTERLACED },
/* 4 640x480-72 VESA */
{ NULL, 72, 640, 480, 31746, 128, 24, 29, 9, 40, 2,
0, FB_VMODE_NONINTERLACED },
/* 5 640x480-75 VESA */
{ NULL, 75, 640, 480, 31746, 120, 16, 16, 01, 64, 3,
0, FB_VMODE_NONINTERLACED },
/* 6 640x480-85 VESA */
{ NULL, 85, 640, 480, 27777, 80, 56, 25, 01, 56, 3,
0, FB_VMODE_NONINTERLACED },
/* 7 800x600-56 VESA */
{ NULL, 56, 800, 600, 27777, 128, 24, 22, 01, 72, 2,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED },
/* 8 800x600-60 VESA */
{ NULL, 60, 800, 600, 25000, 88, 40, 23, 01, 128, 4,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED },
/* 9 800x600-72 VESA */
{ NULL, 72, 800, 600, 20000, 64, 56, 23, 37, 120, 6,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED },
/* 10 800x600-75 VESA */
{ NULL, 75, 800, 600, 20202, 160, 16, 21, 01, 80, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED },
/* 11 800x600-85 VESA */
{ NULL, 85, 800, 600, 17761, 152, 32, 27, 01, 64, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED },
/* 12 1024x768i-43 VESA */
{ NULL, 53, 1024, 768, 22271, 56, 8, 41, 0, 176, 8,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, FB_VMODE_INTERLACED },
/* 13 1024x768-60 VESA */
{ NULL, 60, 1024, 768, 15384, 160, 24, 29, 3, 136, 6,
0, FB_VMODE_NONINTERLACED },
/* 14 1024x768-70 VESA */
{ NULL, 70, 1024, 768, 13333, 144, 24, 29, 3, 136, 6,
0, FB_VMODE_NONINTERLACED },
/* 15 1024x768-75 VESA */
{ NULL, 75, 1024, 768, 12690, 176, 16, 28, 1, 96, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED },
/* 16 1024x768-85 VESA */
{ NULL, 85, 1024, 768, 10582, 208, 48, 36, 1, 96, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED },
/* 17 1152x864-75 VESA */
{ NULL, 75, 1153, 864, 9259, 256, 64, 32, 1, 128, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED },
/* 18 1280x960-60 VESA */
{ NULL, 60, 1280, 960, 9259, 312, 96, 36, 1, 112, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED },
/* 19 1280x960-85 VESA */
{ NULL, 85, 1280, 960, 6734, 224, 64, 47, 1, 160, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED },
/* 20 1280x1024-60 VESA */
{ NULL, 60, 1280, 1024, 9259, 248, 48, 38, 1, 112, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED },
/* 21 1280x1024-75 VESA */
{ NULL, 75, 1280, 1024, 7407, 248, 16, 38, 1, 144, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED },
/* 22 1280x1024-85 VESA */
{ NULL, 85, 1280, 1024, 6349, 224, 64, 44, 1, 160, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED },
/* 23 1600x1200-60 VESA */
{ NULL, 60, 1600, 1200, 6172, 304, 64, 46, 1, 192, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED },
/* 24 1600x1200-65 VESA */
{ NULL, 65, 1600, 1200, 5698, 304, 64, 46, 1, 192, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED },
/* 25 1600x1200-70 VESA */
{ NULL, 70, 1600, 1200, 5291, 304, 64, 46, 1, 192, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED },
/* 26 1600x1200-75 VESA */
{ NULL, 75, 1600, 1200, 4938, 304, 64, 46, 1, 192, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED },
/* 27 1600x1200-85 VESA */
{ NULL, 85, 1600, 1200, 4357, 304, 64, 46, 1, 192, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED },
/* 28 1792x1344-60 VESA */
{ NULL, 60, 1792, 1344, 4882, 328, 128, 46, 1, 200, 3,
FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED },
/* 29 1792x1344-75 VESA */
{ NULL, 75, 1792, 1344, 3831, 352, 96, 69, 1, 216, 3,
FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED },
/* 30 1856x1392-60 VESA */
{ NULL, 60, 1856, 1392, 4580, 352, 96, 43, 1, 224, 3,
FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED },
/* 31 1856x1392-75 VESA */
{ NULL, 75, 1856, 1392, 3472, 352, 128, 104, 1, 224, 3,
FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED },
/* 32 1920x1440-60 VESA */
{ NULL, 60, 1920, 1440, 4273, 344, 128, 56, 1, 200, 3,
FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED },
/* 33 1920x1440-75 VESA */
{ NULL, 60, 1920, 1440, 3367, 352, 144, 56, 1, 224, 3,
FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED },
};
static int __init my_atoi(const char *name)
{
int val = 0;
for (;; name++) {
switch (*name) {
case '0'...'9':
val = 10*val+(*name-'0');
break;
default:
return val;
}
}
}
/**
* __fb_try_mode - test a video mode
* @var: frame buffer user defined part of display
* @info: frame buffer info structure
* @mode: frame buffer video mode structure
* @bpp: color depth in bits per pixel
*
* Tries a video mode to test it's validity for device @info.
*
* Returns 1 on success.
*
*/
int __fb_try_mode(struct fb_var_screeninfo *var, struct fb_info *info,
const struct fb_videomode *mode, unsigned int bpp)
{
int err = 1;
DPRINTK("Trying mode %s %dx%d-%d@%d\n", mode->name ? mode->name : "noname",
mode->xres, mode->yres, bpp, mode->refresh);
var->xres = mode->xres;
var->yres = mode->yres;
var->xres_virtual = mode->xres;
var->yres_virtual = mode->yres;
var->xoffset = 0;
var->yoffset = 0;
var->bits_per_pixel = bpp;
var->activate |= FB_ACTIVATE_TEST;
var->pixclock = mode->pixclock;
var->left_margin = mode->left_margin;
var->right_margin = mode->right_margin;
var->upper_margin = mode->upper_margin;
var->lower_margin = mode->lower_margin;
var->hsync_len = mode->hsync_len;
var->vsync_len = mode->vsync_len;
var->sync = mode->sync;
var->vmode = mode->vmode;
if (info->fbops->fb_check_var)
err = info->fbops->fb_check_var(var, info);
var->activate &= ~FB_ACTIVATE_TEST;
return !err;
}
/**
* fb_find_mode - finds a valid video mode
* @var: frame buffer user defined part of display
* @info: frame buffer info structure
* @mode_option: string video mode to find
* @db: video mode database
* @dbsize: size of @db
* @default_mode: default video mode to fall back to
* @default_bpp: default color depth in bits per pixel
*
* Finds a suitable video mode, starting with the specified mode
* in @mode_option with fallback to @default_mode. If
* @default_mode fails, all modes in the video mode database will
* be tried.
*
* Valid mode specifiers for @mode_option:
*
* <xres>x<yres>[-<bpp>][@<refresh>] or
* <name>[-<bpp>][@<refresh>]
*
* with <xres>, <yres>, <bpp> and <refresh> decimal numbers and
* <name> a string.
*
* NOTE: The passed struct @var is _not_ cleared! This allows you
* to supply values for e.g. the grayscale and accel_flags fields.
*
* Returns zero for failure, 1 if using specified @mode_option,
* 2 if using specified @mode_option with an ignored refresh rate,
* 3 if default mode is used, 4 if fall back to any valid mode.
*
*/
int __init fb_find_mode(struct fb_var_screeninfo *var,
struct fb_info *info, const char *mode_option,
const struct fb_videomode *db, unsigned int dbsize,
const struct fb_videomode *default_mode,
unsigned int default_bpp)
{
int i, j;
/* Set up defaults */
if (!db) {
db = modedb;
dbsize = sizeof(modedb)/sizeof(*modedb);
}
if (!default_mode)
default_mode = &modedb[DEFAULT_MODEDB_INDEX];
if (!default_bpp)
default_bpp = 8;
/* Did the user specify a video mode? */
if (mode_option || (mode_option = global_mode_option)) {
const char *name = mode_option;
unsigned int namelen = strlen(name);
int res_specified = 0, bpp_specified = 0, refresh_specified = 0;
unsigned int xres = 0, yres = 0, bpp = default_bpp, refresh = 0;
int yres_specified = 0;
for (i = namelen-1; i >= 0; i--) {
switch (name[i]) {
case '@':
namelen = i;
if (!refresh_specified && !bpp_specified &&
!yres_specified) {
refresh = my_atoi(&name[i+1]);
refresh_specified = 1;
} else
goto done;
break;
case '-':
namelen = i;
if (!bpp_specified && !yres_specified) {
bpp = my_atoi(&name[i+1]);
bpp_specified = 1;
} else
goto done;
break;
case 'x':
if (!yres_specified) {
yres = my_atoi(&name[i+1]);
yres_specified = 1;
} else
goto done;
break;
case '0'...'9':
break;
default:
goto done;
}
}
if (i < 0 && yres_specified) {
xres = my_atoi(name);
res_specified = 1;
}
done:
for (i = refresh_specified; i >= 0; i--) {
DPRINTK("Trying specified video mode%s\n",
i ? "" : " (ignoring refresh rate)");
for (j = 0; j < dbsize; j++)
if ((name_matches(db[j], name, namelen) ||
(res_specified && res_matches(db[j], xres, yres))) &&
(!i || db[j].refresh == refresh) &&
__fb_try_mode(var, info, &db[j], bpp))
return 2-i;
}
}
DPRINTK("Trying default video mode\n");
if (__fb_try_mode(var, info, default_mode, default_bpp))
return 3;
DPRINTK("Trying all modes\n");
for (i = 0; i < dbsize; i++)
if (__fb_try_mode(var, info, &db[i], default_bpp))
return 4;
DPRINTK("No valid mode found\n");
return 0;
}
EXPORT_SYMBOL(__fb_try_mode);
EXPORT_SYMBOL(vesa_modes);

/shark/trunk/drivers/fb/makefile
11,11 → 11,12
OBJS_PATH = $(BASE)/drivers/fb
OBJS = fbmem.o fbcmap.o cfbfillrect.o softcursor.o cfbcopyarea.o cfbimgblt.o\
vga16fb.o vgastate.o vesafb.o shark_fb26.o
modedb.o vga16fb.o vgastate.o vesafb.o radeonfb.o shark_fb26.o\
./riva/fbdev.o ./riva/nv_driver.o ./riva/riva_hw.o
OTHERINCL += -I$(BASE)/drivers/linuxc26/include
C_OPT += -D__KERNEL__ -D__i386__ -DCONFIG_FB_VGA16
C_OPT += -D__KERNEL__ -D__i386__ -DCONFIG_FB_RIVA
include $(BASE)/config/lib.mk