| 46,6 → 46,11 |
|---|
| unsigned int apic_clk_per_msec = 0; |
| unsigned int apic_set_limit = 0; |
| |
| unsigned int clk_opt_1 = 0; |
| unsigned int clk_opt_2 = 0; |
| unsigned int clk_opt_3 = 0; |
| unsigned int clk_opt_4 = 0; |
| |
| unsigned char save_CMOS_regA; |
| unsigned char save_CMOS_regB; |
| |
| 186,9 → 191,40 |
|---|
| dtsc = irq8_end - irq8_start; |
| |
| clk_per_msec = dtsc / 500; |
| clk_opt_1 = (unsigned int)((unsigned long long)(dtsc << 1)); |
| clk_opt_2 = (unsigned int)((unsigned long long)(dtsc << 33) / 1000000000L); |
| clk_opt_3 = (unsigned int)((unsigned long long)(dtsc << 32) / 1000000000L); |
| clk_opt_4 = (unsigned int)((unsigned long long)(dtsc << 31) / 1000000000L); |
| |
| message("Calibrated CPU Clk/msec = %10d\n",clk_per_msec); |
| message("Calibrated CPU Clk/msec = %10u\n",clk_per_msec); |
| |
| #ifdef __O1000__ |
| if (clk_per_msec < 1000000) { |
| message("Timer Optimization CPU < 1 GHz\n"); |
| } else { |
| message("Bad Timer Optimization\n"); |
| ll_abort(66); |
| } |
| #endif |
| |
| #ifdef __O2000__ |
| if (clk_per_msec < 2000000 && clk_per_msec >= 1000000) { |
| message("Timer Optimization 1 GHz < CPU < 2 GHz\n"); |
| } else { |
| message("Bad Timer Optimization\n"); |
| ll_abort(66); |
| } |
| #endif |
| |
| #ifdef __O4000__ |
| if (clk_per_msec < 4000000 && clk_per_msec >= 2000000) { |
| message("Timer Optimization 2 GHz < CPU < 4 GHz\n"); |
| } else { |
| message("Bad Timer Optimization\n"); |
| ll_abort(66); |
| } |
| #endif |
| |
| irq_mask(8); |
| |
| CMOS_WRITE(0x0A,save_CMOS_regA); |