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/*
   Copyright 2003 Red Hat, Inc.  All rights reserved.
   Copyright 2003 Jeff Garzik

   The contents of this file are subject to the Open
   Software License version 1.1 that can be found at
   http://www.opensource.org/licenses/osl-1.1.txt and is included herein
   by reference.

   Alternatively, the contents of this file may be used under the terms
   of the GNU General Public License version 2 (the "GPL") as distributed
   in the kernel source COPYING file, in which case the provisions of
   the GPL are applicable instead of the above.  If you wish to allow
   the use of your version of this file only under the terms of the
   GPL and not to allow others to use your version of this file under
   the OSL, indicate your decision by deleting the provisions above and
   replace them with the notice and other provisions required by the GPL.
   If you do not delete the provisions above, a recipient may use your
   version of this file under either the OSL or the GPL.

 */


#ifndef __LINUX_ATA_H__
#define __LINUX_ATA_H__

/* defines only for the constants which don't work well as enums */
#define ATA_DMA_BOUNDARY        0xffffUL
#define ATA_DMA_MASK            0xffffffffULL

enum {
        /* various global constants */
        ATA_MAX_DEVICES         = 2,    /* per bus/port */
        ATA_MAX_PRD             = 256/* we could make these 256/256 */
        ATA_SECT_SIZE           = 512,
        ATA_SECT_SIZE_MASK      = (ATA_SECT_SIZE - 1),
        ATA_SECT_DWORDS         = ATA_SECT_SIZE / sizeof(u32),

        ATA_ID_WORDS            = 256,
        ATA_ID_PROD_OFS         = 27,
        ATA_ID_SERNO_OFS        = 10,
        ATA_ID_MAJOR_VER        = 80,
        ATA_ID_PIO_MODES        = 64,
        ATA_ID_UDMA_MODES       = 88,
        ATA_ID_PIO4             = (1 << 1),

        ATA_PCI_CTL_OFS         = 2,
        ATA_SERNO_LEN           = 20,
        ATA_UDMA0               = (1 << 0),
        ATA_UDMA1               = ATA_UDMA0 | (1 << 1),
        ATA_UDMA2               = ATA_UDMA1 | (1 << 2),
        ATA_UDMA3               = ATA_UDMA2 | (1 << 3),
        ATA_UDMA4               = ATA_UDMA3 | (1 << 4),
        ATA_UDMA5               = ATA_UDMA4 | (1 << 5),
        ATA_UDMA6               = ATA_UDMA5 | (1 << 6),
        ATA_UDMA7               = ATA_UDMA6 | (1 << 7),
        /* ATA_UDMA7 is just for completeness... doesn't exist (yet?).  */

        ATA_UDMA_MASK_40C       = ATA_UDMA2,    /* udma0-2 */

        /* DMA-related */
        ATA_PRD_SZ              = 8,
        ATA_PRD_TBL_SZ          = (ATA_MAX_PRD * ATA_PRD_SZ),
        ATA_PRD_EOT             = (1 << 31),    /* end-of-table flag */

        ATA_DMA_TABLE_OFS       = 4,
        ATA_DMA_STATUS          = 2,
        ATA_DMA_CMD             = 0,
        ATA_DMA_WR              = (1 << 3),
        ATA_DMA_START           = (1 << 0),
        ATA_DMA_INTR            = (1 << 2),
        ATA_DMA_ERR             = (1 << 1),
        ATA_DMA_ACTIVE          = (1 << 0),

        /* bits in ATA command block registers */
        ATA_HOB                 = (1 << 7),     /* LBA48 selector */
        ATA_NIEN                = (1 << 1),     /* disable-irq flag */
        ATA_LBA                 = (1 << 6),     /* LBA28 selector */
        ATA_DEV1                = (1 << 4),     /* Select Device 1 (slave) */
        ATA_BUSY                = (1 << 7),     /* BSY status bit */
        ATA_DEVICE_OBS          = (1 << 7) | (1 << 5), /* obs bits in dev reg */
        ATA_DEVCTL_OBS          = (1 << 3),     /* obsolete bit in devctl reg */
        ATA_DRQ                 = (1 << 3),     /* data request i/o */
        ATA_ERR                 = (1 << 0),     /* have an error */
        ATA_SRST                = (1 << 2),     /* software reset */
        ATA_ABORTED             = (1 << 2),     /* command aborted */

        /* ATA command block registers */
        ATA_REG_DATA            = 0x00,
        ATA_REG_ERR             = 0x01,
        ATA_REG_NSECT           = 0x02,
        ATA_REG_LBAL            = 0x03,
        ATA_REG_LBAM            = 0x04,
        ATA_REG_LBAH            = 0x05,
        ATA_REG_DEVICE          = 0x06,
        ATA_REG_STATUS          = 0x07,

        ATA_REG_FEATURE         = ATA_REG_ERR, /* and their aliases */
        ATA_REG_CMD             = ATA_REG_STATUS,
        ATA_REG_BYTEL           = ATA_REG_LBAM,
        ATA_REG_BYTEH           = ATA_REG_LBAH,
        ATA_REG_DEVSEL          = ATA_REG_DEVICE,
        ATA_REG_IRQ             = ATA_REG_NSECT,

        /* ATA taskfile protocols */
        ATA_PROT_UNKNOWN        = 0,
        ATA_PROT_NODATA         = 1,
        ATA_PROT_PIO_READ       = 2,
        ATA_PROT_PIO_WRITE      = 3,
        ATA_PROT_DMA_READ       = 4,
        ATA_PROT_DMA_WRITE      = 5,
        ATA_PROT_ATAPI          = 6,
        ATA_PROT_ATAPI_DMA      = 7,

        /* ATA device commands */
        ATA_CMD_EDD             = 0x90, /* execute device diagnostic */
        ATA_CMD_ID_ATA          = 0xEC,
        ATA_CMD_ID_ATAPI        = 0xA1,
        ATA_CMD_READ            = 0xC8,
        ATA_CMD_READ_EXT        = 0x25,
        ATA_CMD_WRITE           = 0xCA,
        ATA_CMD_WRITE_EXT       = 0x35,
        ATA_CMD_PIO_READ        = 0x20,
        ATA_CMD_PIO_READ_EXT    = 0x24,
        ATA_CMD_PIO_WRITE       = 0x30,
        ATA_CMD_PIO_WRITE_EXT   = 0x34,
        ATA_CMD_SET_FEATURES    = 0xEF,
        ATA_CMD_PACKET          = 0xA0,

        /* SETFEATURES stuff */
        SETFEATURES_XFER        = 0x03,
        XFER_UDMA_7             = 0x47,
        XFER_UDMA_6             = 0x46,
        XFER_UDMA_5             = 0x45,
        XFER_UDMA_4             = 0x44,
        XFER_UDMA_3             = 0x43,
        XFER_UDMA_2             = 0x42,
        XFER_UDMA_1             = 0x41,
        XFER_UDMA_0             = 0x40,
        XFER_PIO_4              = 0x0C,
        XFER_PIO_3              = 0x0B,

        /* ATAPI stuff */
        ATAPI_PKT_DMA           = (1 << 0),

        /* cable types */
        ATA_CBL_NONE            = 0,
        ATA_CBL_PATA40          = 1,
        ATA_CBL_PATA80          = 2,
        ATA_CBL_PATA_UNK        = 3,
        ATA_CBL_SATA            = 4,

        /* SATA Status and Control Registers */
        SCR_STATUS              = 0,
        SCR_ERROR               = 1,
        SCR_CONTROL             = 2,
        SCR_ACTIVE              = 3,
        SCR_NOTIFICATION        = 4,
};

/* core structures */
struct ata_prd {
        u32                     addr;
        u32                     flags_len;
} __attribute__((packed));

#define ata_id_is_ata(dev)      (((dev)->id[0] & (1 << 15)) == 0)
#define ata_id_has_lba48(dev)   ((dev)->id[83] & (1 << 10))
#define ata_id_has_lba(dev)     ((dev)->id[49] & (1 << 8))
#define ata_id_has_dma(dev)     ((dev)->id[49] & (1 << 9))
#define ata_id_u32(dev,n)       \
        (((u32) (dev)->id[(n) + 1] << 16) | ((u32) (dev)->id[(n)]))

#define ata_id_u64(dev,n)       \
        ( ((u64) dev->id[(n) + 3] << 48) |      \
          ((u64) dev->id[(n) + 2] << 32) |      \
          ((u64) dev->id[(n) + 1] << 16) |      \
          ((u64) dev->id[(n) + 0]) )


#endif /* __LINUX_ATA_H__ */