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# S.Ha.R.K. Setup File
#
# Oslib Configuration
#

# Enable the system time computation through TSC register
# Only Pentium or higher CPU class
TSC = TRUE

# Enable timer interrupt through P6 APIC instead of PIT
# Only P6 or higher CPU class, TSC support must be enabled
APIC = FALSE

#Enable Read Timer Optimization
#TIMER_OPT = 1000 (For CPU < 1 GHz          - Wraparound 585 years)
#TIMER_OPT = 2000 (For 1 GHz < CPU < 2 GHz  - Wraparound 146 years)
#TIMER_OPT = 4000 (For 2 GHz < CPU < 4 GHz  - Wraparound  36 years)
#TIMER_OPT = SLOW (No CPU dependent         - Wraparound 585 years)
TIMER_OPT = SLOW